1 /* SPDX-License-Identifier: MIT */ 2 /* Copyright © 2026 Intel Corporation */ 3 4 #ifndef _INTEL_GMD_INTERRUPT_REGS_H_ 5 #define _INTEL_GMD_INTERRUPT_REGS_H_ 6 7 #define I915_PM_INTERRUPT (1 << 31) 8 #define I915_ISP_INTERRUPT (1 << 22) 9 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 10 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 11 #define I915_MIPIC_INTERRUPT (1 << 19) 12 #define I915_MIPIA_INTERRUPT (1 << 18) 13 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 14 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 15 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 16 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 17 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 18 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 19 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 20 #define I915_HWB_OOM_INTERRUPT (1 << 13) 21 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 22 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 23 #define I915_MISC_INTERRUPT (1 << 11) 24 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 25 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 26 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 27 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 28 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 29 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 30 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 31 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 32 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 33 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 34 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 35 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 36 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 37 #define I915_DEBUG_INTERRUPT (1 << 2) 38 #define I915_WINVALID_INTERRUPT (1 << 1) 39 #define I915_USER_INTERRUPT (1 << 1) 40 #define I915_ASLE_INTERRUPT (1 << 0) 41 #define I915_BSD_USER_INTERRUPT (1 << 25) 42 43 #define GEN8_MASTER_IRQ _MMIO(0x44200) 44 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 45 #define GEN8_PCU_IRQ (1 << 30) 46 #define GEN8_DE_PCH_IRQ (1 << 23) 47 #define GEN8_DE_MISC_IRQ (1 << 22) 48 #define GEN8_DE_PORT_IRQ (1 << 20) 49 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 50 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 51 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 52 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 53 #define GEN8_GT_VECS_IRQ (1 << 6) 54 #define GEN8_GT_GUC_IRQ (1 << 5) 55 #define GEN8_GT_PM_IRQ (1 << 4) 56 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 57 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 58 #define GEN8_GT_BCS_IRQ (1 << 1) 59 #define GEN8_GT_RCS_IRQ (1 << 0) 60 61 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 62 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 63 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 64 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 65 #define GEN11_GU_MISC_GSE (1 << 27) 66 67 #define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \ 68 GEN11_GU_MISC_IER, \ 69 GEN11_GU_MISC_IIR) 70 71 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 72 #define GEN11_MASTER_IRQ (1 << 31) 73 #define GEN11_PCU_IRQ (1 << 30) 74 #define GEN11_GU_MISC_IRQ (1 << 29) 75 #define GEN11_DISPLAY_IRQ (1 << 16) 76 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 77 #define GEN11_GT_DW1_IRQ (1 << 1) 78 #define GEN11_GT_DW0_IRQ (1 << 0) 79 80 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 81 #define SCPD_FBC_IGNORE_3D (1 << 6) 82 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 83 84 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 85 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 86 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 87 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 88 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 89 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 90 #define VLV_PCBR_ADDR_SHIFT 12 91 92 #endif 93