1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Handles the Intel 27x USB Device Controller (UDC) 4 * 5 * Inspired by original driver by Frank Becker, David Brownell, and others. 6 * Copyright (C) 2008 Robert Jarzmik 7 */ 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/errno.h> 12 #include <linux/err.h> 13 #include <linux/platform_device.h> 14 #include <linux/delay.h> 15 #include <linux/list.h> 16 #include <linux/interrupt.h> 17 #include <linux/proc_fs.h> 18 #include <linux/clk.h> 19 #include <linux/irq.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/prefetch.h> 24 #include <linux/byteorder/generic.h> 25 #include <linux/platform_data/pxa2xx_udc.h> 26 #include <linux/of.h> 27 28 #include <linux/usb.h> 29 #include <linux/usb/ch9.h> 30 #include <linux/usb/gadget.h> 31 #include <linux/usb/phy.h> 32 33 #include "pxa27x_udc.h" 34 35 /* 36 * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x 37 * series processors. 38 * 39 * Such controller drivers work with a gadget driver. The gadget driver 40 * returns descriptors, implements configuration and data protocols used 41 * by the host to interact with this device, and allocates endpoints to 42 * the different protocol interfaces. The controller driver virtualizes 43 * usb hardware so that the gadget drivers will be more portable. 44 * 45 * This UDC hardware wants to implement a bit too much USB protocol. The 46 * biggest issues are: that the endpoints have to be set up before the 47 * controller can be enabled (minor, and not uncommon); and each endpoint 48 * can only have one configuration, interface and alternative interface 49 * number (major, and very unusual). Once set up, these cannot be changed 50 * without a controller reset. 51 * 52 * The workaround is to setup all combinations necessary for the gadgets which 53 * will work with this driver. This is done in pxa_udc structure, statically. 54 * See pxa_udc, udc_usb_ep versus pxa_ep, and matching function find_pxa_ep. 55 * (You could modify this if needed. Some drivers have a "fifo_mode" module 56 * parameter to facilitate such changes.) 57 * 58 * The combinations have been tested with these gadgets : 59 * - zero gadget 60 * - file storage gadget 61 * - ether gadget 62 * 63 * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is 64 * made of UDC's double buffering either. USB "On-The-Go" is not implemented. 65 * 66 * All the requests are handled the same way : 67 * - the drivers tries to handle the request directly to the IO 68 * - if the IO fifo is not big enough, the remaining is send/received in 69 * interrupt handling. 70 */ 71 72 #define DRIVER_VERSION "2008-04-18" 73 #define DRIVER_DESC "PXA 27x USB Device Controller driver" 74 75 static const char driver_name[] = "pxa27x_udc"; 76 static struct pxa_udc *the_controller; 77 78 static void handle_ep(struct pxa_ep *ep); 79 80 /* 81 * Debug filesystem 82 */ 83 #ifdef CONFIG_USB_GADGET_DEBUG_FS 84 85 #include <linux/debugfs.h> 86 #include <linux/uaccess.h> 87 #include <linux/seq_file.h> 88 89 static int state_dbg_show(struct seq_file *s, void *p) 90 { 91 struct pxa_udc *udc = s->private; 92 u32 tmp; 93 94 if (!udc->driver) 95 return -ENODEV; 96 97 /* basic device status */ 98 seq_printf(s, DRIVER_DESC "\n" 99 "%s version: %s\n" 100 "Gadget driver: %s\n", 101 driver_name, DRIVER_VERSION, 102 udc->driver ? udc->driver->driver.name : "(none)"); 103 104 tmp = udc_readl(udc, UDCCR); 105 seq_printf(s, 106 "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), con=%d,inter=%d,altinter=%d\n", 107 tmp, 108 (tmp & UDCCR_OEN) ? " oen":"", 109 (tmp & UDCCR_AALTHNP) ? " aalthnp":"", 110 (tmp & UDCCR_AHNP) ? " rem" : "", 111 (tmp & UDCCR_BHNP) ? " rstir" : "", 112 (tmp & UDCCR_DWRE) ? " dwre" : "", 113 (tmp & UDCCR_SMAC) ? " smac" : "", 114 (tmp & UDCCR_EMCE) ? " emce" : "", 115 (tmp & UDCCR_UDR) ? " udr" : "", 116 (tmp & UDCCR_UDA) ? " uda" : "", 117 (tmp & UDCCR_UDE) ? " ude" : "", 118 (tmp & UDCCR_ACN) >> UDCCR_ACN_S, 119 (tmp & UDCCR_AIN) >> UDCCR_AIN_S, 120 (tmp & UDCCR_AAISN) >> UDCCR_AAISN_S); 121 /* registers for device and ep0 */ 122 seq_printf(s, "udcicr0=0x%08x udcicr1=0x%08x\n", 123 udc_readl(udc, UDCICR0), udc_readl(udc, UDCICR1)); 124 seq_printf(s, "udcisr0=0x%08x udcisr1=0x%08x\n", 125 udc_readl(udc, UDCISR0), udc_readl(udc, UDCISR1)); 126 seq_printf(s, "udcfnr=%d\n", udc_readl(udc, UDCFNR)); 127 seq_printf(s, "irqs: reset=%lu, suspend=%lu, resume=%lu, reconfig=%lu\n", 128 udc->stats.irqs_reset, udc->stats.irqs_suspend, 129 udc->stats.irqs_resume, udc->stats.irqs_reconfig); 130 131 return 0; 132 } 133 DEFINE_SHOW_ATTRIBUTE(state_dbg); 134 135 static int queues_dbg_show(struct seq_file *s, void *p) 136 { 137 struct pxa_udc *udc = s->private; 138 struct pxa_ep *ep; 139 struct pxa27x_request *req; 140 int i, maxpkt; 141 142 if (!udc->driver) 143 return -ENODEV; 144 145 /* dump endpoint queues */ 146 for (i = 0; i < NR_PXA_ENDPOINTS; i++) { 147 ep = &udc->pxa_ep[i]; 148 maxpkt = ep->fifo_size; 149 seq_printf(s, "%-12s max_pkt=%d %s\n", 150 EPNAME(ep), maxpkt, "pio"); 151 152 if (list_empty(&ep->queue)) { 153 seq_puts(s, "\t(nothing queued)\n"); 154 continue; 155 } 156 157 list_for_each_entry(req, &ep->queue, queue) { 158 seq_printf(s, "\treq %p len %d/%d buf %p\n", 159 &req->req, req->req.actual, 160 req->req.length, req->req.buf); 161 } 162 } 163 164 return 0; 165 } 166 DEFINE_SHOW_ATTRIBUTE(queues_dbg); 167 168 static int eps_dbg_show(struct seq_file *s, void *p) 169 { 170 struct pxa_udc *udc = s->private; 171 struct pxa_ep *ep; 172 int i; 173 u32 tmp; 174 175 if (!udc->driver) 176 return -ENODEV; 177 178 ep = &udc->pxa_ep[0]; 179 tmp = udc_ep_readl(ep, UDCCSR); 180 seq_printf(s, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", 181 tmp, 182 (tmp & UDCCSR0_SA) ? " sa" : "", 183 (tmp & UDCCSR0_RNE) ? " rne" : "", 184 (tmp & UDCCSR0_FST) ? " fst" : "", 185 (tmp & UDCCSR0_SST) ? " sst" : "", 186 (tmp & UDCCSR0_DME) ? " dme" : "", 187 (tmp & UDCCSR0_IPR) ? " ipr" : "", 188 (tmp & UDCCSR0_OPC) ? " opc" : ""); 189 for (i = 0; i < NR_PXA_ENDPOINTS; i++) { 190 ep = &udc->pxa_ep[i]; 191 tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR); 192 seq_printf(s, "%-12s: IN %lu(%lu reqs), OUT %lu(%lu reqs), irqs=%lu, udccr=0x%08x, udccsr=0x%03x, udcbcr=%d\n", 193 EPNAME(ep), 194 ep->stats.in_bytes, ep->stats.in_ops, 195 ep->stats.out_bytes, ep->stats.out_ops, 196 ep->stats.irqs, 197 tmp, udc_ep_readl(ep, UDCCSR), 198 udc_ep_readl(ep, UDCBCR)); 199 } 200 201 return 0; 202 } 203 DEFINE_SHOW_ATTRIBUTE(eps_dbg); 204 205 static void pxa_init_debugfs(struct pxa_udc *udc) 206 { 207 struct dentry *root; 208 209 root = debugfs_create_dir(udc->gadget.name, usb_debug_root); 210 debugfs_create_file("udcstate", 0400, root, udc, &state_dbg_fops); 211 debugfs_create_file("queues", 0400, root, udc, &queues_dbg_fops); 212 debugfs_create_file("epstate", 0400, root, udc, &eps_dbg_fops); 213 } 214 215 static void pxa_cleanup_debugfs(struct pxa_udc *udc) 216 { 217 debugfs_lookup_and_remove(udc->gadget.name, usb_debug_root); 218 } 219 220 #else 221 static inline void pxa_init_debugfs(struct pxa_udc *udc) 222 { 223 } 224 225 static inline void pxa_cleanup_debugfs(struct pxa_udc *udc) 226 { 227 } 228 #endif 229 230 /** 231 * is_match_usb_pxa - check if usb_ep and pxa_ep match 232 * @udc_usb_ep: usb endpoint 233 * @ep: pxa endpoint 234 * @config: configuration required in pxa_ep 235 * @interface: interface required in pxa_ep 236 * @altsetting: altsetting required in pxa_ep 237 * 238 * Returns 1 if all criteria match between pxa and usb endpoint, 0 otherwise 239 */ 240 static int is_match_usb_pxa(struct udc_usb_ep *udc_usb_ep, struct pxa_ep *ep, 241 int config, int interface, int altsetting) 242 { 243 if (usb_endpoint_num(&udc_usb_ep->desc) != ep->addr) 244 return 0; 245 if (usb_endpoint_dir_in(&udc_usb_ep->desc) != ep->dir_in) 246 return 0; 247 if (usb_endpoint_type(&udc_usb_ep->desc) != ep->type) 248 return 0; 249 if ((ep->config != config) || (ep->interface != interface) 250 || (ep->alternate != altsetting)) 251 return 0; 252 return 1; 253 } 254 255 /** 256 * find_pxa_ep - find pxa_ep structure matching udc_usb_ep 257 * @udc: pxa udc 258 * @udc_usb_ep: udc_usb_ep structure 259 * 260 * Match udc_usb_ep and all pxa_ep available, to see if one matches. 261 * This is necessary because of the strong pxa hardware restriction requiring 262 * that once pxa endpoints are initialized, their configuration is freezed, and 263 * no change can be made to their address, direction, or in which configuration, 264 * interface or altsetting they are active ... which differs from more usual 265 * models which have endpoints be roughly just addressable fifos, and leave 266 * configuration events up to gadget drivers (like all control messages). 267 * 268 * Note that there is still a blurred point here : 269 * - we rely on UDCCR register "active interface" and "active altsetting". 270 * This is a nonsense in regard of USB spec, where multiple interfaces are 271 * active at the same time. 272 * - if we knew for sure that the pxa can handle multiple interface at the 273 * same time, assuming Intel's Developer Guide is wrong, this function 274 * should be reviewed, and a cache of couples (iface, altsetting) should 275 * be kept in the pxa_udc structure. In this case this function would match 276 * against the cache of couples instead of the "last altsetting" set up. 277 * 278 * Returns the matched pxa_ep structure or NULL if none found 279 */ 280 static struct pxa_ep *find_pxa_ep(struct pxa_udc *udc, 281 struct udc_usb_ep *udc_usb_ep) 282 { 283 int i; 284 struct pxa_ep *ep; 285 int cfg = udc->config; 286 int iface = udc->last_interface; 287 int alt = udc->last_alternate; 288 289 if (udc_usb_ep == &udc->udc_usb_ep[0]) 290 return &udc->pxa_ep[0]; 291 292 for (i = 1; i < NR_PXA_ENDPOINTS; i++) { 293 ep = &udc->pxa_ep[i]; 294 if (is_match_usb_pxa(udc_usb_ep, ep, cfg, iface, alt)) 295 return ep; 296 } 297 return NULL; 298 } 299 300 /** 301 * update_pxa_ep_matches - update pxa_ep cached values in all udc_usb_ep 302 * @udc: pxa udc 303 * 304 * Context: interrupt handler 305 * 306 * Updates all pxa_ep fields in udc_usb_ep structures, if this field was 307 * previously set up (and is not NULL). The update is necessary is a 308 * configuration change or altsetting change was issued by the USB host. 309 */ 310 static void update_pxa_ep_matches(struct pxa_udc *udc) 311 { 312 int i; 313 struct udc_usb_ep *udc_usb_ep; 314 315 for (i = 1; i < NR_USB_ENDPOINTS; i++) { 316 udc_usb_ep = &udc->udc_usb_ep[i]; 317 if (udc_usb_ep->pxa_ep) 318 udc_usb_ep->pxa_ep = find_pxa_ep(udc, udc_usb_ep); 319 } 320 } 321 322 /** 323 * pio_irq_enable - Enables irq generation for one endpoint 324 * @ep: udc endpoint 325 */ 326 static void pio_irq_enable(struct pxa_ep *ep) 327 { 328 struct pxa_udc *udc = ep->dev; 329 int index = EPIDX(ep); 330 u32 udcicr0 = udc_readl(udc, UDCICR0); 331 u32 udcicr1 = udc_readl(udc, UDCICR1); 332 333 if (index < 16) 334 udc_writel(udc, UDCICR0, udcicr0 | (3 << (index * 2))); 335 else 336 udc_writel(udc, UDCICR1, udcicr1 | (3 << ((index - 16) * 2))); 337 } 338 339 /** 340 * pio_irq_disable - Disables irq generation for one endpoint 341 * @ep: udc endpoint 342 */ 343 static void pio_irq_disable(struct pxa_ep *ep) 344 { 345 struct pxa_udc *udc = ep->dev; 346 int index = EPIDX(ep); 347 u32 udcicr0 = udc_readl(udc, UDCICR0); 348 u32 udcicr1 = udc_readl(udc, UDCICR1); 349 350 if (index < 16) 351 udc_writel(udc, UDCICR0, udcicr0 & ~(3 << (index * 2))); 352 else 353 udc_writel(udc, UDCICR1, udcicr1 & ~(3 << ((index - 16) * 2))); 354 } 355 356 /** 357 * udc_set_mask_UDCCR - set bits in UDCCR 358 * @udc: udc device 359 * @mask: bits to set in UDCCR 360 * 361 * Sets bits in UDCCR, leaving DME and FST bits as they were. 362 */ 363 static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask) 364 { 365 u32 udccr = udc_readl(udc, UDCCR); 366 udc_writel(udc, UDCCR, 367 (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS)); 368 } 369 370 /** 371 * udc_clear_mask_UDCCR - clears bits in UDCCR 372 * @udc: udc device 373 * @mask: bit to clear in UDCCR 374 * 375 * Clears bits in UDCCR, leaving DME and FST bits as they were. 376 */ 377 static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask) 378 { 379 u32 udccr = udc_readl(udc, UDCCR); 380 udc_writel(udc, UDCCR, 381 (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS)); 382 } 383 384 /** 385 * ep_write_UDCCSR - set bits in UDCCSR 386 * @ep: udc endpoint 387 * @mask: bits to set in UDCCR 388 * 389 * Sets bits in UDCCSR (UDCCSR0 and UDCCSR*). 390 * 391 * A specific case is applied to ep0 : the ACM bit is always set to 1, for 392 * SET_INTERFACE and SET_CONFIGURATION. 393 */ 394 static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask) 395 { 396 if (is_ep0(ep)) 397 mask |= UDCCSR0_ACM; 398 udc_ep_writel(ep, UDCCSR, mask); 399 } 400 401 /** 402 * ep_count_bytes_remain - get how many bytes in udc endpoint 403 * @ep: udc endpoint 404 * 405 * Returns number of bytes in OUT fifos. Broken for IN fifos (-EOPNOTSUPP) 406 */ 407 static int ep_count_bytes_remain(struct pxa_ep *ep) 408 { 409 if (ep->dir_in) 410 return -EOPNOTSUPP; 411 return udc_ep_readl(ep, UDCBCR) & 0x3ff; 412 } 413 414 /** 415 * ep_is_empty - checks if ep has byte ready for reading 416 * @ep: udc endpoint 417 * 418 * If endpoint is the control endpoint, checks if there are bytes in the 419 * control endpoint fifo. If endpoint is a data endpoint, checks if bytes 420 * are ready for reading on OUT endpoint. 421 * 422 * Returns 0 if ep not empty, 1 if ep empty, -EOPNOTSUPP if IN endpoint 423 */ 424 static int ep_is_empty(struct pxa_ep *ep) 425 { 426 int ret; 427 428 if (!is_ep0(ep) && ep->dir_in) 429 return -EOPNOTSUPP; 430 if (is_ep0(ep)) 431 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR0_RNE); 432 else 433 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNE); 434 return ret; 435 } 436 437 /** 438 * ep_is_full - checks if ep has place to write bytes 439 * @ep: udc endpoint 440 * 441 * If endpoint is not the control endpoint and is an IN endpoint, checks if 442 * there is place to write bytes into the endpoint. 443 * 444 * Returns 0 if ep not full, 1 if ep full, -EOPNOTSUPP if OUT endpoint 445 */ 446 static int ep_is_full(struct pxa_ep *ep) 447 { 448 if (is_ep0(ep)) 449 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_IPR); 450 if (!ep->dir_in) 451 return -EOPNOTSUPP; 452 return (!(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNF)); 453 } 454 455 /** 456 * epout_has_pkt - checks if OUT endpoint fifo has a packet available 457 * @ep: pxa endpoint 458 * 459 * Returns 1 if a complete packet is available, 0 if not, -EOPNOTSUPP for IN ep. 460 */ 461 static int epout_has_pkt(struct pxa_ep *ep) 462 { 463 if (!is_ep0(ep) && ep->dir_in) 464 return -EOPNOTSUPP; 465 if (is_ep0(ep)) 466 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_OPC); 467 return (udc_ep_readl(ep, UDCCSR) & UDCCSR_PC); 468 } 469 470 /** 471 * set_ep0state - Set ep0 automata state 472 * @udc: udc device 473 * @state: state 474 */ 475 static void set_ep0state(struct pxa_udc *udc, int state) 476 { 477 struct pxa_ep *ep = &udc->pxa_ep[0]; 478 char *old_stname = EP0_STNAME(udc); 479 480 udc->ep0state = state; 481 ep_dbg(ep, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname, 482 EP0_STNAME(udc), udc_ep_readl(ep, UDCCSR), 483 udc_ep_readl(ep, UDCBCR)); 484 } 485 486 /** 487 * ep0_idle - Put control endpoint into idle state 488 * @dev: udc device 489 */ 490 static void ep0_idle(struct pxa_udc *dev) 491 { 492 set_ep0state(dev, WAIT_FOR_SETUP); 493 } 494 495 /** 496 * inc_ep_stats_reqs - Update ep stats counts 497 * @ep: physical endpoint 498 * @is_in: ep direction (USB_DIR_IN or 0) 499 * 500 */ 501 static void inc_ep_stats_reqs(struct pxa_ep *ep, int is_in) 502 { 503 if (is_in) 504 ep->stats.in_ops++; 505 else 506 ep->stats.out_ops++; 507 } 508 509 /** 510 * inc_ep_stats_bytes - Update ep stats counts 511 * @ep: physical endpoint 512 * @count: bytes transferred on endpoint 513 * @is_in: ep direction (USB_DIR_IN or 0) 514 */ 515 static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in) 516 { 517 if (is_in) 518 ep->stats.in_bytes += count; 519 else 520 ep->stats.out_bytes += count; 521 } 522 523 /** 524 * pxa_ep_setup - Sets up an usb physical endpoint 525 * @ep: pxa27x physical endpoint 526 * 527 * Find the physical pxa27x ep, and setup its UDCCR 528 */ 529 static void pxa_ep_setup(struct pxa_ep *ep) 530 { 531 u32 new_udccr; 532 533 new_udccr = ((ep->config << UDCCONR_CN_S) & UDCCONR_CN) 534 | ((ep->interface << UDCCONR_IN_S) & UDCCONR_IN) 535 | ((ep->alternate << UDCCONR_AISN_S) & UDCCONR_AISN) 536 | ((EPADDR(ep) << UDCCONR_EN_S) & UDCCONR_EN) 537 | ((EPXFERTYPE(ep) << UDCCONR_ET_S) & UDCCONR_ET) 538 | ((ep->dir_in) ? UDCCONR_ED : 0) 539 | ((ep->fifo_size << UDCCONR_MPS_S) & UDCCONR_MPS) 540 | UDCCONR_EE; 541 542 udc_ep_writel(ep, UDCCR, new_udccr); 543 } 544 545 /** 546 * pxa_eps_setup - Sets up all usb physical endpoints 547 * @dev: udc device 548 * 549 * Setup all pxa physical endpoints, except ep0 550 */ 551 static void pxa_eps_setup(struct pxa_udc *dev) 552 { 553 unsigned int i; 554 555 dev_dbg(dev->dev, "%s: dev=%p\n", __func__, dev); 556 557 for (i = 1; i < NR_PXA_ENDPOINTS; i++) 558 pxa_ep_setup(&dev->pxa_ep[i]); 559 } 560 561 /** 562 * pxa_ep_alloc_request - Allocate usb request 563 * @_ep: usb endpoint 564 * @gfp_flags: 565 * 566 * For the pxa27x, these can just wrap kmalloc/kfree. gadget drivers 567 * must still pass correctly initialized endpoints, since other controller 568 * drivers may care about how it's currently set up (dma issues etc). 569 */ 570 static struct usb_request * 571 pxa_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 572 { 573 struct pxa27x_request *req; 574 575 req = kzalloc(sizeof *req, gfp_flags); 576 if (!req) 577 return NULL; 578 579 INIT_LIST_HEAD(&req->queue); 580 req->in_use = 0; 581 req->udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 582 583 return &req->req; 584 } 585 586 /** 587 * pxa_ep_free_request - Free usb request 588 * @_ep: usb endpoint 589 * @_req: usb request 590 * 591 * Wrapper around kfree to free _req 592 */ 593 static void pxa_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) 594 { 595 struct pxa27x_request *req; 596 597 req = container_of(_req, struct pxa27x_request, req); 598 WARN_ON(!list_empty(&req->queue)); 599 kfree(req); 600 } 601 602 /** 603 * ep_add_request - add a request to the endpoint's queue 604 * @ep: usb endpoint 605 * @req: usb request 606 * 607 * Context: ep->lock held 608 * 609 * Queues the request in the endpoint's queue, and enables the interrupts 610 * on the endpoint. 611 */ 612 static void ep_add_request(struct pxa_ep *ep, struct pxa27x_request *req) 613 { 614 if (unlikely(!req)) 615 return; 616 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, 617 req->req.length, udc_ep_readl(ep, UDCCSR)); 618 619 req->in_use = 1; 620 list_add_tail(&req->queue, &ep->queue); 621 pio_irq_enable(ep); 622 } 623 624 /** 625 * ep_del_request - removes a request from the endpoint's queue 626 * @ep: usb endpoint 627 * @req: usb request 628 * 629 * Context: ep->lock held 630 * 631 * Unqueue the request from the endpoint's queue. If there are no more requests 632 * on the endpoint, and if it's not the control endpoint, interrupts are 633 * disabled on the endpoint. 634 */ 635 static void ep_del_request(struct pxa_ep *ep, struct pxa27x_request *req) 636 { 637 if (unlikely(!req)) 638 return; 639 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, 640 req->req.length, udc_ep_readl(ep, UDCCSR)); 641 642 list_del_init(&req->queue); 643 req->in_use = 0; 644 if (!is_ep0(ep) && list_empty(&ep->queue)) 645 pio_irq_disable(ep); 646 } 647 648 /** 649 * req_done - Complete an usb request 650 * @ep: pxa physical endpoint 651 * @req: pxa request 652 * @status: usb request status sent to gadget API 653 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 654 * 655 * Context: ep->lock held if flags not NULL, else ep->lock released 656 * 657 * Retire a pxa27x usb request. Endpoint must be locked. 658 */ 659 static void req_done(struct pxa_ep *ep, struct pxa27x_request *req, int status, 660 unsigned long *pflags) 661 { 662 unsigned long flags; 663 664 ep_del_request(ep, req); 665 if (likely(req->req.status == -EINPROGRESS)) 666 req->req.status = status; 667 else 668 status = req->req.status; 669 670 if (status && status != -ESHUTDOWN) 671 ep_dbg(ep, "complete req %p stat %d len %u/%u\n", 672 &req->req, status, 673 req->req.actual, req->req.length); 674 675 if (pflags) 676 spin_unlock_irqrestore(&ep->lock, *pflags); 677 local_irq_save(flags); 678 usb_gadget_giveback_request(&req->udc_usb_ep->usb_ep, &req->req); 679 local_irq_restore(flags); 680 if (pflags) 681 spin_lock_irqsave(&ep->lock, *pflags); 682 } 683 684 /** 685 * ep_end_out_req - Ends endpoint OUT request 686 * @ep: physical endpoint 687 * @req: pxa request 688 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 689 * 690 * Context: ep->lock held or released (see req_done()) 691 * 692 * Ends endpoint OUT request (completes usb request). 693 */ 694 static void ep_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req, 695 unsigned long *pflags) 696 { 697 inc_ep_stats_reqs(ep, !USB_DIR_IN); 698 req_done(ep, req, 0, pflags); 699 } 700 701 /** 702 * ep0_end_out_req - Ends control endpoint OUT request (ends data stage) 703 * @ep: physical endpoint 704 * @req: pxa request 705 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 706 * 707 * Context: ep->lock held or released (see req_done()) 708 * 709 * Ends control endpoint OUT request (completes usb request), and puts 710 * control endpoint into idle state 711 */ 712 static void ep0_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req, 713 unsigned long *pflags) 714 { 715 set_ep0state(ep->dev, OUT_STATUS_STAGE); 716 ep_end_out_req(ep, req, pflags); 717 ep0_idle(ep->dev); 718 } 719 720 /** 721 * ep_end_in_req - Ends endpoint IN request 722 * @ep: physical endpoint 723 * @req: pxa request 724 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 725 * 726 * Context: ep->lock held or released (see req_done()) 727 * 728 * Ends endpoint IN request (completes usb request). 729 */ 730 static void ep_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req, 731 unsigned long *pflags) 732 { 733 inc_ep_stats_reqs(ep, USB_DIR_IN); 734 req_done(ep, req, 0, pflags); 735 } 736 737 /** 738 * ep0_end_in_req - Ends control endpoint IN request (ends data stage) 739 * @ep: physical endpoint 740 * @req: pxa request 741 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 742 * 743 * Context: ep->lock held or released (see req_done()) 744 * 745 * Ends control endpoint IN request (completes usb request), and puts 746 * control endpoint into status state 747 */ 748 static void ep0_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req, 749 unsigned long *pflags) 750 { 751 set_ep0state(ep->dev, IN_STATUS_STAGE); 752 ep_end_in_req(ep, req, pflags); 753 } 754 755 /** 756 * nuke - Dequeue all requests 757 * @ep: pxa endpoint 758 * @status: usb request status 759 * 760 * Context: ep->lock released 761 * 762 * Dequeues all requests on an endpoint. As a side effect, interrupts will be 763 * disabled on that endpoint (because no more requests). 764 */ 765 static void nuke(struct pxa_ep *ep, int status) 766 { 767 struct pxa27x_request *req; 768 unsigned long flags; 769 770 spin_lock_irqsave(&ep->lock, flags); 771 while (!list_empty(&ep->queue)) { 772 req = list_entry(ep->queue.next, struct pxa27x_request, queue); 773 req_done(ep, req, status, &flags); 774 } 775 spin_unlock_irqrestore(&ep->lock, flags); 776 } 777 778 /** 779 * read_packet - transfer 1 packet from an OUT endpoint into request 780 * @ep: pxa physical endpoint 781 * @req: usb request 782 * 783 * Takes bytes from OUT endpoint and transfers them info the usb request. 784 * If there is less space in request than bytes received in OUT endpoint, 785 * bytes are left in the OUT endpoint. 786 * 787 * Returns how many bytes were actually transferred 788 */ 789 static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req) 790 { 791 u32 *buf; 792 int bytes_ep, bufferspace, count, i; 793 794 bytes_ep = ep_count_bytes_remain(ep); 795 bufferspace = req->req.length - req->req.actual; 796 797 buf = (u32 *)(req->req.buf + req->req.actual); 798 prefetchw(buf); 799 800 if (likely(!ep_is_empty(ep))) 801 count = min(bytes_ep, bufferspace); 802 else /* zlp */ 803 count = 0; 804 805 for (i = count; i > 0; i -= 4) 806 *buf++ = udc_ep_readl(ep, UDCDR); 807 req->req.actual += count; 808 809 ep_write_UDCCSR(ep, UDCCSR_PC); 810 811 return count; 812 } 813 814 /** 815 * write_packet - transfer 1 packet from request into an IN endpoint 816 * @ep: pxa physical endpoint 817 * @req: usb request 818 * @max: max bytes that fit into endpoint 819 * 820 * Takes bytes from usb request, and transfers them into the physical 821 * endpoint. If there are no bytes to transfer, doesn't write anything 822 * to physical endpoint. 823 * 824 * Returns how many bytes were actually transferred. 825 */ 826 static int write_packet(struct pxa_ep *ep, struct pxa27x_request *req, 827 unsigned int max) 828 { 829 int length, count, remain, i; 830 u32 *buf; 831 u8 *buf_8; 832 833 buf = (u32 *)(req->req.buf + req->req.actual); 834 prefetch(buf); 835 836 length = min(req->req.length - req->req.actual, max); 837 req->req.actual += length; 838 839 remain = length & 0x3; 840 count = length & ~(0x3); 841 for (i = count; i > 0 ; i -= 4) 842 udc_ep_writel(ep, UDCDR, *buf++); 843 844 buf_8 = (u8 *)buf; 845 for (i = remain; i > 0; i--) 846 udc_ep_writeb(ep, UDCDR, *buf_8++); 847 848 ep_vdbg(ep, "length=%d+%d, udccsr=0x%03x\n", count, remain, 849 udc_ep_readl(ep, UDCCSR)); 850 851 return length; 852 } 853 854 /** 855 * read_fifo - Transfer packets from OUT endpoint into usb request 856 * @ep: pxa physical endpoint 857 * @req: usb request 858 * 859 * Context: interrupt handler 860 * 861 * Unload as many packets as possible from the fifo we use for usb OUT 862 * transfers and put them into the request. Caller should have made sure 863 * there's at least one packet ready. 864 * Doesn't complete the request, that's the caller's job 865 * 866 * Returns 1 if the request completed, 0 otherwise 867 */ 868 static int read_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 869 { 870 int count, is_short, completed = 0; 871 872 while (epout_has_pkt(ep)) { 873 count = read_packet(ep, req); 874 inc_ep_stats_bytes(ep, count, !USB_DIR_IN); 875 876 is_short = (count < ep->fifo_size); 877 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", 878 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", 879 &req->req, req->req.actual, req->req.length); 880 881 /* completion */ 882 if (is_short || req->req.actual == req->req.length) { 883 completed = 1; 884 break; 885 } 886 /* finished that packet. the next one may be waiting... */ 887 } 888 return completed; 889 } 890 891 /** 892 * write_fifo - transfer packets from usb request into an IN endpoint 893 * @ep: pxa physical endpoint 894 * @req: pxa usb request 895 * 896 * Write to an IN endpoint fifo, as many packets as possible. 897 * irqs will use this to write the rest later. 898 * caller guarantees at least one packet buffer is ready (or a zlp). 899 * Doesn't complete the request, that's the caller's job 900 * 901 * Returns 1 if request fully transferred, 0 if partial transfer 902 */ 903 static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 904 { 905 unsigned max; 906 int count, is_short, is_last = 0, completed = 0, totcount = 0; 907 u32 udccsr; 908 909 max = ep->fifo_size; 910 do { 911 udccsr = udc_ep_readl(ep, UDCCSR); 912 if (udccsr & UDCCSR_PC) { 913 ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n", 914 udccsr); 915 ep_write_UDCCSR(ep, UDCCSR_PC); 916 } 917 if (udccsr & UDCCSR_TRN) { 918 ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n", 919 udccsr); 920 ep_write_UDCCSR(ep, UDCCSR_TRN); 921 } 922 923 count = write_packet(ep, req, max); 924 inc_ep_stats_bytes(ep, count, USB_DIR_IN); 925 totcount += count; 926 927 /* last packet is usually short (or a zlp) */ 928 if (unlikely(count < max)) { 929 is_last = 1; 930 is_short = 1; 931 } else { 932 if (likely(req->req.length > req->req.actual) 933 || req->req.zero) 934 is_last = 0; 935 else 936 is_last = 1; 937 /* interrupt/iso maxpacket may not fill the fifo */ 938 is_short = unlikely(max < ep->fifo_size); 939 } 940 941 if (is_short) 942 ep_write_UDCCSR(ep, UDCCSR_SP); 943 944 /* requests complete when all IN data is in the FIFO */ 945 if (is_last) { 946 completed = 1; 947 break; 948 } 949 } while (!ep_is_full(ep)); 950 951 ep_dbg(ep, "wrote count:%d bytes%s%s, left:%d req=%p\n", 952 totcount, is_last ? "/L" : "", is_short ? "/S" : "", 953 req->req.length - req->req.actual, &req->req); 954 955 return completed; 956 } 957 958 /** 959 * read_ep0_fifo - Transfer packets from control endpoint into usb request 960 * @ep: control endpoint 961 * @req: pxa usb request 962 * 963 * Special ep0 version of the above read_fifo. Reads as many bytes from control 964 * endpoint as can be read, and stores them into usb request (limited by request 965 * maximum length). 966 * 967 * Returns 0 if usb request only partially filled, 1 if fully filled 968 */ 969 static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 970 { 971 int count, is_short, completed = 0; 972 973 while (epout_has_pkt(ep)) { 974 count = read_packet(ep, req); 975 ep_write_UDCCSR(ep, UDCCSR0_OPC); 976 inc_ep_stats_bytes(ep, count, !USB_DIR_IN); 977 978 is_short = (count < ep->fifo_size); 979 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", 980 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", 981 &req->req, req->req.actual, req->req.length); 982 983 if (is_short || req->req.actual >= req->req.length) { 984 completed = 1; 985 break; 986 } 987 } 988 989 return completed; 990 } 991 992 /** 993 * write_ep0_fifo - Send a request to control endpoint (ep0 in) 994 * @ep: control endpoint 995 * @req: request 996 * 997 * Context: interrupt handler 998 * 999 * Sends a request (or a part of the request) to the control endpoint (ep0 in). 1000 * If the request doesn't fit, the remaining part will be sent from irq. 1001 * The request is considered fully written only if either : 1002 * - last write transferred all remaining bytes, but fifo was not fully filled 1003 * - last write was a 0 length write 1004 * 1005 * Returns 1 if request fully written, 0 if request only partially sent 1006 */ 1007 static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 1008 { 1009 unsigned count; 1010 int is_last, is_short; 1011 1012 count = write_packet(ep, req, EP0_FIFO_SIZE); 1013 inc_ep_stats_bytes(ep, count, USB_DIR_IN); 1014 1015 is_short = (count < EP0_FIFO_SIZE); 1016 is_last = ((count == 0) || (count < EP0_FIFO_SIZE)); 1017 1018 /* Sends either a short packet or a 0 length packet */ 1019 if (unlikely(is_short)) 1020 ep_write_UDCCSR(ep, UDCCSR0_IPR); 1021 1022 ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n", 1023 count, is_short ? "/S" : "", is_last ? "/L" : "", 1024 req->req.length - req->req.actual, 1025 &req->req, udc_ep_readl(ep, UDCCSR)); 1026 1027 return is_last; 1028 } 1029 1030 /** 1031 * pxa_ep_queue - Queue a request into an IN endpoint 1032 * @_ep: usb endpoint 1033 * @_req: usb request 1034 * @gfp_flags: flags 1035 * 1036 * Context: thread context or from the interrupt handler in the 1037 * special case of ep0 setup : 1038 * (irq->handle_ep0_ctrl_req->gadget_setup->pxa_ep_queue) 1039 * 1040 * Returns 0 if succedeed, error otherwise 1041 */ 1042 static int pxa_ep_queue(struct usb_ep *_ep, struct usb_request *_req, 1043 gfp_t gfp_flags) 1044 { 1045 struct udc_usb_ep *udc_usb_ep; 1046 struct pxa_ep *ep; 1047 struct pxa27x_request *req; 1048 struct pxa_udc *dev; 1049 unsigned long flags; 1050 int rc = 0; 1051 int is_first_req; 1052 unsigned length; 1053 int recursion_detected; 1054 1055 req = container_of(_req, struct pxa27x_request, req); 1056 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1057 1058 if (unlikely(!_req || !_req->complete || !_req->buf)) 1059 return -EINVAL; 1060 1061 if (unlikely(!_ep)) 1062 return -EINVAL; 1063 1064 ep = udc_usb_ep->pxa_ep; 1065 if (unlikely(!ep)) 1066 return -EINVAL; 1067 1068 dev = ep->dev; 1069 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 1070 ep_dbg(ep, "bogus device state\n"); 1071 return -ESHUTDOWN; 1072 } 1073 1074 /* iso is always one packet per request, that's the only way 1075 * we can report per-packet status. that also helps with dma. 1076 */ 1077 if (unlikely(EPXFERTYPE_is_ISO(ep) 1078 && req->req.length > ep->fifo_size)) 1079 return -EMSGSIZE; 1080 1081 spin_lock_irqsave(&ep->lock, flags); 1082 recursion_detected = ep->in_handle_ep; 1083 1084 is_first_req = list_empty(&ep->queue); 1085 ep_dbg(ep, "queue req %p(first=%s), len %d buf %p\n", 1086 _req, is_first_req ? "yes" : "no", 1087 _req->length, _req->buf); 1088 1089 if (!ep->enabled) { 1090 _req->status = -ESHUTDOWN; 1091 rc = -ESHUTDOWN; 1092 goto out_locked; 1093 } 1094 1095 if (req->in_use) { 1096 ep_err(ep, "refusing to queue req %p (already queued)\n", req); 1097 goto out_locked; 1098 } 1099 1100 length = _req->length; 1101 _req->status = -EINPROGRESS; 1102 _req->actual = 0; 1103 1104 ep_add_request(ep, req); 1105 spin_unlock_irqrestore(&ep->lock, flags); 1106 1107 if (is_ep0(ep)) { 1108 switch (dev->ep0state) { 1109 case WAIT_ACK_SET_CONF_INTERF: 1110 if (length == 0) { 1111 ep_end_in_req(ep, req, NULL); 1112 } else { 1113 ep_err(ep, "got a request of %d bytes while" 1114 "in state WAIT_ACK_SET_CONF_INTERF\n", 1115 length); 1116 ep_del_request(ep, req); 1117 rc = -EL2HLT; 1118 } 1119 ep0_idle(ep->dev); 1120 break; 1121 case IN_DATA_STAGE: 1122 if (!ep_is_full(ep)) 1123 if (write_ep0_fifo(ep, req)) 1124 ep0_end_in_req(ep, req, NULL); 1125 break; 1126 case OUT_DATA_STAGE: 1127 if ((length == 0) || !epout_has_pkt(ep)) 1128 if (read_ep0_fifo(ep, req)) 1129 ep0_end_out_req(ep, req, NULL); 1130 break; 1131 default: 1132 ep_err(ep, "odd state %s to send me a request\n", 1133 EP0_STNAME(ep->dev)); 1134 ep_del_request(ep, req); 1135 rc = -EL2HLT; 1136 break; 1137 } 1138 } else { 1139 if (!recursion_detected) 1140 handle_ep(ep); 1141 } 1142 1143 out: 1144 return rc; 1145 out_locked: 1146 spin_unlock_irqrestore(&ep->lock, flags); 1147 goto out; 1148 } 1149 1150 /** 1151 * pxa_ep_dequeue - Dequeue one request 1152 * @_ep: usb endpoint 1153 * @_req: usb request 1154 * 1155 * Return 0 if no error, -EINVAL or -ECONNRESET otherwise 1156 */ 1157 static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1158 { 1159 struct pxa_ep *ep; 1160 struct udc_usb_ep *udc_usb_ep; 1161 struct pxa27x_request *req = NULL, *iter; 1162 unsigned long flags; 1163 int rc = -EINVAL; 1164 1165 if (!_ep) 1166 return rc; 1167 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1168 ep = udc_usb_ep->pxa_ep; 1169 if (!ep || is_ep0(ep)) 1170 return rc; 1171 1172 spin_lock_irqsave(&ep->lock, flags); 1173 1174 /* make sure it's actually queued on this endpoint */ 1175 list_for_each_entry(iter, &ep->queue, queue) { 1176 if (&iter->req != _req) 1177 continue; 1178 req = iter; 1179 rc = 0; 1180 break; 1181 } 1182 1183 spin_unlock_irqrestore(&ep->lock, flags); 1184 if (!rc) 1185 req_done(ep, req, -ECONNRESET, NULL); 1186 return rc; 1187 } 1188 1189 /** 1190 * pxa_ep_set_halt - Halts operations on one endpoint 1191 * @_ep: usb endpoint 1192 * @value: 1193 * 1194 * Returns 0 if no error, -EINVAL, -EROFS, -EAGAIN otherwise 1195 */ 1196 static int pxa_ep_set_halt(struct usb_ep *_ep, int value) 1197 { 1198 struct pxa_ep *ep; 1199 struct udc_usb_ep *udc_usb_ep; 1200 unsigned long flags; 1201 int rc; 1202 1203 1204 if (!_ep) 1205 return -EINVAL; 1206 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1207 ep = udc_usb_ep->pxa_ep; 1208 if (!ep || is_ep0(ep)) 1209 return -EINVAL; 1210 1211 if (value == 0) { 1212 /* 1213 * This path (reset toggle+halt) is needed to implement 1214 * SET_INTERFACE on normal hardware. but it can't be 1215 * done from software on the PXA UDC, and the hardware 1216 * forgets to do it as part of SET_INTERFACE automagic. 1217 */ 1218 ep_dbg(ep, "only host can clear halt\n"); 1219 return -EROFS; 1220 } 1221 1222 spin_lock_irqsave(&ep->lock, flags); 1223 1224 rc = -EAGAIN; 1225 if (ep->dir_in && (ep_is_full(ep) || !list_empty(&ep->queue))) 1226 goto out; 1227 1228 /* FST, FEF bits are the same for control and non control endpoints */ 1229 rc = 0; 1230 ep_write_UDCCSR(ep, UDCCSR_FST | UDCCSR_FEF); 1231 if (is_ep0(ep)) 1232 set_ep0state(ep->dev, STALL); 1233 1234 out: 1235 spin_unlock_irqrestore(&ep->lock, flags); 1236 return rc; 1237 } 1238 1239 /** 1240 * pxa_ep_fifo_status - Get how many bytes in physical endpoint 1241 * @_ep: usb endpoint 1242 * 1243 * Returns number of bytes in OUT fifos. Broken for IN fifos. 1244 */ 1245 static int pxa_ep_fifo_status(struct usb_ep *_ep) 1246 { 1247 struct pxa_ep *ep; 1248 struct udc_usb_ep *udc_usb_ep; 1249 1250 if (!_ep) 1251 return -ENODEV; 1252 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1253 ep = udc_usb_ep->pxa_ep; 1254 if (!ep || is_ep0(ep)) 1255 return -ENODEV; 1256 1257 if (ep->dir_in) 1258 return -EOPNOTSUPP; 1259 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN || ep_is_empty(ep)) 1260 return 0; 1261 else 1262 return ep_count_bytes_remain(ep) + 1; 1263 } 1264 1265 /** 1266 * pxa_ep_fifo_flush - Flushes one endpoint 1267 * @_ep: usb endpoint 1268 * 1269 * Discards all data in one endpoint(IN or OUT), except control endpoint. 1270 */ 1271 static void pxa_ep_fifo_flush(struct usb_ep *_ep) 1272 { 1273 struct pxa_ep *ep; 1274 struct udc_usb_ep *udc_usb_ep; 1275 unsigned long flags; 1276 1277 if (!_ep) 1278 return; 1279 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1280 ep = udc_usb_ep->pxa_ep; 1281 if (!ep || is_ep0(ep)) 1282 return; 1283 1284 spin_lock_irqsave(&ep->lock, flags); 1285 1286 if (unlikely(!list_empty(&ep->queue))) 1287 ep_dbg(ep, "called while queue list not empty\n"); 1288 ep_dbg(ep, "called\n"); 1289 1290 /* for OUT, just read and discard the FIFO contents. */ 1291 if (!ep->dir_in) { 1292 while (!ep_is_empty(ep)) 1293 udc_ep_readl(ep, UDCDR); 1294 } else { 1295 /* most IN status is the same, but ISO can't stall */ 1296 ep_write_UDCCSR(ep, 1297 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN 1298 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST)); 1299 } 1300 1301 spin_unlock_irqrestore(&ep->lock, flags); 1302 } 1303 1304 /** 1305 * pxa_ep_enable - Enables usb endpoint 1306 * @_ep: usb endpoint 1307 * @desc: usb endpoint descriptor 1308 * 1309 * Nothing much to do here, as ep configuration is done once and for all 1310 * before udc is enabled. After udc enable, no physical endpoint configuration 1311 * can be changed. 1312 * Function makes sanity checks and flushes the endpoint. 1313 */ 1314 static int pxa_ep_enable(struct usb_ep *_ep, 1315 const struct usb_endpoint_descriptor *desc) 1316 { 1317 struct pxa_ep *ep; 1318 struct udc_usb_ep *udc_usb_ep; 1319 struct pxa_udc *udc; 1320 1321 if (!_ep || !desc) 1322 return -EINVAL; 1323 1324 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1325 if (udc_usb_ep->pxa_ep) { 1326 ep = udc_usb_ep->pxa_ep; 1327 ep_warn(ep, "usb_ep %s already enabled, doing nothing\n", 1328 _ep->name); 1329 } else { 1330 ep = find_pxa_ep(udc_usb_ep->dev, udc_usb_ep); 1331 } 1332 1333 if (!ep || is_ep0(ep)) { 1334 dev_err(udc_usb_ep->dev->dev, 1335 "unable to match pxa_ep for ep %s\n", 1336 _ep->name); 1337 return -EINVAL; 1338 } 1339 1340 if ((desc->bDescriptorType != USB_DT_ENDPOINT) 1341 || (ep->type != usb_endpoint_type(desc))) { 1342 ep_err(ep, "type mismatch\n"); 1343 return -EINVAL; 1344 } 1345 1346 if (ep->fifo_size < usb_endpoint_maxp(desc)) { 1347 ep_err(ep, "bad maxpacket\n"); 1348 return -ERANGE; 1349 } 1350 1351 udc_usb_ep->pxa_ep = ep; 1352 udc = ep->dev; 1353 1354 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1355 ep_err(ep, "bogus device state\n"); 1356 return -ESHUTDOWN; 1357 } 1358 1359 ep->enabled = 1; 1360 1361 /* flush fifo (mostly for OUT buffers) */ 1362 pxa_ep_fifo_flush(_ep); 1363 1364 ep_dbg(ep, "enabled\n"); 1365 return 0; 1366 } 1367 1368 /** 1369 * pxa_ep_disable - Disable usb endpoint 1370 * @_ep: usb endpoint 1371 * 1372 * Same as for pxa_ep_enable, no physical endpoint configuration can be 1373 * changed. 1374 * Function flushes the endpoint and related requests. 1375 */ 1376 static int pxa_ep_disable(struct usb_ep *_ep) 1377 { 1378 struct pxa_ep *ep; 1379 struct udc_usb_ep *udc_usb_ep; 1380 1381 if (!_ep) 1382 return -EINVAL; 1383 1384 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1385 ep = udc_usb_ep->pxa_ep; 1386 if (!ep || is_ep0(ep) || !list_empty(&ep->queue)) 1387 return -EINVAL; 1388 1389 ep->enabled = 0; 1390 nuke(ep, -ESHUTDOWN); 1391 1392 pxa_ep_fifo_flush(_ep); 1393 udc_usb_ep->pxa_ep = NULL; 1394 1395 ep_dbg(ep, "disabled\n"); 1396 return 0; 1397 } 1398 1399 static const struct usb_ep_ops pxa_ep_ops = { 1400 .enable = pxa_ep_enable, 1401 .disable = pxa_ep_disable, 1402 1403 .alloc_request = pxa_ep_alloc_request, 1404 .free_request = pxa_ep_free_request, 1405 1406 .queue = pxa_ep_queue, 1407 .dequeue = pxa_ep_dequeue, 1408 1409 .set_halt = pxa_ep_set_halt, 1410 .fifo_status = pxa_ep_fifo_status, 1411 .fifo_flush = pxa_ep_fifo_flush, 1412 }; 1413 1414 /** 1415 * dplus_pullup - Connect or disconnect pullup resistor to D+ pin 1416 * @udc: udc device 1417 * @on: 0 if disconnect pullup resistor, 1 otherwise 1418 * Context: any 1419 * 1420 * Handle D+ pullup resistor, make the device visible to the usb bus, and 1421 * declare it as a full speed usb device 1422 */ 1423 static void dplus_pullup(struct pxa_udc *udc, int on) 1424 { 1425 if (udc->gpiod) { 1426 gpiod_set_value(udc->gpiod, on); 1427 } else if (udc->udc_command) { 1428 if (on) 1429 udc->udc_command(PXA2XX_UDC_CMD_CONNECT); 1430 else 1431 udc->udc_command(PXA2XX_UDC_CMD_DISCONNECT); 1432 } 1433 udc->pullup_on = on; 1434 } 1435 1436 /** 1437 * pxa_udc_get_frame - Returns usb frame number 1438 * @_gadget: usb gadget 1439 */ 1440 static int pxa_udc_get_frame(struct usb_gadget *_gadget) 1441 { 1442 struct pxa_udc *udc = to_gadget_udc(_gadget); 1443 1444 return (udc_readl(udc, UDCFNR) & 0x7ff); 1445 } 1446 1447 /** 1448 * pxa_udc_wakeup - Force udc device out of suspend 1449 * @_gadget: usb gadget 1450 * 1451 * Returns 0 if successful, error code otherwise 1452 */ 1453 static int pxa_udc_wakeup(struct usb_gadget *_gadget) 1454 { 1455 struct pxa_udc *udc = to_gadget_udc(_gadget); 1456 1457 /* host may not have enabled remote wakeup */ 1458 if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0) 1459 return -EHOSTUNREACH; 1460 udc_set_mask_UDCCR(udc, UDCCR_UDR); 1461 return 0; 1462 } 1463 1464 static void udc_enable(struct pxa_udc *udc); 1465 static void udc_disable(struct pxa_udc *udc); 1466 1467 /** 1468 * should_enable_udc - Tells if UDC should be enabled 1469 * @udc: udc device 1470 * Context: any 1471 * 1472 * The UDC should be enabled if : 1473 * - the pullup resistor is connected 1474 * - and a gadget driver is bound 1475 * - and vbus is sensed (or no vbus sense is available) 1476 * 1477 * Returns 1 if UDC should be enabled, 0 otherwise 1478 */ 1479 static int should_enable_udc(struct pxa_udc *udc) 1480 { 1481 int put_on; 1482 1483 put_on = ((udc->pullup_on) && (udc->driver)); 1484 put_on &= ((udc->vbus_sensed) || (IS_ERR_OR_NULL(udc->transceiver))); 1485 return put_on; 1486 } 1487 1488 /** 1489 * should_disable_udc - Tells if UDC should be disabled 1490 * @udc: udc device 1491 * Context: any 1492 * 1493 * The UDC should be disabled if : 1494 * - the pullup resistor is not connected 1495 * - or no gadget driver is bound 1496 * - or no vbus is sensed (when vbus sesing is available) 1497 * 1498 * Returns 1 if UDC should be disabled 1499 */ 1500 static int should_disable_udc(struct pxa_udc *udc) 1501 { 1502 int put_off; 1503 1504 put_off = ((!udc->pullup_on) || (!udc->driver)); 1505 put_off |= ((!udc->vbus_sensed) && (!IS_ERR_OR_NULL(udc->transceiver))); 1506 return put_off; 1507 } 1508 1509 /** 1510 * pxa_udc_pullup - Offer manual D+ pullup control 1511 * @_gadget: usb gadget using the control 1512 * @is_active: 0 if disconnect, else connect D+ pullup resistor 1513 * 1514 * Context: task context, might sleep 1515 * 1516 * Returns 0 if OK, -EOPNOTSUPP if udc driver doesn't handle D+ pullup 1517 */ 1518 static int pxa_udc_pullup(struct usb_gadget *_gadget, int is_active) 1519 { 1520 struct pxa_udc *udc = to_gadget_udc(_gadget); 1521 1522 if (!udc->gpiod && !udc->udc_command) 1523 return -EOPNOTSUPP; 1524 1525 dplus_pullup(udc, is_active); 1526 1527 if (should_enable_udc(udc)) 1528 udc_enable(udc); 1529 if (should_disable_udc(udc)) 1530 udc_disable(udc); 1531 return 0; 1532 } 1533 1534 /** 1535 * pxa_udc_vbus_session - Called by external transceiver to enable/disable udc 1536 * @_gadget: usb gadget 1537 * @is_active: 0 if should disable the udc, 1 if should enable 1538 * 1539 * Enables the udc, and optionnaly activates D+ pullup resistor. Or disables the 1540 * udc, and deactivates D+ pullup resistor. 1541 * 1542 * Returns 0 1543 */ 1544 static int pxa_udc_vbus_session(struct usb_gadget *_gadget, int is_active) 1545 { 1546 struct pxa_udc *udc = to_gadget_udc(_gadget); 1547 1548 udc->vbus_sensed = is_active; 1549 if (should_enable_udc(udc)) 1550 udc_enable(udc); 1551 if (should_disable_udc(udc)) 1552 udc_disable(udc); 1553 1554 return 0; 1555 } 1556 1557 /** 1558 * pxa_udc_vbus_draw - Called by gadget driver after SET_CONFIGURATION completed 1559 * @_gadget: usb gadget 1560 * @mA: current drawn 1561 * 1562 * Context: task context, might sleep 1563 * 1564 * Called after a configuration was chosen by a USB host, to inform how much 1565 * current can be drawn by the device from VBus line. 1566 * 1567 * Returns 0 or -EOPNOTSUPP if no transceiver is handling the udc 1568 */ 1569 static int pxa_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) 1570 { 1571 struct pxa_udc *udc; 1572 1573 udc = to_gadget_udc(_gadget); 1574 if (!IS_ERR_OR_NULL(udc->transceiver)) 1575 return usb_phy_set_power(udc->transceiver, mA); 1576 return -EOPNOTSUPP; 1577 } 1578 1579 /** 1580 * pxa_udc_phy_event - Called by phy upon VBus event 1581 * @nb: notifier block 1582 * @action: phy action, is vbus connect or disconnect 1583 * @data: the usb_gadget structure in pxa_udc 1584 * 1585 * Called by the USB Phy when a cable connect or disconnect is sensed. 1586 * 1587 * Returns 0 1588 */ 1589 static int pxa_udc_phy_event(struct notifier_block *nb, unsigned long action, 1590 void *data) 1591 { 1592 struct usb_gadget *gadget = data; 1593 1594 switch (action) { 1595 case USB_EVENT_VBUS: 1596 usb_gadget_vbus_connect(gadget); 1597 return NOTIFY_OK; 1598 case USB_EVENT_NONE: 1599 usb_gadget_vbus_disconnect(gadget); 1600 return NOTIFY_OK; 1601 default: 1602 return NOTIFY_DONE; 1603 } 1604 } 1605 1606 static struct notifier_block pxa27x_udc_phy = { 1607 .notifier_call = pxa_udc_phy_event, 1608 }; 1609 1610 static int pxa27x_udc_start(struct usb_gadget *g, 1611 struct usb_gadget_driver *driver); 1612 static int pxa27x_udc_stop(struct usb_gadget *g); 1613 1614 static const struct usb_gadget_ops pxa_udc_ops = { 1615 .get_frame = pxa_udc_get_frame, 1616 .wakeup = pxa_udc_wakeup, 1617 .pullup = pxa_udc_pullup, 1618 .vbus_session = pxa_udc_vbus_session, 1619 .vbus_draw = pxa_udc_vbus_draw, 1620 .udc_start = pxa27x_udc_start, 1621 .udc_stop = pxa27x_udc_stop, 1622 }; 1623 1624 /** 1625 * udc_disable - disable udc device controller 1626 * @udc: udc device 1627 * Context: any 1628 * 1629 * Disables the udc device : disables clocks, udc interrupts, control endpoint 1630 * interrupts. 1631 */ 1632 static void udc_disable(struct pxa_udc *udc) 1633 { 1634 if (!udc->enabled) 1635 return; 1636 1637 udc_writel(udc, UDCICR0, 0); 1638 udc_writel(udc, UDCICR1, 0); 1639 1640 udc_clear_mask_UDCCR(udc, UDCCR_UDE); 1641 1642 ep0_idle(udc); 1643 udc->gadget.speed = USB_SPEED_UNKNOWN; 1644 clk_disable(udc->clk); 1645 1646 udc->enabled = 0; 1647 } 1648 1649 /** 1650 * udc_init_data - Initialize udc device data structures 1651 * @dev: udc device 1652 * 1653 * Initializes gadget endpoint list, endpoints locks. No action is taken 1654 * on the hardware. 1655 */ 1656 static void udc_init_data(struct pxa_udc *dev) 1657 { 1658 int i; 1659 struct pxa_ep *ep; 1660 1661 /* device/ep0 records init */ 1662 INIT_LIST_HEAD(&dev->gadget.ep_list); 1663 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 1664 dev->udc_usb_ep[0].pxa_ep = &dev->pxa_ep[0]; 1665 dev->gadget.quirk_altset_not_supp = 1; 1666 ep0_idle(dev); 1667 1668 /* PXA endpoints init */ 1669 for (i = 0; i < NR_PXA_ENDPOINTS; i++) { 1670 ep = &dev->pxa_ep[i]; 1671 1672 ep->enabled = is_ep0(ep); 1673 INIT_LIST_HEAD(&ep->queue); 1674 spin_lock_init(&ep->lock); 1675 } 1676 1677 /* USB endpoints init */ 1678 for (i = 1; i < NR_USB_ENDPOINTS; i++) { 1679 list_add_tail(&dev->udc_usb_ep[i].usb_ep.ep_list, 1680 &dev->gadget.ep_list); 1681 usb_ep_set_maxpacket_limit(&dev->udc_usb_ep[i].usb_ep, 1682 dev->udc_usb_ep[i].usb_ep.maxpacket); 1683 } 1684 } 1685 1686 /** 1687 * udc_enable - Enables the udc device 1688 * @udc: udc device 1689 * 1690 * Enables the udc device : enables clocks, udc interrupts, control endpoint 1691 * interrupts, sets usb as UDC client and setups endpoints. 1692 */ 1693 static void udc_enable(struct pxa_udc *udc) 1694 { 1695 if (udc->enabled) 1696 return; 1697 1698 clk_enable(udc->clk); 1699 udc_writel(udc, UDCICR0, 0); 1700 udc_writel(udc, UDCICR1, 0); 1701 udc_clear_mask_UDCCR(udc, UDCCR_UDE); 1702 1703 ep0_idle(udc); 1704 udc->gadget.speed = USB_SPEED_FULL; 1705 memset(&udc->stats, 0, sizeof(udc->stats)); 1706 1707 pxa_eps_setup(udc); 1708 udc_set_mask_UDCCR(udc, UDCCR_UDE); 1709 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_ACM); 1710 udelay(2); 1711 if (udc_readl(udc, UDCCR) & UDCCR_EMCE) 1712 dev_err(udc->dev, "Configuration errors, udc disabled\n"); 1713 1714 /* 1715 * Caller must be able to sleep in order to cope with startup transients 1716 */ 1717 msleep(100); 1718 1719 /* enable suspend/resume and reset irqs */ 1720 udc_writel(udc, UDCICR1, 1721 UDCICR1_IECC | UDCICR1_IERU 1722 | UDCICR1_IESU | UDCICR1_IERS); 1723 1724 /* enable ep0 irqs */ 1725 pio_irq_enable(&udc->pxa_ep[0]); 1726 1727 udc->enabled = 1; 1728 } 1729 1730 /** 1731 * pxa27x_udc_start - Register gadget driver 1732 * @g: gadget 1733 * @driver: gadget driver 1734 * 1735 * When a driver is successfully registered, it will receive control requests 1736 * including set_configuration(), which enables non-control requests. Then 1737 * usb traffic follows until a disconnect is reported. Then a host may connect 1738 * again, or the driver might get unbound. 1739 * 1740 * Note that the udc is not automatically enabled. Check function 1741 * should_enable_udc(). 1742 * 1743 * Returns 0 if no error, -EINVAL, -ENODEV, -EBUSY otherwise 1744 */ 1745 static int pxa27x_udc_start(struct usb_gadget *g, 1746 struct usb_gadget_driver *driver) 1747 { 1748 struct pxa_udc *udc = to_pxa(g); 1749 int retval; 1750 1751 /* first hook up the driver ... */ 1752 udc->driver = driver; 1753 1754 if (!IS_ERR_OR_NULL(udc->transceiver)) { 1755 retval = otg_set_peripheral(udc->transceiver->otg, 1756 &udc->gadget); 1757 if (retval) { 1758 dev_err(udc->dev, "can't bind to transceiver\n"); 1759 goto fail; 1760 } 1761 } 1762 1763 if (should_enable_udc(udc)) 1764 udc_enable(udc); 1765 return 0; 1766 1767 fail: 1768 udc->driver = NULL; 1769 return retval; 1770 } 1771 1772 /** 1773 * stop_activity - Stops udc endpoints 1774 * @udc: udc device 1775 * 1776 * Disables all udc endpoints (even control endpoint), report disconnect to 1777 * the gadget user. 1778 */ 1779 static void stop_activity(struct pxa_udc *udc) 1780 { 1781 int i; 1782 1783 udc->gadget.speed = USB_SPEED_UNKNOWN; 1784 1785 for (i = 0; i < NR_USB_ENDPOINTS; i++) 1786 pxa_ep_disable(&udc->udc_usb_ep[i].usb_ep); 1787 } 1788 1789 /** 1790 * pxa27x_udc_stop - Unregister the gadget driver 1791 * @g: gadget 1792 * 1793 * Returns 0 if no error, -ENODEV, -EINVAL otherwise 1794 */ 1795 static int pxa27x_udc_stop(struct usb_gadget *g) 1796 { 1797 struct pxa_udc *udc = to_pxa(g); 1798 1799 stop_activity(udc); 1800 udc_disable(udc); 1801 1802 udc->driver = NULL; 1803 1804 if (!IS_ERR_OR_NULL(udc->transceiver)) 1805 return otg_set_peripheral(udc->transceiver->otg, NULL); 1806 return 0; 1807 } 1808 1809 /** 1810 * handle_ep0_ctrl_req - handle control endpoint control request 1811 * @udc: udc device 1812 * @req: control request 1813 */ 1814 static void handle_ep0_ctrl_req(struct pxa_udc *udc, 1815 struct pxa27x_request *req) 1816 { 1817 struct pxa_ep *ep = &udc->pxa_ep[0]; 1818 union { 1819 struct usb_ctrlrequest r; 1820 u32 word[2]; 1821 } u; 1822 int i; 1823 int have_extrabytes = 0; 1824 unsigned long flags; 1825 1826 nuke(ep, -EPROTO); 1827 spin_lock_irqsave(&ep->lock, flags); 1828 1829 /* 1830 * In the PXA320 manual, in the section about Back-to-Back setup 1831 * packets, it describes this situation. The solution is to set OPC to 1832 * get rid of the status packet, and then continue with the setup 1833 * packet. Generalize to pxa27x CPUs. 1834 */ 1835 if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0)) 1836 ep_write_UDCCSR(ep, UDCCSR0_OPC); 1837 1838 /* read SETUP packet */ 1839 for (i = 0; i < 2; i++) { 1840 if (unlikely(ep_is_empty(ep))) 1841 goto stall; 1842 u.word[i] = udc_ep_readl(ep, UDCDR); 1843 } 1844 1845 have_extrabytes = !ep_is_empty(ep); 1846 while (!ep_is_empty(ep)) { 1847 i = udc_ep_readl(ep, UDCDR); 1848 ep_err(ep, "wrong to have extra bytes for setup : 0x%08x\n", i); 1849 } 1850 1851 ep_dbg(ep, "SETUP %02x.%02x v%04x i%04x l%04x\n", 1852 u.r.bRequestType, u.r.bRequest, 1853 le16_to_cpu(u.r.wValue), le16_to_cpu(u.r.wIndex), 1854 le16_to_cpu(u.r.wLength)); 1855 if (unlikely(have_extrabytes)) 1856 goto stall; 1857 1858 if (u.r.bRequestType & USB_DIR_IN) 1859 set_ep0state(udc, IN_DATA_STAGE); 1860 else 1861 set_ep0state(udc, OUT_DATA_STAGE); 1862 1863 /* Tell UDC to enter Data Stage */ 1864 ep_write_UDCCSR(ep, UDCCSR0_SA | UDCCSR0_OPC); 1865 1866 spin_unlock_irqrestore(&ep->lock, flags); 1867 i = udc->driver->setup(&udc->gadget, &u.r); 1868 spin_lock_irqsave(&ep->lock, flags); 1869 if (i < 0) 1870 goto stall; 1871 out: 1872 spin_unlock_irqrestore(&ep->lock, flags); 1873 return; 1874 stall: 1875 ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n", 1876 udc_ep_readl(ep, UDCCSR), i); 1877 ep_write_UDCCSR(ep, UDCCSR0_FST | UDCCSR0_FTF); 1878 set_ep0state(udc, STALL); 1879 goto out; 1880 } 1881 1882 /** 1883 * handle_ep0 - Handle control endpoint data transfers 1884 * @udc: udc device 1885 * @fifo_irq: 1 if triggered by fifo service type irq 1886 * @opc_irq: 1 if triggered by output packet complete type irq 1887 * 1888 * Context : interrupt handler 1889 * 1890 * Tries to transfer all pending request data into the endpoint and/or 1891 * transfer all pending data in the endpoint into usb requests. 1892 * Handles states of ep0 automata. 1893 * 1894 * PXA27x hardware handles several standard usb control requests without 1895 * driver notification. The requests fully handled by hardware are : 1896 * SET_ADDRESS, SET_FEATURE, CLEAR_FEATURE, GET_CONFIGURATION, GET_INTERFACE, 1897 * GET_STATUS 1898 * The requests handled by hardware, but with irq notification are : 1899 * SYNCH_FRAME, SET_CONFIGURATION, SET_INTERFACE 1900 * The remaining standard requests really handled by handle_ep0 are : 1901 * GET_DESCRIPTOR, SET_DESCRIPTOR, specific requests. 1902 * Requests standardized outside of USB 2.0 chapter 9 are handled more 1903 * uniformly, by gadget drivers. 1904 * 1905 * The control endpoint state machine is _not_ USB spec compliant, it's even 1906 * hardly compliant with Intel PXA270 developers guide. 1907 * The key points which inferred this state machine are : 1908 * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by 1909 * software. 1910 * - on every OUT packet received, UDCCSR0_OPC is raised and held until 1911 * cleared by software. 1912 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it 1913 * before reading ep0. 1914 * This is true only for PXA27x. This is not true anymore for PXA3xx family 1915 * (check Back-to-Back setup packet in developers guide). 1916 * - irq can be called on a "packet complete" event (opc_irq=1), while 1917 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms 1918 * from experimentation). 1919 * - as UDCCSR0_SA can be activated while in irq handling, and clearing 1920 * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC 1921 * => we never actually read the "status stage" packet of an IN data stage 1922 * => this is not documented in Intel documentation 1923 * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA 1924 * STAGE. The driver add STATUS STAGE to send last zero length packet in 1925 * OUT_STATUS_STAGE. 1926 * - special attention was needed for IN_STATUS_STAGE. If a packet complete 1927 * event is detected, we terminate the status stage without ackowledging the 1928 * packet (not to risk to loose a potential SETUP packet) 1929 */ 1930 static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq) 1931 { 1932 u32 udccsr0; 1933 struct pxa_ep *ep = &udc->pxa_ep[0]; 1934 struct pxa27x_request *req = NULL; 1935 int completed = 0; 1936 1937 if (!list_empty(&ep->queue)) 1938 req = list_entry(ep->queue.next, struct pxa27x_request, queue); 1939 1940 udccsr0 = udc_ep_readl(ep, UDCCSR); 1941 ep_dbg(ep, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n", 1942 EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, UDCBCR), 1943 (fifo_irq << 1 | opc_irq)); 1944 1945 if (udccsr0 & UDCCSR0_SST) { 1946 ep_dbg(ep, "clearing stall status\n"); 1947 nuke(ep, -EPIPE); 1948 ep_write_UDCCSR(ep, UDCCSR0_SST); 1949 ep0_idle(udc); 1950 } 1951 1952 if (udccsr0 & UDCCSR0_SA) { 1953 nuke(ep, 0); 1954 set_ep0state(udc, SETUP_STAGE); 1955 } 1956 1957 switch (udc->ep0state) { 1958 case WAIT_FOR_SETUP: 1959 /* 1960 * Hardware bug : beware, we cannot clear OPC, since we would 1961 * miss a potential OPC irq for a setup packet. 1962 * So, we only do ... nothing, and hope for a next irq with 1963 * UDCCSR0_SA set. 1964 */ 1965 break; 1966 case SETUP_STAGE: 1967 udccsr0 &= UDCCSR0_CTRL_REQ_MASK; 1968 if (likely(udccsr0 == UDCCSR0_CTRL_REQ_MASK)) 1969 handle_ep0_ctrl_req(udc, req); 1970 break; 1971 case IN_DATA_STAGE: /* GET_DESCRIPTOR */ 1972 if (epout_has_pkt(ep)) 1973 ep_write_UDCCSR(ep, UDCCSR0_OPC); 1974 if (req && !ep_is_full(ep)) 1975 completed = write_ep0_fifo(ep, req); 1976 if (completed) 1977 ep0_end_in_req(ep, req, NULL); 1978 break; 1979 case OUT_DATA_STAGE: /* SET_DESCRIPTOR */ 1980 if (epout_has_pkt(ep) && req) 1981 completed = read_ep0_fifo(ep, req); 1982 if (completed) 1983 ep0_end_out_req(ep, req, NULL); 1984 break; 1985 case STALL: 1986 ep_write_UDCCSR(ep, UDCCSR0_FST); 1987 break; 1988 case IN_STATUS_STAGE: 1989 /* 1990 * Hardware bug : beware, we cannot clear OPC, since we would 1991 * miss a potential PC irq for a setup packet. 1992 * So, we only put the ep0 into WAIT_FOR_SETUP state. 1993 */ 1994 if (opc_irq) 1995 ep0_idle(udc); 1996 break; 1997 case OUT_STATUS_STAGE: 1998 case WAIT_ACK_SET_CONF_INTERF: 1999 ep_warn(ep, "should never get in %s state here!!!\n", 2000 EP0_STNAME(ep->dev)); 2001 ep0_idle(udc); 2002 break; 2003 } 2004 } 2005 2006 /** 2007 * handle_ep - Handle endpoint data tranfers 2008 * @ep: pxa physical endpoint 2009 * 2010 * Tries to transfer all pending request data into the endpoint and/or 2011 * transfer all pending data in the endpoint into usb requests. 2012 * 2013 * Is always called from the interrupt handler. ep->lock must not be held. 2014 */ 2015 static void handle_ep(struct pxa_ep *ep) 2016 { 2017 struct pxa27x_request *req; 2018 int completed; 2019 u32 udccsr; 2020 int is_in = ep->dir_in; 2021 int loop = 0; 2022 unsigned long flags; 2023 2024 spin_lock_irqsave(&ep->lock, flags); 2025 if (ep->in_handle_ep) 2026 goto recursion_detected; 2027 ep->in_handle_ep = 1; 2028 2029 do { 2030 completed = 0; 2031 udccsr = udc_ep_readl(ep, UDCCSR); 2032 2033 if (likely(!list_empty(&ep->queue))) 2034 req = list_entry(ep->queue.next, 2035 struct pxa27x_request, queue); 2036 else 2037 req = NULL; 2038 2039 ep_dbg(ep, "req:%p, udccsr 0x%03x loop=%d\n", 2040 req, udccsr, loop++); 2041 2042 if (unlikely(udccsr & (UDCCSR_SST | UDCCSR_TRN))) 2043 udc_ep_writel(ep, UDCCSR, 2044 udccsr & (UDCCSR_SST | UDCCSR_TRN)); 2045 if (!req) 2046 break; 2047 2048 if (unlikely(is_in)) { 2049 if (likely(!ep_is_full(ep))) 2050 completed = write_fifo(ep, req); 2051 } else { 2052 if (likely(epout_has_pkt(ep))) 2053 completed = read_fifo(ep, req); 2054 } 2055 2056 if (completed) { 2057 if (is_in) 2058 ep_end_in_req(ep, req, &flags); 2059 else 2060 ep_end_out_req(ep, req, &flags); 2061 } 2062 } while (completed); 2063 2064 ep->in_handle_ep = 0; 2065 recursion_detected: 2066 spin_unlock_irqrestore(&ep->lock, flags); 2067 } 2068 2069 /** 2070 * pxa27x_change_configuration - Handle SET_CONF usb request notification 2071 * @udc: udc device 2072 * @config: usb configuration 2073 * 2074 * Post the request to upper level. 2075 * Don't use any pxa specific harware configuration capabilities 2076 */ 2077 static void pxa27x_change_configuration(struct pxa_udc *udc, int config) 2078 { 2079 struct usb_ctrlrequest req ; 2080 2081 dev_dbg(udc->dev, "config=%d\n", config); 2082 2083 udc->config = config; 2084 udc->last_interface = 0; 2085 udc->last_alternate = 0; 2086 2087 req.bRequestType = 0; 2088 req.bRequest = USB_REQ_SET_CONFIGURATION; 2089 req.wValue = config; 2090 req.wIndex = 0; 2091 req.wLength = 0; 2092 2093 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); 2094 udc->driver->setup(&udc->gadget, &req); 2095 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN); 2096 } 2097 2098 /** 2099 * pxa27x_change_interface - Handle SET_INTERF usb request notification 2100 * @udc: udc device 2101 * @iface: interface number 2102 * @alt: alternate setting number 2103 * 2104 * Post the request to upper level. 2105 * Don't use any pxa specific harware configuration capabilities 2106 */ 2107 static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt) 2108 { 2109 struct usb_ctrlrequest req; 2110 2111 dev_dbg(udc->dev, "interface=%d, alternate setting=%d\n", iface, alt); 2112 2113 udc->last_interface = iface; 2114 udc->last_alternate = alt; 2115 2116 req.bRequestType = USB_RECIP_INTERFACE; 2117 req.bRequest = USB_REQ_SET_INTERFACE; 2118 req.wValue = alt; 2119 req.wIndex = iface; 2120 req.wLength = 0; 2121 2122 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); 2123 udc->driver->setup(&udc->gadget, &req); 2124 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN); 2125 } 2126 2127 /* 2128 * irq_handle_data - Handle data transfer 2129 * @irq: irq IRQ number 2130 * @udc: dev pxa_udc device structure 2131 * 2132 * Called from irq handler, transferts data to or from endpoint to queue 2133 */ 2134 static void irq_handle_data(int irq, struct pxa_udc *udc) 2135 { 2136 int i; 2137 struct pxa_ep *ep; 2138 u32 udcisr0 = udc_readl(udc, UDCISR0) & UDCCISR0_EP_MASK; 2139 u32 udcisr1 = udc_readl(udc, UDCISR1) & UDCCISR1_EP_MASK; 2140 2141 if (udcisr0 & UDCISR_INT_MASK) { 2142 udc->pxa_ep[0].stats.irqs++; 2143 udc_writel(udc, UDCISR0, UDCISR_INT(0, UDCISR_INT_MASK)); 2144 handle_ep0(udc, !!(udcisr0 & UDCICR_FIFOERR), 2145 !!(udcisr0 & UDCICR_PKTCOMPL)); 2146 } 2147 2148 udcisr0 >>= 2; 2149 for (i = 1; udcisr0 != 0 && i < 16; udcisr0 >>= 2, i++) { 2150 if (!(udcisr0 & UDCISR_INT_MASK)) 2151 continue; 2152 2153 udc_writel(udc, UDCISR0, UDCISR_INT(i, UDCISR_INT_MASK)); 2154 2155 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep)); 2156 if (i < ARRAY_SIZE(udc->pxa_ep)) { 2157 ep = &udc->pxa_ep[i]; 2158 ep->stats.irqs++; 2159 handle_ep(ep); 2160 } 2161 } 2162 2163 for (i = 16; udcisr1 != 0 && i < 24; udcisr1 >>= 2, i++) { 2164 udc_writel(udc, UDCISR1, UDCISR_INT(i - 16, UDCISR_INT_MASK)); 2165 if (!(udcisr1 & UDCISR_INT_MASK)) 2166 continue; 2167 2168 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep)); 2169 if (i < ARRAY_SIZE(udc->pxa_ep)) { 2170 ep = &udc->pxa_ep[i]; 2171 ep->stats.irqs++; 2172 handle_ep(ep); 2173 } 2174 } 2175 2176 } 2177 2178 /** 2179 * irq_udc_suspend - Handle IRQ "UDC Suspend" 2180 * @udc: udc device 2181 */ 2182 static void irq_udc_suspend(struct pxa_udc *udc) 2183 { 2184 udc_writel(udc, UDCISR1, UDCISR1_IRSU); 2185 udc->stats.irqs_suspend++; 2186 2187 if (udc->gadget.speed != USB_SPEED_UNKNOWN 2188 && udc->driver && udc->driver->suspend) 2189 udc->driver->suspend(&udc->gadget); 2190 ep0_idle(udc); 2191 } 2192 2193 /** 2194 * irq_udc_resume - Handle IRQ "UDC Resume" 2195 * @udc: udc device 2196 */ 2197 static void irq_udc_resume(struct pxa_udc *udc) 2198 { 2199 udc_writel(udc, UDCISR1, UDCISR1_IRRU); 2200 udc->stats.irqs_resume++; 2201 2202 if (udc->gadget.speed != USB_SPEED_UNKNOWN 2203 && udc->driver && udc->driver->resume) 2204 udc->driver->resume(&udc->gadget); 2205 } 2206 2207 /** 2208 * irq_udc_reconfig - Handle IRQ "UDC Change Configuration" 2209 * @udc: udc device 2210 */ 2211 static void irq_udc_reconfig(struct pxa_udc *udc) 2212 { 2213 unsigned config, interface, alternate, config_change; 2214 u32 udccr = udc_readl(udc, UDCCR); 2215 2216 udc_writel(udc, UDCISR1, UDCISR1_IRCC); 2217 udc->stats.irqs_reconfig++; 2218 2219 config = (udccr & UDCCR_ACN) >> UDCCR_ACN_S; 2220 config_change = (config != udc->config); 2221 pxa27x_change_configuration(udc, config); 2222 2223 interface = (udccr & UDCCR_AIN) >> UDCCR_AIN_S; 2224 alternate = (udccr & UDCCR_AAISN) >> UDCCR_AAISN_S; 2225 pxa27x_change_interface(udc, interface, alternate); 2226 2227 if (config_change) 2228 update_pxa_ep_matches(udc); 2229 udc_set_mask_UDCCR(udc, UDCCR_SMAC); 2230 } 2231 2232 /** 2233 * irq_udc_reset - Handle IRQ "UDC Reset" 2234 * @udc: udc device 2235 */ 2236 static void irq_udc_reset(struct pxa_udc *udc) 2237 { 2238 u32 udccr = udc_readl(udc, UDCCR); 2239 struct pxa_ep *ep = &udc->pxa_ep[0]; 2240 2241 dev_info(udc->dev, "USB reset\n"); 2242 udc_writel(udc, UDCISR1, UDCISR1_IRRS); 2243 udc->stats.irqs_reset++; 2244 2245 if ((udccr & UDCCR_UDA) == 0) { 2246 dev_dbg(udc->dev, "USB reset start\n"); 2247 stop_activity(udc); 2248 } 2249 udc->gadget.speed = USB_SPEED_FULL; 2250 memset(&udc->stats, 0, sizeof udc->stats); 2251 2252 nuke(ep, -EPROTO); 2253 ep_write_UDCCSR(ep, UDCCSR0_FTF | UDCCSR0_OPC); 2254 ep0_idle(udc); 2255 } 2256 2257 /** 2258 * pxa_udc_irq - Main irq handler 2259 * @irq: irq number 2260 * @_dev: udc device 2261 * 2262 * Handles all udc interrupts 2263 */ 2264 static irqreturn_t pxa_udc_irq(int irq, void *_dev) 2265 { 2266 struct pxa_udc *udc = _dev; 2267 u32 udcisr0 = udc_readl(udc, UDCISR0); 2268 u32 udcisr1 = udc_readl(udc, UDCISR1); 2269 u32 udccr = udc_readl(udc, UDCCR); 2270 u32 udcisr1_spec; 2271 2272 dev_vdbg(udc->dev, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, " 2273 "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr); 2274 2275 udcisr1_spec = udcisr1 & 0xf8000000; 2276 if (unlikely(udcisr1_spec & UDCISR1_IRSU)) 2277 irq_udc_suspend(udc); 2278 if (unlikely(udcisr1_spec & UDCISR1_IRRU)) 2279 irq_udc_resume(udc); 2280 if (unlikely(udcisr1_spec & UDCISR1_IRCC)) 2281 irq_udc_reconfig(udc); 2282 if (unlikely(udcisr1_spec & UDCISR1_IRRS)) 2283 irq_udc_reset(udc); 2284 2285 if ((udcisr0 & UDCCISR0_EP_MASK) | (udcisr1 & UDCCISR1_EP_MASK)) 2286 irq_handle_data(irq, udc); 2287 2288 return IRQ_HANDLED; 2289 } 2290 2291 static struct pxa_udc memory = { 2292 .gadget = { 2293 .ops = &pxa_udc_ops, 2294 .ep0 = &memory.udc_usb_ep[0].usb_ep, 2295 .name = driver_name, 2296 .dev = { 2297 .init_name = "gadget", 2298 }, 2299 }, 2300 2301 .udc_usb_ep = { 2302 USB_EP_CTRL, 2303 USB_EP_OUT_BULK(1), 2304 USB_EP_IN_BULK(2), 2305 USB_EP_IN_ISO(3), 2306 USB_EP_OUT_ISO(4), 2307 USB_EP_IN_INT(5), 2308 }, 2309 2310 .pxa_ep = { 2311 PXA_EP_CTRL, 2312 /* Endpoints for gadget zero */ 2313 PXA_EP_OUT_BULK(1, 1, 3, 0, 0), 2314 PXA_EP_IN_BULK(2, 2, 3, 0, 0), 2315 /* Endpoints for ether gadget, file storage gadget */ 2316 PXA_EP_OUT_BULK(3, 1, 1, 0, 0), 2317 PXA_EP_IN_BULK(4, 2, 1, 0, 0), 2318 PXA_EP_IN_ISO(5, 3, 1, 0, 0), 2319 PXA_EP_OUT_ISO(6, 4, 1, 0, 0), 2320 PXA_EP_IN_INT(7, 5, 1, 0, 0), 2321 /* Endpoints for RNDIS, serial */ 2322 PXA_EP_OUT_BULK(8, 1, 2, 0, 0), 2323 PXA_EP_IN_BULK(9, 2, 2, 0, 0), 2324 PXA_EP_IN_INT(10, 5, 2, 0, 0), 2325 /* 2326 * All the following endpoints are only for completion. They 2327 * won't never work, as multiple interfaces are really broken on 2328 * the pxa. 2329 */ 2330 PXA_EP_OUT_BULK(11, 1, 2, 1, 0), 2331 PXA_EP_IN_BULK(12, 2, 2, 1, 0), 2332 /* Endpoint for CDC Ether */ 2333 PXA_EP_OUT_BULK(13, 1, 1, 1, 1), 2334 PXA_EP_IN_BULK(14, 2, 1, 1, 1), 2335 } 2336 }; 2337 2338 #if defined(CONFIG_OF) 2339 static const struct of_device_id udc_pxa_dt_ids[] = { 2340 { .compatible = "marvell,pxa270-udc" }, 2341 {} 2342 }; 2343 MODULE_DEVICE_TABLE(of, udc_pxa_dt_ids); 2344 #endif 2345 2346 /** 2347 * pxa_udc_probe - probes the udc device 2348 * @pdev: platform device 2349 * 2350 * Perform basic init : allocates udc clock, creates sysfs files, requests 2351 * irq. 2352 */ 2353 static int pxa_udc_probe(struct platform_device *pdev) 2354 { 2355 struct pxa_udc *udc = &memory; 2356 int retval = 0, gpio; 2357 struct pxa2xx_udc_mach_info *mach = dev_get_platdata(&pdev->dev); 2358 unsigned long gpio_flags; 2359 2360 if (mach) { 2361 gpio_flags = mach->gpio_pullup_inverted ? GPIOF_ACTIVE_LOW : 0; 2362 gpio = mach->gpio_pullup; 2363 if (gpio_is_valid(gpio)) { 2364 retval = devm_gpio_request_one(&pdev->dev, gpio, 2365 gpio_flags, 2366 "USB D+ pullup"); 2367 if (retval) 2368 return retval; 2369 udc->gpiod = gpio_to_desc(mach->gpio_pullup); 2370 } 2371 udc->udc_command = mach->udc_command; 2372 } else { 2373 udc->gpiod = devm_gpiod_get(&pdev->dev, NULL, GPIOD_ASIS); 2374 } 2375 2376 udc->regs = devm_platform_ioremap_resource(pdev, 0); 2377 if (IS_ERR(udc->regs)) 2378 return PTR_ERR(udc->regs); 2379 udc->irq = platform_get_irq(pdev, 0); 2380 if (udc->irq < 0) 2381 return udc->irq; 2382 2383 udc->dev = &pdev->dev; 2384 if (of_have_populated_dt()) { 2385 udc->transceiver = 2386 devm_usb_get_phy_by_phandle(udc->dev, "phys", 0); 2387 if (IS_ERR(udc->transceiver)) 2388 return PTR_ERR(udc->transceiver); 2389 } else { 2390 udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); 2391 } 2392 2393 if (IS_ERR(udc->gpiod)) { 2394 dev_err(&pdev->dev, "Couldn't find or request D+ gpio : %ld\n", 2395 PTR_ERR(udc->gpiod)); 2396 return PTR_ERR(udc->gpiod); 2397 } 2398 if (udc->gpiod) 2399 gpiod_direction_output(udc->gpiod, 0); 2400 2401 udc->clk = devm_clk_get(&pdev->dev, NULL); 2402 if (IS_ERR(udc->clk)) 2403 return PTR_ERR(udc->clk); 2404 2405 retval = clk_prepare(udc->clk); 2406 if (retval) 2407 return retval; 2408 2409 udc->vbus_sensed = 0; 2410 2411 the_controller = udc; 2412 platform_set_drvdata(pdev, udc); 2413 udc_init_data(udc); 2414 2415 /* irq setup after old hardware state is cleaned up */ 2416 retval = devm_request_irq(&pdev->dev, udc->irq, pxa_udc_irq, 2417 IRQF_SHARED, driver_name, udc); 2418 if (retval != 0) { 2419 dev_err(udc->dev, "%s: can't get irq %i, err %d\n", 2420 driver_name, udc->irq, retval); 2421 goto err; 2422 } 2423 2424 if (!IS_ERR_OR_NULL(udc->transceiver)) 2425 usb_register_notifier(udc->transceiver, &pxa27x_udc_phy); 2426 retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2427 if (retval) 2428 goto err_add_gadget; 2429 2430 pxa_init_debugfs(udc); 2431 if (should_enable_udc(udc)) 2432 udc_enable(udc); 2433 return 0; 2434 2435 err_add_gadget: 2436 if (!IS_ERR_OR_NULL(udc->transceiver)) 2437 usb_unregister_notifier(udc->transceiver, &pxa27x_udc_phy); 2438 err: 2439 clk_unprepare(udc->clk); 2440 return retval; 2441 } 2442 2443 /** 2444 * pxa_udc_remove - removes the udc device driver 2445 * @_dev: platform device 2446 */ 2447 static void pxa_udc_remove(struct platform_device *_dev) 2448 { 2449 struct pxa_udc *udc = platform_get_drvdata(_dev); 2450 2451 usb_del_gadget_udc(&udc->gadget); 2452 pxa_cleanup_debugfs(udc); 2453 2454 if (!IS_ERR_OR_NULL(udc->transceiver)) { 2455 usb_unregister_notifier(udc->transceiver, &pxa27x_udc_phy); 2456 usb_put_phy(udc->transceiver); 2457 } 2458 2459 udc->transceiver = NULL; 2460 the_controller = NULL; 2461 clk_unprepare(udc->clk); 2462 } 2463 2464 static void pxa_udc_shutdown(struct platform_device *_dev) 2465 { 2466 struct pxa_udc *udc = platform_get_drvdata(_dev); 2467 2468 if (udc_readl(udc, UDCCR) & UDCCR_UDE) 2469 udc_disable(udc); 2470 } 2471 2472 #ifdef CONFIG_PM 2473 /** 2474 * pxa_udc_suspend - Suspend udc device 2475 * @_dev: platform device 2476 * @state: suspend state 2477 * 2478 * Suspends udc : saves configuration registers (UDCCR*), then disables the udc 2479 * device. 2480 */ 2481 static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state) 2482 { 2483 struct pxa_udc *udc = platform_get_drvdata(_dev); 2484 struct pxa_ep *ep; 2485 2486 ep = &udc->pxa_ep[0]; 2487 udc->udccsr0 = udc_ep_readl(ep, UDCCSR); 2488 2489 udc_disable(udc); 2490 udc->pullup_resume = udc->pullup_on; 2491 dplus_pullup(udc, 0); 2492 2493 if (udc->driver) 2494 udc->driver->disconnect(&udc->gadget); 2495 2496 return 0; 2497 } 2498 2499 /** 2500 * pxa_udc_resume - Resume udc device 2501 * @_dev: platform device 2502 * 2503 * Resumes udc : restores configuration registers (UDCCR*), then enables the udc 2504 * device. 2505 */ 2506 static int pxa_udc_resume(struct platform_device *_dev) 2507 { 2508 struct pxa_udc *udc = platform_get_drvdata(_dev); 2509 struct pxa_ep *ep; 2510 2511 ep = &udc->pxa_ep[0]; 2512 udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME)); 2513 2514 dplus_pullup(udc, udc->pullup_resume); 2515 if (should_enable_udc(udc)) 2516 udc_enable(udc); 2517 /* 2518 * We do not handle OTG yet. 2519 * 2520 * OTGPH bit is set when sleep mode is entered. 2521 * it indicates that OTG pad is retaining its state. 2522 * Upon exit from sleep mode and before clearing OTGPH, 2523 * Software must configure the USB OTG pad, UDC, and UHC 2524 * to the state they were in before entering sleep mode. 2525 */ 2526 pxa27x_clear_otgph(); 2527 2528 return 0; 2529 } 2530 #endif 2531 2532 /* work with hotplug and coldplug */ 2533 MODULE_ALIAS("platform:pxa27x-udc"); 2534 2535 static struct platform_driver udc_driver = { 2536 .driver = { 2537 .name = "pxa27x-udc", 2538 .of_match_table = of_match_ptr(udc_pxa_dt_ids), 2539 }, 2540 .probe = pxa_udc_probe, 2541 .remove_new = pxa_udc_remove, 2542 .shutdown = pxa_udc_shutdown, 2543 #ifdef CONFIG_PM 2544 .suspend = pxa_udc_suspend, 2545 .resume = pxa_udc_resume 2546 #endif 2547 }; 2548 2549 module_platform_driver(udc_driver); 2550 2551 MODULE_DESCRIPTION(DRIVER_DESC); 2552 MODULE_AUTHOR("Robert Jarzmik"); 2553 MODULE_LICENSE("GPL"); 2554