1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * core.h - DesignWare HS OTG Controller common declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef __DWC2_CORE_H__ 39 #define __DWC2_CORE_H__ 40 41 #include <linux/acpi.h> 42 #include <linux/phy/phy.h> 43 #include <linux/regulator/consumer.h> 44 #include <linux/usb/gadget.h> 45 #include <linux/usb/otg.h> 46 #include <linux/usb/phy.h> 47 #include "hw.h" 48 49 /* 50 * Suggested defines for tracers: 51 * - no_printk: Disable tracing 52 * - pr_info: Print this info to the console 53 * - trace_printk: Print this info to trace buffer (good for verbose logging) 54 */ 55 56 #define DWC2_TRACE_SCHEDULER no_printk 57 #define DWC2_TRACE_SCHEDULER_VB no_printk 58 59 /* Detailed scheduler tracing, but won't overwhelm console */ 60 #define dwc2_sch_dbg(hsotg, fmt, ...) \ 61 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 62 dev_name(hsotg->dev), ##__VA_ARGS__) 63 64 /* Verbose scheduler tracing */ 65 #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 66 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 67 dev_name(hsotg->dev), ##__VA_ARGS__) 68 69 /* Maximum number of Endpoints/HostChannels */ 70 #define MAX_EPS_CHANNELS 16 71 72 /* dwc2-hsotg declarations */ 73 static const char * const dwc2_hsotg_supply_names[] = { 74 "vusb_d", /* digital USB supply, 1.2V */ 75 "vusb_a", /* analog USB supply, 1.1V */ 76 }; 77 78 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 79 80 /* 81 * EP0_MPS_LIMIT 82 * 83 * Unfortunately there seems to be a limit of the amount of data that can 84 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 85 * packets (which practically means 1 packet and 63 bytes of data) when the 86 * MPS is set to 64. 87 * 88 * This means if we are wanting to move >127 bytes of data, we need to 89 * split the transactions up, but just doing one packet at a time does 90 * not work (this may be an implicit DATA0 PID on first packet of the 91 * transaction) and doing 2 packets is outside the controller's limits. 92 * 93 * If we try to lower the MPS size for EP0, then no transfers work properly 94 * for EP0, and the system will fail basic enumeration. As no cause for this 95 * has currently been found, we cannot support any large IN transfers for 96 * EP0. 97 */ 98 #define EP0_MPS_LIMIT 64 99 100 struct dwc2_hsotg; 101 struct dwc2_hsotg_req; 102 103 /** 104 * struct dwc2_hsotg_ep - driver endpoint definition. 105 * @ep: The gadget layer representation of the endpoint. 106 * @name: The driver generated name for the endpoint. 107 * @queue: Queue of requests for this endpoint. 108 * @parent: Reference back to the parent device structure. 109 * @req: The current request that the endpoint is processing. This is 110 * used to indicate an request has been loaded onto the endpoint 111 * and has yet to be completed (maybe due to data move, or simply 112 * awaiting an ack from the core all the data has been completed). 113 * @debugfs: File entry for debugfs file for this endpoint. 114 * @dir_in: Set to true if this endpoint is of the IN direction, which 115 * means that it is sending data to the Host. 116 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped. 117 * @index: The index for the endpoint registers. 118 * @mc: Multi Count - number of transactions per microframe 119 * @interval: Interval for periodic endpoints, in frames or microframes. 120 * @name: The name array passed to the USB core. 121 * @halted: Set if the endpoint has been halted. 122 * @periodic: Set if this is a periodic ep, such as Interrupt 123 * @isochronous: Set if this is a isochronous ep 124 * @send_zlp: Set if we need to send a zero-length packet. 125 * @desc_list_dma: The DMA address of descriptor chain currently in use. 126 * @desc_list: Pointer to descriptor DMA chain head currently in use. 127 * @desc_count: Count of entries within the DMA descriptor chain of EP. 128 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 129 * @compl_desc: index of next descriptor to be completed by xFerComplete 130 * @total_data: The total number of data bytes done. 131 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 132 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 133 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 134 * @last_load: The offset of data for the last start of request. 135 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 136 * @target_frame: Targeted frame num to setup next ISOC transfer 137 * @frame_overrun: Indicates SOF number overrun in DSTS 138 * 139 * This is the driver's state for each registered endpoint, allowing it 140 * to keep track of transactions that need doing. Each endpoint has a 141 * lock to protect the state, to try and avoid using an overall lock 142 * for the host controller as much as possible. 143 * 144 * For periodic IN endpoints, we have fifo_size and fifo_load to try 145 * and keep track of the amount of data in the periodic FIFO for each 146 * of these as we don't have a status register that tells us how much 147 * is in each of them. (note, this may actually be useless information 148 * as in shared-fifo mode periodic in acts like a single-frame packet 149 * buffer than a fifo) 150 */ 151 struct dwc2_hsotg_ep { 152 struct usb_ep ep; 153 struct list_head queue; 154 struct dwc2_hsotg *parent; 155 struct dwc2_hsotg_req *req; 156 struct dentry *debugfs; 157 158 unsigned long total_data; 159 unsigned int size_loaded; 160 unsigned int last_load; 161 unsigned int fifo_load; 162 unsigned short fifo_size; 163 unsigned short fifo_index; 164 165 unsigned char dir_in; 166 unsigned char map_dir; 167 unsigned char index; 168 unsigned char mc; 169 u16 interval; 170 171 unsigned int halted:1; 172 unsigned int periodic:1; 173 unsigned int isochronous:1; 174 unsigned int send_zlp:1; 175 unsigned int target_frame; 176 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 177 bool frame_overrun; 178 179 dma_addr_t desc_list_dma; 180 struct dwc2_dma_desc *desc_list; 181 u8 desc_count; 182 183 unsigned int next_desc; 184 unsigned int compl_desc; 185 186 char name[10]; 187 }; 188 189 /** 190 * struct dwc2_hsotg_req - data transfer request 191 * @req: The USB gadget request 192 * @queue: The list of requests for the endpoint this is queued for. 193 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 194 */ 195 struct dwc2_hsotg_req { 196 struct usb_request req; 197 struct list_head queue; 198 void *saved_req_buf; 199 }; 200 201 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 202 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 203 #define call_gadget(_hs, _entry) \ 204 do { \ 205 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 206 (_hs)->driver && (_hs)->driver->_entry) { \ 207 spin_unlock(&_hs->lock); \ 208 (_hs)->driver->_entry(&(_hs)->gadget); \ 209 spin_lock(&_hs->lock); \ 210 } \ 211 } while (0) 212 #else 213 #define call_gadget(_hs, _entry) do {} while (0) 214 #endif 215 216 struct dwc2_hsotg; 217 struct dwc2_host_chan; 218 219 /* Device States */ 220 enum dwc2_lx_state { 221 DWC2_L0, /* On state */ 222 DWC2_L1, /* LPM sleep state */ 223 DWC2_L2, /* USB suspend state */ 224 DWC2_L3, /* Off state */ 225 }; 226 227 /* Gadget ep0 states */ 228 enum dwc2_ep0_state { 229 DWC2_EP0_SETUP, 230 DWC2_EP0_DATA_IN, 231 DWC2_EP0_DATA_OUT, 232 DWC2_EP0_STATUS_IN, 233 DWC2_EP0_STATUS_OUT, 234 }; 235 236 /** 237 * struct dwc2_core_params - Parameters for configuring the core 238 * 239 * @otg_cap: Specifies the OTG capabilities. 240 * 0 - HNP and SRP capable 241 * 1 - SRP Only capable 242 * 2 - No HNP/SRP capable (always available) 243 * Defaults to best available option (0, 1, then 2) 244 * @host_dma: Specifies whether to use slave or DMA mode for accessing 245 * the data FIFOs. The driver will automatically detect the 246 * value for this parameter if none is specified. 247 * 0 - Slave (always available) 248 * 1 - DMA (default, if available) 249 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 250 * address DMA mode or descriptor DMA mode for accessing 251 * the data FIFOs. The driver will automatically detect the 252 * value for this if none is specified. 253 * 0 - Address DMA 254 * 1 - Descriptor DMA (default, if available) 255 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 256 * address DMA mode or descriptor DMA mode for accessing 257 * the data FIFOs in Full Speed mode only. The driver 258 * will automatically detect the value for this if none is 259 * specified. 260 * 0 - Address DMA 261 * 1 - Descriptor DMA in FS (default, if available) 262 * @speed: Specifies the maximum speed of operation in host and 263 * device mode. The actual speed depends on the speed of 264 * the attached device and the value of phy_type. 265 * 0 - High Speed 266 * (default when phy_type is UTMI+ or ULPI) 267 * 1 - Full Speed 268 * (default when phy_type is Full Speed) 269 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 270 * 1 - Allow dynamic FIFO sizing (default, if available) 271 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 272 * are enabled for non-periodic IN endpoints in device 273 * mode. 274 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 275 * dynamic FIFO sizing is enabled 276 * 16 to 32768 277 * Actual maximum value is autodetected and also 278 * the default. 279 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 280 * in host mode when dynamic FIFO sizing is enabled 281 * 16 to 32768 282 * Actual maximum value is autodetected and also 283 * the default. 284 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 285 * host mode when dynamic FIFO sizing is enabled 286 * 16 to 32768 287 * Actual maximum value is autodetected and also 288 * the default. 289 * @max_transfer_size: The maximum transfer size supported, in bytes 290 * 2047 to 65,535 291 * Actual maximum value is autodetected and also 292 * the default. 293 * @max_packet_count: The maximum number of packets in a transfer 294 * 15 to 511 295 * Actual maximum value is autodetected and also 296 * the default. 297 * @host_channels: The number of host channel registers to use 298 * 1 to 16 299 * Actual maximum value is autodetected and also 300 * the default. 301 * @phy_type: Specifies the type of PHY interface to use. By default, 302 * the driver will automatically detect the phy_type. 303 * 0 - Full Speed Phy 304 * 1 - UTMI+ Phy 305 * 2 - ULPI Phy 306 * Defaults to best available option (2, 1, then 0) 307 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 308 * is applicable for a phy_type of UTMI+ or ULPI. (For a 309 * ULPI phy_type, this parameter indicates the data width 310 * between the MAC and the ULPI Wrapper.) Also, this 311 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 312 * parameter was set to "8 and 16 bits", meaning that the 313 * core has been configured to work at either data path 314 * width. 315 * 8 or 16 (default 16 if available) 316 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 317 * data rate. This parameter is only applicable if phy_type 318 * is ULPI. 319 * 0 - single data rate ULPI interface with 8 bit wide 320 * data bus (default) 321 * 1 - double data rate ULPI interface with 4 bit wide 322 * data bus 323 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 324 * external supply to drive the VBus 325 * 0 - Internal supply (default) 326 * 1 - External supply 327 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 328 * speed PHY. This parameter is only applicable if phy_type 329 * is FS. 330 * 0 - No (default) 331 * 1 - Yes 332 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 333 * 0 - Disable (default) 334 * 1 - Enable 335 * @acg_enable: For enabling Active Clock Gating in the controller 336 * 0 - No 337 * 1 - Yes 338 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 339 * 0 - No (default) 340 * 1 - Yes 341 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 342 * when attached to a Full Speed or Low Speed device in 343 * host mode. 344 * 0 - Don't support low power mode (default) 345 * 1 - Support low power mode 346 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 347 * when connected to a Low Speed device in host 348 * mode. This parameter is applicable only if 349 * host_support_fs_ls_low_power is enabled. 350 * 0 - 48 MHz 351 * (default when phy_type is UTMI+ or ULPI) 352 * 1 - 6 MHz 353 * (default when phy_type is Full Speed) 354 * @oc_disable: Flag to disable overcurrent condition. 355 * 0 - Allow overcurrent condition to get detected 356 * 1 - Disable overcurrent condtion to get detected 357 * @ts_dline: Enable Term Select Dline pulsing 358 * 0 - No (default) 359 * 1 - Yes 360 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 361 * 0 - No (default for core < 2.92a) 362 * 1 - Yes (default for core >= 2.92a) 363 * @ahbcfg: This field allows the default value of the GAHBCFG 364 * register to be overridden 365 * -1 - GAHBCFG value will be set to 0x06 366 * (INCR, default) 367 * all others - GAHBCFG value will be overridden with 368 * this value 369 * Not all bits can be controlled like this, the 370 * bits defined by GAHBCFG_CTRL_MASK are controlled 371 * by the driver and are ignored in this 372 * configuration value. 373 * @uframe_sched: True to enable the microframe scheduler 374 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 375 * Disable CONIDSTSCHNG controller interrupt in such 376 * case. 377 * 0 - No (default) 378 * 1 - Yes 379 * @power_down: Specifies whether the controller support power_down. 380 * If power_down is enabled, the controller will enter 381 * power_down in both peripheral and host mode when 382 * needed. 383 * 0 - No (default) 384 * 1 - Partial power down 385 * 2 - Hibernation 386 * @lpm: Enable LPM support. 387 * 0 - No 388 * 1 - Yes 389 * @lpm_clock_gating: Enable core PHY clock gating. 390 * 0 - No 391 * 1 - Yes 392 * @besl: Enable LPM Errata support. 393 * 0 - No 394 * 1 - Yes 395 * @hird_threshold_en: HIRD or HIRD Threshold enable. 396 * 0 - No 397 * 1 - Yes 398 * @hird_threshold: Value of BESL or HIRD Threshold. 399 * @ref_clk_per: Indicates in terms of pico seconds the period 400 * of ref_clk. 401 * 62500 - 16MHz 402 * 58823 - 17MHz 403 * 52083 - 19.2MHz 404 * 50000 - 20MHz 405 * 41666 - 24MHz 406 * 33333 - 30MHz (default) 407 * 25000 - 40MHz 408 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which 409 * the controller should generate an interrupt if the 410 * device had been in L1 state until that period. 411 * This is used by SW to initiate Remote WakeUp in the 412 * controller so as to sync to the uF number from the host. 413 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 414 * register. 415 * 0 - Deactivate the transceiver (default) 416 * 1 - Activate the transceiver 417 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level 418 * detection using GGPIO register. 419 * 0 - Deactivate the external level detection (default) 420 * 1 - Activate the external level detection 421 * @g_dma: Enables gadget dma usage (default: autodetect). 422 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 423 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 424 * DWORDS from 16-32768 (default: 2048 if 425 * possible, otherwise autodetect). 426 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 427 * DWORDS from 16-32768 (default: 1024 if 428 * possible, otherwise autodetect). 429 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 430 * mode. Each value corresponds to one EP 431 * starting from EP1 (max 15 values). Sizes are 432 * in DWORDS with possible values from 433 * 16-32768 (default: 256, 256, 256, 256, 768, 434 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 435 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 436 * while full&low speed device connect. And change speed 437 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 438 * 0 - No (default) 439 * 1 - Yes 440 * @service_interval: Enable service interval based scheduling. 441 * 0 - No 442 * 1 - Yes 443 * 444 * The following parameters may be specified when starting the module. These 445 * parameters define how the DWC_otg controller should be configured. A 446 * value of -1 (or any other out of range value) for any parameter means 447 * to read the value from hardware (if possible) or use the builtin 448 * default described above. 449 */ 450 struct dwc2_core_params { 451 u8 otg_cap; 452 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 453 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 454 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 455 456 u8 phy_type; 457 #define DWC2_PHY_TYPE_PARAM_FS 0 458 #define DWC2_PHY_TYPE_PARAM_UTMI 1 459 #define DWC2_PHY_TYPE_PARAM_ULPI 2 460 461 u8 speed; 462 #define DWC2_SPEED_PARAM_HIGH 0 463 #define DWC2_SPEED_PARAM_FULL 1 464 #define DWC2_SPEED_PARAM_LOW 2 465 466 u8 phy_utmi_width; 467 bool phy_ulpi_ddr; 468 bool phy_ulpi_ext_vbus; 469 bool enable_dynamic_fifo; 470 bool en_multiple_tx_fifo; 471 bool i2c_enable; 472 bool acg_enable; 473 bool ulpi_fs_ls; 474 bool ts_dline; 475 bool reload_ctl; 476 bool uframe_sched; 477 bool external_id_pin_ctl; 478 479 int power_down; 480 #define DWC2_POWER_DOWN_PARAM_NONE 0 481 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 482 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 483 484 bool lpm; 485 bool lpm_clock_gating; 486 bool besl; 487 bool hird_threshold_en; 488 bool service_interval; 489 u8 hird_threshold; 490 bool activate_stm_fs_transceiver; 491 bool activate_stm_id_vb_detection; 492 bool ipg_isoc_en; 493 u16 max_packet_count; 494 u32 max_transfer_size; 495 u32 ahbcfg; 496 497 /* GREFCLK parameters */ 498 u32 ref_clk_per; 499 u16 sof_cnt_wkup_alert; 500 501 /* Host parameters */ 502 bool host_dma; 503 bool dma_desc_enable; 504 bool dma_desc_fs_enable; 505 bool host_support_fs_ls_low_power; 506 bool host_ls_low_power_phy_clk; 507 bool oc_disable; 508 509 u8 host_channels; 510 u16 host_rx_fifo_size; 511 u16 host_nperio_tx_fifo_size; 512 u16 host_perio_tx_fifo_size; 513 514 /* Gadget parameters */ 515 bool g_dma; 516 bool g_dma_desc; 517 u32 g_rx_fifo_size; 518 u32 g_np_tx_fifo_size; 519 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 520 521 bool change_speed_quirk; 522 }; 523 524 /** 525 * struct dwc2_hw_params - Autodetected parameters. 526 * 527 * These parameters are the various parameters read from hardware 528 * registers during initialization. They typically contain the best 529 * supported or maximum value that can be configured in the 530 * corresponding dwc2_core_params value. 531 * 532 * The values that are not in dwc2_core_params are documented below. 533 * 534 * @op_mode: Mode of Operation 535 * 0 - HNP- and SRP-Capable OTG (Host & Device) 536 * 1 - SRP-Capable OTG (Host & Device) 537 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 538 * 3 - SRP-Capable Device 539 * 4 - Non-OTG Device 540 * 5 - SRP-Capable Host 541 * 6 - Non-OTG Host 542 * @arch: Architecture 543 * 0 - Slave only 544 * 1 - External DMA 545 * 2 - Internal DMA 546 * @ipg_isoc_en: This feature indicates that the controller supports 547 * the worst-case scenario of Rx followed by Rx 548 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 549 * specification for any token following ISOC OUT token. 550 * 0 - Don't support 551 * 1 - Support 552 * @power_optimized: Are power optimizations enabled? 553 * @num_dev_ep: Number of device endpoints available 554 * @num_dev_in_eps: Number of device IN endpoints available 555 * @num_dev_perio_in_ep: Number of device periodic IN endpoints 556 * available 557 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 558 * Depth 559 * 0 to 30 560 * @host_perio_tx_q_depth: 561 * Host Mode Periodic Request Queue Depth 562 * 2, 4 or 8 563 * @nperio_tx_q_depth: 564 * Non-Periodic Request Queue Depth 565 * 2, 4 or 8 566 * @hs_phy_type: High-speed PHY interface type 567 * 0 - High-speed interface not supported 568 * 1 - UTMI+ 569 * 2 - ULPI 570 * 3 - UTMI+ and ULPI 571 * @fs_phy_type: Full-speed PHY interface type 572 * 0 - Full speed interface not supported 573 * 1 - Dedicated full speed interface 574 * 2 - FS pins shared with UTMI+ pins 575 * 3 - FS pins shared with ULPI pins 576 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 577 * @hibernation: Is hibernation enabled? 578 * @utmi_phy_data_width: UTMI+ PHY data width 579 * 0 - 8 bits 580 * 1 - 16 bits 581 * 2 - 8 or 16 bits 582 * @snpsid: Value from SNPSID register 583 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 584 * @g_tx_fifo_size: Power-on values of TxFIFO sizes 585 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 586 * address DMA mode or descriptor DMA mode for accessing 587 * the data FIFOs. The driver will automatically detect the 588 * value for this if none is specified. 589 * 0 - Address DMA 590 * 1 - Descriptor DMA (default, if available) 591 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 592 * 1 - Allow dynamic FIFO sizing (default, if available) 593 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 594 * are enabled for non-periodic IN endpoints in device 595 * mode. 596 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 597 * in host mode when dynamic FIFO sizing is enabled 598 * 16 to 32768 599 * Actual maximum value is autodetected and also 600 * the default. 601 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 602 * host mode when dynamic FIFO sizing is enabled 603 * 16 to 32768 604 * Actual maximum value is autodetected and also 605 * the default. 606 * @max_transfer_size: The maximum transfer size supported, in bytes 607 * 2047 to 65,535 608 * Actual maximum value is autodetected and also 609 * the default. 610 * @max_packet_count: The maximum number of packets in a transfer 611 * 15 to 511 612 * Actual maximum value is autodetected and also 613 * the default. 614 * @host_channels: The number of host channel registers to use 615 * 1 to 16 616 * Actual maximum value is autodetected and also 617 * the default. 618 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 619 * in device mode when dynamic FIFO sizing is enabled 620 * 16 to 32768 621 * Actual maximum value is autodetected and also 622 * the default. 623 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 624 * speed PHY. This parameter is only applicable if phy_type 625 * is FS. 626 * 0 - No (default) 627 * 1 - Yes 628 * @acg_enable: For enabling Active Clock Gating in the controller 629 * 0 - Disable 630 * 1 - Enable 631 * @lpm_mode: For enabling Link Power Management in the controller 632 * 0 - Disable 633 * 1 - Enable 634 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 635 * FIFO sizing is enabled 16 to 32768 636 * Actual maximum value is autodetected and also 637 * the default. 638 * @service_interval_mode: For enabling service interval based scheduling in the 639 * controller. 640 * 0 - Disable 641 * 1 - Enable 642 */ 643 struct dwc2_hw_params { 644 unsigned op_mode:3; 645 unsigned arch:2; 646 unsigned dma_desc_enable:1; 647 unsigned enable_dynamic_fifo:1; 648 unsigned en_multiple_tx_fifo:1; 649 unsigned rx_fifo_size:16; 650 unsigned host_nperio_tx_fifo_size:16; 651 unsigned dev_nperio_tx_fifo_size:16; 652 unsigned host_perio_tx_fifo_size:16; 653 unsigned nperio_tx_q_depth:3; 654 unsigned host_perio_tx_q_depth:3; 655 unsigned dev_token_q_depth:5; 656 unsigned max_transfer_size:26; 657 unsigned max_packet_count:11; 658 unsigned host_channels:5; 659 unsigned hs_phy_type:2; 660 unsigned fs_phy_type:2; 661 unsigned i2c_enable:1; 662 unsigned acg_enable:1; 663 unsigned num_dev_ep:4; 664 unsigned num_dev_in_eps : 4; 665 unsigned num_dev_perio_in_ep:4; 666 unsigned total_fifo_size:16; 667 unsigned power_optimized:1; 668 unsigned hibernation:1; 669 unsigned utmi_phy_data_width:2; 670 unsigned lpm_mode:1; 671 unsigned ipg_isoc_en:1; 672 unsigned service_interval_mode:1; 673 u32 snpsid; 674 u32 dev_ep_dirs; 675 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 676 }; 677 678 /* Size of control and EP0 buffers */ 679 #define DWC2_CTRL_BUFF_SIZE 8 680 681 /** 682 * struct dwc2_gregs_backup - Holds global registers state before 683 * entering partial power down 684 * @gotgctl: Backup of GOTGCTL register 685 * @gintmsk: Backup of GINTMSK register 686 * @gahbcfg: Backup of GAHBCFG register 687 * @gusbcfg: Backup of GUSBCFG register 688 * @grxfsiz: Backup of GRXFSIZ register 689 * @gnptxfsiz: Backup of GNPTXFSIZ register 690 * @gi2cctl: Backup of GI2CCTL register 691 * @glpmcfg: Backup of GLPMCFG register 692 * @gdfifocfg: Backup of GDFIFOCFG register 693 * @pcgcctl: Backup of PCGCCTL register 694 * @pcgcctl1: Backup of PCGCCTL1 register 695 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 696 * @gpwrdn: Backup of GPWRDN register 697 * @valid: True if registers values backuped. 698 */ 699 struct dwc2_gregs_backup { 700 u32 gotgctl; 701 u32 gintmsk; 702 u32 gahbcfg; 703 u32 gusbcfg; 704 u32 grxfsiz; 705 u32 gnptxfsiz; 706 u32 gi2cctl; 707 u32 glpmcfg; 708 u32 pcgcctl; 709 u32 pcgcctl1; 710 u32 gdfifocfg; 711 u32 gpwrdn; 712 bool valid; 713 }; 714 715 /** 716 * struct dwc2_dregs_backup - Holds device registers state before 717 * entering partial power down 718 * @dcfg: Backup of DCFG register 719 * @dctl: Backup of DCTL register 720 * @daintmsk: Backup of DAINTMSK register 721 * @diepmsk: Backup of DIEPMSK register 722 * @doepmsk: Backup of DOEPMSK register 723 * @diepctl: Backup of DIEPCTL register 724 * @dieptsiz: Backup of DIEPTSIZ register 725 * @diepdma: Backup of DIEPDMA register 726 * @doepctl: Backup of DOEPCTL register 727 * @doeptsiz: Backup of DOEPTSIZ register 728 * @doepdma: Backup of DOEPDMA register 729 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 730 * @valid: True if registers values backuped. 731 */ 732 struct dwc2_dregs_backup { 733 u32 dcfg; 734 u32 dctl; 735 u32 daintmsk; 736 u32 diepmsk; 737 u32 doepmsk; 738 u32 diepctl[MAX_EPS_CHANNELS]; 739 u32 dieptsiz[MAX_EPS_CHANNELS]; 740 u32 diepdma[MAX_EPS_CHANNELS]; 741 u32 doepctl[MAX_EPS_CHANNELS]; 742 u32 doeptsiz[MAX_EPS_CHANNELS]; 743 u32 doepdma[MAX_EPS_CHANNELS]; 744 u32 dtxfsiz[MAX_EPS_CHANNELS]; 745 bool valid; 746 }; 747 748 /** 749 * struct dwc2_hregs_backup - Holds host registers state before 750 * entering partial power down 751 * @hcfg: Backup of HCFG register 752 * @haintmsk: Backup of HAINTMSK register 753 * @hcintmsk: Backup of HCINTMSK register 754 * @hprt0: Backup of HPTR0 register 755 * @hfir: Backup of HFIR register 756 * @hptxfsiz: Backup of HPTXFSIZ register 757 * @valid: True if registers values backuped. 758 */ 759 struct dwc2_hregs_backup { 760 u32 hcfg; 761 u32 haintmsk; 762 u32 hcintmsk[MAX_EPS_CHANNELS]; 763 u32 hprt0; 764 u32 hfir; 765 u32 hptxfsiz; 766 bool valid; 767 }; 768 769 /* 770 * Constants related to high speed periodic scheduling 771 * 772 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 773 * reservation point of view it's assumed that the schedule goes right back to 774 * the beginning after the end of the schedule. 775 * 776 * What does that mean for scheduling things with a long interval? It means 777 * we'll reserve time for them in every possible microframe that they could 778 * ever be scheduled in. ...but we'll still only actually schedule them as 779 * often as they were requested. 780 * 781 * We keep our schedule in a "bitmap" structure. This simplifies having 782 * to keep track of and merge intervals: we just let the bitmap code do most 783 * of the heavy lifting. In a way scheduling is much like memory allocation. 784 * 785 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 786 * supposed to schedule for periodic transfers). That's according to spec. 787 * 788 * Note that though we only schedule 80% of each microframe, the bitmap that we 789 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 790 * space for each uFrame). 791 * 792 * Requirements: 793 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 794 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 795 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 796 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 797 */ 798 #define DWC2_US_PER_UFRAME 125 799 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 800 801 #define DWC2_HS_SCHEDULE_UFRAMES 8 802 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 803 DWC2_HS_PERIODIC_US_PER_UFRAME) 804 805 /* 806 * Constants related to low speed scheduling 807 * 808 * For high speed we schedule every 1us. For low speed that's a bit overkill, 809 * so we make up a unit called a "slice" that's worth 25us. There are 40 810 * slices in a full frame and we can schedule 36 of those (90%) for periodic 811 * transfers. 812 * 813 * Our low speed schedule can be as short as 1 frame or could be longer. When 814 * we only schedule 1 frame it means that we'll need to reserve a time every 815 * frame even for things that only transfer very rarely, so something that runs 816 * every 2048 frames will get time reserved in every frame. Our low speed 817 * schedule can be longer and we'll be able to handle more overlap, but that 818 * will come at increased memory cost and increased time to schedule. 819 * 820 * Note: one other advantage of a short low speed schedule is that if we mess 821 * up and miss scheduling we can jump in and use any of the slots that we 822 * happened to reserve. 823 * 824 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 825 * the schedule. There will be one schedule per TT. 826 * 827 * Requirements: 828 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 829 */ 830 #define DWC2_US_PER_SLICE 25 831 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 832 833 #define DWC2_ROUND_US_TO_SLICE(us) \ 834 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 835 DWC2_US_PER_SLICE) 836 837 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 838 900 839 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 840 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 841 DWC2_US_PER_SLICE) 842 843 #define DWC2_LS_SCHEDULE_FRAMES 1 844 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 845 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 846 847 /** 848 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 849 * and periodic schedules 850 * 851 * These are common for both host and peripheral modes: 852 * 853 * @dev: The struct device pointer 854 * @regs: Pointer to controller regs 855 * @hw_params: Parameters that were autodetected from the 856 * hardware registers 857 * @params: Parameters that define how the core should be configured 858 * @op_state: The operational State, during transitions (a_host=> 859 * a_peripheral and b_device=>b_host) this may not match 860 * the core, but allows the software to determine 861 * transitions 862 * @dr_mode: Requested mode of operation, one of following: 863 * - USB_DR_MODE_PERIPHERAL 864 * - USB_DR_MODE_HOST 865 * - USB_DR_MODE_OTG 866 * @role_sw: usb_role_switch handle 867 * @hcd_enabled: Host mode sub-driver initialization indicator. 868 * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 869 * @ll_hw_enabled: Status of low-level hardware resources. 870 * @hibernated: True if core is hibernated 871 * @in_ppd: True if core is partial power down mode. 872 * @bus_suspended: True if bus is suspended 873 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a 874 * remote wakeup. 875 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. 876 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at 877 * suspend if we need USB to wake us up. 878 * @frame_number: Frame number read from the core. For both device 879 * and host modes. The value ranges are from 0 880 * to HFNUM_MAX_FRNUM. 881 * @phy: The otg phy transceiver structure for phy control. 882 * @uphy: The otg phy transceiver structure for old USB phy 883 * control. 884 * @plat: The platform specific configuration data. This can be 885 * removed once all SoCs support usb transceiver. 886 * @supplies: Definition of USB power supplies 887 * @vbus_supply: Regulator supplying vbus. 888 * @usb33d: Optional 3.3v regulator used on some stm32 devices to 889 * supply ID and VBUS detection hardware. 890 * @lock: Spinlock that protects all the driver data structures 891 * @priv: Stores a pointer to the struct usb_hcd 892 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 893 * transfer are in process of being queued 894 * @srp_success: Stores status of SRP request in the case of a FS PHY 895 * with an I2C interface 896 * @wq_otg: Workqueue object used for handling of some interrupts 897 * @wf_otg: Work object for handling Connector ID Status Change 898 * interrupt 899 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 900 * @lx_state: Lx state of connected device 901 * @gr_backup: Backup of global registers during suspend 902 * @dr_backup: Backup of device registers during suspend 903 * @hr_backup: Backup of host registers during suspend 904 * @needs_byte_swap: Specifies whether the opposite endianness. 905 * 906 * These are for host mode: 907 * 908 * @flags: Flags for handling root port state changes 909 * @flags.d32: Contain all root port flags 910 * @flags.b: Separate root port flags from each other 911 * @flags.b.port_connect_status_change: True if root port connect status 912 * changed 913 * @flags.b.port_connect_status: True if device connected to root port 914 * @flags.b.port_reset_change: True if root port reset status changed 915 * @flags.b.port_enable_change: True if root port enable status changed 916 * @flags.b.port_suspend_change: True if root port suspend status changed 917 * @flags.b.port_over_current_change: True if root port over current state 918 * changed. 919 * @flags.b.port_l1_change: True if root port l1 status changed 920 * @flags.b.reserved: Reserved bits of root port register 921 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 922 * Transfers associated with these QHs are not currently 923 * assigned to a host channel. 924 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 925 * Transfers associated with these QHs are currently 926 * assigned to a host channel. 927 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 928 * non-periodic schedule 929 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 930 * Transfers associated with these QHs are not currently 931 * assigned to a host channel. 932 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 933 * list of QHs for periodic transfers that are _not_ 934 * scheduled for the next frame. Each QH in the list has an 935 * interval counter that determines when it needs to be 936 * scheduled for execution. This scheduling mechanism 937 * allows only a simple calculation for periodic bandwidth 938 * used (i.e. must assume that all periodic transfers may 939 * need to execute in the same frame). However, it greatly 940 * simplifies scheduling and should be sufficient for the 941 * vast majority of OTG hosts, which need to connect to a 942 * small number of peripherals at one time. Items move from 943 * this list to periodic_sched_ready when the QH interval 944 * counter is 0 at SOF. 945 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 946 * the next frame, but have not yet been assigned to host 947 * channels. Items move from this list to 948 * periodic_sched_assigned as host channels become 949 * available during the current frame. 950 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 951 * frame that are assigned to host channels. Items move 952 * from this list to periodic_sched_queued as the 953 * transactions for the QH are queued to the DWC_otg 954 * controller. 955 * @periodic_sched_queued: List of periodic QHs that have been queued for 956 * execution. Items move from this list to either 957 * periodic_sched_inactive or periodic_sched_ready when the 958 * channel associated with the transfer is released. If the 959 * interval for the QH is 1, the item moves to 960 * periodic_sched_ready because it must be rescheduled for 961 * the next frame. Otherwise, the item moves to 962 * periodic_sched_inactive. 963 * @split_order: List keeping track of channels doing splits, in order. 964 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 965 * This value is in microseconds per (micro)frame. The 966 * assumption is that all periodic transfers may occur in 967 * the same (micro)frame. 968 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 969 * host is in high speed mode; low speed schedules are 970 * stored elsewhere since we need one per TT. 971 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 972 * SOF enable/disable. 973 * @free_hc_list: Free host channels in the controller. This is a list of 974 * struct dwc2_host_chan items. 975 * @periodic_channels: Number of host channels assigned to periodic transfers. 976 * Currently assuming that there is a dedicated host 977 * channel for each periodic transaction and at least one 978 * host channel is available for non-periodic transactions. 979 * @non_periodic_channels: Number of host channels assigned to non-periodic 980 * transfers 981 * @available_host_channels: Number of host channels available for the 982 * microframe scheduler to use 983 * @hc_ptr_array: Array of pointers to the host channel descriptors. 984 * Allows accessing a host channel descriptor given the 985 * host channel number. This is useful in interrupt 986 * handlers. 987 * @status_buf: Buffer used for data received during the status phase of 988 * a control transfer. 989 * @status_buf_dma: DMA address for status_buf 990 * @start_work: Delayed work for handling host A-cable connection 991 * @reset_work: Delayed work for handling a port reset 992 * @phy_reset_work: Work structure for doing a PHY reset 993 * @otg_port: OTG port number 994 * @frame_list: Frame list 995 * @frame_list_dma: Frame list DMA address 996 * @frame_list_sz: Frame list size 997 * @desc_gen_cache: Kmem cache for generic descriptors 998 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 999 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 1000 * 1001 * These are for peripheral mode: 1002 * 1003 * @driver: USB gadget driver 1004 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 1005 * @num_of_eps: Number of available EPs (excluding EP0) 1006 * @debug_root: Root directrory for debugfs. 1007 * @ep0_reply: Request used for ep0 reply. 1008 * @ep0_buff: Buffer for EP0 reply data, if needed. 1009 * @ctrl_buff: Buffer for EP0 control requests. 1010 * @ctrl_req: Request for EP0 control packets. 1011 * @ep0_state: EP0 control transfers state 1012 * @delayed_status: true when gadget driver asks for delayed status 1013 * @test_mode: USB test mode requested by the host 1014 * @remote_wakeup_allowed: True if device is allowed to wake-up host by 1015 * remote-wakeup signalling 1016 * @setup_desc_dma: EP0 setup stage desc chain DMA address 1017 * @setup_desc: EP0 setup stage desc chain pointer 1018 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 1019 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 1020 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 1021 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 1022 * @irq: Interrupt request line number 1023 * @clk: Pointer to otg clock 1024 * @reset: Pointer to dwc2 reset controller 1025 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 1026 * @regset: A pointer to a struct debugfs_regset32, which contains 1027 * a pointer to an array of register definitions, the 1028 * array size and the base address where the register bank 1029 * is to be found. 1030 * @last_frame_num: Number of last frame. Range from 0 to 32768 1031 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1032 * defined, for missed SOFs tracking. Array holds that 1033 * frame numbers, which not equal to last_frame_num +1 1034 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1035 * defined, for missed SOFs tracking. 1036 * If current_frame_number != last_frame_num+1 1037 * then last_frame_num added to this array 1038 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 1039 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 1040 * 0 - if missed SOFs frame numbers not dumbed 1041 * @fifo_mem: Total internal RAM for FIFOs (bytes) 1042 * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 1043 * then that fifo is used 1044 * @gadget: Represents a usb gadget device 1045 * @connected: Used in slave mode. True if device connected with host 1046 * @eps_in: The IN endpoints being supplied to the gadget framework 1047 * @eps_out: The OUT endpoints being supplied to the gadget framework 1048 * @new_connection: Used in host mode. True if there are new connected 1049 * device 1050 * @enabled: Indicates the enabling state of controller 1051 * 1052 */ 1053 struct dwc2_hsotg { 1054 struct device *dev; 1055 void __iomem *regs; 1056 /** Params detected from hardware */ 1057 struct dwc2_hw_params hw_params; 1058 /** Params to actually use */ 1059 struct dwc2_core_params params; 1060 enum usb_otg_state op_state; 1061 enum usb_dr_mode dr_mode; 1062 struct usb_role_switch *role_sw; 1063 unsigned int hcd_enabled:1; 1064 unsigned int gadget_enabled:1; 1065 unsigned int ll_hw_enabled:1; 1066 unsigned int hibernated:1; 1067 unsigned int in_ppd:1; 1068 bool bus_suspended; 1069 unsigned int reset_phy_on_wake:1; 1070 unsigned int need_phy_for_wake:1; 1071 unsigned int phy_off_for_suspend:1; 1072 u16 frame_number; 1073 1074 struct phy *phy; 1075 struct usb_phy *uphy; 1076 struct dwc2_hsotg_plat *plat; 1077 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1078 struct regulator *vbus_supply; 1079 struct regulator *usb33d; 1080 1081 spinlock_t lock; 1082 void *priv; 1083 int irq; 1084 struct clk *clk; 1085 struct reset_control *reset; 1086 struct reset_control *reset_ecc; 1087 1088 unsigned int queuing_high_bandwidth:1; 1089 unsigned int srp_success:1; 1090 1091 struct workqueue_struct *wq_otg; 1092 struct work_struct wf_otg; 1093 struct timer_list wkp_timer; 1094 enum dwc2_lx_state lx_state; 1095 struct dwc2_gregs_backup gr_backup; 1096 struct dwc2_dregs_backup dr_backup; 1097 struct dwc2_hregs_backup hr_backup; 1098 1099 struct dentry *debug_root; 1100 struct debugfs_regset32 *regset; 1101 bool needs_byte_swap; 1102 1103 /* DWC OTG HW Release versions */ 1104 #define DWC2_CORE_REV_2_71a 0x4f54271a 1105 #define DWC2_CORE_REV_2_72a 0x4f54272a 1106 #define DWC2_CORE_REV_2_80a 0x4f54280a 1107 #define DWC2_CORE_REV_2_90a 0x4f54290a 1108 #define DWC2_CORE_REV_2_91a 0x4f54291a 1109 #define DWC2_CORE_REV_2_92a 0x4f54292a 1110 #define DWC2_CORE_REV_2_94a 0x4f54294a 1111 #define DWC2_CORE_REV_3_00a 0x4f54300a 1112 #define DWC2_CORE_REV_3_10a 0x4f54310a 1113 #define DWC2_CORE_REV_4_00a 0x4f54400a 1114 #define DWC2_CORE_REV_4_20a 0x4f54420a 1115 #define DWC2_FS_IOT_REV_1_00a 0x5531100a 1116 #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1117 #define DWC2_CORE_REV_MASK 0x0000ffff 1118 1119 /* DWC OTG HW Core ID */ 1120 #define DWC2_OTG_ID 0x4f540000 1121 #define DWC2_FS_IOT_ID 0x55310000 1122 #define DWC2_HS_IOT_ID 0x55320000 1123 1124 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1125 union dwc2_hcd_internal_flags { 1126 u32 d32; 1127 struct { 1128 unsigned port_connect_status_change:1; 1129 unsigned port_connect_status:1; 1130 unsigned port_reset_change:1; 1131 unsigned port_enable_change:1; 1132 unsigned port_suspend_change:1; 1133 unsigned port_over_current_change:1; 1134 unsigned port_l1_change:1; 1135 unsigned reserved:25; 1136 } b; 1137 } flags; 1138 1139 struct list_head non_periodic_sched_inactive; 1140 struct list_head non_periodic_sched_waiting; 1141 struct list_head non_periodic_sched_active; 1142 struct list_head *non_periodic_qh_ptr; 1143 struct list_head periodic_sched_inactive; 1144 struct list_head periodic_sched_ready; 1145 struct list_head periodic_sched_assigned; 1146 struct list_head periodic_sched_queued; 1147 struct list_head split_order; 1148 u16 periodic_usecs; 1149 unsigned long hs_periodic_bitmap[ 1150 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1151 u16 periodic_qh_count; 1152 bool new_connection; 1153 1154 u16 last_frame_num; 1155 1156 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1157 #define FRAME_NUM_ARRAY_SIZE 1000 1158 u16 *frame_num_array; 1159 u16 *last_frame_num_array; 1160 int frame_num_idx; 1161 int dumped_frame_num_array; 1162 #endif 1163 1164 struct list_head free_hc_list; 1165 int periodic_channels; 1166 int non_periodic_channels; 1167 int available_host_channels; 1168 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1169 u8 *status_buf; 1170 dma_addr_t status_buf_dma; 1171 #define DWC2_HCD_STATUS_BUF_SIZE 64 1172 1173 struct delayed_work start_work; 1174 struct delayed_work reset_work; 1175 struct work_struct phy_reset_work; 1176 u8 otg_port; 1177 u32 *frame_list; 1178 dma_addr_t frame_list_dma; 1179 u32 frame_list_sz; 1180 struct kmem_cache *desc_gen_cache; 1181 struct kmem_cache *desc_hsisoc_cache; 1182 struct kmem_cache *unaligned_cache; 1183 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1184 1185 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1186 1187 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1188 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1189 /* Gadget structures */ 1190 struct usb_gadget_driver *driver; 1191 int fifo_mem; 1192 unsigned int dedicated_fifos:1; 1193 unsigned char num_of_eps; 1194 u32 fifo_map; 1195 1196 struct usb_request *ep0_reply; 1197 struct usb_request *ctrl_req; 1198 void *ep0_buff; 1199 void *ctrl_buff; 1200 enum dwc2_ep0_state ep0_state; 1201 unsigned delayed_status : 1; 1202 u8 test_mode; 1203 1204 dma_addr_t setup_desc_dma[2]; 1205 struct dwc2_dma_desc *setup_desc[2]; 1206 dma_addr_t ctrl_in_desc_dma; 1207 struct dwc2_dma_desc *ctrl_in_desc; 1208 dma_addr_t ctrl_out_desc_dma; 1209 struct dwc2_dma_desc *ctrl_out_desc; 1210 1211 struct usb_gadget gadget; 1212 unsigned int enabled:1; 1213 unsigned int connected:1; 1214 unsigned int remote_wakeup_allowed:1; 1215 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1216 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1217 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1218 }; 1219 1220 /* Normal architectures just use readl/write */ 1221 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 1222 { 1223 u32 val; 1224 1225 val = readl(hsotg->regs + offset); 1226 if (hsotg->needs_byte_swap) 1227 return swab32(val); 1228 else 1229 return val; 1230 } 1231 1232 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 1233 { 1234 if (hsotg->needs_byte_swap) 1235 writel(swab32(value), hsotg->regs + offset); 1236 else 1237 writel(value, hsotg->regs + offset); 1238 1239 #ifdef DWC2_LOG_WRITES 1240 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 1241 #endif 1242 } 1243 1244 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1245 void *buffer, unsigned int count) 1246 { 1247 if (count) { 1248 u32 *buf = buffer; 1249 1250 do { 1251 u32 x = dwc2_readl(hsotg, offset); 1252 *buf++ = x; 1253 } while (--count); 1254 } 1255 } 1256 1257 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1258 const void *buffer, unsigned int count) 1259 { 1260 if (count) { 1261 const u32 *buf = buffer; 1262 1263 do { 1264 dwc2_writel(hsotg, *buf++, offset); 1265 } while (--count); 1266 } 1267 } 1268 1269 /* Reasons for halting a host channel */ 1270 enum dwc2_halt_status { 1271 DWC2_HC_XFER_NO_HALT_STATUS, 1272 DWC2_HC_XFER_COMPLETE, 1273 DWC2_HC_XFER_URB_COMPLETE, 1274 DWC2_HC_XFER_ACK, 1275 DWC2_HC_XFER_NAK, 1276 DWC2_HC_XFER_NYET, 1277 DWC2_HC_XFER_STALL, 1278 DWC2_HC_XFER_XACT_ERR, 1279 DWC2_HC_XFER_FRAME_OVERRUN, 1280 DWC2_HC_XFER_BABBLE_ERR, 1281 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1282 DWC2_HC_XFER_AHB_ERR, 1283 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1284 DWC2_HC_XFER_URB_DEQUEUE, 1285 }; 1286 1287 /* Core version information */ 1288 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1289 { 1290 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1291 } 1292 1293 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1294 { 1295 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1296 } 1297 1298 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1299 { 1300 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1301 } 1302 1303 /* 1304 * The following functions support initialization of the core driver component 1305 * and the DWC_otg controller 1306 */ 1307 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1308 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1309 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 1310 bool restore); 1311 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1312 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1313 int reset, int is_host); 1314 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); 1315 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); 1316 1317 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 1318 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1319 1320 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1321 1322 int dwc2_check_core_version(struct dwc2_hsotg *hsotg); 1323 1324 /* 1325 * Common core Functions. 1326 * The following functions support managing the DWC_otg controller in either 1327 * device or host mode. 1328 */ 1329 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1330 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1331 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1332 1333 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1334 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1335 1336 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 1337 int is_host); 1338 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1339 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 1340 1341 void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 1342 1343 /* This function should be called on every hardware interrupt. */ 1344 irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1345 1346 /* The device ID match table */ 1347 extern const struct of_device_id dwc2_of_match_table[]; 1348 extern const struct acpi_device_id dwc2_acpi_match[]; 1349 1350 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1351 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1352 1353 /* Common polling functions */ 1354 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1355 u32 timeout); 1356 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1357 u32 timeout); 1358 /* Parameters */ 1359 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1360 int dwc2_init_params(struct dwc2_hsotg *hsotg); 1361 1362 /* 1363 * The following functions check the controller's OTG operation mode 1364 * capability (GHWCFG2.OTG_MODE). 1365 * 1366 * These functions can be used before the internal hsotg->hw_params 1367 * are read in and cached so they always read directly from the 1368 * GHWCFG2 register. 1369 */ 1370 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1371 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1372 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1373 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1374 1375 /* 1376 * Returns the mode of operation, host or device 1377 */ 1378 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1379 { 1380 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1381 } 1382 1383 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1384 { 1385 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1386 } 1387 1388 int dwc2_drd_init(struct dwc2_hsotg *hsotg); 1389 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg); 1390 void dwc2_drd_resume(struct dwc2_hsotg *hsotg); 1391 void dwc2_drd_exit(struct dwc2_hsotg *hsotg); 1392 1393 /* 1394 * Dump core registers and SPRAM 1395 */ 1396 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1397 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1398 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1399 1400 /* Gadget defines */ 1401 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1402 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1403 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1404 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1405 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1406 int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 1407 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1408 bool reset); 1409 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg); 1410 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1411 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1412 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1413 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1414 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1415 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1416 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1417 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1418 int rem_wakeup, int reset); 1419 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1420 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1421 bool restore); 1422 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); 1423 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1424 int rem_wakeup); 1425 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1426 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1427 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1428 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1429 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); 1430 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) 1431 { hsotg->fifo_map = 0; } 1432 #else 1433 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1434 { return 0; } 1435 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1436 { return 0; } 1437 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1438 { return 0; } 1439 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1440 { return 0; } 1441 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1442 bool reset) {} 1443 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {} 1444 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1445 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1446 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1447 int testmode) 1448 { return 0; } 1449 #define dwc2_is_device_connected(hsotg) (0) 1450 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1451 { return 0; } 1452 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 1453 int remote_wakeup) 1454 { return 0; } 1455 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1456 { return 0; } 1457 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1458 int rem_wakeup, int reset) 1459 { return 0; } 1460 static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1461 { return 0; } 1462 static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1463 bool restore) 1464 { return 0; } 1465 static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1466 static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1467 int rem_wakeup) {} 1468 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1469 { return 0; } 1470 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1471 { return 0; } 1472 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1473 { return 0; } 1474 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1475 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} 1476 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {} 1477 #endif 1478 1479 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1480 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1481 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1482 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1483 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1484 void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1485 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 1486 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex); 1487 int dwc2_port_resume(struct dwc2_hsotg *hsotg); 1488 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1489 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1490 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1491 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1492 int rem_wakeup, int reset); 1493 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1494 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1495 int rem_wakeup, bool restore); 1496 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg); 1497 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup); 1498 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); 1499 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) 1500 { schedule_work(&hsotg->phy_reset_work); } 1501 #else 1502 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1503 { return 0; } 1504 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1505 int us) 1506 { return 0; } 1507 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1508 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1509 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1510 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1511 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 1512 { return 0; } 1513 static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1514 { return 0; } 1515 static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg) 1516 { return 0; } 1517 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1518 { return 0; } 1519 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1520 { return 0; } 1521 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1522 { return 0; } 1523 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1524 { return 0; } 1525 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1526 int rem_wakeup, int reset) 1527 { return 0; } 1528 static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1529 { return 0; } 1530 static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1531 int rem_wakeup, bool restore) 1532 { return 0; } 1533 static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1534 static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, 1535 int rem_wakeup) {} 1536 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 1537 { return false; } 1538 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} 1539 1540 #endif 1541 1542 #endif /* __DWC2_CORE_H__ */ 1543