1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * core.h - DesignWare HS OTG Controller common declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 */ 7 8 #ifndef __DWC2_CORE_H__ 9 #define __DWC2_CORE_H__ 10 11 #include <linux/acpi.h> 12 #include <linux/device-id/pci.h> 13 #include <linux/phy/phy.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/usb/gadget.h> 16 #include <linux/usb/otg.h> 17 #include <linux/usb/phy.h> 18 #include "hw.h" 19 20 /* 21 * Suggested defines for tracers: 22 * - no_printk: Disable tracing 23 * - pr_info: Print this info to the console 24 * - trace_printk: Print this info to trace buffer (good for verbose logging) 25 */ 26 27 #define DWC2_TRACE_SCHEDULER no_printk 28 #define DWC2_TRACE_SCHEDULER_VB no_printk 29 30 /* Detailed scheduler tracing, but won't overwhelm console */ 31 #define dwc2_sch_dbg(hsotg, fmt, ...) \ 32 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 33 dev_name(hsotg->dev), ##__VA_ARGS__) 34 35 /* Verbose scheduler tracing */ 36 #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 37 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 38 dev_name(hsotg->dev), ##__VA_ARGS__) 39 40 /* Maximum number of Endpoints/HostChannels */ 41 #define MAX_EPS_CHANNELS 16 42 43 /* dwc2-hsotg declarations */ 44 static const char * const dwc2_hsotg_supply_names[] = { 45 "vusb_d", /* digital USB supply, 1.2V */ 46 "vusb_a", /* analog USB supply, 1.1V */ 47 }; 48 49 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 50 51 /* 52 * EP0_MPS_LIMIT 53 * 54 * Unfortunately there seems to be a limit of the amount of data that can 55 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 56 * packets (which practically means 1 packet and 63 bytes of data) when the 57 * MPS is set to 64. 58 * 59 * This means if we are wanting to move >127 bytes of data, we need to 60 * split the transactions up, but just doing one packet at a time does 61 * not work (this may be an implicit DATA0 PID on first packet of the 62 * transaction) and doing 2 packets is outside the controller's limits. 63 * 64 * If we try to lower the MPS size for EP0, then no transfers work properly 65 * for EP0, and the system will fail basic enumeration. As no cause for this 66 * has currently been found, we cannot support any large IN transfers for 67 * EP0. 68 */ 69 #define EP0_MPS_LIMIT 64 70 71 struct dwc2_hsotg; 72 struct dwc2_hsotg_req; 73 74 /** 75 * struct dwc2_hsotg_ep - driver endpoint definition. 76 * @ep: The gadget layer representation of the endpoint. 77 * @name: The driver generated name for the endpoint. 78 * @queue: Queue of requests for this endpoint. 79 * @parent: Reference back to the parent device structure. 80 * @req: The current request that the endpoint is processing. This is 81 * used to indicate an request has been loaded onto the endpoint 82 * and has yet to be completed (maybe due to data move, or simply 83 * awaiting an ack from the core all the data has been completed). 84 * @debugfs: File entry for debugfs file for this endpoint. 85 * @dir_in: Set to true if this endpoint is of the IN direction, which 86 * means that it is sending data to the Host. 87 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped. 88 * @index: The index for the endpoint registers. 89 * @mc: Multi Count - number of transactions per microframe 90 * @interval: Interval for periodic endpoints, in frames or microframes. 91 * @name: The name array passed to the USB core. 92 * @halted: Set if the endpoint has been halted. 93 * @periodic: Set if this is a periodic ep, such as Interrupt 94 * @isochronous: Set if this is a isochronous ep 95 * @send_zlp: Set if we need to send a zero-length packet. 96 * @wedged: Set if ep is wedged. 97 * @desc_list_dma: The DMA address of descriptor chain currently in use. 98 * @desc_list: Pointer to descriptor DMA chain head currently in use. 99 * @desc_count: Count of entries within the DMA descriptor chain of EP. 100 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 101 * @compl_desc: index of next descriptor to be completed by xFerComplete 102 * @total_data: The total number of data bytes done. 103 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 104 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 105 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 106 * @last_load: The offset of data for the last start of request. 107 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 108 * @target_frame: Targeted frame num to setup next ISOC transfer 109 * @frame_overrun: Indicates SOF number overrun in DSTS 110 * 111 * This is the driver's state for each registered endpoint, allowing it 112 * to keep track of transactions that need doing. Each endpoint has a 113 * lock to protect the state, to try and avoid using an overall lock 114 * for the host controller as much as possible. 115 * 116 * For periodic IN endpoints, we have fifo_size and fifo_load to try 117 * and keep track of the amount of data in the periodic FIFO for each 118 * of these as we don't have a status register that tells us how much 119 * is in each of them. (note, this may actually be useless information 120 * as in shared-fifo mode periodic in acts like a single-frame packet 121 * buffer than a fifo) 122 */ 123 struct dwc2_hsotg_ep { 124 struct usb_ep ep; 125 struct list_head queue; 126 struct dwc2_hsotg *parent; 127 struct dwc2_hsotg_req *req; 128 struct dentry *debugfs; 129 130 unsigned long total_data; 131 unsigned int size_loaded; 132 unsigned int last_load; 133 unsigned int fifo_load; 134 unsigned short fifo_size; 135 unsigned short fifo_index; 136 137 unsigned char dir_in; 138 unsigned char map_dir; 139 unsigned char index; 140 unsigned char mc; 141 u16 interval; 142 143 unsigned int halted:1; 144 unsigned int periodic:1; 145 unsigned int isochronous:1; 146 unsigned int send_zlp:1; 147 unsigned int wedged:1; 148 unsigned int target_frame; 149 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 150 bool frame_overrun; 151 152 dma_addr_t desc_list_dma; 153 struct dwc2_dma_desc *desc_list; 154 u8 desc_count; 155 156 unsigned int next_desc; 157 unsigned int compl_desc; 158 159 char name[10]; 160 }; 161 162 /** 163 * struct dwc2_hsotg_req - data transfer request 164 * @req: The USB gadget request 165 * @queue: The list of requests for the endpoint this is queued for. 166 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 167 */ 168 struct dwc2_hsotg_req { 169 struct usb_request req; 170 struct list_head queue; 171 void *saved_req_buf; 172 }; 173 174 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 175 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 176 #define call_gadget(_hs, _entry) \ 177 do { \ 178 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 179 (_hs)->driver && (_hs)->driver->_entry) { \ 180 spin_unlock(&_hs->lock); \ 181 (_hs)->driver->_entry(&(_hs)->gadget); \ 182 spin_lock(&_hs->lock); \ 183 } \ 184 } while (0) 185 #else 186 #define call_gadget(_hs, _entry) do {} while (0) 187 #endif 188 189 struct dwc2_hsotg; 190 struct dwc2_host_chan; 191 192 /* Device States */ 193 enum dwc2_lx_state { 194 DWC2_L0, /* On state */ 195 DWC2_L1, /* LPM sleep state */ 196 DWC2_L2, /* USB suspend state */ 197 DWC2_L3, /* Off state */ 198 }; 199 200 /* Gadget ep0 states */ 201 enum dwc2_ep0_state { 202 DWC2_EP0_SETUP, 203 DWC2_EP0_DATA_IN, 204 DWC2_EP0_DATA_OUT, 205 DWC2_EP0_STATUS_IN, 206 DWC2_EP0_STATUS_OUT, 207 }; 208 209 /** 210 * struct dwc2_core_params - Parameters for configuring the core 211 * 212 * @otg_caps: Specifies the OTG capabilities. OTG caps from the platform parameters, 213 * used to setup the: 214 * - HNP and SRP capable 215 * - SRP Only capable 216 * - No HNP/SRP capable (always available) 217 * Defaults to best available option 218 * - OTG revision number the device is compliant with, in binary-coded 219 * decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps) 220 * @host_dma: Specifies whether to use slave or DMA mode for accessing 221 * the data FIFOs. The driver will automatically detect the 222 * value for this parameter if none is specified. 223 * 0 - Slave (always available) 224 * 1 - DMA (default, if available) 225 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 226 * address DMA mode or descriptor DMA mode for accessing 227 * the data FIFOs. The driver will automatically detect the 228 * value for this if none is specified. 229 * 0 - Address DMA 230 * 1 - Descriptor DMA (default, if available) 231 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 232 * address DMA mode or descriptor DMA mode for accessing 233 * the data FIFOs in Full Speed mode only. The driver 234 * will automatically detect the value for this if none is 235 * specified. 236 * 0 - Address DMA 237 * 1 - Descriptor DMA in FS (default, if available) 238 * @speed: Specifies the maximum speed of operation in host and 239 * device mode. The actual speed depends on the speed of 240 * the attached device and the value of phy_type. 241 * 0 - High Speed 242 * (default when phy_type is UTMI+ or ULPI) 243 * 1 - Full Speed 244 * (default when phy_type is Full Speed) 245 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 246 * 1 - Allow dynamic FIFO sizing (default, if available) 247 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 248 * are enabled for non-periodic IN endpoints in device 249 * mode. 250 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 251 * dynamic FIFO sizing is enabled 252 * 16 to 32768 253 * Actual maximum value is autodetected and also 254 * the default. 255 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 256 * in host mode when dynamic FIFO sizing is enabled 257 * 16 to 32768 258 * Actual maximum value is autodetected and also 259 * the default. 260 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 261 * host mode when dynamic FIFO sizing is enabled 262 * 16 to 32768 263 * Actual maximum value is autodetected and also 264 * the default. 265 * @max_transfer_size: The maximum transfer size supported, in bytes 266 * 2047 to 65,535 267 * Actual maximum value is autodetected and also 268 * the default. 269 * @max_packet_count: The maximum number of packets in a transfer 270 * 15 to 511 271 * Actual maximum value is autodetected and also 272 * the default. 273 * @host_channels: The number of host channel registers to use 274 * 1 to 16 275 * Actual maximum value is autodetected and also 276 * the default. 277 * @phy_type: Specifies the type of PHY interface to use. By default, 278 * the driver will automatically detect the phy_type. 279 * 0 - Full Speed Phy 280 * 1 - UTMI+ Phy 281 * 2 - ULPI Phy 282 * Defaults to best available option (2, 1, then 0) 283 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 284 * is applicable for a phy_type of UTMI+ or ULPI. (For a 285 * ULPI phy_type, this parameter indicates the data width 286 * between the MAC and the ULPI Wrapper.) Also, this 287 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 288 * parameter was set to "8 and 16 bits", meaning that the 289 * core has been configured to work at either data path 290 * width. 291 * 8 or 16 (default 16 if available) 292 * @eusb2_disc: Specifies whether eUSB2 PHY disconnect support flow 293 * applicable or no. Applicable in device mode of HSOTG 294 * and HS IOT cores v5.00 or higher. 295 * 0 - eUSB2 PHY disconnect support flow not applicable 296 * 1 - eUSB2 PHY disconnect support flow applicable 297 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 298 * data rate. This parameter is only applicable if phy_type 299 * is ULPI. 300 * 0 - single data rate ULPI interface with 8 bit wide 301 * data bus (default) 302 * 1 - double data rate ULPI interface with 4 bit wide 303 * data bus 304 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 305 * external supply to drive the VBus 306 * 0 - Internal supply (default) 307 * 1 - External supply 308 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 309 * speed PHY. This parameter is only applicable if phy_type 310 * is FS. 311 * 0 - No (default) 312 * 1 - Yes 313 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 314 * 0 - Disable (default) 315 * 1 - Enable 316 * @acg_enable: For enabling Active Clock Gating in the controller 317 * 0 - No 318 * 1 - Yes 319 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 320 * 0 - No (default) 321 * 1 - Yes 322 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 323 * when attached to a Full Speed or Low Speed device in 324 * host mode. 325 * 0 - Don't support low power mode (default) 326 * 1 - Support low power mode 327 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 328 * when connected to a Low Speed device in host 329 * mode. This parameter is applicable only if 330 * host_support_fs_ls_low_power is enabled. 331 * 0 - 48 MHz 332 * (default when phy_type is UTMI+ or ULPI) 333 * 1 - 6 MHz 334 * (default when phy_type is Full Speed) 335 * @oc_disable: Flag to disable overcurrent condition. 336 * 0 - Allow overcurrent condition to get detected 337 * 1 - Disable overcurrent condtion to get detected 338 * @ts_dline: Enable Term Select Dline pulsing 339 * 0 - No (default) 340 * 1 - Yes 341 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 342 * 0 - No (default for core < 2.92a) 343 * 1 - Yes (default for core >= 2.92a) 344 * @ahbcfg: This field allows the default value of the GAHBCFG 345 * register to be overridden 346 * -1 - GAHBCFG value will be set to 0x06 347 * (INCR, default) 348 * all others - GAHBCFG value will be overridden with 349 * this value 350 * Not all bits can be controlled like this, the 351 * bits defined by GAHBCFG_CTRL_MASK are controlled 352 * by the driver and are ignored in this 353 * configuration value. 354 * @uframe_sched: True to enable the microframe scheduler 355 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 356 * Disable CONIDSTSCHNG controller interrupt in such 357 * case. 358 * 0 - No (default) 359 * 1 - Yes 360 * @power_down: Specifies whether the controller support power_down. 361 * If power_down is enabled, the controller will enter 362 * power_down in both peripheral and host mode when 363 * needed. 364 * 0 - No (default) 365 * 1 - Partial power down 366 * 2 - Hibernation 367 * @no_clock_gating: Specifies whether to avoid clock gating feature. 368 * 0 - No (use clock gating) 369 * 1 - Yes (avoid it) 370 * @lpm: Enable LPM support. 371 * 0 - No 372 * 1 - Yes 373 * @lpm_clock_gating: Enable core PHY clock gating. 374 * 0 - No 375 * 1 - Yes 376 * @besl: Enable LPM Errata support. 377 * 0 - No 378 * 1 - Yes 379 * @hird_threshold_en: HIRD or HIRD Threshold enable. 380 * 0 - No 381 * 1 - Yes 382 * @hird_threshold: Value of BESL or HIRD Threshold. 383 * @ref_clk_per: Indicates in terms of pico seconds the period 384 * of ref_clk. 385 * 62500 - 16MHz 386 * 58823 - 17MHz 387 * 52083 - 19.2MHz 388 * 50000 - 20MHz 389 * 41666 - 24MHz 390 * 33333 - 30MHz (default) 391 * 25000 - 40MHz 392 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which 393 * the controller should generate an interrupt if the 394 * device had been in L1 state until that period. 395 * This is used by SW to initiate Remote WakeUp in the 396 * controller so as to sync to the uF number from the host. 397 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 398 * register. 399 * 0 - Deactivate the transceiver (default) 400 * 1 - Activate the transceiver 401 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level 402 * detection using GGPIO register. 403 * 0 - Deactivate the external level detection (default) 404 * 1 - Activate the external level detection 405 * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent 406 * detection. 407 * 0 - Deactivate the overcurrent detection 408 * 1 - Activate the overcurrent detection (default) 409 * @g_dma: Enables gadget dma usage (default: autodetect). 410 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 411 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 412 * DWORDS from 16-32768 (default: 2048 if 413 * possible, otherwise autodetect). 414 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 415 * DWORDS from 16-32768 (default: 1024 if 416 * possible, otherwise autodetect). 417 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 418 * mode. Each value corresponds to one EP 419 * starting from EP1 (max 15 values). Sizes are 420 * in DWORDS with possible values from 421 * 16-32768 (default: 256, 256, 256, 256, 768, 422 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 423 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 424 * while full&low speed device connect. And change speed 425 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 426 * 0 - No (default) 427 * 1 - Yes 428 * @service_interval: Enable service interval based scheduling. 429 * 0 - No 430 * 1 - Yes 431 * 432 * The following parameters may be specified when starting the module. These 433 * parameters define how the DWC_otg controller should be configured. A 434 * value of -1 (or any other out of range value) for any parameter means 435 * to read the value from hardware (if possible) or use the builtin 436 * default described above. 437 */ 438 struct dwc2_core_params { 439 struct usb_otg_caps otg_caps; 440 u8 phy_type; 441 #define DWC2_PHY_TYPE_PARAM_FS 0 442 #define DWC2_PHY_TYPE_PARAM_UTMI 1 443 #define DWC2_PHY_TYPE_PARAM_ULPI 2 444 445 u8 speed; 446 #define DWC2_SPEED_PARAM_HIGH 0 447 #define DWC2_SPEED_PARAM_FULL 1 448 #define DWC2_SPEED_PARAM_LOW 2 449 450 u8 phy_utmi_width; 451 bool eusb2_disc; 452 bool phy_ulpi_ddr; 453 bool phy_ulpi_ext_vbus; 454 bool enable_dynamic_fifo; 455 bool en_multiple_tx_fifo; 456 bool i2c_enable; 457 bool acg_enable; 458 bool ulpi_fs_ls; 459 bool ts_dline; 460 bool reload_ctl; 461 bool uframe_sched; 462 bool external_id_pin_ctl; 463 464 int power_down; 465 #define DWC2_POWER_DOWN_PARAM_NONE 0 466 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 467 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 468 bool no_clock_gating; 469 470 bool lpm; 471 bool lpm_clock_gating; 472 bool besl; 473 bool hird_threshold_en; 474 bool service_interval; 475 u8 hird_threshold; 476 bool activate_stm_fs_transceiver; 477 bool activate_stm_id_vb_detection; 478 bool activate_ingenic_overcurrent_detection; 479 bool ipg_isoc_en; 480 u16 max_packet_count; 481 u32 max_transfer_size; 482 u32 ahbcfg; 483 484 /* GREFCLK parameters */ 485 u32 ref_clk_per; 486 u16 sof_cnt_wkup_alert; 487 488 /* Host parameters */ 489 bool host_dma; 490 bool dma_desc_enable; 491 bool dma_desc_fs_enable; 492 bool host_support_fs_ls_low_power; 493 bool host_ls_low_power_phy_clk; 494 bool oc_disable; 495 496 u8 host_channels; 497 u16 host_rx_fifo_size; 498 u16 host_nperio_tx_fifo_size; 499 u16 host_perio_tx_fifo_size; 500 501 /* Gadget parameters */ 502 bool g_dma; 503 bool g_dma_desc; 504 u32 g_rx_fifo_size; 505 u32 g_np_tx_fifo_size; 506 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 507 508 bool change_speed_quirk; 509 }; 510 511 /** 512 * struct dwc2_hw_params - Autodetected parameters. 513 * 514 * These parameters are the various parameters read from hardware 515 * registers during initialization. They typically contain the best 516 * supported or maximum value that can be configured in the 517 * corresponding dwc2_core_params value. 518 * 519 * The values that are not in dwc2_core_params are documented below. 520 * 521 * @op_mode: Mode of Operation 522 * 0 - HNP- and SRP-Capable OTG (Host & Device) 523 * 1 - SRP-Capable OTG (Host & Device) 524 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 525 * 3 - SRP-Capable Device 526 * 4 - Non-OTG Device 527 * 5 - SRP-Capable Host 528 * 6 - Non-OTG Host 529 * @arch: Architecture 530 * 0 - Slave only 531 * 1 - External DMA 532 * 2 - Internal DMA 533 * @ipg_isoc_en: This feature indicates that the controller supports 534 * the worst-case scenario of Rx followed by Rx 535 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 536 * specification for any token following ISOC OUT token. 537 * 0 - Don't support 538 * 1 - Support 539 * @power_optimized: Are power optimizations enabled? 540 * @num_dev_ep: Number of device endpoints available 541 * @num_dev_in_eps: Number of device IN endpoints available 542 * @num_dev_perio_in_ep: Number of device periodic IN endpoints 543 * available 544 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 545 * Depth 546 * 0 to 30 547 * @host_perio_tx_q_depth: 548 * Host Mode Periodic Request Queue Depth 549 * 2, 4 or 8 550 * @nperio_tx_q_depth: 551 * Non-Periodic Request Queue Depth 552 * 2, 4 or 8 553 * @hs_phy_type: High-speed PHY interface type 554 * 0 - High-speed interface not supported 555 * 1 - UTMI+ 556 * 2 - ULPI 557 * 3 - UTMI+ and ULPI 558 * @fs_phy_type: Full-speed PHY interface type 559 * 0 - Full speed interface not supported 560 * 1 - Dedicated full speed interface 561 * 2 - FS pins shared with UTMI+ pins 562 * 3 - FS pins shared with ULPI pins 563 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 564 * @hibernation: Is hibernation enabled? 565 * @utmi_phy_data_width: UTMI+ PHY data width 566 * 0 - 8 bits 567 * 1 - 16 bits 568 * 2 - 8 or 16 bits 569 * @snpsid: Value from SNPSID register 570 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 571 * @g_tx_fifo_size: Power-on values of TxFIFO sizes 572 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 573 * address DMA mode or descriptor DMA mode for accessing 574 * the data FIFOs. The driver will automatically detect the 575 * value for this if none is specified. 576 * 0 - Address DMA 577 * 1 - Descriptor DMA (default, if available) 578 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 579 * 1 - Allow dynamic FIFO sizing (default, if available) 580 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 581 * are enabled for non-periodic IN endpoints in device 582 * mode. 583 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 584 * in host mode when dynamic FIFO sizing is enabled 585 * 16 to 32768 586 * Actual maximum value is autodetected and also 587 * the default. 588 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 589 * host mode when dynamic FIFO sizing is enabled 590 * 16 to 32768 591 * Actual maximum value is autodetected and also 592 * the default. 593 * @max_transfer_size: The maximum transfer size supported, in bytes 594 * 2047 to 65,535 595 * Actual maximum value is autodetected and also 596 * the default. 597 * @max_packet_count: The maximum number of packets in a transfer 598 * 15 to 511 599 * Actual maximum value is autodetected and also 600 * the default. 601 * @host_channels: The number of host channel registers to use 602 * 1 to 16 603 * Actual maximum value is autodetected and also 604 * the default. 605 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 606 * in device mode when dynamic FIFO sizing is enabled 607 * 16 to 32768 608 * Actual maximum value is autodetected and also 609 * the default. 610 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 611 * speed PHY. This parameter is only applicable if phy_type 612 * is FS. 613 * 0 - No (default) 614 * 1 - Yes 615 * @acg_enable: For enabling Active Clock Gating in the controller 616 * 0 - Disable 617 * 1 - Enable 618 * @lpm_mode: For enabling Link Power Management in the controller 619 * 0 - Disable 620 * 1 - Enable 621 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 622 * FIFO sizing is enabled 16 to 32768 623 * Actual maximum value is autodetected and also 624 * the default. 625 * @service_interval_mode: For enabling service interval based scheduling in the 626 * controller. 627 * 0 - Disable 628 * 1 - Enable 629 */ 630 struct dwc2_hw_params { 631 unsigned op_mode:3; 632 unsigned arch:2; 633 unsigned dma_desc_enable:1; 634 unsigned enable_dynamic_fifo:1; 635 unsigned en_multiple_tx_fifo:1; 636 unsigned rx_fifo_size:16; 637 unsigned host_nperio_tx_fifo_size:16; 638 unsigned dev_nperio_tx_fifo_size:16; 639 unsigned host_perio_tx_fifo_size:16; 640 unsigned nperio_tx_q_depth:3; 641 unsigned host_perio_tx_q_depth:3; 642 unsigned dev_token_q_depth:5; 643 unsigned max_transfer_size:26; 644 unsigned max_packet_count:11; 645 unsigned host_channels:5; 646 unsigned hs_phy_type:2; 647 unsigned fs_phy_type:2; 648 unsigned i2c_enable:1; 649 unsigned acg_enable:1; 650 unsigned num_dev_ep:4; 651 unsigned num_dev_in_eps : 4; 652 unsigned num_dev_perio_in_ep:4; 653 unsigned total_fifo_size:16; 654 unsigned power_optimized:1; 655 unsigned hibernation:1; 656 unsigned utmi_phy_data_width:2; 657 unsigned lpm_mode:1; 658 unsigned ipg_isoc_en:1; 659 unsigned service_interval_mode:1; 660 u32 snpsid; 661 u32 dev_ep_dirs; 662 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 663 }; 664 665 /* Size of control and EP0 buffers */ 666 #define DWC2_CTRL_BUFF_SIZE 8 667 668 /** 669 * struct dwc2_gregs_backup - Holds global registers state before 670 * entering partial power down 671 * @gintsts: Backup of GINTSTS register 672 * @gotgctl: Backup of GOTGCTL register 673 * @gintmsk: Backup of GINTMSK register 674 * @gahbcfg: Backup of GAHBCFG register 675 * @gusbcfg: Backup of GUSBCFG register 676 * @grxfsiz: Backup of GRXFSIZ register 677 * @gnptxfsiz: Backup of GNPTXFSIZ register 678 * @gi2cctl: Backup of GI2CCTL register 679 * @glpmcfg: Backup of GLPMCFG register 680 * @gdfifocfg: Backup of GDFIFOCFG register 681 * @pcgcctl: Backup of PCGCCTL register 682 * @pcgcctl1: Backup of PCGCCTL1 register 683 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 684 * @gpwrdn: Backup of GPWRDN register 685 * @valid: True if registers values backuped. 686 */ 687 struct dwc2_gregs_backup { 688 u32 gintsts; 689 u32 gotgctl; 690 u32 gintmsk; 691 u32 gahbcfg; 692 u32 gusbcfg; 693 u32 grxfsiz; 694 u32 gnptxfsiz; 695 u32 gi2cctl; 696 u32 glpmcfg; 697 u32 pcgcctl; 698 u32 pcgcctl1; 699 u32 gdfifocfg; 700 u32 gpwrdn; 701 bool valid; 702 }; 703 704 /** 705 * struct dwc2_dregs_backup - Holds device registers state before 706 * entering partial power down 707 * @dcfg: Backup of DCFG register 708 * @dctl: Backup of DCTL register 709 * @daintmsk: Backup of DAINTMSK register 710 * @diepmsk: Backup of DIEPMSK register 711 * @doepmsk: Backup of DOEPMSK register 712 * @diepctl: Backup of DIEPCTL register 713 * @dieptsiz: Backup of DIEPTSIZ register 714 * @diepdma: Backup of DIEPDMA register 715 * @doepctl: Backup of DOEPCTL register 716 * @doeptsiz: Backup of DOEPTSIZ register 717 * @doepdma: Backup of DOEPDMA register 718 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 719 * @valid: True if registers values backuped. 720 */ 721 struct dwc2_dregs_backup { 722 u32 dcfg; 723 u32 dctl; 724 u32 daintmsk; 725 u32 diepmsk; 726 u32 doepmsk; 727 u32 diepctl[MAX_EPS_CHANNELS]; 728 u32 dieptsiz[MAX_EPS_CHANNELS]; 729 u32 diepdma[MAX_EPS_CHANNELS]; 730 u32 doepctl[MAX_EPS_CHANNELS]; 731 u32 doeptsiz[MAX_EPS_CHANNELS]; 732 u32 doepdma[MAX_EPS_CHANNELS]; 733 u32 dtxfsiz[MAX_EPS_CHANNELS]; 734 bool valid; 735 }; 736 737 /** 738 * struct dwc2_hregs_backup - Holds host registers state before 739 * entering partial power down 740 * @hcfg: Backup of HCFG register 741 * @hflbaddr: Backup of HFLBADDR register 742 * @haintmsk: Backup of HAINTMSK register 743 * @hcchar: Backup of HCCHAR register 744 * @hcsplt: Backup of HCSPLT register 745 * @hcintmsk: Backup of HCINTMSK register 746 * @hctsiz: Backup of HCTSIZ register 747 * @hdma: Backup of HCDMA register 748 * @hcdmab: Backup of HCDMAB register 749 * @hprt0: Backup of HPTR0 register 750 * @hfir: Backup of HFIR register 751 * @hptxfsiz: Backup of HPTXFSIZ register 752 * @valid: True if registers values backuped. 753 */ 754 struct dwc2_hregs_backup { 755 u32 hcfg; 756 u32 hflbaddr; 757 u32 haintmsk; 758 u32 hcchar[MAX_EPS_CHANNELS]; 759 u32 hcsplt[MAX_EPS_CHANNELS]; 760 u32 hcintmsk[MAX_EPS_CHANNELS]; 761 u32 hctsiz[MAX_EPS_CHANNELS]; 762 u32 hcidma[MAX_EPS_CHANNELS]; 763 u32 hcidmab[MAX_EPS_CHANNELS]; 764 u32 hprt0; 765 u32 hfir; 766 u32 hptxfsiz; 767 bool valid; 768 }; 769 770 /* 771 * Constants related to high speed periodic scheduling 772 * 773 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 774 * reservation point of view it's assumed that the schedule goes right back to 775 * the beginning after the end of the schedule. 776 * 777 * What does that mean for scheduling things with a long interval? It means 778 * we'll reserve time for them in every possible microframe that they could 779 * ever be scheduled in. ...but we'll still only actually schedule them as 780 * often as they were requested. 781 * 782 * We keep our schedule in a "bitmap" structure. This simplifies having 783 * to keep track of and merge intervals: we just let the bitmap code do most 784 * of the heavy lifting. In a way scheduling is much like memory allocation. 785 * 786 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 787 * supposed to schedule for periodic transfers). That's according to spec. 788 * 789 * Note that though we only schedule 80% of each microframe, the bitmap that we 790 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 791 * space for each uFrame). 792 * 793 * Requirements: 794 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 795 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 796 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 797 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 798 */ 799 #define DWC2_US_PER_UFRAME 125 800 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 801 802 #define DWC2_HS_SCHEDULE_UFRAMES 8 803 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 804 DWC2_HS_PERIODIC_US_PER_UFRAME) 805 806 /* 807 * Constants related to low speed scheduling 808 * 809 * For high speed we schedule every 1us. For low speed that's a bit overkill, 810 * so we make up a unit called a "slice" that's worth 25us. There are 40 811 * slices in a full frame and we can schedule 36 of those (90%) for periodic 812 * transfers. 813 * 814 * Our low speed schedule can be as short as 1 frame or could be longer. When 815 * we only schedule 1 frame it means that we'll need to reserve a time every 816 * frame even for things that only transfer very rarely, so something that runs 817 * every 2048 frames will get time reserved in every frame. Our low speed 818 * schedule can be longer and we'll be able to handle more overlap, but that 819 * will come at increased memory cost and increased time to schedule. 820 * 821 * Note: one other advantage of a short low speed schedule is that if we mess 822 * up and miss scheduling we can jump in and use any of the slots that we 823 * happened to reserve. 824 * 825 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 826 * the schedule. There will be one schedule per TT. 827 * 828 * Requirements: 829 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 830 */ 831 #define DWC2_US_PER_SLICE 25 832 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 833 834 #define DWC2_ROUND_US_TO_SLICE(us) \ 835 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 836 DWC2_US_PER_SLICE) 837 838 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 839 900 840 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 841 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 842 DWC2_US_PER_SLICE) 843 844 #define DWC2_LS_SCHEDULE_FRAMES 1 845 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 846 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 847 848 /** 849 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 850 * and periodic schedules 851 * 852 * These are common for both host and peripheral modes: 853 * 854 * @dev: The struct device pointer 855 * @regs: Pointer to controller regs 856 * @hw_params: Parameters that were autodetected from the 857 * hardware registers 858 * @params: Parameters that define how the core should be configured 859 * @op_state: The operational State, during transitions (a_host=> 860 * a_peripheral and b_device=>b_host) this may not match 861 * the core, but allows the software to determine 862 * transitions 863 * @dr_mode: Requested mode of operation, one of following: 864 * - USB_DR_MODE_PERIPHERAL 865 * - USB_DR_MODE_HOST 866 * - USB_DR_MODE_OTG 867 * @role_sw: usb_role_switch handle 868 * @role_sw_default_mode: default operation mode of controller while usb role 869 * is USB_ROLE_NONE 870 * @hcd_enabled: Host mode sub-driver initialization indicator. 871 * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 872 * @ll_hw_enabled: Status of low-level hardware resources. 873 * @hibernated: True if core is hibernated 874 * @in_ppd: True if core is partial power down mode. 875 * @bus_suspended: True if bus is suspended 876 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a 877 * remote wakeup. 878 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. 879 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at 880 * suspend if we need USB to wake us up. 881 * @frame_number: Frame number read from the core. For both device 882 * and host modes. The value ranges are from 0 883 * to HFNUM_MAX_FRNUM. 884 * @phy: The otg phy transceiver structure for phy control. 885 * @uphy: The otg phy transceiver structure for old USB phy 886 * control. 887 * @plat: The platform specific configuration data. This can be 888 * removed once all SoCs support usb transceiver. 889 * @supplies: Definition of USB power supplies 890 * @vbus_supply: Regulator supplying vbus. 891 * @usb33d: Optional 3.3v regulator used on some stm32 devices to 892 * supply ID and VBUS detection hardware. 893 * @lock: Spinlock that protects all the driver data structures 894 * @priv: Stores a pointer to the struct usb_hcd 895 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 896 * transfer are in process of being queued 897 * @srp_success: Stores status of SRP request in the case of a FS PHY 898 * with an I2C interface 899 * @wq_otg: Workqueue object used for handling of some interrupts 900 * @wf_otg: Work object for handling Connector ID Status Change 901 * interrupt 902 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 903 * @lx_state: Lx state of connected device 904 * @gr_backup: Backup of global registers during suspend 905 * @dr_backup: Backup of device registers during suspend 906 * @hr_backup: Backup of host registers during suspend 907 * @needs_byte_swap: Specifies whether the opposite endianness. 908 * 909 * These are for host mode: 910 * 911 * @flags: Flags for handling root port state changes 912 * @flags.d32: Contain all root port flags 913 * @flags.b: Separate root port flags from each other 914 * @flags.b.port_connect_status_change: True if root port connect status 915 * changed 916 * @flags.b.port_connect_status: True if device connected to root port 917 * @flags.b.port_reset_change: True if root port reset status changed 918 * @flags.b.port_enable_change: True if root port enable status changed 919 * @flags.b.port_suspend_change: True if root port suspend status changed 920 * @flags.b.port_over_current_change: True if root port over current state 921 * changed. 922 * @flags.b.port_l1_change: True if root port l1 status changed 923 * @flags.b.reserved: Reserved bits of root port register 924 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 925 * Transfers associated with these QHs are not currently 926 * assigned to a host channel. 927 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 928 * Transfers associated with these QHs are currently 929 * assigned to a host channel. 930 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 931 * non-periodic schedule 932 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 933 * Transfers associated with these QHs are not currently 934 * assigned to a host channel. 935 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 936 * list of QHs for periodic transfers that are _not_ 937 * scheduled for the next frame. Each QH in the list has an 938 * interval counter that determines when it needs to be 939 * scheduled for execution. This scheduling mechanism 940 * allows only a simple calculation for periodic bandwidth 941 * used (i.e. must assume that all periodic transfers may 942 * need to execute in the same frame). However, it greatly 943 * simplifies scheduling and should be sufficient for the 944 * vast majority of OTG hosts, which need to connect to a 945 * small number of peripherals at one time. Items move from 946 * this list to periodic_sched_ready when the QH interval 947 * counter is 0 at SOF. 948 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 949 * the next frame, but have not yet been assigned to host 950 * channels. Items move from this list to 951 * periodic_sched_assigned as host channels become 952 * available during the current frame. 953 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 954 * frame that are assigned to host channels. Items move 955 * from this list to periodic_sched_queued as the 956 * transactions for the QH are queued to the DWC_otg 957 * controller. 958 * @periodic_sched_queued: List of periodic QHs that have been queued for 959 * execution. Items move from this list to either 960 * periodic_sched_inactive or periodic_sched_ready when the 961 * channel associated with the transfer is released. If the 962 * interval for the QH is 1, the item moves to 963 * periodic_sched_ready because it must be rescheduled for 964 * the next frame. Otherwise, the item moves to 965 * periodic_sched_inactive. 966 * @split_order: List keeping track of channels doing splits, in order. 967 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 968 * This value is in microseconds per (micro)frame. The 969 * assumption is that all periodic transfers may occur in 970 * the same (micro)frame. 971 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 972 * host is in high speed mode; low speed schedules are 973 * stored elsewhere since we need one per TT. 974 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 975 * SOF enable/disable. 976 * @free_hc_list: Free host channels in the controller. This is a list of 977 * struct dwc2_host_chan items. 978 * @periodic_channels: Number of host channels assigned to periodic transfers. 979 * Currently assuming that there is a dedicated host 980 * channel for each periodic transaction and at least one 981 * host channel is available for non-periodic transactions. 982 * @non_periodic_channels: Number of host channels assigned to non-periodic 983 * transfers 984 * @available_host_channels: Number of host channels available for the 985 * microframe scheduler to use 986 * @hc_ptr_array: Array of pointers to the host channel descriptors. 987 * Allows accessing a host channel descriptor given the 988 * host channel number. This is useful in interrupt 989 * handlers. 990 * @status_buf: Buffer used for data received during the status phase of 991 * a control transfer. 992 * @status_buf_dma: DMA address for status_buf 993 * @start_work: Delayed work for handling host A-cable connection 994 * @reset_work: Delayed work for handling a port reset 995 * @phy_reset_work: Work structure for doing a PHY reset 996 * @otg_port: OTG port number 997 * @frame_list: Frame list 998 * @frame_list_dma: Frame list DMA address 999 * @frame_list_sz: Frame list size 1000 * @desc_gen_cache: Kmem cache for generic descriptors 1001 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 1002 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 1003 * 1004 * These are for peripheral mode: 1005 * 1006 * @driver: USB gadget driver 1007 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 1008 * @num_of_eps: Number of available EPs (excluding EP0) 1009 * @debug_root: Root directrory for debugfs. 1010 * @ep0_reply: Request used for ep0 reply. 1011 * @ep0_buff: Buffer for EP0 reply data, if needed. 1012 * @ctrl_buff: Buffer for EP0 control requests. 1013 * @ctrl_req: Request for EP0 control packets. 1014 * @ep0_state: EP0 control transfers state 1015 * @delayed_status: true when gadget driver asks for delayed status 1016 * @test_mode: USB test mode requested by the host 1017 * @remote_wakeup_allowed: True if device is allowed to wake-up host by 1018 * remote-wakeup signalling 1019 * @setup_desc_dma: EP0 setup stage desc chain DMA address 1020 * @setup_desc: EP0 setup stage desc chain pointer 1021 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 1022 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 1023 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 1024 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 1025 * @irq: Interrupt request line number 1026 * @clk: Pointer to otg clock 1027 * @utmi_clk: Pointer to utmi_clk clock 1028 * @reset: Pointer to dwc2 reset controller 1029 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 1030 * @regset: A pointer to a struct debugfs_regset32, which contains 1031 * a pointer to an array of register definitions, the 1032 * array size and the base address where the register bank 1033 * is to be found. 1034 * @last_frame_num: Number of last frame. Range from 0 to 32768 1035 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1036 * defined, for missed SOFs tracking. Array holds that 1037 * frame numbers, which not equal to last_frame_num +1 1038 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1039 * defined, for missed SOFs tracking. 1040 * If current_frame_number != last_frame_num+1 1041 * then last_frame_num added to this array 1042 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 1043 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 1044 * 0 - if missed SOFs frame numbers not dumbed 1045 * @fifo_mem: Total internal RAM for FIFOs (bytes) 1046 * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 1047 * then that fifo is used 1048 * @gadget: Represents a usb gadget device 1049 * @connected: Used in slave mode. True if device connected with host 1050 * @eps_in: The IN endpoints being supplied to the gadget framework 1051 * @eps_out: The OUT endpoints being supplied to the gadget framework 1052 * @new_connection: Used in host mode. True if there are new connected 1053 * device 1054 * @enabled: Indicates the enabling state of controller 1055 * 1056 */ 1057 struct dwc2_hsotg { 1058 struct device *dev; 1059 void __iomem *regs; 1060 /** Params detected from hardware */ 1061 struct dwc2_hw_params hw_params; 1062 /** Params to actually use */ 1063 struct dwc2_core_params params; 1064 enum usb_otg_state op_state; 1065 enum usb_dr_mode dr_mode; 1066 struct usb_role_switch *role_sw; 1067 enum usb_dr_mode role_sw_default_mode; 1068 unsigned int hcd_enabled:1; 1069 unsigned int gadget_enabled:1; 1070 unsigned int ll_hw_enabled:1; 1071 unsigned int hibernated:1; 1072 unsigned int in_ppd:1; 1073 bool bus_suspended; 1074 unsigned int reset_phy_on_wake:1; 1075 unsigned int need_phy_for_wake:1; 1076 unsigned int phy_off_for_suspend:1; 1077 u16 frame_number; 1078 1079 struct phy *phy; 1080 struct usb_phy *uphy; 1081 struct dwc2_hsotg_plat *plat; 1082 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1083 struct regulator *vbus_supply; 1084 struct regulator *usb33d; 1085 1086 spinlock_t lock; 1087 void *priv; 1088 int irq; 1089 struct clk *clk; 1090 struct clk *utmi_clk; 1091 struct reset_control *reset; 1092 struct reset_control *reset_ecc; 1093 1094 unsigned int queuing_high_bandwidth:1; 1095 unsigned int srp_success:1; 1096 1097 struct workqueue_struct *wq_otg; 1098 struct work_struct wf_otg; 1099 struct timer_list wkp_timer; 1100 enum dwc2_lx_state lx_state; 1101 struct dwc2_gregs_backup gr_backup; 1102 struct dwc2_dregs_backup dr_backup; 1103 struct dwc2_hregs_backup hr_backup; 1104 1105 struct dentry *debug_root; 1106 struct debugfs_regset32 *regset; 1107 bool needs_byte_swap; 1108 1109 /* DWC OTG HW Release versions */ 1110 #define DWC2_CORE_REV_4_30a 0x4f54430a 1111 #define DWC2_CORE_REV_2_71a 0x4f54271a 1112 #define DWC2_CORE_REV_2_72a 0x4f54272a 1113 #define DWC2_CORE_REV_2_80a 0x4f54280a 1114 #define DWC2_CORE_REV_2_90a 0x4f54290a 1115 #define DWC2_CORE_REV_2_91a 0x4f54291a 1116 #define DWC2_CORE_REV_2_92a 0x4f54292a 1117 #define DWC2_CORE_REV_2_94a 0x4f54294a 1118 #define DWC2_CORE_REV_3_00a 0x4f54300a 1119 #define DWC2_CORE_REV_3_10a 0x4f54310a 1120 #define DWC2_CORE_REV_4_00a 0x4f54400a 1121 #define DWC2_CORE_REV_4_20a 0x4f54420a 1122 #define DWC2_CORE_REV_5_00a 0x4f54500a 1123 #define DWC2_FS_IOT_REV_1_00a 0x5531100a 1124 #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1125 #define DWC2_HS_IOT_REV_5_00a 0x5532500a 1126 #define DWC2_CORE_REV_MASK 0x0000ffff 1127 1128 /* DWC OTG HW Core ID */ 1129 #define DWC2_OTG_ID 0x4f540000 1130 #define DWC2_FS_IOT_ID 0x55310000 1131 #define DWC2_HS_IOT_ID 0x55320000 1132 1133 #define DWC2_RESTORE_DCTL BIT(0) 1134 #define DWC2_RESTORE_DCFG BIT(1) 1135 1136 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1137 union dwc2_hcd_internal_flags { 1138 u32 d32; 1139 struct { 1140 unsigned port_connect_status_change:1; 1141 unsigned port_connect_status:1; 1142 unsigned port_reset_change:1; 1143 unsigned port_enable_change:1; 1144 unsigned port_suspend_change:1; 1145 unsigned port_over_current_change:1; 1146 unsigned port_l1_change:1; 1147 unsigned reserved:25; 1148 } b; 1149 } flags; 1150 1151 struct list_head non_periodic_sched_inactive; 1152 struct list_head non_periodic_sched_waiting; 1153 struct list_head non_periodic_sched_active; 1154 struct list_head *non_periodic_qh_ptr; 1155 struct list_head periodic_sched_inactive; 1156 struct list_head periodic_sched_ready; 1157 struct list_head periodic_sched_assigned; 1158 struct list_head periodic_sched_queued; 1159 struct list_head split_order; 1160 u16 periodic_usecs; 1161 DECLARE_BITMAP(hs_periodic_bitmap, DWC2_HS_SCHEDULE_US); 1162 u16 periodic_qh_count; 1163 bool new_connection; 1164 1165 u16 last_frame_num; 1166 1167 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1168 #define FRAME_NUM_ARRAY_SIZE 1000 1169 u16 *frame_num_array; 1170 u16 *last_frame_num_array; 1171 int frame_num_idx; 1172 int dumped_frame_num_array; 1173 #endif 1174 1175 struct list_head free_hc_list; 1176 int periodic_channels; 1177 int non_periodic_channels; 1178 int available_host_channels; 1179 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1180 u8 *status_buf; 1181 dma_addr_t status_buf_dma; 1182 #define DWC2_HCD_STATUS_BUF_SIZE 64 1183 1184 struct delayed_work start_work; 1185 struct delayed_work reset_work; 1186 struct work_struct phy_reset_work; 1187 u8 otg_port; 1188 u32 *frame_list; 1189 dma_addr_t frame_list_dma; 1190 u32 frame_list_sz; 1191 struct kmem_cache *desc_gen_cache; 1192 struct kmem_cache *desc_hsisoc_cache; 1193 struct kmem_cache *unaligned_cache; 1194 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1195 1196 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1197 1198 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1199 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1200 /* Gadget structures */ 1201 struct usb_gadget_driver *driver; 1202 int fifo_mem; 1203 unsigned int dedicated_fifos:1; 1204 unsigned char num_of_eps; 1205 u32 fifo_map; 1206 1207 struct usb_request *ep0_reply; 1208 struct usb_request *ctrl_req; 1209 void *ep0_buff; 1210 void *ctrl_buff; 1211 enum dwc2_ep0_state ep0_state; 1212 unsigned delayed_status : 1; 1213 u8 test_mode; 1214 1215 dma_addr_t setup_desc_dma[2]; 1216 struct dwc2_dma_desc *setup_desc[2]; 1217 dma_addr_t ctrl_in_desc_dma; 1218 struct dwc2_dma_desc *ctrl_in_desc; 1219 dma_addr_t ctrl_out_desc_dma; 1220 struct dwc2_dma_desc *ctrl_out_desc; 1221 1222 struct usb_gadget gadget; 1223 unsigned int enabled:1; 1224 unsigned int connected:1; 1225 unsigned int remote_wakeup_allowed:1; 1226 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1227 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1228 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1229 }; 1230 1231 /* Normal architectures just use readl/write */ 1232 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 1233 { 1234 u32 val; 1235 1236 val = readl(hsotg->regs + offset); 1237 if (hsotg->needs_byte_swap) 1238 return swab32(val); 1239 else 1240 return val; 1241 } 1242 1243 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 1244 { 1245 if (hsotg->needs_byte_swap) 1246 writel(swab32(value), hsotg->regs + offset); 1247 else 1248 writel(value, hsotg->regs + offset); 1249 1250 #ifdef DWC2_LOG_WRITES 1251 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 1252 #endif 1253 } 1254 1255 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1256 void *buffer, unsigned int count) 1257 { 1258 if (count) { 1259 u32 *buf = buffer; 1260 1261 do { 1262 u32 x = dwc2_readl(hsotg, offset); 1263 *buf++ = x; 1264 } while (--count); 1265 } 1266 } 1267 1268 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1269 const void *buffer, unsigned int count) 1270 { 1271 if (count) { 1272 const u32 *buf = buffer; 1273 1274 do { 1275 dwc2_writel(hsotg, *buf++, offset); 1276 } while (--count); 1277 } 1278 } 1279 1280 /* Reasons for halting a host channel */ 1281 enum dwc2_halt_status { 1282 DWC2_HC_XFER_NO_HALT_STATUS, 1283 DWC2_HC_XFER_COMPLETE, 1284 DWC2_HC_XFER_URB_COMPLETE, 1285 DWC2_HC_XFER_ACK, 1286 DWC2_HC_XFER_NAK, 1287 DWC2_HC_XFER_NYET, 1288 DWC2_HC_XFER_STALL, 1289 DWC2_HC_XFER_XACT_ERR, 1290 DWC2_HC_XFER_FRAME_OVERRUN, 1291 DWC2_HC_XFER_BABBLE_ERR, 1292 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1293 DWC2_HC_XFER_AHB_ERR, 1294 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1295 DWC2_HC_XFER_URB_DEQUEUE, 1296 }; 1297 1298 /* Core version information */ 1299 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1300 { 1301 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1302 } 1303 1304 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1305 { 1306 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1307 } 1308 1309 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1310 { 1311 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1312 } 1313 1314 /* 1315 * The following functions support initialization of the core driver component 1316 * and the DWC_otg controller 1317 */ 1318 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1319 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1320 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 1321 bool restore); 1322 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1323 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1324 int reset, int is_host); 1325 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); 1326 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); 1327 1328 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 1329 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1330 1331 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1332 1333 int dwc2_check_core_version(struct dwc2_hsotg *hsotg); 1334 1335 /* 1336 * Common core Functions. 1337 * The following functions support managing the DWC_otg controller in either 1338 * device or host mode. 1339 */ 1340 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1341 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1342 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1343 1344 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1345 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1346 1347 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 1348 int is_host); 1349 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1350 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 1351 1352 void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 1353 void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg, bool remotewakeup); 1354 1355 /* This function should be called on every hardware interrupt. */ 1356 irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1357 1358 /* The device ID match table */ 1359 extern const struct of_device_id dwc2_of_match_table[]; 1360 extern const struct acpi_device_id dwc2_acpi_match[]; 1361 extern const struct pci_device_id dwc2_pci_ids[]; 1362 1363 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1364 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1365 1366 /* Common polling functions */ 1367 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1368 u32 timeout); 1369 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1370 u32 timeout); 1371 /* Parameters */ 1372 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1373 int dwc2_init_params(struct dwc2_hsotg *hsotg); 1374 1375 /* 1376 * The following functions check the controller's OTG operation mode 1377 * capability (GHWCFG2.OTG_MODE). 1378 * 1379 * These functions can be used before the internal hsotg->hw_params 1380 * are read in and cached so they always read directly from the 1381 * GHWCFG2 register. 1382 */ 1383 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1384 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1385 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1386 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1387 1388 /* 1389 * Returns the mode of operation, host or device 1390 */ 1391 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1392 { 1393 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1394 } 1395 1396 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1397 { 1398 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1399 } 1400 1401 int dwc2_drd_init(struct dwc2_hsotg *hsotg); 1402 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg); 1403 void dwc2_drd_resume(struct dwc2_hsotg *hsotg); 1404 void dwc2_drd_exit(struct dwc2_hsotg *hsotg); 1405 1406 /* 1407 * Dump core registers and SPRAM 1408 */ 1409 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1410 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1411 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1412 1413 /* Gadget defines */ 1414 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1415 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1416 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1417 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1418 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1419 int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 1420 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1421 bool reset); 1422 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg); 1423 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1424 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1425 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1426 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1427 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled) 1428 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1429 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, unsigned int flags); 1430 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1431 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1432 int rem_wakeup, int reset); 1433 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1434 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1435 bool restore); 1436 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); 1437 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1438 int rem_wakeup); 1439 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1440 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1441 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1442 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1443 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); 1444 int dwc2_gadget_backup_critical_registers(struct dwc2_hsotg *hsotg); 1445 int dwc2_gadget_restore_critical_registers(struct dwc2_hsotg *hsotg, 1446 unsigned int flags); 1447 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) 1448 { hsotg->fifo_map = 0; } 1449 #else 1450 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1451 { return 0; } 1452 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1453 { return 0; } 1454 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1455 { return 0; } 1456 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1457 { return 0; } 1458 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1459 bool reset) {} 1460 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {} 1461 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1462 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1463 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1464 int testmode) 1465 { return 0; } 1466 #define dwc2_is_device_connected(hsotg) (0) 1467 #define dwc2_is_device_enabled(hsotg) (0) 1468 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1469 { return 0; } 1470 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 1471 unsigned int flags) 1472 { return 0; } 1473 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1474 { return 0; } 1475 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1476 int rem_wakeup, int reset) 1477 { return 0; } 1478 static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1479 { return 0; } 1480 static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1481 bool restore) 1482 { return 0; } 1483 static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1484 static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1485 int rem_wakeup) {} 1486 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1487 { return 0; } 1488 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1489 { return 0; } 1490 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1491 { return 0; } 1492 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1493 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} 1494 static inline int dwc2_gadget_backup_critical_registers(struct dwc2_hsotg *hsotg) 1495 { return 0; } 1496 static inline int dwc2_gadget_restore_critical_registers(struct dwc2_hsotg *hsotg, 1497 unsigned int flags) 1498 { return 0; } 1499 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {} 1500 #endif 1501 1502 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1503 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1504 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1505 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1506 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1507 void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1508 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 1509 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex); 1510 int dwc2_port_resume(struct dwc2_hsotg *hsotg); 1511 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1512 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1513 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1514 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1515 int rem_wakeup, int reset); 1516 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1517 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1518 int rem_wakeup, bool restore); 1519 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg); 1520 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup); 1521 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); 1522 int dwc2_host_backup_critical_registers(struct dwc2_hsotg *hsotg); 1523 int dwc2_host_restore_critical_registers(struct dwc2_hsotg *hsotg); 1524 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) 1525 { schedule_work(&hsotg->phy_reset_work); } 1526 #else 1527 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1528 { return 0; } 1529 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1530 int us) 1531 { return 0; } 1532 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1533 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1534 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1535 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1536 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 1537 { return 0; } 1538 static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1539 { return 0; } 1540 static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg) 1541 { return 0; } 1542 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1543 { return 0; } 1544 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1545 { return 0; } 1546 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1547 { return 0; } 1548 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1549 { return 0; } 1550 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1551 int rem_wakeup, int reset) 1552 { return 0; } 1553 static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1554 { return 0; } 1555 static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1556 int rem_wakeup, bool restore) 1557 { return 0; } 1558 static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1559 static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, 1560 int rem_wakeup) {} 1561 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 1562 { return false; } 1563 static inline int dwc2_host_backup_critical_registers(struct dwc2_hsotg *hsotg) 1564 { return 0; } 1565 static inline int dwc2_host_restore_critical_registers(struct dwc2_hsotg *hsotg) 1566 { return 0; } 1567 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} 1568 1569 #endif 1570 1571 #endif /* __DWC2_CORE_H__ */ 1572