1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 #ifdef DWC2_LOG_WRITES 48 static inline void do_write(u32 value, void *addr) 49 { 50 writel(value, addr); 51 pr_info("INFO:: wrote %08x to %p\n", value, addr); 52 } 53 54 #undef writel 55 #define writel(v, a) do_write(v, a) 56 #endif 57 58 /* Maximum number of Endpoints/HostChannels */ 59 #define MAX_EPS_CHANNELS 16 60 61 /* s3c-hsotg declarations */ 62 static const char * const s3c_hsotg_supply_names[] = { 63 "vusb_d", /* digital USB supply, 1.2V */ 64 "vusb_a", /* analog USB supply, 1.1V */ 65 }; 66 67 /* 68 * EP0_MPS_LIMIT 69 * 70 * Unfortunately there seems to be a limit of the amount of data that can 71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72 * packets (which practically means 1 packet and 63 bytes of data) when the 73 * MPS is set to 64. 74 * 75 * This means if we are wanting to move >127 bytes of data, we need to 76 * split the transactions up, but just doing one packet at a time does 77 * not work (this may be an implicit DATA0 PID on first packet of the 78 * transaction) and doing 2 packets is outside the controller's limits. 79 * 80 * If we try to lower the MPS size for EP0, then no transfers work properly 81 * for EP0, and the system will fail basic enumeration. As no cause for this 82 * has currently been found, we cannot support any large IN transfers for 83 * EP0. 84 */ 85 #define EP0_MPS_LIMIT 64 86 87 struct dwc2_hsotg; 88 struct s3c_hsotg_req; 89 90 /** 91 * struct s3c_hsotg_ep - driver endpoint definition. 92 * @ep: The gadget layer representation of the endpoint. 93 * @name: The driver generated name for the endpoint. 94 * @queue: Queue of requests for this endpoint. 95 * @parent: Reference back to the parent device structure. 96 * @req: The current request that the endpoint is processing. This is 97 * used to indicate an request has been loaded onto the endpoint 98 * and has yet to be completed (maybe due to data move, or simply 99 * awaiting an ack from the core all the data has been completed). 100 * @debugfs: File entry for debugfs file for this endpoint. 101 * @lock: State lock to protect contents of endpoint. 102 * @dir_in: Set to true if this endpoint is of the IN direction, which 103 * means that it is sending data to the Host. 104 * @index: The index for the endpoint registers. 105 * @mc: Multi Count - number of transactions per microframe 106 * @interval - Interval for periodic endpoints 107 * @name: The name array passed to the USB core. 108 * @halted: Set if the endpoint has been halted. 109 * @periodic: Set if this is a periodic ep, such as Interrupt 110 * @isochronous: Set if this is a isochronous ep 111 * @send_zlp: Set if we need to send a zero-length packet. 112 * @total_data: The total number of data bytes done. 113 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115 * @last_load: The offset of data for the last start of request. 116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117 * 118 * This is the driver's state for each registered enpoint, allowing it 119 * to keep track of transactions that need doing. Each endpoint has a 120 * lock to protect the state, to try and avoid using an overall lock 121 * for the host controller as much as possible. 122 * 123 * For periodic IN endpoints, we have fifo_size and fifo_load to try 124 * and keep track of the amount of data in the periodic FIFO for each 125 * of these as we don't have a status register that tells us how much 126 * is in each of them. (note, this may actually be useless information 127 * as in shared-fifo mode periodic in acts like a single-frame packet 128 * buffer than a fifo) 129 */ 130 struct s3c_hsotg_ep { 131 struct usb_ep ep; 132 struct list_head queue; 133 struct dwc2_hsotg *parent; 134 struct s3c_hsotg_req *req; 135 struct dentry *debugfs; 136 137 unsigned long total_data; 138 unsigned int size_loaded; 139 unsigned int last_load; 140 unsigned int fifo_load; 141 unsigned short fifo_size; 142 unsigned short fifo_index; 143 144 unsigned char dir_in; 145 unsigned char index; 146 unsigned char mc; 147 unsigned char interval; 148 149 unsigned int halted:1; 150 unsigned int periodic:1; 151 unsigned int isochronous:1; 152 unsigned int send_zlp:1; 153 154 char name[10]; 155 }; 156 157 /** 158 * struct s3c_hsotg_req - data transfer request 159 * @req: The USB gadget request 160 * @queue: The list of requests for the endpoint this is queued for. 161 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 162 */ 163 struct s3c_hsotg_req { 164 struct usb_request req; 165 struct list_head queue; 166 void *saved_req_buf; 167 }; 168 169 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 170 #define call_gadget(_hs, _entry) \ 171 do { \ 172 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 173 (_hs)->driver && (_hs)->driver->_entry) { \ 174 spin_unlock(&_hs->lock); \ 175 (_hs)->driver->_entry(&(_hs)->gadget); \ 176 spin_lock(&_hs->lock); \ 177 } \ 178 } while (0) 179 #else 180 #define call_gadget(_hs, _entry) do {} while (0) 181 #endif 182 183 struct dwc2_hsotg; 184 struct dwc2_host_chan; 185 186 /* Device States */ 187 enum dwc2_lx_state { 188 DWC2_L0, /* On state */ 189 DWC2_L1, /* LPM sleep state */ 190 DWC2_L2, /* USB suspend state */ 191 DWC2_L3, /* Off state */ 192 }; 193 194 /* 195 * Gadget periodic tx fifo sizes as used by legacy driver 196 * EP0 is not included 197 */ 198 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 199 768, 0, 0, 0, 0, 0, 0, 0} 200 201 /* Gadget ep0 states */ 202 enum dwc2_ep0_state { 203 DWC2_EP0_SETUP, 204 DWC2_EP0_DATA_IN, 205 DWC2_EP0_DATA_OUT, 206 DWC2_EP0_STATUS_IN, 207 DWC2_EP0_STATUS_OUT, 208 }; 209 210 /** 211 * struct dwc2_core_params - Parameters for configuring the core 212 * 213 * @otg_cap: Specifies the OTG capabilities. 214 * 0 - HNP and SRP capable 215 * 1 - SRP Only capable 216 * 2 - No HNP/SRP capable (always available) 217 * Defaults to best available option (0, 1, then 2) 218 * @otg_ver: OTG version supported 219 * 0 - 1.3 (default) 220 * 1 - 2.0 221 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 222 * the data FIFOs. The driver will automatically detect the 223 * value for this parameter if none is specified. 224 * 0 - Slave (always available) 225 * 1 - DMA (default, if available) 226 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 227 * address DMA mode or descriptor DMA mode for accessing 228 * the data FIFOs. The driver will automatically detect the 229 * value for this if none is specified. 230 * 0 - Address DMA 231 * 1 - Descriptor DMA (default, if available) 232 * @speed: Specifies the maximum speed of operation in host and 233 * device mode. The actual speed depends on the speed of 234 * the attached device and the value of phy_type. 235 * 0 - High Speed 236 * (default when phy_type is UTMI+ or ULPI) 237 * 1 - Full Speed 238 * (default when phy_type is Full Speed) 239 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 240 * 1 - Allow dynamic FIFO sizing (default, if available) 241 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 242 * are enabled 243 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 244 * dynamic FIFO sizing is enabled 245 * 16 to 32768 246 * Actual maximum value is autodetected and also 247 * the default. 248 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 249 * in host mode when dynamic FIFO sizing is enabled 250 * 16 to 32768 251 * Actual maximum value is autodetected and also 252 * the default. 253 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 254 * host mode when dynamic FIFO sizing is enabled 255 * 16 to 32768 256 * Actual maximum value is autodetected and also 257 * the default. 258 * @max_transfer_size: The maximum transfer size supported, in bytes 259 * 2047 to 65,535 260 * Actual maximum value is autodetected and also 261 * the default. 262 * @max_packet_count: The maximum number of packets in a transfer 263 * 15 to 511 264 * Actual maximum value is autodetected and also 265 * the default. 266 * @host_channels: The number of host channel registers to use 267 * 1 to 16 268 * Actual maximum value is autodetected and also 269 * the default. 270 * @phy_type: Specifies the type of PHY interface to use. By default, 271 * the driver will automatically detect the phy_type. 272 * 0 - Full Speed Phy 273 * 1 - UTMI+ Phy 274 * 2 - ULPI Phy 275 * Defaults to best available option (2, 1, then 0) 276 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 277 * is applicable for a phy_type of UTMI+ or ULPI. (For a 278 * ULPI phy_type, this parameter indicates the data width 279 * between the MAC and the ULPI Wrapper.) Also, this 280 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 281 * parameter was set to "8 and 16 bits", meaning that the 282 * core has been configured to work at either data path 283 * width. 284 * 8 or 16 (default 16 if available) 285 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 286 * data rate. This parameter is only applicable if phy_type 287 * is ULPI. 288 * 0 - single data rate ULPI interface with 8 bit wide 289 * data bus (default) 290 * 1 - double data rate ULPI interface with 4 bit wide 291 * data bus 292 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 293 * external supply to drive the VBus 294 * 0 - Internal supply (default) 295 * 1 - External supply 296 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 297 * speed PHY. This parameter is only applicable if phy_type 298 * is FS. 299 * 0 - No (default) 300 * 1 - Yes 301 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 302 * 0 - No (default) 303 * 1 - Yes 304 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 305 * when attached to a Full Speed or Low Speed device in 306 * host mode. 307 * 0 - Don't support low power mode (default) 308 * 1 - Support low power mode 309 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 310 * when connected to a Low Speed device in host 311 * mode. This parameter is applicable only if 312 * host_support_fs_ls_low_power is enabled. 313 * 0 - 48 MHz 314 * (default when phy_type is UTMI+ or ULPI) 315 * 1 - 6 MHz 316 * (default when phy_type is Full Speed) 317 * @ts_dline: Enable Term Select Dline pulsing 318 * 0 - No (default) 319 * 1 - Yes 320 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 321 * 0 - No (default for core < 2.92a) 322 * 1 - Yes (default for core >= 2.92a) 323 * @ahbcfg: This field allows the default value of the GAHBCFG 324 * register to be overridden 325 * -1 - GAHBCFG value will be set to 0x06 326 * (INCR4, default) 327 * all others - GAHBCFG value will be overridden with 328 * this value 329 * Not all bits can be controlled like this, the 330 * bits defined by GAHBCFG_CTRL_MASK are controlled 331 * by the driver and are ignored in this 332 * configuration value. 333 * @uframe_sched: True to enable the microframe scheduler 334 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 335 * Disable CONIDSTSCHNG controller interrupt in such 336 * case. 337 * 0 - No (default) 338 * 1 - Yes 339 * @hibernation: Specifies whether the controller support hibernation. 340 * If hibernation is enabled, the controller will enter 341 * hibernation in both peripheral and host mode when 342 * needed. 343 * 0 - No (default) 344 * 1 - Yes 345 * 346 * The following parameters may be specified when starting the module. These 347 * parameters define how the DWC_otg controller should be configured. A 348 * value of -1 (or any other out of range value) for any parameter means 349 * to read the value from hardware (if possible) or use the builtin 350 * default described above. 351 */ 352 struct dwc2_core_params { 353 /* 354 * Don't add any non-int members here, this will break 355 * dwc2_set_all_params! 356 */ 357 int otg_cap; 358 int otg_ver; 359 int dma_enable; 360 int dma_desc_enable; 361 int speed; 362 int enable_dynamic_fifo; 363 int en_multiple_tx_fifo; 364 int host_rx_fifo_size; 365 int host_nperio_tx_fifo_size; 366 int host_perio_tx_fifo_size; 367 int max_transfer_size; 368 int max_packet_count; 369 int host_channels; 370 int phy_type; 371 int phy_utmi_width; 372 int phy_ulpi_ddr; 373 int phy_ulpi_ext_vbus; 374 int i2c_enable; 375 int ulpi_fs_ls; 376 int host_support_fs_ls_low_power; 377 int host_ls_low_power_phy_clk; 378 int ts_dline; 379 int reload_ctl; 380 int ahbcfg; 381 int uframe_sched; 382 int external_id_pin_ctl; 383 int hibernation; 384 }; 385 386 /** 387 * struct dwc2_hw_params - Autodetected parameters. 388 * 389 * These parameters are the various parameters read from hardware 390 * registers during initialization. They typically contain the best 391 * supported or maximum value that can be configured in the 392 * corresponding dwc2_core_params value. 393 * 394 * The values that are not in dwc2_core_params are documented below. 395 * 396 * @op_mode Mode of Operation 397 * 0 - HNP- and SRP-Capable OTG (Host & Device) 398 * 1 - SRP-Capable OTG (Host & Device) 399 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 400 * 3 - SRP-Capable Device 401 * 4 - Non-OTG Device 402 * 5 - SRP-Capable Host 403 * 6 - Non-OTG Host 404 * @arch Architecture 405 * 0 - Slave only 406 * 1 - External DMA 407 * 2 - Internal DMA 408 * @power_optimized Are power optimizations enabled? 409 * @num_dev_ep Number of device endpoints available 410 * @num_dev_perio_in_ep Number of device periodic IN endpoints 411 * available 412 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 413 * Depth 414 * 0 to 30 415 * @host_perio_tx_q_depth 416 * Host Mode Periodic Request Queue Depth 417 * 2, 4 or 8 418 * @nperio_tx_q_depth 419 * Non-Periodic Request Queue Depth 420 * 2, 4 or 8 421 * @hs_phy_type High-speed PHY interface type 422 * 0 - High-speed interface not supported 423 * 1 - UTMI+ 424 * 2 - ULPI 425 * 3 - UTMI+ and ULPI 426 * @fs_phy_type Full-speed PHY interface type 427 * 0 - Full speed interface not supported 428 * 1 - Dedicated full speed interface 429 * 2 - FS pins shared with UTMI+ pins 430 * 3 - FS pins shared with ULPI pins 431 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 432 * @utmi_phy_data_width UTMI+ PHY data width 433 * 0 - 8 bits 434 * 1 - 16 bits 435 * 2 - 8 or 16 bits 436 * @snpsid: Value from SNPSID register 437 */ 438 struct dwc2_hw_params { 439 unsigned op_mode:3; 440 unsigned arch:2; 441 unsigned dma_desc_enable:1; 442 unsigned enable_dynamic_fifo:1; 443 unsigned en_multiple_tx_fifo:1; 444 unsigned host_rx_fifo_size:16; 445 unsigned host_nperio_tx_fifo_size:16; 446 unsigned host_perio_tx_fifo_size:16; 447 unsigned nperio_tx_q_depth:3; 448 unsigned host_perio_tx_q_depth:3; 449 unsigned dev_token_q_depth:5; 450 unsigned max_transfer_size:26; 451 unsigned max_packet_count:11; 452 unsigned host_channels:5; 453 unsigned hs_phy_type:2; 454 unsigned fs_phy_type:2; 455 unsigned i2c_enable:1; 456 unsigned num_dev_ep:4; 457 unsigned num_dev_perio_in_ep:4; 458 unsigned total_fifo_size:16; 459 unsigned power_optimized:1; 460 unsigned utmi_phy_data_width:2; 461 u32 snpsid; 462 }; 463 464 /* Size of control and EP0 buffers */ 465 #define DWC2_CTRL_BUFF_SIZE 8 466 467 /** 468 * struct dwc2_gregs_backup - Holds global registers state before entering partial 469 * power down 470 * @gotgctl: Backup of GOTGCTL register 471 * @gintmsk: Backup of GINTMSK register 472 * @gahbcfg: Backup of GAHBCFG register 473 * @gusbcfg: Backup of GUSBCFG register 474 * @grxfsiz: Backup of GRXFSIZ register 475 * @gnptxfsiz: Backup of GNPTXFSIZ register 476 * @gi2cctl: Backup of GI2CCTL register 477 * @hptxfsiz: Backup of HPTXFSIZ register 478 * @gdfifocfg: Backup of GDFIFOCFG register 479 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 480 * @gpwrdn: Backup of GPWRDN register 481 */ 482 struct dwc2_gregs_backup { 483 u32 gotgctl; 484 u32 gintmsk; 485 u32 gahbcfg; 486 u32 gusbcfg; 487 u32 grxfsiz; 488 u32 gnptxfsiz; 489 u32 gi2cctl; 490 u32 hptxfsiz; 491 u32 pcgcctl; 492 u32 gdfifocfg; 493 u32 dtxfsiz[MAX_EPS_CHANNELS]; 494 u32 gpwrdn; 495 }; 496 497 /** 498 * struct dwc2_dregs_backup - Holds device registers state before entering partial 499 * power down 500 * @dcfg: Backup of DCFG register 501 * @dctl: Backup of DCTL register 502 * @daintmsk: Backup of DAINTMSK register 503 * @diepmsk: Backup of DIEPMSK register 504 * @doepmsk: Backup of DOEPMSK register 505 * @diepctl: Backup of DIEPCTL register 506 * @dieptsiz: Backup of DIEPTSIZ register 507 * @diepdma: Backup of DIEPDMA register 508 * @doepctl: Backup of DOEPCTL register 509 * @doeptsiz: Backup of DOEPTSIZ register 510 * @doepdma: Backup of DOEPDMA register 511 */ 512 struct dwc2_dregs_backup { 513 u32 dcfg; 514 u32 dctl; 515 u32 daintmsk; 516 u32 diepmsk; 517 u32 doepmsk; 518 u32 diepctl[MAX_EPS_CHANNELS]; 519 u32 dieptsiz[MAX_EPS_CHANNELS]; 520 u32 diepdma[MAX_EPS_CHANNELS]; 521 u32 doepctl[MAX_EPS_CHANNELS]; 522 u32 doeptsiz[MAX_EPS_CHANNELS]; 523 u32 doepdma[MAX_EPS_CHANNELS]; 524 }; 525 526 /** 527 * struct dwc2_hregs_backup - Holds host registers state before entering partial 528 * power down 529 * @hcfg: Backup of HCFG register 530 * @haintmsk: Backup of HAINTMSK register 531 * @hcintmsk: Backup of HCINTMSK register 532 * @hptr0: Backup of HPTR0 register 533 * @hfir: Backup of HFIR register 534 */ 535 struct dwc2_hregs_backup { 536 u32 hcfg; 537 u32 haintmsk; 538 u32 hcintmsk[MAX_EPS_CHANNELS]; 539 u32 hprt0; 540 u32 hfir; 541 }; 542 543 /** 544 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 545 * and periodic schedules 546 * 547 * These are common for both host and peripheral modes: 548 * 549 * @dev: The struct device pointer 550 * @regs: Pointer to controller regs 551 * @hw_params: Parameters that were autodetected from the 552 * hardware registers 553 * @core_params: Parameters that define how the core should be configured 554 * @op_state: The operational State, during transitions (a_host=> 555 * a_peripheral and b_device=>b_host) this may not match 556 * the core, but allows the software to determine 557 * transitions 558 * @dr_mode: Requested mode of operation, one of following: 559 * - USB_DR_MODE_PERIPHERAL 560 * - USB_DR_MODE_HOST 561 * - USB_DR_MODE_OTG 562 * @lock: Spinlock that protects all the driver data structures 563 * @priv: Stores a pointer to the struct usb_hcd 564 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 565 * transfer are in process of being queued 566 * @srp_success: Stores status of SRP request in the case of a FS PHY 567 * with an I2C interface 568 * @wq_otg: Workqueue object used for handling of some interrupts 569 * @wf_otg: Work object for handling Connector ID Status Change 570 * interrupt 571 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 572 * @lx_state: Lx state of connected device 573 * @gregs_backup: Backup of global registers during suspend 574 * @dregs_backup: Backup of device registers during suspend 575 * @hregs_backup: Backup of host registers during suspend 576 * 577 * These are for host mode: 578 * 579 * @flags: Flags for handling root port state changes 580 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 581 * Transfers associated with these QHs are not currently 582 * assigned to a host channel. 583 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 584 * Transfers associated with these QHs are currently 585 * assigned to a host channel. 586 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 587 * non-periodic schedule 588 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 589 * list of QHs for periodic transfers that are _not_ 590 * scheduled for the next frame. Each QH in the list has an 591 * interval counter that determines when it needs to be 592 * scheduled for execution. This scheduling mechanism 593 * allows only a simple calculation for periodic bandwidth 594 * used (i.e. must assume that all periodic transfers may 595 * need to execute in the same frame). However, it greatly 596 * simplifies scheduling and should be sufficient for the 597 * vast majority of OTG hosts, which need to connect to a 598 * small number of peripherals at one time. Items move from 599 * this list to periodic_sched_ready when the QH interval 600 * counter is 0 at SOF. 601 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 602 * the next frame, but have not yet been assigned to host 603 * channels. Items move from this list to 604 * periodic_sched_assigned as host channels become 605 * available during the current frame. 606 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 607 * frame that are assigned to host channels. Items move 608 * from this list to periodic_sched_queued as the 609 * transactions for the QH are queued to the DWC_otg 610 * controller. 611 * @periodic_sched_queued: List of periodic QHs that have been queued for 612 * execution. Items move from this list to either 613 * periodic_sched_inactive or periodic_sched_ready when the 614 * channel associated with the transfer is released. If the 615 * interval for the QH is 1, the item moves to 616 * periodic_sched_ready because it must be rescheduled for 617 * the next frame. Otherwise, the item moves to 618 * periodic_sched_inactive. 619 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 620 * This value is in microseconds per (micro)frame. The 621 * assumption is that all periodic transfers may occur in 622 * the same (micro)frame. 623 * @frame_usecs: Internal variable used by the microframe scheduler 624 * @frame_number: Frame number read from the core at SOF. The value ranges 625 * from 0 to HFNUM_MAX_FRNUM. 626 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 627 * SOF enable/disable. 628 * @free_hc_list: Free host channels in the controller. This is a list of 629 * struct dwc2_host_chan items. 630 * @periodic_channels: Number of host channels assigned to periodic transfers. 631 * Currently assuming that there is a dedicated host 632 * channel for each periodic transaction and at least one 633 * host channel is available for non-periodic transactions. 634 * @non_periodic_channels: Number of host channels assigned to non-periodic 635 * transfers 636 * @available_host_channels Number of host channels available for the microframe 637 * scheduler to use 638 * @hc_ptr_array: Array of pointers to the host channel descriptors. 639 * Allows accessing a host channel descriptor given the 640 * host channel number. This is useful in interrupt 641 * handlers. 642 * @status_buf: Buffer used for data received during the status phase of 643 * a control transfer. 644 * @status_buf_dma: DMA address for status_buf 645 * @start_work: Delayed work for handling host A-cable connection 646 * @reset_work: Delayed work for handling a port reset 647 * @otg_port: OTG port number 648 * @frame_list: Frame list 649 * @frame_list_dma: Frame list DMA address 650 * 651 * These are for peripheral mode: 652 * 653 * @driver: USB gadget driver 654 * @phy: The otg phy transceiver structure for phy control. 655 * @uphy: The otg phy transceiver structure for old USB phy control. 656 * @plat: The platform specific configuration data. This can be removed once 657 * all SoCs support usb transceiver. 658 * @supplies: Definition of USB power supplies 659 * @phyif: PHY interface width 660 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 661 * @num_of_eps: Number of available EPs (excluding EP0) 662 * @debug_root: Root directrory for debugfs. 663 * @debug_file: Main status file for debugfs. 664 * @debug_testmode: Testmode status file for debugfs. 665 * @debug_fifo: FIFO status file for debugfs. 666 * @ep0_reply: Request used for ep0 reply. 667 * @ep0_buff: Buffer for EP0 reply data, if needed. 668 * @ctrl_buff: Buffer for EP0 control requests. 669 * @ctrl_req: Request for EP0 control packets. 670 * @ep0_state: EP0 control transfers state 671 * @test_mode: USB test mode requested by the host 672 * @last_rst: Time of last reset 673 * @eps: The endpoints being supplied to the gadget framework 674 * @g_using_dma: Indicate if dma usage is enabled 675 * @g_rx_fifo_sz: Contains rx fifo size value 676 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 677 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 678 */ 679 struct dwc2_hsotg { 680 struct device *dev; 681 void __iomem *regs; 682 /** Params detected from hardware */ 683 struct dwc2_hw_params hw_params; 684 /** Params to actually use */ 685 struct dwc2_core_params *core_params; 686 enum usb_otg_state op_state; 687 enum usb_dr_mode dr_mode; 688 unsigned int hcd_enabled:1; 689 unsigned int gadget_enabled:1; 690 691 struct phy *phy; 692 struct usb_phy *uphy; 693 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 694 695 spinlock_t lock; 696 struct mutex init_mutex; 697 void *priv; 698 int irq; 699 struct clk *clk; 700 701 unsigned int queuing_high_bandwidth:1; 702 unsigned int srp_success:1; 703 704 struct workqueue_struct *wq_otg; 705 struct work_struct wf_otg; 706 struct timer_list wkp_timer; 707 enum dwc2_lx_state lx_state; 708 struct dwc2_gregs_backup *gr_backup; 709 struct dwc2_dregs_backup *dr_backup; 710 struct dwc2_hregs_backup *hr_backup; 711 712 struct dentry *debug_root; 713 struct debugfs_regset32 *regset; 714 715 /* DWC OTG HW Release versions */ 716 #define DWC2_CORE_REV_2_71a 0x4f54271a 717 #define DWC2_CORE_REV_2_90a 0x4f54290a 718 #define DWC2_CORE_REV_2_92a 0x4f54292a 719 #define DWC2_CORE_REV_2_94a 0x4f54294a 720 #define DWC2_CORE_REV_3_00a 0x4f54300a 721 722 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 723 union dwc2_hcd_internal_flags { 724 u32 d32; 725 struct { 726 unsigned port_connect_status_change:1; 727 unsigned port_connect_status:1; 728 unsigned port_reset_change:1; 729 unsigned port_enable_change:1; 730 unsigned port_suspend_change:1; 731 unsigned port_over_current_change:1; 732 unsigned port_l1_change:1; 733 unsigned reserved:25; 734 } b; 735 } flags; 736 737 struct list_head non_periodic_sched_inactive; 738 struct list_head non_periodic_sched_active; 739 struct list_head *non_periodic_qh_ptr; 740 struct list_head periodic_sched_inactive; 741 struct list_head periodic_sched_ready; 742 struct list_head periodic_sched_assigned; 743 struct list_head periodic_sched_queued; 744 u16 periodic_usecs; 745 u16 frame_usecs[8]; 746 u16 frame_number; 747 u16 periodic_qh_count; 748 749 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 750 #define FRAME_NUM_ARRAY_SIZE 1000 751 u16 last_frame_num; 752 u16 *frame_num_array; 753 u16 *last_frame_num_array; 754 int frame_num_idx; 755 int dumped_frame_num_array; 756 #endif 757 758 struct list_head free_hc_list; 759 int periodic_channels; 760 int non_periodic_channels; 761 int available_host_channels; 762 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 763 u8 *status_buf; 764 dma_addr_t status_buf_dma; 765 #define DWC2_HCD_STATUS_BUF_SIZE 64 766 767 struct delayed_work start_work; 768 struct delayed_work reset_work; 769 u8 otg_port; 770 u32 *frame_list; 771 dma_addr_t frame_list_dma; 772 773 #ifdef DEBUG 774 u32 frrem_samples; 775 u64 frrem_accum; 776 777 u32 hfnum_7_samples_a; 778 u64 hfnum_7_frrem_accum_a; 779 u32 hfnum_0_samples_a; 780 u64 hfnum_0_frrem_accum_a; 781 u32 hfnum_other_samples_a; 782 u64 hfnum_other_frrem_accum_a; 783 784 u32 hfnum_7_samples_b; 785 u64 hfnum_7_frrem_accum_b; 786 u32 hfnum_0_samples_b; 787 u64 hfnum_0_frrem_accum_b; 788 u32 hfnum_other_samples_b; 789 u64 hfnum_other_frrem_accum_b; 790 #endif 791 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 792 793 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 794 /* Gadget structures */ 795 struct usb_gadget_driver *driver; 796 struct s3c_hsotg_plat *plat; 797 798 u32 phyif; 799 int fifo_mem; 800 unsigned int dedicated_fifos:1; 801 unsigned char num_of_eps; 802 u32 fifo_map; 803 804 struct usb_request *ep0_reply; 805 struct usb_request *ctrl_req; 806 void *ep0_buff; 807 void *ctrl_buff; 808 enum dwc2_ep0_state ep0_state; 809 u8 test_mode; 810 811 struct usb_gadget gadget; 812 unsigned int enabled:1; 813 unsigned int connected:1; 814 unsigned long last_rst; 815 struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 816 struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 817 u32 g_using_dma; 818 u32 g_rx_fifo_sz; 819 u32 g_np_g_tx_fifo_sz; 820 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 821 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 822 }; 823 824 /* Reasons for halting a host channel */ 825 enum dwc2_halt_status { 826 DWC2_HC_XFER_NO_HALT_STATUS, 827 DWC2_HC_XFER_COMPLETE, 828 DWC2_HC_XFER_URB_COMPLETE, 829 DWC2_HC_XFER_ACK, 830 DWC2_HC_XFER_NAK, 831 DWC2_HC_XFER_NYET, 832 DWC2_HC_XFER_STALL, 833 DWC2_HC_XFER_XACT_ERR, 834 DWC2_HC_XFER_FRAME_OVERRUN, 835 DWC2_HC_XFER_BABBLE_ERR, 836 DWC2_HC_XFER_DATA_TOGGLE_ERR, 837 DWC2_HC_XFER_AHB_ERR, 838 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 839 DWC2_HC_XFER_URB_DEQUEUE, 840 }; 841 842 /* 843 * The following functions support initialization of the core driver component 844 * and the DWC_otg controller 845 */ 846 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 847 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 848 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 849 850 /* 851 * Host core Functions. 852 * The following functions support managing the DWC_otg controller in host 853 * mode. 854 */ 855 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 856 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 857 enum dwc2_halt_status halt_status); 858 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 859 struct dwc2_host_chan *chan); 860 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 861 struct dwc2_host_chan *chan); 862 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 863 struct dwc2_host_chan *chan); 864 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 865 struct dwc2_host_chan *chan); 866 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 867 struct dwc2_host_chan *chan); 868 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 869 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 870 871 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 872 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 873 874 /* 875 * Common core Functions. 876 * The following functions support managing the DWC_otg controller in either 877 * device or host mode. 878 */ 879 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 880 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 881 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 882 883 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 884 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 885 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 886 887 /* This function should be called on every hardware interrupt. */ 888 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 889 890 /* OTG Core Parameters */ 891 892 /* 893 * Specifies the OTG capabilities. The driver will automatically 894 * detect the value for this parameter if none is specified. 895 * 0 - HNP and SRP capable (default) 896 * 1 - SRP Only capable 897 * 2 - No HNP/SRP capable 898 */ 899 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 900 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 901 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 902 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 903 904 /* 905 * Specifies whether to use slave or DMA mode for accessing the data 906 * FIFOs. The driver will automatically detect the value for this 907 * parameter if none is specified. 908 * 0 - Slave 909 * 1 - DMA (default, if available) 910 */ 911 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 912 913 /* 914 * When DMA mode is enabled specifies whether to use 915 * address DMA or DMA Descritor mode for accessing the data 916 * FIFOs in device mode. The driver will automatically detect 917 * the value for this parameter if none is specified. 918 * 0 - address DMA 919 * 1 - DMA Descriptor(default, if available) 920 */ 921 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 922 923 /* 924 * Specifies the maximum speed of operation in host and device mode. 925 * The actual speed depends on the speed of the attached device and 926 * the value of phy_type. The actual speed depends on the speed of the 927 * attached device. 928 * 0 - High Speed (default) 929 * 1 - Full Speed 930 */ 931 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 932 #define DWC2_SPEED_PARAM_HIGH 0 933 #define DWC2_SPEED_PARAM_FULL 1 934 935 /* 936 * Specifies whether low power mode is supported when attached 937 * to a Full Speed or Low Speed device in host mode. 938 * 939 * 0 - Don't support low power mode (default) 940 * 1 - Support low power mode 941 */ 942 extern void dwc2_set_param_host_support_fs_ls_low_power( 943 struct dwc2_hsotg *hsotg, int val); 944 945 /* 946 * Specifies the PHY clock rate in low power mode when connected to a 947 * Low Speed device in host mode. This parameter is applicable only if 948 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 949 * then defaults to 6 MHZ otherwise 48 MHZ. 950 * 951 * 0 - 48 MHz 952 * 1 - 6 MHz 953 */ 954 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 955 int val); 956 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 957 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 958 959 /* 960 * 0 - Use cC FIFO size parameters 961 * 1 - Allow dynamic FIFO sizing (default) 962 */ 963 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 964 int val); 965 966 /* 967 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 968 * FIFO sizing is enabled. 969 * 16 to 32768 (default 1024) 970 */ 971 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 972 973 /* 974 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 975 * when Dynamic FIFO sizing is enabled in the core. 976 * 16 to 32768 (default 256) 977 */ 978 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 979 int val); 980 981 /* 982 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 983 * FIFO sizing is enabled. 984 * 16 to 32768 (default 256) 985 */ 986 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 987 int val); 988 989 /* 990 * The maximum transfer size supported in bytes. 991 * 2047 to 65,535 (default 65,535) 992 */ 993 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 994 995 /* 996 * The maximum number of packets in a transfer. 997 * 15 to 511 (default 511) 998 */ 999 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1000 1001 /* 1002 * The number of host channel registers to use. 1003 * 1 to 16 (default 11) 1004 * Note: The FPGA configuration supports a maximum of 11 host channels. 1005 */ 1006 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1007 1008 /* 1009 * Specifies the type of PHY interface to use. By default, the driver 1010 * will automatically detect the phy_type. 1011 * 1012 * 0 - Full Speed PHY 1013 * 1 - UTMI+ (default) 1014 * 2 - ULPI 1015 */ 1016 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1017 #define DWC2_PHY_TYPE_PARAM_FS 0 1018 #define DWC2_PHY_TYPE_PARAM_UTMI 1 1019 #define DWC2_PHY_TYPE_PARAM_ULPI 2 1020 1021 /* 1022 * Specifies the UTMI+ Data Width. This parameter is 1023 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1024 * PHY_TYPE, this parameter indicates the data width between 1025 * the MAC and the ULPI Wrapper.) Also, this parameter is 1026 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1027 * to "8 and 16 bits", meaning that the core has been 1028 * configured to work at either data path width. 1029 * 1030 * 8 or 16 bits (default 16) 1031 */ 1032 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1033 1034 /* 1035 * Specifies whether the ULPI operates at double or single 1036 * data rate. This parameter is only applicable if PHY_TYPE is 1037 * ULPI. 1038 * 1039 * 0 - single data rate ULPI interface with 8 bit wide data 1040 * bus (default) 1041 * 1 - double data rate ULPI interface with 4 bit wide data 1042 * bus 1043 */ 1044 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1045 1046 /* 1047 * Specifies whether to use the internal or external supply to 1048 * drive the vbus with a ULPI phy. 1049 */ 1050 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1051 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1052 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1053 1054 /* 1055 * Specifies whether to use the I2Cinterface for full speed PHY. This 1056 * parameter is only applicable if PHY_TYPE is FS. 1057 * 0 - No (default) 1058 * 1 - Yes 1059 */ 1060 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1061 1062 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1063 1064 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1065 1066 /* 1067 * Specifies whether dedicated transmit FIFOs are 1068 * enabled for non periodic IN endpoints in device mode 1069 * 0 - No 1070 * 1 - Yes 1071 */ 1072 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1073 int val); 1074 1075 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1076 1077 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1078 1079 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1080 1081 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1082 const struct dwc2_core_params *params); 1083 1084 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1085 1086 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1087 1088 1089 1090 /* 1091 * Dump core registers and SPRAM 1092 */ 1093 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1094 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1095 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1096 1097 /* 1098 * Return OTG version - either 1.3 or 2.0 1099 */ 1100 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1101 1102 /* Gadget defines */ 1103 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1104 extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg); 1105 extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2); 1106 extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2); 1107 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1108 extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1109 bool reset); 1110 extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1111 extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1112 extern int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1113 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1114 #else 1115 static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2) 1116 { return 0; } 1117 static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2) 1118 { return 0; } 1119 static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2) 1120 { return 0; } 1121 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1122 { return 0; } 1123 static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1124 bool reset) {} 1125 static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1126 static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1127 static inline int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1128 int testmode) 1129 { return 0; } 1130 #define dwc2_is_device_connected(hsotg) (0) 1131 #endif 1132 1133 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1134 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1135 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 1136 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1137 #else 1138 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1139 { return 0; } 1140 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 1141 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1142 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1143 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1144 { return 0; } 1145 #endif 1146 1147 #endif /* __DWC2_CORE_H__ */ 1148