1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __SH_SCI_COMMON_H__ 4 #define __SH_SCI_COMMON_H__ 5 6 #include <linux/serial_core.h> 7 8 /* Private port IDs */ 9 enum SCI_PORT_TYPE { 10 RSCI_PORT_SCIF16 = BIT(7) | 0, 11 RSCI_PORT_SCIF32 = BIT(7) | 1, 12 RSCI_PORT_SCIF32_SINGLE_TCLK = BIT(7) | 2, 13 }; 14 15 enum SCI_CLKS { 16 SCI_FCK, /* Functional Clock */ 17 SCI_SCK, /* Optional External Clock */ 18 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 19 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 20 SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */ 21 SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */ 22 SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */ 23 SCI_NUM_CLKS 24 }; 25 26 /* Offsets into the sci_port->irqs array */ 27 enum { 28 SCIx_ERI_IRQ, 29 SCIx_RXI_IRQ, 30 SCIx_TXI_IRQ, 31 SCIx_BRI_IRQ, 32 SCIx_DRI_IRQ, 33 SCIx_TEI_IRQ, 34 SCIx_NR_IRQS, 35 36 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 37 }; 38 39 /* Bit x set means sampling rate x + 1 is supported */ 40 #define SCI_SR(x) BIT((x) - 1) 41 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 42 43 void sci_release_port(struct uart_port *port); 44 int sci_request_port(struct uart_port *port); 45 void sci_config_port(struct uart_port *port, int flags); 46 int sci_verify_port(struct uart_port *port, struct serial_struct *ser); 47 void sci_pm(struct uart_port *port, unsigned int state, 48 unsigned int oldstate); 49 50 struct plat_sci_reg { 51 u8 offset; 52 u8 size; 53 }; 54 55 struct sci_port_params_bits { 56 unsigned int rxtx_enable; 57 unsigned int te_clear; 58 unsigned int poll_sent_bits; 59 }; 60 61 struct sci_common_regs { 62 unsigned int status; 63 unsigned int control; 64 }; 65 66 /* The actual number of needed registers. This is used by sci only */ 67 #define SCI_NR_REGS 20 68 69 struct sci_port_params { 70 const struct plat_sci_reg regs[SCI_NR_REGS]; 71 const struct sci_common_regs *common_regs; 72 const struct sci_port_params_bits *param_bits; 73 unsigned int fifosize; 74 unsigned int overrun_reg; 75 unsigned int overrun_mask; 76 unsigned int sampling_rate_mask; 77 unsigned int error_mask; 78 unsigned int error_clear; 79 }; 80 81 struct sci_port_ops { 82 u32 (*read_reg)(struct uart_port *port, int reg); 83 void (*write_reg)(struct uart_port *port, int reg, int value); 84 void (*clear_SCxSR)(struct uart_port *port, unsigned int mask); 85 86 void (*transmit_chars)(struct uart_port *port); 87 void (*receive_chars)(struct uart_port *port); 88 89 void (*poll_put_char)(struct uart_port *port, unsigned char c); 90 91 int (*set_rtrg)(struct uart_port *port, int rx_trig); 92 int (*rtrg_enabled)(struct uart_port *port); 93 94 void (*shutdown_complete)(struct uart_port *port); 95 96 void (*prepare_console_write)(struct uart_port *port, u32 ctrl); 97 void (*finish_console_write)(struct uart_port *port, u32 ctrl); 98 void (*console_save)(struct uart_port *port); 99 void (*console_restore)(struct uart_port *port); 100 size_t (*suspend_regs_size)(void); 101 }; 102 103 struct sci_of_data { 104 const struct sci_port_params *params; 105 const struct uart_ops *uart_ops; 106 const struct sci_port_ops *ops; 107 unsigned short regtype; 108 unsigned short type; 109 }; 110 111 struct sci_port { 112 struct uart_port port; 113 114 /* Platform configuration */ 115 const struct sci_port_params *params; 116 const struct plat_sci_port *cfg; 117 118 unsigned int sampling_rate_mask; 119 resource_size_t reg_size; 120 struct mctrl_gpios *gpios; 121 122 /* Clocks */ 123 struct clk *clks[SCI_NUM_CLKS]; 124 unsigned long clk_rates[SCI_NUM_CLKS]; 125 126 int irqs[SCIx_NR_IRQS]; 127 char *irqstr[SCIx_NR_IRQS]; 128 129 struct dma_chan *chan_tx; 130 struct dma_chan *chan_rx; 131 132 struct reset_control *rstc; 133 struct sci_suspend_regs *suspend_regs; 134 135 #ifdef CONFIG_SERIAL_SH_SCI_DMA 136 struct dma_chan *chan_tx_saved; 137 struct dma_chan *chan_rx_saved; 138 dma_cookie_t cookie_tx; 139 dma_cookie_t cookie_rx[2]; 140 dma_cookie_t active_rx; 141 dma_addr_t tx_dma_addr; 142 unsigned int tx_dma_len; 143 struct scatterlist sg_rx[2]; 144 void *rx_buf[2]; 145 size_t buf_len_rx; 146 struct work_struct work_tx; 147 struct hrtimer rx_timer; 148 unsigned int rx_timeout; /* microseconds */ 149 #endif 150 unsigned int rx_frame; 151 int rx_trigger; 152 struct timer_list rx_fifo_timer; 153 int rx_fifo_timeout; 154 u16 hscif_tot; 155 156 u8 type; 157 u8 regtype; 158 159 const struct sci_port_ops *ops; 160 161 bool has_rtscts; 162 bool autorts; 163 bool tx_occurred; 164 }; 165 166 #define to_sci_port(uart) container_of((uart), struct sci_port, port) 167 168 void sci_port_disable(struct sci_port *sci_port); 169 void sci_port_enable(struct sci_port *sci_port); 170 171 int sci_startup(struct uart_port *port); 172 void sci_shutdown(struct uart_port *port); 173 174 int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, 175 unsigned int *srr, unsigned int *cks); 176 177 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 178 #define max_sr(_port) fls((_port)->sampling_rate_mask) 179 180 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 181 int __init scix_early_console_setup(struct earlycon_device *device, const struct sci_of_data *data); 182 #endif 183 184 #endif /* __SH_SCI_COMMON_H__ */ 185