xref: /linux/drivers/tty/serial/sh-sci-common.h (revision 378ec25aec5a8444879f8696d580c94950a1f1df)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 
3 #ifndef __SH_SCI_COMMON_H__
4 #define __SH_SCI_COMMON_H__
5 
6 #include <linux/serial_core.h>
7 
8 enum SCI_CLKS {
9 	SCI_FCK,		/* Functional Clock */
10 	SCI_SCK,		/* Optional External Clock */
11 	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
12 	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
13 	SCI_NUM_CLKS
14 };
15 
16 /* Offsets into the sci_port->irqs array */
17 enum {
18 	SCIx_ERI_IRQ,
19 	SCIx_RXI_IRQ,
20 	SCIx_TXI_IRQ,
21 	SCIx_BRI_IRQ,
22 	SCIx_DRI_IRQ,
23 	SCIx_TEI_IRQ,
24 	SCIx_NR_IRQS,
25 
26 	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
27 };
28 
29 /* Bit x set means sampling rate x + 1 is supported */
30 #define SCI_SR(x)		BIT((x) - 1)
31 #define SCI_SR_RANGE(x, y)	GENMASK((y) - 1, (x) - 1)
32 
33 void sci_release_port(struct uart_port *port);
34 int sci_request_port(struct uart_port *port);
35 void sci_config_port(struct uart_port *port, int flags);
36 int sci_verify_port(struct uart_port *port, struct serial_struct *ser);
37 void sci_pm(struct uart_port *port, unsigned int state,
38 		   unsigned int oldstate);
39 
40 struct plat_sci_reg {
41 	u8 offset;
42 	u8 size;
43 };
44 
45 struct sci_port_params_bits {
46 	unsigned int rxtx_enable;
47 	unsigned int te_clear;
48 	unsigned int poll_sent_bits;
49 };
50 
51 struct sci_common_regs {
52 	unsigned int status;
53 	unsigned int control;
54 };
55 
56 /* The actual number of needed registers. This is used by sci only */
57 #define SCI_NR_REGS 20
58 
59 struct sci_port_params {
60 	const struct plat_sci_reg regs[SCI_NR_REGS];
61 	const struct sci_common_regs *common_regs;
62 	const struct sci_port_params_bits *param_bits;
63 	unsigned int fifosize;
64 	unsigned int overrun_reg;
65 	unsigned int overrun_mask;
66 	unsigned int sampling_rate_mask;
67 	unsigned int error_mask;
68 	unsigned int error_clear;
69 };
70 
71 struct sci_port_ops {
72 	u32 (*read_reg)(struct uart_port *port, int reg);
73 	void (*write_reg)(struct uart_port *port, int reg, int value);
74 	void (*clear_SCxSR)(struct uart_port *port, unsigned int mask);
75 
76 	void (*transmit_chars)(struct uart_port *port);
77 	void (*receive_chars)(struct uart_port *port);
78 
79 	void (*poll_put_char)(struct uart_port *port, unsigned char c);
80 
81 	int (*set_rtrg)(struct uart_port *port, int rx_trig);
82 	int (*rtrg_enabled)(struct uart_port *port);
83 
84 	void (*shutdown_complete)(struct uart_port *port);
85 
86 	void (*prepare_console_write)(struct uart_port *port, u32 ctrl);
87 	void (*console_save)(struct uart_port *port);
88 	void (*console_restore)(struct uart_port *port);
89 	size_t (*suspend_regs_size)(void);
90 };
91 
92 struct sci_of_data {
93 	const struct sci_port_params *params;
94 	const struct uart_ops *uart_ops;
95 	const struct sci_port_ops *ops;
96 	unsigned short regtype;
97 	unsigned short type;
98 };
99 
100 struct sci_port {
101 	struct uart_port	port;
102 
103 	/* Platform configuration */
104 	const struct sci_port_params *params;
105 	const struct plat_sci_port *cfg;
106 
107 	unsigned int		sampling_rate_mask;
108 	resource_size_t		reg_size;
109 	struct mctrl_gpios	*gpios;
110 
111 	/* Clocks */
112 	struct clk		*clks[SCI_NUM_CLKS];
113 	unsigned long		clk_rates[SCI_NUM_CLKS];
114 
115 	int			irqs[SCIx_NR_IRQS];
116 	char			*irqstr[SCIx_NR_IRQS];
117 
118 	struct dma_chan			*chan_tx;
119 	struct dma_chan			*chan_rx;
120 
121 	struct reset_control		*rstc;
122 	struct sci_suspend_regs		*suspend_regs;
123 
124 #ifdef CONFIG_SERIAL_SH_SCI_DMA
125 	struct dma_chan			*chan_tx_saved;
126 	struct dma_chan			*chan_rx_saved;
127 	dma_cookie_t			cookie_tx;
128 	dma_cookie_t			cookie_rx[2];
129 	dma_cookie_t			active_rx;
130 	dma_addr_t			tx_dma_addr;
131 	unsigned int			tx_dma_len;
132 	struct scatterlist		sg_rx[2];
133 	void				*rx_buf[2];
134 	size_t				buf_len_rx;
135 	struct work_struct		work_tx;
136 	struct hrtimer			rx_timer;
137 	unsigned int			rx_timeout;	/* microseconds */
138 #endif
139 	unsigned int			rx_frame;
140 	int				rx_trigger;
141 	struct timer_list		rx_fifo_timer;
142 	int				rx_fifo_timeout;
143 	u16				hscif_tot;
144 
145 	const struct sci_port_ops *ops;
146 
147 	bool has_rtscts;
148 	bool autorts;
149 	bool tx_occurred;
150 };
151 
152 #define to_sci_port(uart) container_of((uart), struct sci_port, port)
153 
154 void sci_port_disable(struct sci_port *sci_port);
155 void sci_port_enable(struct sci_port *sci_port);
156 
157 int sci_startup(struct uart_port *port);
158 void sci_shutdown(struct uart_port *port);
159 
160 #define min_sr(_port)		ffs((_port)->sampling_rate_mask)
161 #define max_sr(_port)		fls((_port)->sampling_rate_mask)
162 
163 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
164 int __init scix_early_console_setup(struct earlycon_device *device, const struct sci_of_data *data);
165 #endif
166 
167 #endif /* __SH_SCI_COMMON_H__ */
168