1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __SH_SCI_COMMON_H__ 4 #define __SH_SCI_COMMON_H__ 5 6 #include <linux/serial_core.h> 7 8 /* Private port IDs */ 9 enum SCI_PORT_TYPE { 10 RSCI_PORT_SCIF16 = BIT(7) | 0, 11 RSCI_PORT_SCIF32 = BIT(7) | 1, 12 }; 13 14 enum SCI_CLKS { 15 SCI_FCK, /* Functional Clock */ 16 SCI_SCK, /* Optional External Clock */ 17 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 18 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 19 SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */ 20 SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */ 21 SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */ 22 SCI_NUM_CLKS 23 }; 24 25 /* Offsets into the sci_port->irqs array */ 26 enum { 27 SCIx_ERI_IRQ, 28 SCIx_RXI_IRQ, 29 SCIx_TXI_IRQ, 30 SCIx_BRI_IRQ, 31 SCIx_DRI_IRQ, 32 SCIx_TEI_IRQ, 33 SCIx_NR_IRQS, 34 35 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 36 }; 37 38 /* Bit x set means sampling rate x + 1 is supported */ 39 #define SCI_SR(x) BIT((x) - 1) 40 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 41 42 void sci_release_port(struct uart_port *port); 43 int sci_request_port(struct uart_port *port); 44 void sci_config_port(struct uart_port *port, int flags); 45 int sci_verify_port(struct uart_port *port, struct serial_struct *ser); 46 void sci_pm(struct uart_port *port, unsigned int state, 47 unsigned int oldstate); 48 49 struct plat_sci_reg { 50 u8 offset; 51 u8 size; 52 }; 53 54 struct sci_port_params_bits { 55 unsigned int rxtx_enable; 56 unsigned int te_clear; 57 unsigned int poll_sent_bits; 58 }; 59 60 struct sci_common_regs { 61 unsigned int status; 62 unsigned int control; 63 }; 64 65 /* The actual number of needed registers. This is used by sci only */ 66 #define SCI_NR_REGS 20 67 68 struct sci_port_params { 69 const struct plat_sci_reg regs[SCI_NR_REGS]; 70 const struct sci_common_regs *common_regs; 71 const struct sci_port_params_bits *param_bits; 72 unsigned int fifosize; 73 unsigned int overrun_reg; 74 unsigned int overrun_mask; 75 unsigned int sampling_rate_mask; 76 unsigned int error_mask; 77 unsigned int error_clear; 78 }; 79 80 struct sci_port_ops { 81 u32 (*read_reg)(struct uart_port *port, int reg); 82 void (*write_reg)(struct uart_port *port, int reg, int value); 83 void (*clear_SCxSR)(struct uart_port *port, unsigned int mask); 84 85 void (*transmit_chars)(struct uart_port *port); 86 void (*receive_chars)(struct uart_port *port); 87 88 void (*poll_put_char)(struct uart_port *port, unsigned char c); 89 90 int (*set_rtrg)(struct uart_port *port, int rx_trig); 91 int (*rtrg_enabled)(struct uart_port *port); 92 93 void (*shutdown_complete)(struct uart_port *port); 94 95 void (*prepare_console_write)(struct uart_port *port, u32 ctrl); 96 void (*finish_console_write)(struct uart_port *port, u32 ctrl); 97 void (*console_save)(struct uart_port *port); 98 void (*console_restore)(struct uart_port *port); 99 size_t (*suspend_regs_size)(void); 100 }; 101 102 struct sci_of_data { 103 const struct sci_port_params *params; 104 const struct uart_ops *uart_ops; 105 const struct sci_port_ops *ops; 106 unsigned short regtype; 107 unsigned short type; 108 }; 109 110 struct sci_port { 111 struct uart_port port; 112 113 /* Platform configuration */ 114 const struct sci_port_params *params; 115 const struct plat_sci_port *cfg; 116 117 unsigned int sampling_rate_mask; 118 resource_size_t reg_size; 119 struct mctrl_gpios *gpios; 120 121 /* Clocks */ 122 struct clk *clks[SCI_NUM_CLKS]; 123 unsigned long clk_rates[SCI_NUM_CLKS]; 124 125 int irqs[SCIx_NR_IRQS]; 126 char *irqstr[SCIx_NR_IRQS]; 127 128 struct dma_chan *chan_tx; 129 struct dma_chan *chan_rx; 130 131 struct reset_control *rstc; 132 struct sci_suspend_regs *suspend_regs; 133 134 #ifdef CONFIG_SERIAL_SH_SCI_DMA 135 struct dma_chan *chan_tx_saved; 136 struct dma_chan *chan_rx_saved; 137 dma_cookie_t cookie_tx; 138 dma_cookie_t cookie_rx[2]; 139 dma_cookie_t active_rx; 140 dma_addr_t tx_dma_addr; 141 unsigned int tx_dma_len; 142 struct scatterlist sg_rx[2]; 143 void *rx_buf[2]; 144 size_t buf_len_rx; 145 struct work_struct work_tx; 146 struct hrtimer rx_timer; 147 unsigned int rx_timeout; /* microseconds */ 148 #endif 149 unsigned int rx_frame; 150 int rx_trigger; 151 struct timer_list rx_fifo_timer; 152 int rx_fifo_timeout; 153 u16 hscif_tot; 154 155 u8 type; 156 u8 regtype; 157 158 const struct sci_port_ops *ops; 159 160 bool has_rtscts; 161 bool autorts; 162 bool tx_occurred; 163 }; 164 165 #define to_sci_port(uart) container_of((uart), struct sci_port, port) 166 167 void sci_port_disable(struct sci_port *sci_port); 168 void sci_port_enable(struct sci_port *sci_port); 169 170 int sci_startup(struct uart_port *port); 171 void sci_shutdown(struct uart_port *port); 172 173 int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr, 174 unsigned int *srr, unsigned int *cks); 175 176 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 177 #define max_sr(_port) fls((_port)->sampling_rate_mask) 178 179 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 180 int __init scix_early_console_setup(struct earlycon_device *device, const struct sci_of_data *data); 181 #endif 182 183 #endif /* __SH_SCI_COMMON_H__ */ 184