1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Moxa PCIe multiport serial device driver 4 * 5 * Copyright (C) 2025 Moxa Inc. (support@moxa.com) 6 * Author: Crescent Hsieh <crescentcy.hsieh@moxa.com> 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/dev_printk.h> 12 #include <linux/io.h> 13 #include <linux/ioport.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/tty_flip.h> 17 #include <linux/types.h> 18 19 #include <linux/8250_pci.h> 20 #include <linux/serial_8250.h> 21 22 #include "8250.h" 23 24 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 25 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 26 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027 27 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 28 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046 29 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121 30 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 31 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145 32 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 33 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 34 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 35 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 36 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 37 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323 38 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 39 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343 40 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 41 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 42 43 /* Bits in PCI device ID encoding board capabilities */ 44 #define MOXA_DEV_ID_IFACE_MASK GENMASK(11, 8) /* Supported serial interface */ 45 #define MOXA_DEV_ID_NPORTS_MASK GENMASK(7, 4) /* Number of UART ports */ 46 47 /* UART */ 48 #define MOXA_PUART_BASE_BAUD 921600 49 #define MOXA_PUART_OFFSET 0x200 50 #define MOXA_PUART_TX_TRIG_DEFAULT 0 51 #define MOXA_PUART_RX_TRIG_DEFAULT 96 52 #define MOXA_PUART_RX_FLOW_LOW_DEFAULT 16 53 #define MOXA_PUART_RX_FLOW_HIGH_DEFAULT 110 54 55 /* Special Function Register (SFR) */ 56 #define MOXA_PUART_SFR 0x07 57 #define MOXA_PUART_SFR_FORCE_TX BIT(0) 58 #define MOXA_PUART_SFR_950 BIT(5) 59 60 /* Enhanced Function Register (EFR) */ 61 #define MOXA_PUART_EFR 0x0A 62 #define MOXA_PUART_EFR_ENHANCED BIT(4) 63 #define MOXA_PUART_EFR_AUTO_RTS BIT(6) 64 #define MOXA_PUART_EFR_AUTO_CTS BIT(7) 65 #define MOXA_PUART_EFR_RX_FLOW_MASK GENMASK(1, 0) 66 #define MOXA_PUART_EFR_RX_FLOW_DISABLED 0x0 67 #define MOXA_PUART_EFR_RX_FLOW_XON2_XOFF2 0x1 68 #define MOXA_PUART_EFR_RX_FLOW_XON1_XOFF1 0x2 69 #define MOXA_PUART_EFR_RX_FLOW_COPY_TX 0x3 70 #define MOXA_PUART_EFR_TX_FLOW_MASK GENMASK(3, 2) 71 #define MOXA_PUART_EFR_TX_FLOW_DISABLED 0x0 72 #define MOXA_PUART_EFR_TX_FLOW_XON2_XOFF2 0x1 73 #define MOXA_PUART_EFR_TX_FLOW_XON1_XOFF1 0x2 74 #define MOXA_PUART_EFR_TX_FLOW_RESERVED 0x3 75 76 #define MOXA_PUART_XON1 0x0B 77 #define MOXA_PUART_XON2 0x0C 78 #define MOXA_PUART_XOFF1 0x0D 79 #define MOXA_PUART_XOFF2 0x0E 80 #define MOXA_PUART_TTL 0x10 /* Tx Interrupt Trigger Level */ 81 #define MOXA_PUART_RTL 0x11 /* Rx Interrupt Trigger Level */ 82 #define MOXA_PUART_FCL 0x12 /* Flow Control Low Trigger Level */ 83 #define MOXA_PUART_FCH 0x13 /* Flow Control High Trigger Level */ 84 #define MOXA_PUART_RX_FIFO_CNT 0x15 /* Rx FIFO Data Counter */ 85 #define MOXA_PUART_TX_FIFO_CNT 0x16 /* Tx FIFO Data Counter */ 86 87 #define MOXA_PUART_RX_FIFO_MEM 0x100 /* Memory Space to Rx FIFO Data Register */ 88 #define MOXA_PUART_TX_FIFO_MEM 0x100 /* Memory Space to Tx FIFO Data Register */ 89 90 #define MOXA_GPIO_DIRECTION 0x09 91 #define MOXA_GPIO_OUTPUT 0x0A 92 93 #define MOXA_GPIO_PIN2 BIT(2) 94 95 #define MOXA_UIR_OFFSET 0x04 96 #define MOXA_UIR_RS232 0x00 97 #define MOXA_UIR_RS422 0x01 98 #define MOXA_UIR_RS485_4W 0x0B 99 #define MOXA_UIR_RS485_2W 0x0F 100 101 #define MOXA_EVEN_RS_MASK GENMASK(3, 0) 102 #define MOXA_ODD_RS_MASK GENMASK(7, 4) 103 104 struct mxpcie8250_port { 105 int line; 106 u8 rx_trig_level; 107 }; 108 109 struct mxpcie8250 { 110 unsigned int supp_rs; 111 unsigned int num_ports; 112 void __iomem *bar1_base; /* UART registers (MMIO) */ 113 void __iomem *bar2_base; /* UIR / GPIO / CPLD (IO) */ 114 struct mxpcie8250_port port[] __counted_by(num_ports); 115 }; 116 117 enum { 118 MOXA_SUPP_RS232 = BIT(0), 119 MOXA_SUPP_RS422 = BIT(1), 120 MOXA_SUPP_RS485 = BIT(2), 121 }; 122 123 static const struct serial_rs485 mxpcie8250_rs485_supported = { 124 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX | SER_RS485_MODE_RS422, 125 }; 126 127 static bool mxpcie8250_is_mini_pcie(unsigned short device) 128 { 129 if (device == PCI_DEVICE_ID_MOXA_CP102N || 130 device == PCI_DEVICE_ID_MOXA_CP104N || 131 device == PCI_DEVICE_ID_MOXA_CP112N || 132 device == PCI_DEVICE_ID_MOXA_CP114N || 133 device == PCI_DEVICE_ID_MOXA_CP132N || 134 device == PCI_DEVICE_ID_MOXA_CP134N) 135 return true; 136 137 return false; 138 } 139 140 static unsigned int mxpcie8250_get_supp_rs(unsigned short device) 141 { 142 switch (device & MOXA_DEV_ID_IFACE_MASK) { 143 case 0x0000: 144 case 0x0600: 145 return MOXA_SUPP_RS232; 146 case 0x0100: 147 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 148 case 0x0300: 149 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 150 default: 151 return 0; 152 } 153 } 154 155 static unsigned short mxpcie8250_get_nports(unsigned short device) 156 { 157 switch (device) { 158 case PCI_DEVICE_ID_MOXA_CP116E_A_A: 159 case PCI_DEVICE_ID_MOXA_CP116E_A_B: 160 return 8; 161 default: 162 return FIELD_GET(MOXA_DEV_ID_NPORTS_MASK, device); 163 } 164 } 165 166 static void mxpcie8250_set_interface(struct mxpcie8250 *priv, 167 unsigned int port_idx, 168 u8 mode) 169 { 170 void __iomem *uir_addr = priv->bar2_base + MOXA_UIR_OFFSET + port_idx / 2; 171 u8 cval; 172 173 cval = ioread8(uir_addr); 174 175 if (port_idx % 2) 176 FIELD_MODIFY(MOXA_ODD_RS_MASK, &cval, mode); 177 else 178 FIELD_MODIFY(MOXA_EVEN_RS_MASK, &cval, mode); 179 180 iowrite8(cval, uir_addr); 181 } 182 183 /* 184 * Moxa PCIe multiport serial boards support switching serial interfaces 185 * via the ioctl() command "TIOCSRS485". Supported modes and corresponding 186 * flags in "serial_rs485": 187 * 188 * RS232 = (no flags set) 189 * RS422 = SER_RS485_ENABLED | SER_RS485_MODE_RS422 190 * RS485_2W (half-duplex) = SER_RS485_ENABLED 191 * RS485_4W (full-duplex) = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX 192 */ 193 static int mxpcie8250_rs485_config(struct uart_port *port, 194 struct ktermios *termios, 195 struct serial_rs485 *rs485) 196 { 197 struct mxpcie8250 *priv = dev_get_drvdata(port->dev); 198 u8 mode = MOXA_UIR_RS232; 199 200 if (rs485->flags & SER_RS485_ENABLED) { 201 if (rs485->flags & SER_RS485_MODE_RS422) 202 mode = MOXA_UIR_RS422; 203 else if (rs485->flags & SER_RS485_RX_DURING_TX) 204 mode = MOXA_UIR_RS485_4W; 205 else 206 mode = MOXA_UIR_RS485_2W; 207 } else if (!(priv->supp_rs & MOXA_SUPP_RS232)) { 208 return -ENODEV; 209 } 210 mxpcie8250_set_interface(priv, port->port_id, mode); 211 212 return 0; 213 } 214 215 static void mxpcie8250_set_termios(struct uart_port *port, 216 struct ktermios *new, 217 const struct ktermios *old) 218 { 219 struct uart_8250_port *up = up_to_u8250p(port); 220 struct tty_struct *tty = port->state->port.tty; 221 unsigned int cflag = tty->termios.c_cflag; 222 u8 efr, val; 223 224 serial8250_do_set_termios(port, new, old); 225 226 up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS | UPSTAT_AUTOXOFF); 227 228 efr = serial_in(up, MOXA_PUART_EFR); 229 efr &= ~(MOXA_PUART_EFR_AUTO_RTS | MOXA_PUART_EFR_AUTO_CTS); 230 231 if (cflag & CRTSCTS) { 232 efr |= (MOXA_PUART_EFR_AUTO_RTS | MOXA_PUART_EFR_AUTO_CTS); 233 up->port.status |= (UPSTAT_AUTORTS | UPSTAT_AUTOCTS); 234 } 235 /* Set on-chip software flow control character */ 236 serial_out(up, MOXA_PUART_XON1, START_CHAR(tty)); 237 serial_out(up, MOXA_PUART_XON2, START_CHAR(tty)); 238 serial_out(up, MOXA_PUART_XOFF1, STOP_CHAR(tty)); 239 serial_out(up, MOXA_PUART_XOFF2, STOP_CHAR(tty)); 240 241 val = I_IXON(tty) ? MOXA_PUART_EFR_RX_FLOW_XON1_XOFF1 : MOXA_PUART_EFR_RX_FLOW_DISABLED; 242 FIELD_MODIFY(MOXA_PUART_EFR_RX_FLOW_MASK, &efr, val); 243 244 val = I_IXOFF(tty) ? MOXA_PUART_EFR_TX_FLOW_XON1_XOFF1 : MOXA_PUART_EFR_TX_FLOW_DISABLED; 245 FIELD_MODIFY(MOXA_PUART_EFR_TX_FLOW_MASK, &efr, val); 246 247 if (I_IXOFF(tty)) 248 up->port.status |= UPSTAT_AUTOXOFF; 249 250 serial_out(up, MOXA_PUART_EFR, efr); 251 } 252 253 static int mxpcie8250_get_rxtrig(struct uart_port *port) 254 { 255 return serial_port_in(port, MOXA_PUART_RTL); 256 } 257 258 static int mxpcie8250_set_rxtrig(struct uart_port *port, unsigned char bytes) 259 { 260 struct mxpcie8250 *priv = dev_get_drvdata(port->dev); 261 262 if (bytes > port->fifosize) 263 return -EINVAL; 264 265 serial_port_out(port, MOXA_PUART_RTL, bytes); 266 priv->port[port->port_id].rx_trig_level = bytes; 267 268 return 0; 269 } 270 271 static int mxpcie8250_startup(struct uart_port *port) 272 { 273 struct mxpcie8250 *priv = dev_get_drvdata(port->dev); 274 struct uart_8250_port *up = up_to_u8250p(port); 275 int ret; 276 277 ret = serial8250_do_startup(port); 278 if (ret) 279 return ret; 280 281 /* 282 * The TX FIFO write pointer (w_ptr) and read pointer (r_ptr) 283 * are driven by different clocks: w_ptr uses the PCIe clock 284 * and r_ptr uses the UART clock. When TX FIFO flush is requested, 285 * w_ptr may be cleared before r_ptr, so the UART can still observe 286 * pending TX data. 287 * 288 * It is recommended to clear the FIFOs at least 5 times to ensure 289 * both pointers are reset. 290 */ 291 for (unsigned int i = 0; i < 5; ++i) 292 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 293 294 serial_out(up, MOXA_PUART_EFR, MOXA_PUART_EFR_ENHANCED); 295 serial_out(up, MOXA_PUART_SFR, MOXA_PUART_SFR_950); 296 297 serial_out(up, MOXA_PUART_TTL, MOXA_PUART_TX_TRIG_DEFAULT); 298 serial_out(up, MOXA_PUART_RTL, priv->port[port->port_id].rx_trig_level); 299 serial_out(up, MOXA_PUART_FCL, MOXA_PUART_RX_FLOW_LOW_DEFAULT); 300 serial_out(up, MOXA_PUART_FCH, MOXA_PUART_RX_FLOW_HIGH_DEFAULT); 301 302 return 0; 303 } 304 305 static void mxpcie8250_shutdown(struct uart_port *port) 306 { 307 struct uart_8250_port *up = up_to_u8250p(port); 308 309 serial_out(up, MOXA_PUART_EFR, 0); 310 serial_out(up, MOXA_PUART_SFR, 0); 311 312 serial8250_do_shutdown(port); 313 } 314 315 static void mxpcie8250_throttle(struct uart_port *port) 316 { 317 guard(uart_port_lock_irqsave)(port); 318 319 port->ops->stop_rx(port); 320 } 321 322 static void mxpcie8250_unthrottle(struct uart_port *port) 323 { 324 struct uart_8250_port *up = up_to_u8250p(port); 325 326 guard(uart_port_lock_irqsave)(port); 327 328 up->ier |= UART_IER_RLSI | UART_IER_RDI; 329 port->read_status_mask |= UART_LSR_DR; 330 serial_out(up, UART_IER, up->ier); 331 } 332 333 static void mxpcie8250_rx_chars(struct uart_8250_port *up) 334 { 335 struct uart_port *port = &up->port; 336 struct tty_port *tport = &port->state->port; 337 unsigned int count; 338 u8 *buf; 339 340 count = serial_in(up, MOXA_PUART_RX_FIFO_CNT); 341 count = min(count, port->fifosize); 342 count = tty_prepare_flip_string(tport, &buf, count); 343 if (!count) 344 return; 345 346 for (unsigned int i = 0; i < count; ++i) 347 buf[i] = serial_in(up, MOXA_PUART_RX_FIFO_MEM + i); 348 349 port->icount.rx += count; 350 tty_flip_buffer_push(tport); 351 } 352 353 static bool mxpcie8250_should_rx(struct uart_8250_port *up, u16 lsr) 354 { 355 struct uart_port *port = &up->port; 356 357 if (!(lsr & (UART_LSR_DR | UART_LSR_BI))) 358 return false; 359 360 if (!(port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS))) 361 return true; 362 if (lsr & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) 363 return true; 364 if (port->read_status_mask & UART_LSR_DR) 365 return true; 366 367 return false; 368 } 369 370 static void mxpcie8250_tx_chars(struct uart_8250_port *up) 371 { 372 struct uart_port *port = &up->port; 373 unsigned int offset = 0; 374 unsigned char c; 375 376 uart_port_tx_limited(port, c, port->fifosize - serial_in(up, MOXA_PUART_TX_FIFO_CNT), 377 true, 378 serial_out(up, MOXA_PUART_TX_FIFO_MEM + offset++, c), 379 ({})); 380 } 381 382 static int mxpcie8250_handle_irq(struct uart_port *port) 383 { 384 struct uart_8250_port *up = up_to_u8250p(port); 385 u16 lsr; 386 u8 iir; 387 388 iir = serial_in(up, UART_IIR); 389 if (iir & UART_IIR_NO_INT) 390 return 0; 391 392 guard(uart_port_lock_check_sysrq_irqsave)(port); 393 394 lsr = serial_lsr_in(up); 395 if (mxpcie8250_should_rx(up, lsr)) { 396 if (!(lsr & UART_LSR_BRK_ERROR_BITS)) 397 mxpcie8250_rx_chars(up); 398 else 399 lsr = serial8250_rx_chars(up, lsr); 400 } 401 402 serial8250_modem_status(up); 403 404 if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) 405 mxpcie8250_tx_chars(up); 406 407 return 1; 408 } 409 410 static void mxpcie8250_software_break_ctl(struct uart_port *port, int break_state) 411 { 412 struct uart_8250_port *up = up_to_u8250p(port); 413 struct tty_struct *tty = port->state->port.tty; 414 unsigned int baud, quot; 415 u8 sfr, tx_byte = 0x01; 416 417 guard(uart_port_lock_irqsave)(port); 418 419 if (break_state == -1) { 420 serial_out(up, UART_LCR, up->lcr | UART_LCR_DLAB); 421 serial_dl_write(up, 0); 422 serial_out(up, UART_LCR, up->lcr); 423 424 serial_out(up, MOXA_PUART_TX_FIFO_MEM, tx_byte); 425 426 sfr = serial_in(up, MOXA_PUART_SFR); 427 serial_out(up, MOXA_PUART_SFR, sfr | MOXA_PUART_SFR_FORCE_TX); 428 429 up->lcr |= UART_LCR_SBC; 430 serial_out(up, UART_LCR, up->lcr); 431 } else { 432 up->lcr &= ~UART_LCR_SBC; 433 serial_out(up, UART_LCR, up->lcr); 434 435 sfr = serial_in(up, MOXA_PUART_SFR); 436 serial_out(up, MOXA_PUART_SFR, sfr & ~MOXA_PUART_SFR_FORCE_TX); 437 438 serial_out(up, UART_FCR, UART_FCR_CLEAR_XMIT); 439 440 baud = tty_get_baud_rate(tty); 441 quot = uart_get_divisor(port, baud); 442 serial8250_do_set_divisor(port, baud, quot); 443 serial_out(up, UART_LCR, up->lcr); 444 } 445 } 446 447 static void mxpcie8250_break_ctl(struct uart_port *port, int break_state) 448 { 449 if (port->rs485.flags & SER_RS485_ENABLED && 450 !(port->rs485.flags & SER_RS485_MODE_RS422)) 451 mxpcie8250_software_break_ctl(port, break_state); 452 else 453 serial8250_do_break_ctl(port, break_state); 454 } 455 456 static void mxpcie8250_init_board(struct pci_dev *pdev, struct mxpcie8250 *priv) 457 { 458 void __iomem *bar2_base = priv->bar2_base; 459 unsigned short device = pdev->device; 460 u8 cval; 461 462 /* Initial terminator */ 463 if (device == PCI_DEVICE_ID_MOXA_CP114EL || 464 device == PCI_DEVICE_ID_MOXA_CP118EL_A) { 465 iowrite8(0xff, bar2_base + MOXA_GPIO_DIRECTION); 466 iowrite8(0x00, bar2_base + MOXA_GPIO_OUTPUT); 467 } 468 /* 469 * Enable hardware buffer to prevent break signal output when system boots up. 470 * This hardware buffer is only supported on Mini PCIe series. 471 */ 472 if (mxpcie8250_is_mini_pcie(device)) { 473 /* Set GPIO direction */ 474 cval = ioread8(bar2_base + MOXA_GPIO_DIRECTION); 475 cval |= MOXA_GPIO_PIN2; 476 iowrite8(cval, bar2_base + MOXA_GPIO_DIRECTION); 477 /* Enable low GPIO */ 478 cval = ioread8(bar2_base + MOXA_GPIO_OUTPUT); 479 cval &= ~MOXA_GPIO_PIN2; 480 iowrite8(cval, bar2_base + MOXA_GPIO_OUTPUT); 481 } 482 } 483 484 static void mxpcie8250_setup_port(struct pci_dev *pdev, 485 struct mxpcie8250 *priv, 486 struct uart_8250_port *up, 487 int idx) 488 { 489 unsigned short device = pdev->device; 490 int offset = idx * MOXA_PUART_OFFSET; 491 u8 init_mode = MOXA_UIR_RS232; 492 493 if (priv->supp_rs & MOXA_SUPP_RS485) { 494 up->port.rs485_config = mxpcie8250_rs485_config; 495 up->port.rs485_supported = mxpcie8250_rs485_supported; 496 } 497 if (!(priv->supp_rs & MOXA_SUPP_RS232)) { 498 init_mode = MOXA_UIR_RS422; 499 up->port.rs485.flags = SER_RS485_ENABLED | SER_RS485_MODE_RS422; 500 } 501 mxpcie8250_set_interface(priv, idx, init_mode); 502 503 if (idx == 3 && 504 (device == PCI_DEVICE_ID_MOXA_CP104EL_A || 505 device == PCI_DEVICE_ID_MOXA_CP114EL || 506 device == PCI_DEVICE_ID_MOXA_CP134EL_A)) 507 offset = 7 * MOXA_PUART_OFFSET; 508 509 up->port.mapbase = pci_resource_start(pdev, FL_BASE1) + offset; 510 up->port.membase = pcim_iomap_table(pdev)[FL_BASE1] + offset; 511 } 512 513 static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id) 514 { 515 struct device *dev = &pdev->dev; 516 struct uart_8250_port up = {}; 517 struct mxpcie8250 *priv; 518 unsigned short device = pdev->device; 519 unsigned int num_ports; 520 int ret; 521 522 ret = pcim_enable_device(pdev); 523 if (ret) 524 return ret; 525 526 num_ports = mxpcie8250_get_nports(device); 527 528 priv = devm_kzalloc(dev, struct_size(priv, port, num_ports), GFP_KERNEL); 529 if (!priv) 530 return -ENOMEM; 531 532 priv->num_ports = num_ports; 533 priv->supp_rs = mxpcie8250_get_supp_rs(device); 534 535 priv->bar1_base = pcim_iomap(pdev, FL_BASE1, 0); 536 if (!priv->bar1_base) 537 return -ENOMEM; 538 539 priv->bar2_base = pcim_iomap(pdev, FL_BASE2, 0); 540 if (!priv->bar2_base) 541 return -ENOMEM; 542 543 mxpcie8250_init_board(pdev, priv); 544 545 up.port.dev = dev; 546 up.port.irq = pdev->irq; 547 up.port.uartclk = MOXA_PUART_BASE_BAUD * 16; 548 up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 549 up.port.type = PORT_MUEX50; 550 551 up.port.iotype = UPIO_MEM; 552 up.port.iobase = 0; 553 up.port.regshift = 0; 554 555 up.port.set_termios = mxpcie8250_set_termios; 556 up.port.get_rxtrig = mxpcie8250_get_rxtrig; 557 up.port.set_rxtrig = mxpcie8250_set_rxtrig; 558 up.port.startup = mxpcie8250_startup; 559 up.port.shutdown = mxpcie8250_shutdown; 560 up.port.throttle = mxpcie8250_throttle; 561 up.port.unthrottle = mxpcie8250_unthrottle; 562 up.port.handle_irq = mxpcie8250_handle_irq; 563 up.port.break_ctl = mxpcie8250_break_ctl; 564 565 for (unsigned int i = 0; i < num_ports; i++) { 566 mxpcie8250_setup_port(pdev, priv, &up, i); 567 568 dev_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 569 up.port.iobase, up.port.irq, up.port.iotype); 570 571 priv->port[i].line = serial8250_register_8250_port(&up); 572 if (priv->port[i].line < 0) { 573 dev_err(dev, 574 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 575 up.port.iobase, up.port.irq, 576 up.port.iotype, priv->port[i].line); 577 break; 578 } 579 priv->port[i].rx_trig_level = MOXA_PUART_RX_TRIG_DEFAULT; 580 } 581 pci_set_drvdata(pdev, priv); 582 583 return 0; 584 } 585 586 static void mxpcie8250_remove(struct pci_dev *pdev) 587 { 588 struct mxpcie8250 *priv = pci_get_drvdata(pdev); 589 590 for (unsigned int i = 0; i < priv->num_ports; i++) 591 serial8250_unregister_port(priv->port[i].line); 592 } 593 594 static const struct pci_device_id mxpcie8250_pci_ids[] = { 595 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E) }, 596 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL) }, 597 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N) }, 598 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A) }, 599 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N) }, 600 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N) }, 601 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL) }, 602 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N) }, 603 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A) }, 604 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B) }, 605 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A) }, 606 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I) }, 607 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL) }, 608 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N) }, 609 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A) }, 610 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N) }, 611 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A) }, 612 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A) }, 613 { } 614 }; 615 MODULE_DEVICE_TABLE(pci, mxpcie8250_pci_ids); 616 617 static struct pci_driver mxpcie8250_pci_driver = { 618 .name = "8250_mxpcie", 619 .id_table = mxpcie8250_pci_ids, 620 .probe = mxpcie8250_probe, 621 .remove = mxpcie8250_remove, 622 }; 623 module_pci_driver(mxpcie8250_pci_driver); 624 625 MODULE_AUTHOR("Moxa Inc."); 626 MODULE_LICENSE("GPL"); 627 MODULE_DESCRIPTION("Moxa PCIe Multiport Serial Device Driver"); 628