1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thunderbolt driver - PCI NHI driver 4 * 5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6 * Copyright (C) 2018, Intel Corporation 7 */ 8 9 #include <linux/pm_runtime.h> 10 #include <linux/slab.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/interrupt.h> 15 #include <linux/iommu.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/property.h> 19 #include <linux/string_helpers.h> 20 #include <linux/suspend.h> 21 22 #include "nhi.h" 23 #include "nhi_regs.h" 24 #include "tb.h" 25 26 /** 27 * struct tb_nhi_pci - NHI device connected over PCIe 28 * @nhi: NHI device 29 * @msix_ida: Used to allocate MSI-X vectors for rings 30 */ 31 struct tb_nhi_pci { 32 struct tb_nhi nhi; 33 struct ida msix_ida; 34 }; 35 36 static inline struct tb_nhi_pci *nhi_to_pci(struct tb_nhi *nhi) 37 { 38 return container_of(nhi, struct tb_nhi_pci, nhi); 39 } 40 41 static void nhi_pci_check_quirks(struct tb_nhi_pci *nhi_pci) 42 { 43 struct tb_nhi *nhi = &nhi_pci->nhi; 44 struct pci_dev *pdev = to_pci_dev(nhi->dev); 45 46 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 47 /* 48 * Intel hardware supports auto clear of the interrupt 49 * status register right after interrupt is being 50 * issued. 51 */ 52 nhi->quirks |= QUIRK_AUTO_CLEAR_INT; 53 54 switch (pdev->device) { 55 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: 56 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: 57 /* 58 * Falcon Ridge controller needs the end-to-end 59 * flow control workaround to avoid losing Rx 60 * packets when RING_FLAG_E2E is set. 61 */ 62 nhi->quirks |= QUIRK_E2E; 63 break; 64 } 65 } else if (pdev->vendor == PCI_VENDOR_ID_AMD) { 66 switch (pdev->device) { 67 case PCI_DEVICE_ID_AMD_1AH_M60H_NHI0: 68 case PCI_DEVICE_ID_AMD_1AH_M60H_NHI1: 69 case PCI_DEVICE_ID_AMD_1AH_M68H_NHI0: 70 case PCI_DEVICE_ID_AMD_1AH_M68H_NHI1: 71 case PCI_DEVICE_ID_AMD_1AH_M80H_NHI0: 72 case PCI_DEVICE_ID_AMD_1AH_M80H_NHI1: 73 case PCI_DEVICE_ID_AMD_1AH_M80H_NHI2: 74 case PCI_DEVICE_ID_AMD_1AH_M24H_NHI0: 75 case PCI_DEVICE_ID_AMD_1AH_M24H_NHI1: 76 case PCI_DEVICE_ID_AMD_1AH_M70H_NHI0: 77 case PCI_DEVICE_ID_AMD_1AH_M70H_NHI1: 78 /* 79 * These AMD hosts may hang the Tx ring when the 80 * DMA paths are torn down so they need the host 81 * interface reset after each teardown. 82 */ 83 nhi->quirks |= QUIRK_RESET_DMA_ON_TEARDOWN; 84 break; 85 } 86 } 87 } 88 89 static int nhi_pci_check_iommu_pdev(struct pci_dev *pdev, void *data) 90 { 91 if (!pdev->external_facing || 92 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION)) 93 return 0; 94 *(bool *)data = true; 95 return 1; /* Stop walking */ 96 } 97 98 static void nhi_pci_check_iommu(struct tb_nhi_pci *nhi_pci) 99 { 100 struct tb_nhi *nhi = &nhi_pci->nhi; 101 struct pci_dev *pdev = to_pci_dev(nhi->dev); 102 struct pci_bus *bus = pdev->bus; 103 bool port_ok = false; 104 105 /* 106 * Ideally what we'd do here is grab every PCI device that 107 * represents a tunnelling adapter for this NHI and check their 108 * status directly, but unfortunately USB4 seems to make it 109 * obnoxiously difficult to reliably make any correlation. 110 * 111 * So for now we'll have to bodge it... Hoping that the system 112 * is at least sane enough that an adapter is in the same PCI 113 * segment as its NHI, if we can find *something* on that segment 114 * which meets the requirements for Kernel DMA Protection, we'll 115 * take that to imply that firmware is aware and has (hopefully) 116 * done the right thing in general. We need to know that the PCI 117 * layer has seen the ExternalFacingPort property which will then 118 * inform the IOMMU layer to enforce the complete "untrusted DMA" 119 * flow, but also that the IOMMU driver itself can be trusted not 120 * to have been subverted by a pre-boot DMA attack. 121 */ 122 while (bus->parent) 123 bus = bus->parent; 124 125 pci_walk_bus(bus, nhi_pci_check_iommu_pdev, &port_ok); 126 127 nhi->iommu_dma_protection = port_ok; 128 dev_dbg(nhi->dev, "IOMMU DMA protection is %s\n", 129 str_enabled_disabled(port_ok)); 130 } 131 132 static int nhi_pci_init_msi(struct tb_nhi *nhi) 133 { 134 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi); 135 struct pci_dev *pdev = to_pci_dev(nhi->dev); 136 int res, irq, nvec; 137 138 ida_init(&nhi_pci->msix_ida); 139 140 /* 141 * The NHI has 16 MSI-X vectors or a single MSI. We first try to 142 * get all MSI-X vectors and if we succeed, each ring will have 143 * one MSI-X. If for some reason that does not work out, we 144 * fallback to a single MSI. 145 */ 146 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS, 147 PCI_IRQ_MSIX); 148 if (nvec < 0) { 149 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 150 if (nvec < 0) 151 return nvec; 152 153 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work); 154 155 irq = pci_irq_vector(pdev, 0); 156 if (irq < 0) 157 return irq; 158 159 res = devm_request_irq(&pdev->dev, irq, nhi_msi, 160 IRQF_NO_SUSPEND, "thunderbolt", nhi); 161 if (res) 162 return res; 163 } 164 165 return 0; 166 } 167 168 static bool nhi_pci_imr_valid(struct pci_dev *pdev) 169 { 170 u8 val; 171 172 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) 173 return !!val; 174 175 return true; 176 } 177 178 static void nhi_pci_start_dma_port(struct tb_nhi *nhi) 179 { 180 struct pci_dev *pdev = to_pci_dev(nhi->dev); 181 struct pci_dev *root_port; 182 183 /* 184 * During host router NVM upgrade we should not allow root port to 185 * go into D3cold because some root ports cannot trigger PME 186 * itself. To be on the safe side keep the root port in D0 during 187 * the whole upgrade process. 188 */ 189 root_port = pcie_find_root_port(pdev); 190 if (root_port) 191 pm_runtime_get_noresume(&root_port->dev); 192 } 193 194 static void nhi_pci_complete_dma_port(struct tb_nhi *nhi) 195 { 196 struct pci_dev *pdev = to_pci_dev(nhi->dev); 197 struct pci_dev *root_port; 198 199 root_port = pcie_find_root_port(pdev); 200 if (root_port) 201 pm_runtime_put(&root_port->dev); 202 } 203 204 static int nhi_pci_ring_request_msix(struct tb_ring *ring, bool no_suspend) 205 { 206 struct tb_nhi *nhi = ring->nhi; 207 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi); 208 struct pci_dev *pdev = to_pci_dev(nhi->dev); 209 unsigned long irqflags; 210 int ret; 211 212 if (!pdev->msix_enabled) 213 return 0; 214 215 ret = ida_alloc_max(&nhi_pci->msix_ida, MSIX_MAX_VECS - 1, GFP_KERNEL); 216 if (ret < 0) 217 return ret; 218 219 ring->vector = ret; 220 221 ret = pci_irq_vector(pdev, ring->vector); 222 if (ret < 0) 223 goto err_ida_remove; 224 225 ring->irq = ret; 226 227 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0; 228 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring); 229 if (ret) 230 goto err_ida_remove; 231 232 return 0; 233 234 err_ida_remove: 235 ida_free(&nhi_pci->msix_ida, ring->vector); 236 237 return ret; 238 } 239 240 static void nhi_pci_ring_release_msix(struct tb_ring *ring) 241 { 242 struct tb_nhi_pci *nhi_pci = nhi_to_pci(ring->nhi); 243 244 if (ring->irq <= 0) 245 return; 246 247 free_irq(ring->irq, ring); 248 ida_free(&nhi_pci->msix_ida, ring->vector); 249 ring->vector = 0; 250 ring->irq = 0; 251 } 252 253 static void nhi_pci_release_irq(struct tb_nhi *nhi) 254 { 255 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi); 256 struct pci_dev *pdev = to_pci_dev(nhi->dev); 257 258 /* 259 * We have to release the irq before calling flush_work. Otherwise an 260 * already executing IRQ handler could call schedule_work again. 261 */ 262 if (!pdev->msix_enabled) { 263 devm_free_irq(nhi->dev, pdev->irq, nhi); 264 flush_work(&nhi->interrupt_work); 265 } 266 ida_destroy(&nhi_pci->msix_ida); 267 } 268 269 static bool nhi_pci_is_present(struct tb_nhi *nhi) 270 { 271 return pci_device_is_present(to_pci_dev(nhi->dev)); 272 } 273 274 static const struct tb_nhi_ops pci_nhi_default_ops = { 275 .pre_nvm_auth = nhi_pci_start_dma_port, 276 .post_nvm_auth = nhi_pci_complete_dma_port, 277 .request_ring_irq = nhi_pci_ring_request_msix, 278 .release_ring_irq = nhi_pci_ring_release_msix, 279 .shutdown = nhi_pci_release_irq, 280 .is_present = nhi_pci_is_present, 281 .init_interrupts = nhi_pci_init_msi, 282 .reset_interface = nhi_reset_interface, 283 }; 284 285 /* Ice Lake specific NHI operations */ 286 287 #define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */ 288 289 static int check_for_device(struct device *dev, void *data) 290 { 291 return tb_is_switch(dev); 292 } 293 294 static bool icl_nhi_is_device_connected(struct tb_nhi *nhi) 295 { 296 struct tb *tb = dev_get_drvdata(nhi->dev); 297 int ret; 298 299 ret = device_for_each_child(&tb->root_switch->dev, NULL, 300 check_for_device); 301 return ret > 0; 302 } 303 304 static int icl_nhi_force_power(struct tb_nhi *nhi, bool power) 305 { 306 struct pci_dev *pdev = to_pci_dev(nhi->dev); 307 u32 vs_cap; 308 309 /* 310 * The Thunderbolt host controller is present always in Ice Lake 311 * but the firmware may not be loaded and running (depending 312 * whether there is device connected and so on). Each time the 313 * controller is used we need to "Force Power" it first and wait 314 * for the firmware to indicate it is up and running. This "Force 315 * Power" is really not about actually powering on/off the 316 * controller so it is accessible even if "Force Power" is off. 317 * 318 * The actual power management happens inside shared ACPI power 319 * resources using standard ACPI methods. 320 */ 321 pci_read_config_dword(pdev, VS_CAP_22, &vs_cap); 322 if (power) { 323 vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK; 324 vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT; 325 vs_cap |= VS_CAP_22_FORCE_POWER; 326 } else { 327 vs_cap &= ~VS_CAP_22_FORCE_POWER; 328 } 329 pci_write_config_dword(pdev, VS_CAP_22, vs_cap); 330 331 if (power) { 332 unsigned int retries = 350; 333 u32 val; 334 335 /* Wait until the firmware tells it is up and running */ 336 do { 337 pci_read_config_dword(pdev, VS_CAP_9, &val); 338 if (val & VS_CAP_9_FW_READY) 339 return 0; 340 usleep_range(3000, 3100); 341 } while (--retries); 342 343 return -ETIMEDOUT; 344 } 345 346 return 0; 347 } 348 349 static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd) 350 { 351 struct pci_dev *pdev = to_pci_dev(nhi->dev); 352 u32 data; 353 354 data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK; 355 pci_write_config_dword(pdev, VS_CAP_19, data | VS_CAP_19_VALID); 356 } 357 358 static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout) 359 { 360 struct pci_dev *pdev = to_pci_dev(nhi->dev); 361 unsigned long end; 362 u32 data; 363 364 if (!timeout) 365 goto clear; 366 367 end = jiffies + msecs_to_jiffies(timeout); 368 do { 369 pci_read_config_dword(pdev, VS_CAP_18, &data); 370 if (data & VS_CAP_18_DONE) 371 goto clear; 372 usleep_range(1000, 1100); 373 } while (time_before(jiffies, end)); 374 375 return -ETIMEDOUT; 376 377 clear: 378 /* Clear the valid bit */ 379 pci_write_config_dword(pdev, VS_CAP_19, 0); 380 return 0; 381 } 382 383 static void icl_nhi_set_ltr(struct tb_nhi *nhi) 384 { 385 struct pci_dev *pdev = to_pci_dev(nhi->dev); 386 u32 max_ltr, ltr; 387 388 pci_read_config_dword(pdev, VS_CAP_16, &max_ltr); 389 max_ltr &= 0xffff; 390 /* Program the same value for both snoop and no-snoop */ 391 ltr = max_ltr << 16 | max_ltr; 392 pci_write_config_dword(pdev, VS_CAP_15, ltr); 393 } 394 395 static int icl_nhi_suspend(struct tb_nhi *nhi) 396 { 397 struct tb *tb = dev_get_drvdata(nhi->dev); 398 int ret; 399 400 if (icl_nhi_is_device_connected(nhi)) 401 return 0; 402 403 if (tb_switch_is_icm(tb->root_switch)) { 404 /* 405 * If there is no device connected we need to perform 406 * both: a handshake through LC mailbox and force power 407 * down before entering D3. 408 */ 409 icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET); 410 ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT); 411 if (ret) 412 return ret; 413 } 414 415 return icl_nhi_force_power(nhi, false); 416 } 417 418 static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup) 419 { 420 struct tb *tb = dev_get_drvdata(nhi->dev); 421 enum icl_lc_mailbox_cmd cmd; 422 423 if (!pm_suspend_via_firmware()) 424 return icl_nhi_suspend(nhi); 425 426 if (!tb_switch_is_icm(tb->root_switch)) 427 return 0; 428 429 cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE; 430 icl_nhi_lc_mailbox_cmd(nhi, cmd); 431 return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT); 432 } 433 434 static int icl_nhi_resume(struct tb_nhi *nhi) 435 { 436 int ret; 437 438 ret = icl_nhi_force_power(nhi, true); 439 if (ret) 440 return ret; 441 442 icl_nhi_set_ltr(nhi); 443 return 0; 444 } 445 446 static void icl_nhi_shutdown(struct tb_nhi *nhi) 447 { 448 nhi_pci_release_irq(nhi); 449 450 icl_nhi_force_power(nhi, false); 451 } 452 453 static const struct tb_nhi_ops icl_nhi_ops = { 454 .init = icl_nhi_resume, 455 .suspend_noirq = icl_nhi_suspend_noirq, 456 .resume_noirq = icl_nhi_resume, 457 .runtime_suspend = icl_nhi_suspend, 458 .runtime_resume = icl_nhi_resume, 459 .shutdown = icl_nhi_shutdown, 460 .pre_nvm_auth = nhi_pci_start_dma_port, 461 .post_nvm_auth = nhi_pci_complete_dma_port, 462 .request_ring_irq = nhi_pci_ring_request_msix, 463 .release_ring_irq = nhi_pci_ring_release_msix, 464 .is_present = nhi_pci_is_present, 465 .init_interrupts = nhi_pci_init_msi, 466 .reset_interface = nhi_reset_interface, 467 }; 468 469 static int nhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 470 { 471 struct device *dev = &pdev->dev; 472 struct tb_nhi_pci *nhi_pci; 473 struct tb_nhi *nhi; 474 int res; 475 476 if (!nhi_pci_imr_valid(pdev)) 477 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n"); 478 479 res = pcim_enable_device(pdev); 480 if (res) 481 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n"); 482 483 nhi_pci = devm_kzalloc(dev, sizeof(*nhi_pci), GFP_KERNEL); 484 if (!nhi_pci) 485 return -ENOMEM; 486 487 nhi = &nhi_pci->nhi; 488 nhi->dev = dev; 489 nhi->ops = (const struct tb_nhi_ops *)id->driver_data ?: &pci_nhi_default_ops; 490 491 nhi->iobase = pcim_iomap_region(pdev, 0, "thunderbolt"); 492 res = PTR_ERR_OR_ZERO(nhi->iobase); 493 if (res) 494 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n"); 495 496 nhi_pci_check_quirks(nhi_pci); 497 nhi_pci_check_iommu(nhi_pci); 498 499 pci_set_master(pdev); 500 501 return nhi_probe(&nhi_pci->nhi); 502 } 503 504 static void nhi_pci_do_remove(struct pci_dev *pdev, bool reset) 505 { 506 struct tb *tb = pci_get_drvdata(pdev); 507 struct tb_nhi *nhi = tb->nhi; 508 509 /* 510 * On system shutdown/reboot force a host router reset so the 511 * connection manager asserts DPR on connected Thunderbolt 3 devices 512 * before the router tree is removed (see tb_stop()). 513 */ 514 if (reset) 515 nhi->host_reset = true; 516 517 pm_runtime_get_sync(&pdev->dev); 518 pm_runtime_dont_use_autosuspend(&pdev->dev); 519 pm_runtime_forbid(&pdev->dev); 520 521 tb_domain_remove(tb); 522 wait_for_completion(&nhi->domain_released); 523 nhi_shutdown(nhi); 524 } 525 526 static void nhi_pci_remove(struct pci_dev *pdev) 527 { 528 nhi_pci_do_remove(pdev, false); 529 } 530 531 static void nhi_pci_shutdown(struct pci_dev *pdev) 532 { 533 nhi_pci_do_remove(pdev, true); 534 } 535 536 static struct pci_device_id nhi_ids[] = { 537 /* 538 * We have to specify class, the TB bridges use the same device and 539 * vendor (sub)id on gen 1 and gen 2 controllers. 540 */ 541 { 542 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 543 .vendor = PCI_VENDOR_ID_INTEL, 544 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 545 .subvendor = 0x2222, .subdevice = 0x1111, 546 }, 547 { 548 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 549 .vendor = PCI_VENDOR_ID_INTEL, 550 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 551 .subvendor = 0x2222, .subdevice = 0x1111, 552 }, 553 { 554 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 555 .vendor = PCI_VENDOR_ID_INTEL, 556 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, 557 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 558 }, 559 { 560 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 561 .vendor = PCI_VENDOR_ID_INTEL, 562 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, 563 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 564 }, 565 566 /* Thunderbolt 3 */ 567 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) }, 568 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) }, 569 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) }, 570 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) }, 571 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) }, 572 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) }, 573 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) }, 574 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) }, 575 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) }, 576 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) }, 577 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0), 578 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 579 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1), 580 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 581 /* Thunderbolt 4 */ 582 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0), 583 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 584 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1), 585 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 586 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0), 587 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 588 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1), 589 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 590 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0), 591 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 592 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1), 593 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 594 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0), 595 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 596 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1), 597 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 598 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0), 599 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 600 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0), 601 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 602 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1), 603 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 604 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI0), 605 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 606 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI1), 607 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 608 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI0), 609 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 610 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI1), 611 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 612 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI0), 613 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 614 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI1), 615 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 616 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_WCL_NHI0), 617 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 618 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) }, 619 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) }, 620 621 /* Any USB4 compliant host */ 622 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, 623 624 { 0,} 625 }; 626 627 MODULE_DEVICE_TABLE(pci, nhi_ids); 628 MODULE_DESCRIPTION("Thunderbolt/USB4 core driver"); 629 MODULE_LICENSE("GPL"); 630 631 static struct pci_driver nhi_driver = { 632 .name = "thunderbolt", 633 .id_table = nhi_ids, 634 .probe = nhi_pci_probe, 635 .remove = nhi_pci_remove, 636 .shutdown = nhi_pci_shutdown, 637 .driver.pm = &nhi_pm_ops, 638 }; 639 640 static int __init nhi_init(void) 641 { 642 int ret; 643 644 ret = tb_domain_init(); 645 if (ret) 646 return ret; 647 648 ret = pci_register_driver(&nhi_driver); 649 if (ret) 650 tb_domain_exit(); 651 652 return ret; 653 } 654 655 static void __exit nhi_unload(void) 656 { 657 pci_unregister_driver(&nhi_driver); 658 tb_domain_exit(); 659 } 660 661 rootfs_initcall(nhi_init); 662 module_exit(nhi_unload); 663