1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thunderbolt driver - PCI NHI driver 4 * 5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6 * Copyright (C) 2018, Intel Corporation 7 */ 8 9 #include <linux/pm_runtime.h> 10 #include <linux/slab.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/interrupt.h> 15 #include <linux/iommu.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/property.h> 19 #include <linux/string_helpers.h> 20 #include <linux/suspend.h> 21 22 #include "nhi.h" 23 #include "nhi_regs.h" 24 #include "tb.h" 25 26 /** 27 * struct tb_nhi_pci - NHI device connected over PCIe 28 * @nhi: NHI device 29 * @msix_ida: Used to allocate MSI-X vectors for rings 30 */ 31 struct tb_nhi_pci { 32 struct tb_nhi nhi; 33 struct ida msix_ida; 34 }; 35 36 static inline struct tb_nhi_pci *nhi_to_pci(struct tb_nhi *nhi) 37 { 38 return container_of(nhi, struct tb_nhi_pci, nhi); 39 } 40 41 static void nhi_pci_check_quirks(struct tb_nhi_pci *nhi_pci) 42 { 43 struct tb_nhi *nhi = &nhi_pci->nhi; 44 struct pci_dev *pdev = to_pci_dev(nhi->dev); 45 46 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 47 /* 48 * Intel hardware supports auto clear of the interrupt 49 * status register right after interrupt is being 50 * issued. 51 */ 52 nhi->quirks |= QUIRK_AUTO_CLEAR_INT; 53 54 switch (pdev->device) { 55 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: 56 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: 57 /* 58 * Falcon Ridge controller needs the end-to-end 59 * flow control workaround to avoid losing Rx 60 * packets when RING_FLAG_E2E is set. 61 */ 62 nhi->quirks |= QUIRK_E2E; 63 break; 64 } 65 } 66 } 67 68 static int nhi_pci_check_iommu_pdev(struct pci_dev *pdev, void *data) 69 { 70 if (!pdev->external_facing || 71 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION)) 72 return 0; 73 *(bool *)data = true; 74 return 1; /* Stop walking */ 75 } 76 77 static void nhi_pci_check_iommu(struct tb_nhi_pci *nhi_pci) 78 { 79 struct tb_nhi *nhi = &nhi_pci->nhi; 80 struct pci_dev *pdev = to_pci_dev(nhi->dev); 81 struct pci_bus *bus = pdev->bus; 82 bool port_ok = false; 83 84 /* 85 * Ideally what we'd do here is grab every PCI device that 86 * represents a tunnelling adapter for this NHI and check their 87 * status directly, but unfortunately USB4 seems to make it 88 * obnoxiously difficult to reliably make any correlation. 89 * 90 * So for now we'll have to bodge it... Hoping that the system 91 * is at least sane enough that an adapter is in the same PCI 92 * segment as its NHI, if we can find *something* on that segment 93 * which meets the requirements for Kernel DMA Protection, we'll 94 * take that to imply that firmware is aware and has (hopefully) 95 * done the right thing in general. We need to know that the PCI 96 * layer has seen the ExternalFacingPort property which will then 97 * inform the IOMMU layer to enforce the complete "untrusted DMA" 98 * flow, but also that the IOMMU driver itself can be trusted not 99 * to have been subverted by a pre-boot DMA attack. 100 */ 101 while (bus->parent) 102 bus = bus->parent; 103 104 pci_walk_bus(bus, nhi_pci_check_iommu_pdev, &port_ok); 105 106 nhi->iommu_dma_protection = port_ok; 107 dev_dbg(nhi->dev, "IOMMU DMA protection is %s\n", 108 str_enabled_disabled(port_ok)); 109 } 110 111 static int nhi_pci_init_msi(struct tb_nhi *nhi) 112 { 113 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi); 114 struct pci_dev *pdev = to_pci_dev(nhi->dev); 115 struct device *dev = &pdev->dev; 116 int res, irq, nvec; 117 118 ida_init(&nhi_pci->msix_ida); 119 120 /* 121 * The NHI has 16 MSI-X vectors or a single MSI. We first try to 122 * get all MSI-X vectors and if we succeed, each ring will have 123 * one MSI-X. If for some reason that does not work out, we 124 * fallback to a single MSI. 125 */ 126 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS, 127 PCI_IRQ_MSIX); 128 if (nvec < 0) { 129 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 130 if (nvec < 0) 131 return nvec; 132 133 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work); 134 135 irq = pci_irq_vector(pdev, 0); 136 if (irq < 0) 137 return irq; 138 139 res = devm_request_irq(&pdev->dev, irq, nhi_msi, 140 IRQF_NO_SUSPEND, "thunderbolt", nhi); 141 if (res) 142 return dev_err_probe(dev, res, "request_irq failed, aborting\n"); 143 } 144 145 return 0; 146 } 147 148 static bool nhi_pci_imr_valid(struct pci_dev *pdev) 149 { 150 u8 val; 151 152 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) 153 return !!val; 154 155 return true; 156 } 157 158 static void nhi_pci_start_dma_port(struct tb_nhi *nhi) 159 { 160 struct pci_dev *pdev = to_pci_dev(nhi->dev); 161 struct pci_dev *root_port; 162 163 /* 164 * During host router NVM upgrade we should not allow root port to 165 * go into D3cold because some root ports cannot trigger PME 166 * itself. To be on the safe side keep the root port in D0 during 167 * the whole upgrade process. 168 */ 169 root_port = pcie_find_root_port(pdev); 170 if (root_port) 171 pm_runtime_get_noresume(&root_port->dev); 172 } 173 174 static void nhi_pci_complete_dma_port(struct tb_nhi *nhi) 175 { 176 struct pci_dev *pdev = to_pci_dev(nhi->dev); 177 struct pci_dev *root_port; 178 179 root_port = pcie_find_root_port(pdev); 180 if (root_port) 181 pm_runtime_put(&root_port->dev); 182 } 183 184 static int nhi_pci_ring_request_msix(struct tb_ring *ring, bool no_suspend) 185 { 186 struct tb_nhi *nhi = ring->nhi; 187 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi); 188 struct pci_dev *pdev = to_pci_dev(nhi->dev); 189 unsigned long irqflags; 190 int ret; 191 192 if (!pdev->msix_enabled) 193 return 0; 194 195 ret = ida_alloc_max(&nhi_pci->msix_ida, MSIX_MAX_VECS - 1, GFP_KERNEL); 196 if (ret < 0) 197 return ret; 198 199 ring->vector = ret; 200 201 ret = pci_irq_vector(pdev, ring->vector); 202 if (ret < 0) 203 goto err_ida_remove; 204 205 ring->irq = ret; 206 207 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0; 208 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring); 209 if (ret) 210 goto err_ida_remove; 211 212 return 0; 213 214 err_ida_remove: 215 ida_free(&nhi_pci->msix_ida, ring->vector); 216 217 return ret; 218 } 219 220 static void nhi_pci_ring_release_msix(struct tb_ring *ring) 221 { 222 struct tb_nhi_pci *nhi_pci = nhi_to_pci(ring->nhi); 223 224 if (ring->irq <= 0) 225 return; 226 227 free_irq(ring->irq, ring); 228 ida_free(&nhi_pci->msix_ida, ring->vector); 229 ring->vector = 0; 230 ring->irq = 0; 231 } 232 233 static void nhi_pci_shutdown(struct tb_nhi *nhi) 234 { 235 struct tb_nhi_pci *nhi_pci = nhi_to_pci(nhi); 236 struct pci_dev *pdev = to_pci_dev(nhi->dev); 237 238 /* 239 * We have to release the irq before calling flush_work. Otherwise an 240 * already executing IRQ handler could call schedule_work again. 241 */ 242 if (!pdev->msix_enabled) { 243 devm_free_irq(nhi->dev, pdev->irq, nhi); 244 flush_work(&nhi->interrupt_work); 245 } 246 ida_destroy(&nhi_pci->msix_ida); 247 } 248 249 static bool nhi_pci_is_present(struct tb_nhi *nhi) 250 { 251 return pci_device_is_present(to_pci_dev(nhi->dev)); 252 } 253 254 static const struct tb_nhi_ops pci_nhi_default_ops = { 255 .pre_nvm_auth = nhi_pci_start_dma_port, 256 .post_nvm_auth = nhi_pci_complete_dma_port, 257 .request_ring_irq = nhi_pci_ring_request_msix, 258 .release_ring_irq = nhi_pci_ring_release_msix, 259 .shutdown = nhi_pci_shutdown, 260 .is_present = nhi_pci_is_present, 261 .init_interrupts = nhi_pci_init_msi, 262 }; 263 264 /* Ice Lake specific NHI operations */ 265 266 #define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */ 267 268 static int check_for_device(struct device *dev, void *data) 269 { 270 return tb_is_switch(dev); 271 } 272 273 static bool icl_nhi_is_device_connected(struct tb_nhi *nhi) 274 { 275 struct tb *tb = dev_get_drvdata(nhi->dev); 276 int ret; 277 278 ret = device_for_each_child(&tb->root_switch->dev, NULL, 279 check_for_device); 280 return ret > 0; 281 } 282 283 static int icl_nhi_force_power(struct tb_nhi *nhi, bool power) 284 { 285 struct pci_dev *pdev = to_pci_dev(nhi->dev); 286 u32 vs_cap; 287 288 /* 289 * The Thunderbolt host controller is present always in Ice Lake 290 * but the firmware may not be loaded and running (depending 291 * whether there is device connected and so on). Each time the 292 * controller is used we need to "Force Power" it first and wait 293 * for the firmware to indicate it is up and running. This "Force 294 * Power" is really not about actually powering on/off the 295 * controller so it is accessible even if "Force Power" is off. 296 * 297 * The actual power management happens inside shared ACPI power 298 * resources using standard ACPI methods. 299 */ 300 pci_read_config_dword(pdev, VS_CAP_22, &vs_cap); 301 if (power) { 302 vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK; 303 vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT; 304 vs_cap |= VS_CAP_22_FORCE_POWER; 305 } else { 306 vs_cap &= ~VS_CAP_22_FORCE_POWER; 307 } 308 pci_write_config_dword(pdev, VS_CAP_22, vs_cap); 309 310 if (power) { 311 unsigned int retries = 350; 312 u32 val; 313 314 /* Wait until the firmware tells it is up and running */ 315 do { 316 pci_read_config_dword(pdev, VS_CAP_9, &val); 317 if (val & VS_CAP_9_FW_READY) 318 return 0; 319 usleep_range(3000, 3100); 320 } while (--retries); 321 322 return -ETIMEDOUT; 323 } 324 325 return 0; 326 } 327 328 static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd) 329 { 330 struct pci_dev *pdev = to_pci_dev(nhi->dev); 331 u32 data; 332 333 data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK; 334 pci_write_config_dword(pdev, VS_CAP_19, data | VS_CAP_19_VALID); 335 } 336 337 static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout) 338 { 339 struct pci_dev *pdev = to_pci_dev(nhi->dev); 340 unsigned long end; 341 u32 data; 342 343 if (!timeout) 344 goto clear; 345 346 end = jiffies + msecs_to_jiffies(timeout); 347 do { 348 pci_read_config_dword(pdev, VS_CAP_18, &data); 349 if (data & VS_CAP_18_DONE) 350 goto clear; 351 usleep_range(1000, 1100); 352 } while (time_before(jiffies, end)); 353 354 return -ETIMEDOUT; 355 356 clear: 357 /* Clear the valid bit */ 358 pci_write_config_dword(pdev, VS_CAP_19, 0); 359 return 0; 360 } 361 362 static void icl_nhi_set_ltr(struct tb_nhi *nhi) 363 { 364 struct pci_dev *pdev = to_pci_dev(nhi->dev); 365 u32 max_ltr, ltr; 366 367 pci_read_config_dword(pdev, VS_CAP_16, &max_ltr); 368 max_ltr &= 0xffff; 369 /* Program the same value for both snoop and no-snoop */ 370 ltr = max_ltr << 16 | max_ltr; 371 pci_write_config_dword(pdev, VS_CAP_15, ltr); 372 } 373 374 static int icl_nhi_suspend(struct tb_nhi *nhi) 375 { 376 struct tb *tb = dev_get_drvdata(nhi->dev); 377 int ret; 378 379 if (icl_nhi_is_device_connected(nhi)) 380 return 0; 381 382 if (tb_switch_is_icm(tb->root_switch)) { 383 /* 384 * If there is no device connected we need to perform 385 * both: a handshake through LC mailbox and force power 386 * down before entering D3. 387 */ 388 icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET); 389 ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT); 390 if (ret) 391 return ret; 392 } 393 394 return icl_nhi_force_power(nhi, false); 395 } 396 397 static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup) 398 { 399 struct tb *tb = dev_get_drvdata(nhi->dev); 400 enum icl_lc_mailbox_cmd cmd; 401 402 if (!pm_suspend_via_firmware()) 403 return icl_nhi_suspend(nhi); 404 405 if (!tb_switch_is_icm(tb->root_switch)) 406 return 0; 407 408 cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE; 409 icl_nhi_lc_mailbox_cmd(nhi, cmd); 410 return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT); 411 } 412 413 static int icl_nhi_resume(struct tb_nhi *nhi) 414 { 415 int ret; 416 417 ret = icl_nhi_force_power(nhi, true); 418 if (ret) 419 return ret; 420 421 icl_nhi_set_ltr(nhi); 422 return 0; 423 } 424 425 static void icl_nhi_shutdown(struct tb_nhi *nhi) 426 { 427 nhi_pci_shutdown(nhi); 428 429 icl_nhi_force_power(nhi, false); 430 } 431 432 static const struct tb_nhi_ops icl_nhi_ops = { 433 .init = icl_nhi_resume, 434 .suspend_noirq = icl_nhi_suspend_noirq, 435 .resume_noirq = icl_nhi_resume, 436 .runtime_suspend = icl_nhi_suspend, 437 .runtime_resume = icl_nhi_resume, 438 .shutdown = icl_nhi_shutdown, 439 .pre_nvm_auth = nhi_pci_start_dma_port, 440 .post_nvm_auth = nhi_pci_complete_dma_port, 441 .request_ring_irq = nhi_pci_ring_request_msix, 442 .release_ring_irq = nhi_pci_ring_release_msix, 443 .is_present = nhi_pci_is_present, 444 .init_interrupts = nhi_pci_init_msi, 445 }; 446 447 static int nhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 448 { 449 struct device *dev = &pdev->dev; 450 struct tb_nhi_pci *nhi_pci; 451 struct tb_nhi *nhi; 452 int res; 453 454 if (!nhi_pci_imr_valid(pdev)) 455 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n"); 456 457 res = pcim_enable_device(pdev); 458 if (res) 459 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n"); 460 461 nhi_pci = devm_kzalloc(dev, sizeof(*nhi_pci), GFP_KERNEL); 462 if (!nhi_pci) 463 return -ENOMEM; 464 465 nhi = &nhi_pci->nhi; 466 nhi->dev = dev; 467 nhi->ops = (const struct tb_nhi_ops *)id->driver_data ?: &pci_nhi_default_ops; 468 469 nhi->iobase = pcim_iomap_region(pdev, 0, "thunderbolt"); 470 res = PTR_ERR_OR_ZERO(nhi->iobase); 471 if (res) 472 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n"); 473 474 nhi_pci_check_quirks(nhi_pci); 475 nhi_pci_check_iommu(nhi_pci); 476 477 pci_set_master(pdev); 478 479 return nhi_probe(&nhi_pci->nhi); 480 } 481 482 static void nhi_pci_remove(struct pci_dev *pdev) 483 { 484 struct tb *tb = pci_get_drvdata(pdev); 485 struct tb_nhi *nhi = tb->nhi; 486 487 pm_runtime_get_sync(&pdev->dev); 488 pm_runtime_dont_use_autosuspend(&pdev->dev); 489 pm_runtime_forbid(&pdev->dev); 490 491 tb_domain_remove(tb); 492 wait_for_completion(&nhi->domain_released); 493 nhi_shutdown(nhi); 494 } 495 496 static struct pci_device_id nhi_ids[] = { 497 /* 498 * We have to specify class, the TB bridges use the same device and 499 * vendor (sub)id on gen 1 and gen 2 controllers. 500 */ 501 { 502 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 503 .vendor = PCI_VENDOR_ID_INTEL, 504 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 505 .subvendor = 0x2222, .subdevice = 0x1111, 506 }, 507 { 508 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 509 .vendor = PCI_VENDOR_ID_INTEL, 510 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 511 .subvendor = 0x2222, .subdevice = 0x1111, 512 }, 513 { 514 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 515 .vendor = PCI_VENDOR_ID_INTEL, 516 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, 517 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 518 }, 519 { 520 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 521 .vendor = PCI_VENDOR_ID_INTEL, 522 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, 523 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 524 }, 525 526 /* Thunderbolt 3 */ 527 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) }, 528 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) }, 529 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) }, 530 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) }, 531 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) }, 532 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) }, 533 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) }, 534 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) }, 535 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) }, 536 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) }, 537 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0), 538 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 539 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1), 540 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 541 /* Thunderbolt 4 */ 542 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0), 543 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 544 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1), 545 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 546 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0), 547 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 548 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1), 549 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 550 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0), 551 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 552 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1), 553 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 554 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0), 555 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 556 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1), 557 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 558 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0), 559 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 560 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0), 561 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 562 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1), 563 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 564 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI0), 565 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 566 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_LNL_NHI1), 567 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 568 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI0), 569 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 570 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_M_NHI1), 571 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 572 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI0), 573 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 574 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_PTL_P_NHI1), 575 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 576 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_WCL_NHI0), 577 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 578 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) }, 579 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) }, 580 581 /* Any USB4 compliant host */ 582 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, 583 584 { 0,} 585 }; 586 587 MODULE_DEVICE_TABLE(pci, nhi_ids); 588 MODULE_DESCRIPTION("Thunderbolt/USB4 core driver"); 589 MODULE_LICENSE("GPL"); 590 591 static struct pci_driver nhi_driver = { 592 .name = "thunderbolt", 593 .id_table = nhi_ids, 594 .probe = nhi_pci_probe, 595 .remove = nhi_pci_remove, 596 .shutdown = nhi_pci_remove, 597 .driver.pm = &nhi_pm_ops, 598 }; 599 600 static int __init nhi_init(void) 601 { 602 int ret; 603 604 ret = tb_domain_init(); 605 if (ret) 606 return ret; 607 608 ret = pci_register_driver(&nhi_driver); 609 if (ret) 610 tb_domain_exit(); 611 612 return ret; 613 } 614 615 static void __exit nhi_unload(void) 616 { 617 pci_unregister_driver(&nhi_driver); 618 tb_domain_exit(); 619 } 620 621 rootfs_initcall(nhi_init); 622 module_exit(nhi_unload); 623