1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 - 2025 Intel Corporation 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/bitfield.h> 8 #include <linux/bits.h> 9 #include <linux/bug.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/err.h> 12 #include <linux/firmware.h> 13 #include <linux/kernel.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/list.h> 17 #include <linux/module.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/scatterlist.h> 21 #include <linux/slab.h> 22 #include <linux/types.h> 23 #include <linux/vmalloc.h> 24 #include <linux/version.h> 25 26 #include <media/ipu-bridge.h> 27 28 #include "abi/ipu7_fw_common_abi.h" 29 30 #include "ipu7.h" 31 #include "ipu7-bus.h" 32 #include "ipu7-buttress.h" 33 #include "ipu7-buttress-regs.h" 34 #include "ipu7-cpd.h" 35 #include "ipu7-dma.h" 36 #include "ipu7-isys-csi2-regs.h" 37 #include "ipu7-mmu.h" 38 #include "ipu7-platform-regs.h" 39 40 #define IPU_PCI_BAR 0 41 #define IPU_PCI_PBBAR 4 42 43 static const unsigned int ipu7_csi_offsets[] = { 44 IPU_CSI_PORT_A_ADDR_OFFSET, 45 IPU_CSI_PORT_B_ADDR_OFFSET, 46 IPU_CSI_PORT_C_ADDR_OFFSET, 47 IPU_CSI_PORT_D_ADDR_OFFSET, 48 }; 49 50 static struct ipu_isys_internal_pdata ipu7p5_isys_ipdata = { 51 .csi2 = { 52 .gpreg = IS_IO_CSI2_GPREGS_BASE, 53 }, 54 .hw_variant = { 55 .offset = IPU_UNIFIED_OFFSET, 56 .nr_mmus = IPU7P5_IS_MMU_NUM, 57 .mmu_hw = { 58 { 59 .name = "IS_FW_RD", 60 .offset = IPU7P5_IS_MMU_FW_RD_OFFSET, 61 .zlx_offset = IPU7P5_IS_ZLX_UC_RD_OFFSET, 62 .uao_offset = IPU7P5_IS_UAO_UC_RD_OFFSET, 63 .info_bits = 0x20005101, 64 .refill = 0x00002726, 65 .collapse_en_bitmap = 0x1, 66 .at_sp_arb_cfg = 0x1, 67 .l1_block = IPU7P5_IS_MMU_FW_RD_L1_BLOCKNR_REG, 68 .l2_block = IPU7P5_IS_MMU_FW_RD_L2_BLOCKNR_REG, 69 .nr_l1streams = IPU7P5_IS_MMU_FW_RD_STREAM_NUM, 70 .nr_l2streams = IPU7P5_IS_MMU_FW_RD_STREAM_NUM, 71 .l1_block_sz = { 72 0x0, 0x8, 0xa, 73 }, 74 .l2_block_sz = { 75 0x0, 0x2, 0x4, 76 }, 77 .zlx_nr = IPU7P5_IS_ZLX_UC_RD_NUM, 78 .zlx_axi_pool = { 79 0x00000f30, 80 }, 81 .zlx_en = { 82 0, 1, 0, 0 83 }, 84 .zlx_conf = { 85 0x0, 86 }, 87 .uao_p_num = IPU7P5_IS_UAO_UC_RD_PLANENUM, 88 .uao_p2tlb = { 89 0x00000049, 90 0x0000004c, 91 0x0000004d, 92 0x00000000, 93 }, 94 }, 95 { 96 .name = "IS_FW_WR", 97 .offset = IPU7P5_IS_MMU_FW_WR_OFFSET, 98 .zlx_offset = IPU7P5_IS_ZLX_UC_WR_OFFSET, 99 .uao_offset = IPU7P5_IS_UAO_UC_WR_OFFSET, 100 .info_bits = 0x20005001, 101 .refill = 0x00002524, 102 .collapse_en_bitmap = 0x1, 103 .at_sp_arb_cfg = 0x1, 104 .l1_block = IPU7P5_IS_MMU_FW_WR_L1_BLOCKNR_REG, 105 .l2_block = IPU7P5_IS_MMU_FW_WR_L2_BLOCKNR_REG, 106 .nr_l1streams = IPU7P5_IS_MMU_FW_WR_STREAM_NUM, 107 .nr_l2streams = IPU7P5_IS_MMU_FW_WR_STREAM_NUM, 108 .l1_block_sz = { 109 0x0, 0x8, 0xa, 110 }, 111 .l2_block_sz = { 112 0x0, 0x2, 0x4, 113 }, 114 .zlx_nr = IPU7P5_IS_ZLX_UC_WR_NUM, 115 .zlx_axi_pool = { 116 0x00000f20, 117 }, 118 .zlx_en = { 119 0, 1, 1, 0, 120 }, 121 .zlx_conf = { 122 0x0, 123 0x00010101, 124 0x00010101, 125 0x0, 126 }, 127 .uao_p_num = IPU7P5_IS_UAO_UC_WR_PLANENUM, 128 .uao_p2tlb = { 129 0x00000049, 130 0x0000004a, 131 0x0000004b, 132 0x00000000, 133 }, 134 }, 135 { 136 .name = "IS_DATA_WR_ISOC", 137 .offset = IPU7P5_IS_MMU_M0_OFFSET, 138 .zlx_offset = IPU7P5_IS_ZLX_M0_OFFSET, 139 .uao_offset = IPU7P5_IS_UAO_M0_WR_OFFSET, 140 .info_bits = 0x20004e01, 141 .refill = 0x00002120, 142 .collapse_en_bitmap = 0x1, 143 .at_sp_arb_cfg = 0x1, 144 .l1_block = IPU7P5_IS_MMU_M0_L1_BLOCKNR_REG, 145 .l2_block = IPU7P5_IS_MMU_M0_L2_BLOCKNR_REG, 146 .nr_l1streams = IPU7P5_IS_MMU_M0_STREAM_NUM, 147 .nr_l2streams = IPU7P5_IS_MMU_M0_STREAM_NUM, 148 .l1_block_sz = { 149 0x00000000, 150 0x00000002, 151 0x00000004, 152 0x00000006, 153 0x00000008, 154 0x0000000a, 155 0x0000000c, 156 0x0000000e, 157 0x00000010, 158 0x00000012, 159 0x00000014, 160 0x00000016, 161 0x00000018, 162 0x0000001a, 163 0x0000001c, 164 0x0000001e, 165 }, 166 .l2_block_sz = { 167 0x00000000, 168 0x00000002, 169 0x00000004, 170 0x00000006, 171 0x00000008, 172 0x0000000a, 173 0x0000000c, 174 0x0000000e, 175 0x00000010, 176 0x00000012, 177 0x00000014, 178 0x00000016, 179 0x00000018, 180 0x0000001a, 181 0x0000001c, 182 0x0000001e, 183 }, 184 .zlx_nr = IPU7P5_IS_ZLX_M0_NUM, 185 .zlx_axi_pool = { 186 0x00000f10, 187 }, 188 .zlx_en = { 189 1, 1, 1, 1, 1, 1, 1, 1, 190 1, 1, 1, 1, 1, 1, 1, 1, 191 }, 192 .zlx_conf = { 193 0x00010103, 194 0x00010103, 195 0x00010103, 196 0x00010103, 197 0x00010103, 198 0x00010103, 199 0x00010103, 200 0x00010103, 201 0x00010103, 202 0x00010103, 203 0x00010103, 204 0x00010103, 205 0x00010103, 206 0x00010103, 207 0x00010103, 208 0x00010103, 209 }, 210 .uao_p_num = IPU7P5_IS_UAO_M0_WR_PLANENUM, 211 .uao_p2tlb = { 212 0x00000041, 213 0x00000042, 214 0x00000043, 215 0x00000044, 216 0x00000041, 217 0x00000042, 218 0x00000043, 219 0x00000044, 220 0x00000041, 221 0x00000042, 222 0x00000043, 223 0x00000044, 224 0x00000041, 225 0x00000042, 226 0x00000043, 227 0x00000044, 228 }, 229 }, 230 { 231 .name = "IS_DATA_WR_SNOOP", 232 .offset = IPU7P5_IS_MMU_M1_OFFSET, 233 .zlx_offset = IPU7P5_IS_ZLX_M1_OFFSET, 234 .uao_offset = IPU7P5_IS_UAO_M1_WR_OFFSET, 235 .info_bits = 0x20004f01, 236 .refill = 0x00002322, 237 .collapse_en_bitmap = 0x1, 238 .at_sp_arb_cfg = 0x1, 239 .l1_block = IPU7P5_IS_MMU_M1_L1_BLOCKNR_REG, 240 .l2_block = IPU7P5_IS_MMU_M1_L2_BLOCKNR_REG, 241 .nr_l1streams = IPU7P5_IS_MMU_M1_STREAM_NUM, 242 .nr_l2streams = IPU7P5_IS_MMU_M1_STREAM_NUM, 243 .l1_block_sz = { 244 0x00000000, 245 0x00000002, 246 0x00000004, 247 0x00000006, 248 0x00000008, 249 0x0000000a, 250 0x0000000c, 251 0x0000000e, 252 0x00000010, 253 0x00000012, 254 0x00000014, 255 0x00000016, 256 0x00000018, 257 0x0000001a, 258 0x0000001c, 259 0x0000001e, 260 }, 261 .l2_block_sz = { 262 0x00000000, 263 0x00000002, 264 0x00000004, 265 0x00000006, 266 0x00000008, 267 0x0000000a, 268 0x0000000c, 269 0x0000000e, 270 0x00000010, 271 0x00000012, 272 0x00000014, 273 0x00000016, 274 0x00000018, 275 0x0000001a, 276 0x0000001c, 277 0x0000001e, 278 }, 279 .zlx_nr = IPU7P5_IS_ZLX_M1_NUM, 280 .zlx_axi_pool = { 281 0x00000f20, 282 }, 283 .zlx_en = { 284 1, 1, 1, 1, 1, 1, 1, 1, 285 1, 1, 1, 1, 1, 1, 1, 1, 286 }, 287 .zlx_conf = { 288 0x00010103, 289 0x00010103, 290 0x00010103, 291 0x00010103, 292 0x00010103, 293 0x00010103, 294 0x00010103, 295 0x00010103, 296 0x00010103, 297 0x00010103, 298 0x00010103, 299 0x00010103, 300 0x00010103, 301 0x00010103, 302 0x00010103, 303 0x00010103, 304 }, 305 .uao_p_num = IPU7P5_IS_UAO_M1_WR_PLANENUM, 306 .uao_p2tlb = { 307 0x00000045, 308 0x00000046, 309 0x00000047, 310 0x00000048, 311 0x00000045, 312 0x00000046, 313 0x00000047, 314 0x00000048, 315 0x00000045, 316 0x00000046, 317 0x00000047, 318 0x00000048, 319 0x00000045, 320 0x00000046, 321 0x00000047, 322 0x00000048, 323 }, 324 }, 325 }, 326 .cdc_fifos = 3, 327 .cdc_fifo_threshold = {6, 8, 2}, 328 .dmem_offset = IPU_ISYS_DMEM_OFFSET, 329 .spc_offset = IPU_ISYS_SPC_OFFSET, 330 }, 331 .isys_dma_overshoot = IPU_ISYS_OVERALLOC_MIN, 332 }; 333 334 static struct ipu_psys_internal_pdata ipu7p5_psys_ipdata = { 335 .hw_variant = { 336 .offset = IPU_UNIFIED_OFFSET, 337 .nr_mmus = IPU7P5_PS_MMU_NUM, 338 .mmu_hw = { 339 { 340 .name = "PS_FW_RD", 341 .offset = IPU7P5_PS_MMU_FW_RD_OFFSET, 342 .zlx_offset = IPU7P5_PS_ZLX_FW_RD_OFFSET, 343 .uao_offset = IPU7P5_PS_UAO_FW_RD_OFFSET, 344 .info_bits = 0x20004001, 345 .refill = 0x00002726, 346 .collapse_en_bitmap = 0x1, 347 .at_sp_arb_cfg = 0x1, 348 .l1_block = IPU7P5_PS_MMU_FW_RD_L1_BLOCKNR_REG, 349 .l2_block = IPU7P5_PS_MMU_FW_RD_L2_BLOCKNR_REG, 350 .nr_l1streams = IPU7P5_PS_MMU_FW_RD_STREAM_NUM, 351 .nr_l2streams = IPU7P5_PS_MMU_FW_RD_STREAM_NUM, 352 .l1_block_sz = { 353 0x00000000, 354 0x00000008, 355 0x0000000a, 356 0x0000000c, 357 0x0000000d, 358 0x0000000f, 359 0x00000011, 360 0x00000012, 361 0x00000013, 362 0x00000014, 363 0x00000016, 364 0x00000018, 365 0x00000019, 366 0x0000001a, 367 0x0000001a, 368 0x0000001a, 369 }, 370 .l2_block_sz = { 371 0x00000000, 372 0x00000002, 373 0x00000004, 374 0x00000006, 375 0x00000008, 376 0x0000000a, 377 0x0000000c, 378 0x0000000e, 379 0x00000010, 380 0x00000012, 381 0x00000014, 382 0x00000016, 383 0x00000018, 384 0x0000001a, 385 0x0000001c, 386 0x0000001e, 387 }, 388 .zlx_nr = IPU7P5_PS_ZLX_FW_RD_NUM, 389 .zlx_axi_pool = { 390 0x00000f30, 391 }, 392 .zlx_en = { 393 0, 1, 0, 0, 1, 1, 0, 0, 394 0, 1, 1, 0, 0, 0, 0, 0, 395 }, 396 .zlx_conf = { 397 0x00000000, 398 0x00010101, 399 0x00000000, 400 0x00000000, 401 0x00010101, 402 0x00010101, 403 0x00000000, 404 0x00000000, 405 0x00000000, 406 0x00010101, 407 0x00010101, 408 0x00000000, 409 0x00000000, 410 0x00000000, 411 0x00000000, 412 0x00000000, 413 }, 414 .uao_p_num = IPU7P5_PS_UAO_FW_RD_PLANENUM, 415 .uao_p2tlb = { 416 0x0000002e, 417 0x00000035, 418 0x00000036, 419 0x00000031, 420 0x00000037, 421 0x00000038, 422 0x00000039, 423 0x00000032, 424 0x00000033, 425 0x0000003a, 426 0x0000003b, 427 0x0000003c, 428 0x00000034, 429 0x0, 430 0x0, 431 0x0, 432 }, 433 }, 434 { 435 .name = "PS_FW_WR", 436 .offset = IPU7P5_PS_MMU_FW_WR_OFFSET, 437 .zlx_offset = IPU7P5_PS_ZLX_FW_WR_OFFSET, 438 .uao_offset = IPU7P5_PS_UAO_FW_WR_OFFSET, 439 .info_bits = 0x20003e01, 440 .refill = 0x00002322, 441 .collapse_en_bitmap = 0x1, 442 .at_sp_arb_cfg = 0x1, 443 .l1_block = IPU7P5_PS_MMU_FW_WR_L1_BLOCKNR_REG, 444 .l2_block = IPU7P5_PS_MMU_FW_WR_L2_BLOCKNR_REG, 445 .nr_l1streams = IPU7P5_PS_MMU_FW_WR_STREAM_NUM, 446 .nr_l2streams = IPU7P5_PS_MMU_FW_WR_STREAM_NUM, 447 .l1_block_sz = { 448 0x00000000, 449 0x00000008, 450 0x0000000a, 451 0x0000000c, 452 0x0000000d, 453 0x0000000e, 454 0x0000000f, 455 0x00000010, 456 0x00000010, 457 0x00000010, 458 }, 459 .l2_block_sz = { 460 0x00000000, 461 0x00000002, 462 0x00000004, 463 0x00000006, 464 0x00000008, 465 0x0000000a, 466 0x0000000c, 467 0x0000000e, 468 0x00000010, 469 0x00000012, 470 }, 471 .zlx_nr = IPU7P5_PS_ZLX_FW_WR_NUM, 472 .zlx_axi_pool = { 473 0x00000f20, 474 }, 475 .zlx_en = { 476 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 477 }, 478 .zlx_conf = { 479 0x00000000, 480 0x00010101, 481 0x00010101, 482 0x00000000, 483 0x00000000, 484 0x00000000, 485 0x00000000, 486 0x00000000, 487 0x00000000, 488 0x00000000, 489 }, 490 .uao_p_num = IPU7P5_PS_UAO_FW_WR_PLANENUM, 491 .uao_p2tlb = { 492 0x0000002e, 493 0x0000002f, 494 0x00000030, 495 0x00000031, 496 0x00000032, 497 0x00000033, 498 0x00000034, 499 0x0, 500 0x0, 501 0x0, 502 }, 503 }, 504 { 505 .name = "PS_DATA_RD", 506 .offset = IPU7P5_PS_MMU_SRT_RD_OFFSET, 507 .zlx_offset = IPU7P5_PS_ZLX_DATA_RD_OFFSET, 508 .uao_offset = IPU7P5_PS_UAO_SRT_RD_OFFSET, 509 .info_bits = 0x20003f01, 510 .refill = 0x00002524, 511 .collapse_en_bitmap = 0x1, 512 .at_sp_arb_cfg = 0x1, 513 .l1_block = IPU7P5_PS_MMU_SRT_RD_L1_BLOCKNR_REG, 514 .l2_block = IPU7P5_PS_MMU_SRT_RD_L2_BLOCKNR_REG, 515 .nr_l1streams = IPU7P5_PS_MMU_SRT_RD_STREAM_NUM, 516 .nr_l2streams = IPU7P5_PS_MMU_SRT_RD_STREAM_NUM, 517 .l1_block_sz = { 518 0x00000000, 519 0x00000004, 520 0x00000006, 521 0x00000008, 522 0x0000000b, 523 0x0000000d, 524 0x0000000f, 525 0x00000013, 526 0x00000017, 527 0x00000019, 528 0x0000001b, 529 0x0000001d, 530 0x0000001f, 531 0x0000002b, 532 0x00000033, 533 0x0000003f, 534 0x00000047, 535 0x00000049, 536 0x0000004b, 537 0x0000004c, 538 0x0000004d, 539 0x0000004e, 540 }, 541 .l2_block_sz = { 542 0x00000000, 543 0x00000002, 544 0x00000004, 545 0x00000006, 546 0x00000008, 547 0x0000000a, 548 0x0000000c, 549 0x0000000e, 550 0x00000010, 551 0x00000012, 552 0x00000014, 553 0x00000016, 554 0x00000018, 555 0x0000001a, 556 0x0000001c, 557 0x0000001e, 558 0x00000020, 559 0x00000022, 560 0x00000024, 561 0x00000026, 562 0x00000028, 563 0x0000002a, 564 }, 565 .zlx_nr = IPU7P5_PS_ZLX_DATA_RD_NUM, 566 .zlx_axi_pool = { 567 0x00000f30, 568 }, 569 .zlx_en = { 570 1, 1, 1, 1, 1, 1, 1, 1, 571 1, 1, 1, 1, 1, 1, 1, 1, 572 1, 1, 0, 0, 0, 0, 573 }, 574 .zlx_conf = { 575 0x00030303, 576 0x00010101, 577 0x00010101, 578 0x00030202, 579 0x00010101, 580 0x00010101, 581 0x00030303, 582 0x00030303, 583 0x00010101, 584 0x00030800, 585 0x00030500, 586 0x00020101, 587 0x00042000, 588 0x00031000, 589 0x00042000, 590 0x00031000, 591 0x00020400, 592 0x00010101, 593 0x00000000, 594 0x00000000, 595 0x00000000, 596 0x00000000, 597 }, 598 .uao_p_num = IPU7P5_PS_UAO_SRT_RD_PLANENUM, 599 .uao_p2tlb = { 600 0x0000001c, 601 0x0000001d, 602 0x0000001e, 603 0x0000001f, 604 0x00000020, 605 0x00000021, 606 0x00000022, 607 0x00000023, 608 0x00000024, 609 0x00000025, 610 0x00000026, 611 0x00000027, 612 0x00000028, 613 0x00000029, 614 0x0000002a, 615 0x0000002b, 616 0x0000002c, 617 0x0000002d, 618 0x00000000, 619 0x00000000, 620 0x00000000, 621 0x00000000, 622 }, 623 }, 624 { 625 .name = "PS_DATA_WR", 626 .offset = IPU7P5_PS_MMU_SRT_WR_OFFSET, 627 .zlx_offset = IPU7P5_PS_ZLX_DATA_WR_OFFSET, 628 .uao_offset = IPU7P5_PS_UAO_SRT_WR_OFFSET, 629 .info_bits = 0x20003d01, 630 .refill = 0x00002120, 631 .collapse_en_bitmap = 0x1, 632 .at_sp_arb_cfg = 0x1, 633 .l1_block = IPU7P5_PS_MMU_SRT_WR_L1_BLOCKNR_REG, 634 .l2_block = IPU7P5_PS_MMU_SRT_WR_L2_BLOCKNR_REG, 635 .nr_l1streams = IPU7P5_PS_MMU_SRT_WR_STREAM_NUM, 636 .nr_l2streams = IPU7P5_PS_MMU_SRT_WR_STREAM_NUM, 637 .l1_block_sz = { 638 0x00000000, 639 0x00000002, 640 0x00000006, 641 0x0000000a, 642 0x0000000c, 643 0x0000000e, 644 0x00000010, 645 0x00000012, 646 0x00000014, 647 0x00000016, 648 0x00000018, 649 0x0000001a, 650 0x0000001c, 651 0x0000001e, 652 0x00000020, 653 0x00000022, 654 0x00000024, 655 0x00000028, 656 0x0000002a, 657 0x00000036, 658 0x0000003e, 659 0x00000040, 660 0x00000042, 661 0x0000004e, 662 0x00000056, 663 0x0000005c, 664 0x00000068, 665 0x00000070, 666 0x00000076, 667 0x00000077, 668 0x00000078, 669 0x00000079, 670 }, 671 .l2_block_sz = { 672 0x00000000, 673 0x00000002, 674 0x00000006, 675 0x0000000a, 676 0x0000000c, 677 0x0000000e, 678 0x00000010, 679 0x00000012, 680 0x00000014, 681 0x00000016, 682 0x00000018, 683 0x0000001a, 684 0x0000001c, 685 0x0000001e, 686 0x00000020, 687 0x00000022, 688 0x00000024, 689 0x00000028, 690 0x0000002a, 691 0x00000036, 692 0x0000003e, 693 0x00000040, 694 0x00000042, 695 0x0000004e, 696 0x00000056, 697 0x0000005c, 698 0x00000068, 699 0x00000070, 700 0x00000076, 701 0x00000077, 702 0x00000078, 703 0x00000079, 704 }, 705 .zlx_nr = IPU7P5_PS_ZLX_DATA_WR_NUM, 706 .zlx_axi_pool = { 707 0x00000f50, 708 }, 709 .zlx_en = { 710 1, 1, 1, 1, 1, 1, 1, 1, 711 0, 0, 1, 1, 1, 1, 1, 1, 712 1, 1, 1, 1, 1, 1, 1, 1, 713 1, 1, 1, 1, 0, 0, 0, 0, 714 }, 715 .zlx_conf = { 716 0x00010102, 717 0x00030103, 718 0x00030103, 719 0x00010101, 720 0x00010101, 721 0x00030101, 722 0x00010101, 723 0x38010101, 724 0x00000000, 725 0x00000000, 726 0x38010101, 727 0x38010101, 728 0x38010101, 729 0x38010101, 730 0x38010101, 731 0x38010101, 732 0x00030303, 733 0x00010101, 734 0x00042000, 735 0x00031000, 736 0x00010101, 737 0x00010101, 738 0x00042000, 739 0x00031000, 740 0x00031000, 741 0x00042000, 742 0x00031000, 743 0x00031000, 744 0x00000000, 745 0x00000000, 746 0x00000000, 747 0x00000000, 748 }, 749 .uao_p_num = IPU7P5_PS_UAO_SRT_WR_PLANENUM, 750 .uao_p2tlb = { 751 0x00000000, 752 0x00000001, 753 0x00000002, 754 0x00000003, 755 0x00000004, 756 0x00000005, 757 0x00000006, 758 0x00000007, 759 0x00000008, 760 0x00000009, 761 0x0000000a, 762 0x0000000b, 763 0x0000000c, 764 0x0000000d, 765 0x0000000e, 766 0x0000000f, 767 0x00000010, 768 0x00000011, 769 0x00000012, 770 0x00000013, 771 0x00000014, 772 0x00000015, 773 0x00000016, 774 0x00000017, 775 0x00000018, 776 0x00000019, 777 0x0000001a, 778 0x0000001b, 779 0x00000000, 780 0x00000000, 781 0x00000000, 782 0x00000000, 783 }, 784 }, 785 }, 786 .dmem_offset = IPU_PSYS_DMEM_OFFSET, 787 }, 788 }; 789 790 static struct ipu_isys_internal_pdata ipu7_isys_ipdata = { 791 .csi2 = { 792 .gpreg = IS_IO_CSI2_GPREGS_BASE, 793 }, 794 .hw_variant = { 795 .offset = IPU_UNIFIED_OFFSET, 796 .nr_mmus = IPU7_IS_MMU_NUM, 797 .mmu_hw = { 798 { 799 .name = "IS_FW_RD", 800 .offset = IPU7_IS_MMU_FW_RD_OFFSET, 801 .zlx_offset = IPU7_IS_ZLX_UC_RD_OFFSET, 802 .uao_offset = IPU7_IS_UAO_UC_RD_OFFSET, 803 .info_bits = 0x20006701, 804 .refill = 0x00002726, 805 .collapse_en_bitmap = 0x0, 806 .l1_block = IPU7_IS_MMU_FW_RD_L1_BLOCKNR_REG, 807 .l2_block = IPU7_IS_MMU_FW_RD_L2_BLOCKNR_REG, 808 .nr_l1streams = IPU7_IS_MMU_FW_RD_STREAM_NUM, 809 .nr_l2streams = IPU7_IS_MMU_FW_RD_STREAM_NUM, 810 .l1_block_sz = { 811 0x0, 0x8, 0xa, 812 }, 813 .l2_block_sz = { 814 0x0, 0x2, 0x4, 815 }, 816 .zlx_nr = IPU7_IS_ZLX_UC_RD_NUM, 817 .zlx_axi_pool = { 818 0x00000f30, 819 }, 820 .zlx_en = { 821 0, 0, 0, 0 822 }, 823 .zlx_conf = { 824 0x0, 0x0, 0x0, 0x0, 825 }, 826 .uao_p_num = IPU7_IS_UAO_UC_RD_PLANENUM, 827 .uao_p2tlb = { 828 0x00000061, 829 0x00000064, 830 0x00000065, 831 }, 832 }, 833 { 834 .name = "IS_FW_WR", 835 .offset = IPU7_IS_MMU_FW_WR_OFFSET, 836 .zlx_offset = IPU7_IS_ZLX_UC_WR_OFFSET, 837 .uao_offset = IPU7_IS_UAO_UC_WR_OFFSET, 838 .info_bits = 0x20006801, 839 .refill = 0x00002524, 840 .collapse_en_bitmap = 0x0, 841 .l1_block = IPU7_IS_MMU_FW_WR_L1_BLOCKNR_REG, 842 .l2_block = IPU7_IS_MMU_FW_WR_L2_BLOCKNR_REG, 843 .nr_l1streams = IPU7_IS_MMU_FW_WR_STREAM_NUM, 844 .nr_l2streams = IPU7_IS_MMU_FW_WR_STREAM_NUM, 845 .l1_block_sz = { 846 0x0, 0x8, 0xa, 847 }, 848 .l2_block_sz = { 849 0x0, 0x2, 0x4, 850 }, 851 .zlx_nr = IPU7_IS_ZLX_UC_WR_NUM, 852 .zlx_axi_pool = { 853 0x00000f20, 854 }, 855 .zlx_en = { 856 0, 1, 1, 0, 857 }, 858 .zlx_conf = { 859 0x0, 860 0x00010101, 861 0x00010101, 862 }, 863 .uao_p_num = IPU7_IS_UAO_UC_WR_PLANENUM, 864 .uao_p2tlb = { 865 0x00000061, 866 0x00000062, 867 0x00000063, 868 }, 869 }, 870 { 871 .name = "IS_DATA_WR_ISOC", 872 .offset = IPU7_IS_MMU_M0_OFFSET, 873 .zlx_offset = IPU7_IS_ZLX_M0_OFFSET, 874 .uao_offset = IPU7_IS_UAO_M0_WR_OFFSET, 875 .info_bits = 0x20006601, 876 .refill = 0x00002120, 877 .collapse_en_bitmap = 0x0, 878 .l1_block = IPU7_IS_MMU_M0_L1_BLOCKNR_REG, 879 .l2_block = IPU7_IS_MMU_M0_L2_BLOCKNR_REG, 880 .nr_l1streams = IPU7_IS_MMU_M0_STREAM_NUM, 881 .nr_l2streams = IPU7_IS_MMU_M0_STREAM_NUM, 882 .l1_block_sz = { 883 0x0, 0x3, 0x6, 0x8, 0xa, 0xc, 0xe, 0x10, 884 }, 885 .l2_block_sz = { 886 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, 0xe, 887 }, 888 .zlx_nr = IPU7_IS_ZLX_M0_NUM, 889 .zlx_axi_pool = { 890 0x00000f10, 891 }, 892 .zlx_en = { 893 1, 1, 1, 1, 1, 1, 1, 1, 894 }, 895 .zlx_conf = { 896 0x00010103, 897 0x00010103, 898 0x00010101, 899 0x00010101, 900 0x00010101, 901 0x00010101, 902 0x00010101, 903 0x00010101, 904 }, 905 .uao_p_num = IPU7_IS_UAO_M0_WR_PLANENUM, 906 .uao_p2tlb = { 907 0x00000049, 908 0x0000004a, 909 0x0000004b, 910 0x0000004c, 911 0x0000004d, 912 0x0000004e, 913 0x0000004f, 914 0x00000050, 915 }, 916 }, 917 { 918 .name = "IS_DATA_WR_SNOOP", 919 .offset = IPU7_IS_MMU_M1_OFFSET, 920 .zlx_offset = IPU7_IS_ZLX_M1_OFFSET, 921 .uao_offset = IPU7_IS_UAO_M1_WR_OFFSET, 922 .info_bits = 0x20006901, 923 .refill = 0x00002322, 924 .collapse_en_bitmap = 0x0, 925 .l1_block = IPU7_IS_MMU_M1_L1_BLOCKNR_REG, 926 .l2_block = IPU7_IS_MMU_M1_L2_BLOCKNR_REG, 927 .nr_l1streams = IPU7_IS_MMU_M1_STREAM_NUM, 928 .nr_l2streams = IPU7_IS_MMU_M1_STREAM_NUM, 929 .l1_block_sz = { 930 0x0, 0x3, 0x6, 0x9, 0xc, 931 0xe, 0x10, 0x12, 0x14, 0x16, 932 0x18, 0x1a, 0x1c, 0x1e, 0x20, 933 0x22, 934 }, 935 .l2_block_sz = { 936 0x0, 0x2, 0x4, 0x6, 0x8, 937 0xa, 0xc, 0xe, 0x10, 0x12, 938 0x14, 0x16, 0x18, 0x1a, 0x1c, 939 0x1e, 940 }, 941 .zlx_nr = IPU7_IS_ZLX_M1_NUM, 942 .zlx_axi_pool = { 943 0x00000f20, 944 }, 945 .zlx_en = { 946 1, 1, 1, 1, 1, 1, 1, 1, 947 1, 1, 1, 1, 1, 1, 1, 1, 948 }, 949 .zlx_conf = { 950 0x00010103, 951 0x00010103, 952 0x00010103, 953 0x00010103, 954 0x00010103, 955 0x00010103, 956 0x00010103, 957 0x00010103, 958 0x00010101, 959 0x00010101, 960 0x00010101, 961 0x00010101, 962 0x00010101, 963 0x00010101, 964 0x00010101, 965 0x00010101, 966 }, 967 .uao_p_num = IPU7_IS_UAO_M1_WR_PLANENUM, 968 .uao_p2tlb = { 969 0x00000051, 970 0x00000052, 971 0x00000053, 972 0x00000054, 973 0x00000055, 974 0x00000056, 975 0x00000057, 976 0x00000058, 977 0x00000059, 978 0x0000005a, 979 0x0000005b, 980 0x0000005c, 981 0x0000005d, 982 0x0000005e, 983 0x0000005f, 984 0x00000060, 985 }, 986 }, 987 }, 988 .cdc_fifos = 3, 989 .cdc_fifo_threshold = {6, 8, 2}, 990 .dmem_offset = IPU_ISYS_DMEM_OFFSET, 991 .spc_offset = IPU_ISYS_SPC_OFFSET, 992 }, 993 .isys_dma_overshoot = IPU_ISYS_OVERALLOC_MIN, 994 }; 995 996 static struct ipu_psys_internal_pdata ipu7_psys_ipdata = { 997 .hw_variant = { 998 .offset = IPU_UNIFIED_OFFSET, 999 .nr_mmus = IPU7_PS_MMU_NUM, 1000 .mmu_hw = { 1001 { 1002 .name = "PS_FW_RD", 1003 .offset = IPU7_PS_MMU_FW_RD_OFFSET, 1004 .zlx_offset = IPU7_PS_ZLX_FW_RD_OFFSET, 1005 .uao_offset = IPU7_PS_UAO_FW_RD_OFFSET, 1006 .info_bits = 0x20004801, 1007 .refill = 0x00002726, 1008 .collapse_en_bitmap = 0x0, 1009 .l1_block = IPU7_PS_MMU_FW_RD_L1_BLOCKNR_REG, 1010 .l2_block = IPU7_PS_MMU_FW_RD_L2_BLOCKNR_REG, 1011 .nr_l1streams = IPU7_PS_MMU_FW_RD_STREAM_NUM, 1012 .nr_l2streams = IPU7_PS_MMU_FW_RD_STREAM_NUM, 1013 .l1_block_sz = { 1014 0, 0x8, 0xa, 0xc, 0xd, 1015 0xf, 0x11, 0x12, 0x13, 0x14, 1016 0x16, 0x18, 0x19, 0x1a, 0x1a, 1017 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 1018 }, 1019 .l2_block_sz = { 1020 0x0, 0x2, 0x4, 0x6, 0x8, 1021 0xa, 0xc, 0xe, 0x10, 0x12, 1022 0x14, 0x16, 0x18, 0x1a, 0x1c, 1023 0x1e, 0x20, 0x22, 0x24, 0x26, 1024 }, 1025 .zlx_nr = IPU7_PS_ZLX_FW_RD_NUM, 1026 .zlx_axi_pool = { 1027 0x00000f30, 1028 }, 1029 .zlx_en = { 1030 0, 0, 0, 0, 0, 0, 0, 0, 1031 0, 0, 0, 0, 0, 0, 0, 0, 1032 }, 1033 .zlx_conf = { 1034 0x0, 1035 }, 1036 .uao_p_num = IPU7_PS_UAO_FW_RD_PLANENUM, 1037 .uao_p2tlb = { 1038 0x00000036, 1039 0x0000003d, 1040 0x0000003e, 1041 0x00000039, 1042 0x0000003f, 1043 0x00000040, 1044 0x00000041, 1045 0x0000003a, 1046 0x0000003b, 1047 0x00000042, 1048 0x00000043, 1049 0x00000044, 1050 0x0000003c, 1051 }, 1052 }, 1053 { 1054 .name = "PS_FW_WR", 1055 .offset = IPU7_PS_MMU_FW_WR_OFFSET, 1056 .zlx_offset = IPU7_PS_ZLX_FW_WR_OFFSET, 1057 .uao_offset = IPU7_PS_UAO_FW_WR_OFFSET, 1058 .info_bits = 0x20004601, 1059 .refill = 0x00002322, 1060 .collapse_en_bitmap = 0x0, 1061 .l1_block = IPU7_PS_MMU_FW_WR_L1_BLOCKNR_REG, 1062 .l2_block = IPU7_PS_MMU_FW_WR_L2_BLOCKNR_REG, 1063 .nr_l1streams = IPU7_PS_MMU_FW_WR_STREAM_NUM, 1064 .nr_l2streams = IPU7_PS_MMU_FW_WR_STREAM_NUM, 1065 .l1_block_sz = { 1066 0, 0x8, 0xa, 0xc, 0xd, 1067 0xe, 0xf, 0x10, 0x10, 0x10, 1068 }, 1069 .l2_block_sz = { 1070 0x0, 0x2, 0x4, 0x6, 0x8, 1071 0xa, 0xc, 0xe, 0x10, 0x12, 1072 }, 1073 .zlx_nr = IPU7_PS_ZLX_FW_WR_NUM, 1074 .zlx_axi_pool = { 1075 0x00000f20, 1076 }, 1077 .zlx_en = { 1078 0, 1, 1, 0, 0, 0, 0, 0, 1079 0, 0, 1080 }, 1081 .zlx_conf = { 1082 0x0, 1083 0x00010101, 1084 0x00010101, 1085 }, 1086 .uao_p_num = IPU7_PS_UAO_FW_WR_PLANENUM, 1087 .uao_p2tlb = { 1088 0x00000036, 1089 0x00000037, 1090 0x00000038, 1091 0x00000039, 1092 0x0000003a, 1093 0x0000003b, 1094 0x0000003c, 1095 }, 1096 }, 1097 { 1098 .name = "PS_DATA_RD", 1099 .offset = IPU7_PS_MMU_SRT_RD_OFFSET, 1100 .zlx_offset = IPU7_PS_ZLX_DATA_RD_OFFSET, 1101 .uao_offset = IPU7_PS_UAO_SRT_RD_OFFSET, 1102 .info_bits = 0x20004701, 1103 .refill = 0x00002120, 1104 .collapse_en_bitmap = 0x0, 1105 .l1_block = IPU7_PS_MMU_SRT_RD_L1_BLOCKNR_REG, 1106 .l2_block = IPU7_PS_MMU_SRT_RD_L2_BLOCKNR_REG, 1107 .nr_l1streams = IPU7_PS_MMU_SRT_RD_STREAM_NUM, 1108 .nr_l2streams = IPU7_PS_MMU_SRT_RD_STREAM_NUM, 1109 .l1_block_sz = { 1110 0x0, 0x4, 0x6, 0x8, 0xb, 1111 0xd, 0xf, 0x11, 0x13, 0x15, 1112 0x17, 0x23, 0x2b, 0x37, 0x3f, 1113 0x41, 0x43, 0x44, 0x45, 0x46, 1114 0x47, 0x48, 0x49, 0x4a, 0x4b, 1115 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 1116 0x51, 0x52, 0x53, 0x55, 0x57, 1117 0x59, 0x5b, 0x5d, 0x5f, 0x61, 1118 }, 1119 .l2_block_sz = { 1120 0x0, 0x2, 0x4, 0x6, 0x8, 1121 0xa, 0xc, 0xe, 0x10, 0x12, 1122 0x14, 0x16, 0x18, 0x1a, 0x1c, 1123 0x1e, 0x20, 0x22, 0x24, 0x26, 1124 0x28, 0x2a, 0x2c, 0x2e, 0x30, 1125 0x32, 0x34, 0x36, 0x38, 0x3a, 1126 0x3c, 0x3e, 0x40, 0x42, 0x44, 1127 0x46, 0x48, 0x4a, 0x4c, 0x4e, 1128 }, 1129 .zlx_nr = IPU7_PS_ZLX_DATA_RD_NUM, 1130 .zlx_axi_pool = { 1131 0x00000f30, 1132 }, 1133 .zlx_en = { 1134 1, 1, 1, 1, 1, 1, 1, 1, 1135 1, 1, 1, 1, 1, 1, 1, 1, 1136 0, 0, 0, 0, 0, 0, 0, 0, 1137 0, 0, 0, 0, 0, 0, 0, 0, 1138 }, 1139 .zlx_conf = { 1140 0x00030303, 1141 0x00010101, 1142 0x00010101, 1143 0x00030202, 1144 0x00010101, 1145 0x00010101, 1146 0x00010101, 1147 0x00030800, 1148 0x00030500, 1149 0x00020101, 1150 0x00042000, 1151 0x00031000, 1152 0x00042000, 1153 0x00031000, 1154 0x00020400, 1155 0x00010101, 1156 }, 1157 .uao_p_num = IPU7_PS_UAO_SRT_RD_PLANENUM, 1158 .uao_p2tlb = { 1159 0x00000022, 1160 0x00000023, 1161 0x00000024, 1162 0x00000025, 1163 0x00000026, 1164 0x00000027, 1165 0x00000028, 1166 0x00000029, 1167 0x0000002a, 1168 0x0000002b, 1169 0x0000002c, 1170 0x0000002d, 1171 0x0000002e, 1172 0x0000002f, 1173 0x00000030, 1174 0x00000031, 1175 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 1176 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 1177 0x0000001e, 1178 0x0000001f, 1179 0x00000020, 1180 0x00000021, 1181 0x00000032, 1182 0x00000033, 1183 0x00000034, 1184 0x00000035, 1185 }, 1186 }, 1187 { 1188 .name = "PS_DATA_WR", 1189 .offset = IPU7_PS_MMU_SRT_WR_OFFSET, 1190 .zlx_offset = IPU7_PS_ZLX_DATA_WR_OFFSET, 1191 .uao_offset = IPU7_PS_UAO_SRT_WR_OFFSET, 1192 .info_bits = 0x20004501, 1193 .refill = 0x00002120, 1194 .collapse_en_bitmap = 0x0, 1195 .l1_block = IPU7_PS_MMU_SRT_WR_L1_BLOCKNR_REG, 1196 .l2_block = IPU7_PS_MMU_SRT_WR_L2_BLOCKNR_REG, 1197 .nr_l1streams = IPU7_PS_MMU_SRT_WR_STREAM_NUM, 1198 .nr_l2streams = IPU7_PS_MMU_SRT_WR_STREAM_NUM, 1199 .l1_block_sz = { 1200 0x0, 0x2, 0x6, 0xa, 0xc, 1201 0xe, 0x10, 0x12, 0x14, 0x16, 1202 0x18, 0x1a, 0x1c, 0x1e, 0x20, 1203 0x22, 0x24, 0x26, 0x32, 0x3a, 1204 0x3c, 0x3e, 0x4a, 0x52, 0x58, 1205 0x64, 0x6c, 0x72, 0x7e, 0x86, 1206 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 1207 0x91, 0x92, 0x94, 0x96, 0x98, 1208 }, 1209 .l2_block_sz = { 1210 0x0, 0x2, 0x4, 0x6, 0x8, 1211 0xa, 0xc, 0xe, 0x10, 0x12, 1212 0x14, 0x16, 0x18, 0x1a, 0x1c, 1213 0x1e, 0x20, 0x22, 0x24, 0x26, 1214 0x28, 0x2a, 0x2c, 0x2e, 0x30, 1215 0x32, 0x34, 0x36, 0x38, 0x3a, 1216 0x3c, 0x3e, 0x40, 0x42, 0x44, 1217 0x46, 0x48, 0x4a, 0x4c, 0x4e, 1218 }, 1219 .zlx_nr = IPU7_PS_ZLX_DATA_WR_NUM, 1220 .zlx_axi_pool = { 1221 0x00000f50, 1222 }, 1223 .zlx_en = { 1224 1, 1, 1, 1, 1, 1, 1, 1, 1225 0, 0, 1, 1, 1, 1, 1, 1, 1226 1, 1, 1, 1, 1, 1, 1, 1, 1227 1, 1, 1, 1, 1, 1, 0, 0, 1228 }, 1229 .zlx_conf = { 1230 0x00010102, 1231 0x00030103, 1232 0x00030103, 1233 0x00010101, 1234 0x00010101, 1235 0x00030101, 1236 0x00010101, 1237 0x38010101, 1238 0x0, 1239 0x0, 1240 0x38010101, 1241 0x38010101, 1242 0x38010101, 1243 0x38010101, 1244 0x38010101, 1245 0x38010101, 1246 0x00010101, 1247 0x00042000, 1248 0x00031000, 1249 0x00010101, 1250 0x00010101, 1251 0x00042000, 1252 0x00031000, 1253 0x00031000, 1254 0x00042000, 1255 0x00031000, 1256 0x00031000, 1257 0x00042000, 1258 0x00031000, 1259 0x00031000, 1260 0x0, 1261 0x0, 1262 }, 1263 .uao_p_num = IPU7_PS_UAO_SRT_WR_PLANENUM, 1264 .uao_p2tlb = { 1265 0x00000000, 1266 0x00000001, 1267 0x00000002, 1268 0x00000003, 1269 0x00000004, 1270 0x00000005, 1271 0x00000006, 1272 0x00000007, 1273 0x00000008, 1274 0x00000009, 1275 0x0000000a, 1276 0x0000000b, 1277 0x0000000c, 1278 0x0000000d, 1279 0x0000000e, 1280 0x0000000f, 1281 0x00000010, 1282 0x00000011, 1283 0x00000012, 1284 0x00000013, 1285 0x00000014, 1286 0x00000015, 1287 0x00000016, 1288 0x00000017, 1289 0x00000018, 1290 0x00000019, 1291 0x0000001a, 1292 0x0000001b, 1293 0x0000001c, 1294 0x0000001d, 1295 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 1296 0x0000001e, 1297 0x0000001f, 1298 0x00000020, 1299 0x00000021, 1300 }, 1301 }, 1302 }, 1303 .dmem_offset = IPU_PSYS_DMEM_OFFSET, 1304 }, 1305 }; 1306 1307 static struct ipu_isys_internal_pdata ipu8_isys_ipdata = { 1308 .csi2 = { 1309 .gpreg = IPU8_IS_IO_CSI2_GPREGS_BASE, 1310 }, 1311 .hw_variant = { 1312 .offset = IPU_UNIFIED_OFFSET, 1313 .nr_mmus = IPU8_IS_MMU_NUM, 1314 .mmu_hw = { 1315 { 1316 .name = "IS_FW_RD", 1317 .offset = IPU8_IS_MMU_FW_RD_OFFSET, 1318 .zlx_offset = IPU8_IS_ZLX_UC_RD_OFFSET, 1319 .uao_offset = IPU8_IS_UAO_UC_RD_OFFSET, 1320 .info_bits = 0x20005101, 1321 .refill = 0x00002726, 1322 .collapse_en_bitmap = 0x1, 1323 .at_sp_arb_cfg = 0x1, 1324 .l1_block = IPU8_IS_MMU_FW_RD_L1_BLOCKNR_REG, 1325 .l2_block = IPU8_IS_MMU_FW_RD_L2_BLOCKNR_REG, 1326 .nr_l1streams = IPU8_IS_MMU_FW_RD_STREAM_NUM, 1327 .nr_l2streams = IPU8_IS_MMU_FW_RD_STREAM_NUM, 1328 .l1_block_sz = { 1329 0x0, 0x8, 0xa, 1330 }, 1331 .l2_block_sz = { 1332 0x0, 0x2, 0x4, 1333 }, 1334 .zlx_nr = IPU8_IS_ZLX_UC_RD_NUM, 1335 .zlx_axi_pool = { 1336 0x00000f30, 1337 }, 1338 .zlx_en = { 1339 0, 1, 0, 0 1340 }, 1341 .zlx_conf = { 1342 0, 2, 0, 0 1343 }, 1344 .uao_p_num = IPU8_IS_UAO_UC_RD_PLANENUM, 1345 .uao_p2tlb = { 1346 0x00000049, 1347 0x0000004c, 1348 0x0000004d, 1349 0x00000000, 1350 }, 1351 }, 1352 { 1353 .name = "IS_FW_WR", 1354 .offset = IPU8_IS_MMU_FW_WR_OFFSET, 1355 .zlx_offset = IPU8_IS_ZLX_UC_WR_OFFSET, 1356 .uao_offset = IPU8_IS_UAO_UC_WR_OFFSET, 1357 .info_bits = 0x20005001, 1358 .refill = 0x00002524, 1359 .collapse_en_bitmap = 0x1, 1360 .at_sp_arb_cfg = 0x1, 1361 .l1_block = IPU8_IS_MMU_FW_WR_L1_BLOCKNR_REG, 1362 .l2_block = IPU8_IS_MMU_FW_WR_L2_BLOCKNR_REG, 1363 .nr_l1streams = IPU8_IS_MMU_FW_WR_STREAM_NUM, 1364 .nr_l2streams = IPU8_IS_MMU_FW_WR_STREAM_NUM, 1365 .l1_block_sz = { 1366 0x0, 0x8, 0xa, 1367 }, 1368 .l2_block_sz = { 1369 0x0, 0x2, 0x4, 1370 }, 1371 .zlx_nr = IPU8_IS_ZLX_UC_WR_NUM, 1372 .zlx_axi_pool = { 1373 0x00000f20, 1374 }, 1375 .zlx_en = { 1376 0, 1, 1, 0, 1377 }, 1378 .zlx_conf = { 1379 0x0, 1380 0x2, 1381 0x2, 1382 0x0, 1383 }, 1384 .uao_p_num = IPU8_IS_UAO_UC_WR_PLANENUM, 1385 .uao_p2tlb = { 1386 0x00000049, 1387 0x0000004a, 1388 0x0000004b, 1389 0x00000000, 1390 }, 1391 }, 1392 { 1393 .name = "IS_DATA_WR_ISOC", 1394 .offset = IPU8_IS_MMU_M0_OFFSET, 1395 .zlx_offset = IPU8_IS_ZLX_M0_OFFSET, 1396 .uao_offset = IPU8_IS_UAO_M0_WR_OFFSET, 1397 .info_bits = 0x20004e01, 1398 .refill = 0x00002120, 1399 .collapse_en_bitmap = 0x1, 1400 .at_sp_arb_cfg = 0x1, 1401 .l1_block = IPU8_IS_MMU_M0_L1_BLOCKNR_REG, 1402 .l2_block = IPU8_IS_MMU_M0_L2_BLOCKNR_REG, 1403 .nr_l1streams = IPU8_IS_MMU_M0_STREAM_NUM, 1404 .nr_l2streams = IPU8_IS_MMU_M0_STREAM_NUM, 1405 .l1_block_sz = { 1406 0x00000000, 1407 0x00000002, 1408 0x00000004, 1409 0x00000006, 1410 0x00000008, 1411 0x0000000a, 1412 0x0000000c, 1413 0x0000000e, 1414 0x00000010, 1415 0x00000012, 1416 0x00000014, 1417 0x00000016, 1418 0x00000018, 1419 0x0000001a, 1420 0x0000001c, 1421 0x0000001e, 1422 }, 1423 .l2_block_sz = { 1424 0x00000000, 1425 0x00000002, 1426 0x00000004, 1427 0x00000006, 1428 0x00000008, 1429 0x0000000a, 1430 0x0000000c, 1431 0x0000000e, 1432 0x00000010, 1433 0x00000012, 1434 0x00000014, 1435 0x00000016, 1436 0x00000018, 1437 0x0000001a, 1438 0x0000001c, 1439 0x0000001e, 1440 }, 1441 .zlx_nr = IPU8_IS_ZLX_M0_NUM, 1442 .zlx_axi_pool = { 1443 0x00000f10, 1444 }, 1445 .zlx_en = { 1446 1, 1, 1, 1, 1, 1, 1, 1, 1447 1, 1, 1, 1, 1, 1, 1, 1, 1448 }, 1449 .zlx_conf = { 1450 0x3, 1451 0x3, 1452 0x3, 1453 0x3, 1454 0x3, 1455 0x3, 1456 0x3, 1457 0x3, 1458 0x3, 1459 0x3, 1460 0x3, 1461 0x3, 1462 0x3, 1463 0x3, 1464 0x3, 1465 0x3, 1466 }, 1467 .uao_p_num = IPU8_IS_UAO_M0_WR_PLANENUM, 1468 .uao_p2tlb = { 1469 0x0000003b, 1470 0x0000003c, 1471 0x0000003d, 1472 0x0000003e, 1473 0x0000003b, 1474 0x0000003c, 1475 0x0000003d, 1476 0x0000003e, 1477 0x0000003b, 1478 0x0000003c, 1479 0x0000003d, 1480 0x0000003e, 1481 0x0000003b, 1482 0x0000003c, 1483 0x0000003d, 1484 0x0000003e, 1485 }, 1486 }, 1487 { 1488 .name = "IS_DATA_WR_SNOOP", 1489 .offset = IPU8_IS_MMU_M1_OFFSET, 1490 .zlx_offset = IPU8_IS_ZLX_M1_OFFSET, 1491 .uao_offset = IPU8_IS_UAO_M1_WR_OFFSET, 1492 .info_bits = 0x20004f01, 1493 .refill = 0x00002322, 1494 .collapse_en_bitmap = 0x1, 1495 .at_sp_arb_cfg = 0x1, 1496 .l1_block = IPU8_IS_MMU_M1_L1_BLOCKNR_REG, 1497 .l2_block = IPU8_IS_MMU_M1_L2_BLOCKNR_REG, 1498 .nr_l1streams = IPU8_IS_MMU_M1_STREAM_NUM, 1499 .nr_l2streams = IPU8_IS_MMU_M1_STREAM_NUM, 1500 .l1_block_sz = { 1501 0x00000000, 1502 0x00000002, 1503 0x00000004, 1504 0x00000006, 1505 0x00000008, 1506 0x0000000a, 1507 0x0000000c, 1508 0x0000000e, 1509 0x00000010, 1510 0x00000012, 1511 0x00000014, 1512 0x00000016, 1513 0x00000018, 1514 0x0000001a, 1515 0x0000001c, 1516 0x0000001e, 1517 }, 1518 .l2_block_sz = { 1519 0x00000000, 1520 0x00000002, 1521 0x00000004, 1522 0x00000006, 1523 0x00000008, 1524 0x0000000a, 1525 0x0000000c, 1526 0x0000000e, 1527 0x00000010, 1528 0x00000012, 1529 0x00000014, 1530 0x00000016, 1531 0x00000018, 1532 0x0000001a, 1533 0x0000001c, 1534 0x0000001e, 1535 }, 1536 .zlx_nr = IPU8_IS_ZLX_M1_NUM, 1537 .zlx_axi_pool = { 1538 0x00000f20, 1539 }, 1540 .zlx_en = { 1541 1, 1, 1, 1, 1, 1, 1, 1, 1542 1, 1, 1, 1, 1, 1, 1, 1, 1543 }, 1544 .zlx_conf = { 1545 0x3, 1546 0x3, 1547 0x3, 1548 0x3, 1549 0x3, 1550 0x3, 1551 0x3, 1552 0x3, 1553 0x3, 1554 0x3, 1555 0x3, 1556 0x3, 1557 0x3, 1558 0x3, 1559 0x3, 1560 0x3, 1561 }, 1562 .uao_p_num = IPU8_IS_UAO_M1_WR_PLANENUM, 1563 .uao_p2tlb = { 1564 0x0000003f, 1565 0x00000040, 1566 0x00000041, 1567 0x00000042, 1568 0x0000003f, 1569 0x00000040, 1570 0x00000041, 1571 0x00000042, 1572 0x0000003f, 1573 0x00000040, 1574 0x00000041, 1575 0x00000042, 1576 0x0000003f, 1577 0x00000040, 1578 0x00000041, 1579 0x00000042, 1580 }, 1581 }, 1582 { 1583 .name = "IS_UPIPE", 1584 .offset = IPU8_IS_MMU_UPIPE_OFFSET, 1585 .zlx_offset = IPU8_IS_ZLX_UPIPE_OFFSET, 1586 .uao_offset = IPU8_IS_UAO_UPIPE_OFFSET, 1587 .info_bits = 0x20005201, 1588 .refill = 0x00002928, 1589 .collapse_en_bitmap = 0x1, 1590 .at_sp_arb_cfg = 0x1, 1591 .l1_block = IPU8_IS_MMU_UPIPE_L1_BLOCKNR_REG, 1592 .l2_block = IPU8_IS_MMU_UPIPE_L2_BLOCKNR_REG, 1593 .nr_l1streams = IPU8_IS_MMU_UPIPE_STREAM_NUM, 1594 .nr_l2streams = IPU8_IS_MMU_UPIPE_STREAM_NUM, 1595 .l1_block_sz = { 1596 0x00000000, 1597 0x00000002, 1598 0x00000004, 1599 0x00000006, 1600 0x00000008, 1601 0x0000000a, 1602 }, 1603 .l2_block_sz = { 1604 0x00000000, 1605 0x00000002, 1606 0x00000004, 1607 0x00000006, 1608 0x00000008, 1609 0x0000000a, 1610 }, 1611 .zlx_nr = IPU8_IS_ZLX_UPIPE_NUM, 1612 .zlx_axi_pool = { 1613 0x00000f20, 1614 }, 1615 .zlx_en = { 1616 1, 1, 1, 1, 1, 1, 1617 }, 1618 .zlx_conf = { 1619 0x3, 1620 0x3, 1621 0x3, 1622 0x3, 1623 0x3, 1624 0x3, 1625 }, 1626 .uao_p_num = IPU8_IS_UAO_UPIPE_PLANENUM, 1627 .uao_p2tlb = { 1628 0x00000043, 1629 0x00000044, 1630 0x00000045, 1631 0x00000046, 1632 0x00000047, 1633 0x00000048, 1634 }, 1635 }, 1636 }, 1637 .cdc_fifos = 3, 1638 .cdc_fifo_threshold = {6, 8, 2}, 1639 .dmem_offset = IPU_ISYS_DMEM_OFFSET, 1640 .spc_offset = IPU_ISYS_SPC_OFFSET, 1641 }, 1642 .isys_dma_overshoot = IPU_ISYS_OVERALLOC_MIN, 1643 }; 1644 1645 static struct ipu_psys_internal_pdata ipu8_psys_ipdata = { 1646 .hw_variant = { 1647 .offset = IPU_UNIFIED_OFFSET, 1648 .nr_mmus = IPU8_PS_MMU_NUM, 1649 .mmu_hw = { 1650 { 1651 .name = "PS_FW_RD", 1652 .offset = IPU8_PS_MMU_FW_RD_OFFSET, 1653 .zlx_offset = IPU8_PS_ZLX_FW_RD_OFFSET, 1654 .uao_offset = IPU8_PS_UAO_FW_RD_OFFSET, 1655 .info_bits = 0x20003a01, 1656 .refill = 0x00002726, 1657 .collapse_en_bitmap = 0x1, 1658 .at_sp_arb_cfg = 0x1, 1659 .l1_block = IPU8_PS_MMU_FW_RD_L1_BLOCKNR_REG, 1660 .l2_block = IPU8_PS_MMU_FW_RD_L2_BLOCKNR_REG, 1661 .nr_l1streams = IPU8_PS_MMU_FW_RD_STREAM_NUM, 1662 .nr_l2streams = IPU8_PS_MMU_FW_RD_STREAM_NUM, 1663 .l1_block_sz = { 1664 0x00000000, 1665 0x00000008, 1666 0x0000000a, 1667 0x0000000e, 1668 0x00000010, 1669 0x00000012, 1670 0x00000014, 1671 0x00000016, 1672 0x00000018, 1673 0x00000018, 1674 0x00000018, 1675 0x00000018, 1676 }, 1677 .l2_block_sz = { 1678 0x00000000, 1679 0x00000002, 1680 0x00000004, 1681 0x00000006, 1682 0x00000008, 1683 0x0000000a, 1684 0x0000000c, 1685 0x0000000e, 1686 0x00000010, 1687 0x00000012, 1688 0x00000014, 1689 0x00000016, 1690 }, 1691 .zlx_nr = IPU8_PS_ZLX_FW_RD_NUM, 1692 .zlx_axi_pool = { 1693 0x00000f30, 1694 }, 1695 .zlx_en = { 1696 0, 1, 0, 0, 1, 1, 0, 0, 1697 0, 0, 0, 0, 1698 }, 1699 .zlx_conf = { 1700 0x0, 1701 0x2, 1702 0x0, 1703 0x0, 1704 0x2, 1705 0x2, 1706 0x0, 1707 0x0, 1708 0x0, 1709 0x0, 1710 0x0, 1711 0x0, 1712 }, 1713 .uao_p_num = IPU8_PS_UAO_FW_RD_PLANENUM, 1714 .uao_p2tlb = { 1715 0x0000002d, 1716 0x00000032, 1717 0x00000033, 1718 0x00000030, 1719 0x00000034, 1720 0x00000035, 1721 0x00000036, 1722 0x00000031, 1723 0x0, 1724 0x0, 1725 0x0, 1726 0x0, 1727 }, 1728 }, 1729 { 1730 .name = "PS_FW_WR", 1731 .offset = IPU8_PS_MMU_FW_WR_OFFSET, 1732 .zlx_offset = IPU8_PS_ZLX_FW_WR_OFFSET, 1733 .uao_offset = IPU8_PS_UAO_FW_WR_OFFSET, 1734 .info_bits = 0x20003901, 1735 .refill = 0x00002524, 1736 .collapse_en_bitmap = 0x1, 1737 .at_sp_arb_cfg = 0x1, 1738 .l1_block = IPU8_PS_MMU_FW_WR_L1_BLOCKNR_REG, 1739 .l2_block = IPU8_PS_MMU_FW_WR_L2_BLOCKNR_REG, 1740 .nr_l1streams = IPU8_PS_MMU_FW_WR_STREAM_NUM, 1741 .nr_l2streams = IPU8_PS_MMU_FW_WR_STREAM_NUM, 1742 .l1_block_sz = { 1743 0x00000000, 1744 0x00000008, 1745 0x0000000a, 1746 0x0000000c, 1747 0x0000000e, 1748 0x00000010, 1749 0x00000010, 1750 0x00000010, 1751 }, 1752 .l2_block_sz = { 1753 0x00000000, 1754 0x00000002, 1755 0x00000004, 1756 0x00000006, 1757 0x00000008, 1758 0x0000000a, 1759 0x0000000c, 1760 0x0000000e, 1761 }, 1762 .zlx_nr = IPU8_PS_ZLX_FW_WR_NUM, 1763 .zlx_axi_pool = { 1764 0x00000f20, 1765 }, 1766 .zlx_en = { 1767 0, 1, 1, 0, 0, 0, 0, 0, 1768 }, 1769 .zlx_conf = { 1770 0x0, 0x2, 0x2, 0x0, 1771 0x0, 0x0, 0x0, 0x0, 1772 }, 1773 .uao_p_num = IPU8_PS_UAO_FW_WR_PLANENUM, 1774 .uao_p2tlb = { 1775 0x0000002d, 1776 0x0000002e, 1777 0x0000002f, 1778 0x00000030, 1779 0x00000031, 1780 0x0, 1781 0x0, 1782 0x0, 1783 }, 1784 }, 1785 { 1786 .name = "PS_DATA_RD", 1787 .offset = IPU8_PS_MMU_SRT_RD_OFFSET, 1788 .zlx_offset = IPU8_PS_ZLX_DATA_RD_OFFSET, 1789 .uao_offset = IPU8_PS_UAO_SRT_RD_OFFSET, 1790 .info_bits = 0x20003801, 1791 .refill = 0x00002322, 1792 .collapse_en_bitmap = 0x1, 1793 .at_sp_arb_cfg = 0x1, 1794 .l1_block = IPU8_PS_MMU_SRT_RD_L1_BLOCKNR_REG, 1795 .l2_block = IPU8_PS_MMU_SRT_RD_L2_BLOCKNR_REG, 1796 .nr_l1streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM, 1797 .nr_l2streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM, 1798 .l1_block_sz = { 1799 0x00000000, 1800 0x00000004, 1801 0x00000006, 1802 0x00000008, 1803 0x0000000c, 1804 0x0000000e, 1805 0x00000010, 1806 0x00000014, 1807 0x00000018, 1808 0x0000001c, 1809 0x0000001e, 1810 0x00000022, 1811 0x00000024, 1812 0x00000026, 1813 0x00000028, 1814 0x0000002a, 1815 0x0000002c, 1816 0x0000002e, 1817 0x00000030, 1818 0x00000032, 1819 0x00000036, 1820 0x0000003a, 1821 0x0000003c, 1822 0x0000003c, 1823 0x0000003c, 1824 0x0000003c, 1825 }, 1826 .l2_block_sz = { 1827 0x00000000, 1828 0x00000002, 1829 0x00000004, 1830 0x00000006, 1831 0x00000008, 1832 0x0000000a, 1833 0x0000000c, 1834 0x0000000e, 1835 0x00000010, 1836 0x00000012, 1837 0x00000014, 1838 0x00000016, 1839 0x00000018, 1840 0x0000001a, 1841 0x0000001c, 1842 0x0000001e, 1843 0x00000020, 1844 0x00000022, 1845 0x00000024, 1846 0x00000026, 1847 0x00000028, 1848 0x0000002a, 1849 0x0000002c, 1850 0x0000002e, 1851 0x00000030, 1852 0x00000032, 1853 }, 1854 .zlx_nr = IPU8_PS_ZLX_DATA_RD_NUM, 1855 .zlx_axi_pool = { 1856 0x00000f30, 1857 }, 1858 .zlx_en = { 1859 1, 1, 1, 1, 1, 1, 1, 1, 1860 1, 1, 1, 1, 1, 1, 1, 1, 1861 1, 1, 1, 1, 1, 1, 0, 0, 1862 0, 0, 1863 }, 1864 .zlx_conf = { 1865 0x6, 0x3, 0x3, 0x6, 1866 0x2, 0x2, 0x6, 0x6, 1867 0x6, 0x3, 0x6, 0x3, 1868 0x3, 0x2, 0x2, 0x2, 1869 0x2, 0x2, 0x2, 0x6, 1870 0x6, 0x3, 0x0, 0x0, 1871 0x0, 0x0, 1872 }, 1873 .uao_p_num = IPU8_PS_UAO_SRT_RD_PLANENUM, 1874 .uao_p2tlb = { 1875 0x00000017, 1876 0x00000018, 1877 0x00000019, 1878 0x0000001a, 1879 0x0000001b, 1880 0x0000001c, 1881 0x0000001d, 1882 0x0000001e, 1883 0x0000001f, 1884 0x00000020, 1885 0x00000021, 1886 0x00000022, 1887 0x00000023, 1888 0x00000024, 1889 0x00000025, 1890 0x00000026, 1891 0x00000027, 1892 0x00000028, 1893 0x00000029, 1894 0x0000002a, 1895 0x0000002b, 1896 0x0000002c, 1897 0x0, 1898 0x0, 1899 0x0, 1900 0x0, 1901 }, 1902 }, 1903 { 1904 .name = "PS_DATA_WR", 1905 .offset = IPU8_PS_MMU_SRT_WR_OFFSET, 1906 .zlx_offset = IPU8_PS_ZLX_DATA_WR_OFFSET, 1907 .uao_offset = IPU8_PS_UAO_SRT_WR_OFFSET, 1908 .info_bits = 0x20003701, 1909 .refill = 0x00002120, 1910 .collapse_en_bitmap = 0x1, 1911 .at_sp_arb_cfg = 0x1, 1912 .l1_block = IPU8_PS_MMU_SRT_WR_L1_BLOCKNR_REG, 1913 .l2_block = IPU8_PS_MMU_SRT_WR_L2_BLOCKNR_REG, 1914 .nr_l1streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM, 1915 .nr_l2streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM, 1916 .l1_block_sz = { 1917 0x00000000, 1918 0x00000002, 1919 0x00000006, 1920 0x00000008, 1921 0x0000000a, 1922 0x0000000c, 1923 0x0000000e, 1924 0x00000010, 1925 0x00000012, 1926 0x00000014, 1927 0x00000016, 1928 0x00000018, 1929 0x0000001c, 1930 0x0000001e, 1931 0x00000022, 1932 0x00000024, 1933 0x00000028, 1934 0x0000002a, 1935 0x0000002e, 1936 0x00000030, 1937 0x00000032, 1938 0x00000036, 1939 0x00000038, 1940 0x0000003a, 1941 0x0000003a, 1942 0x0000003a, 1943 }, 1944 .l2_block_sz = { 1945 0x00000000, 1946 0x00000002, 1947 0x00000004, 1948 0x00000006, 1949 0x00000008, 1950 0x0000000a, 1951 0x0000000c, 1952 0x0000000e, 1953 0x00000010, 1954 0x00000012, 1955 0x00000014, 1956 0x00000016, 1957 0x00000018, 1958 0x0000001a, 1959 0x0000001c, 1960 0x0000001e, 1961 0x00000020, 1962 0x00000022, 1963 0x00000024, 1964 0x00000026, 1965 0x00000028, 1966 0x0000002a, 1967 0x0000002c, 1968 0x0000002e, 1969 0x00000030, 1970 0x00000032, 1971 }, 1972 .zlx_nr = IPU8_PS_ZLX_DATA_WR_NUM, 1973 .zlx_axi_pool = { 1974 0x00000f50, 1975 }, 1976 .zlx_en = { 1977 1, 1, 1, 0, 1, 1, 1, 1, 1978 1, 1, 1, 1, 1, 1, 1, 1, 1979 1, 1, 1, 1, 1, 1, 1, 0, 1980 0, 0, 1981 }, 1982 .zlx_conf = { 1983 0x3, 1984 0x6, 1985 0x38000002, 1986 0x38000000, 1987 0x3, 1988 0x38000002, 1989 0x38000002, 1990 0x38000002, 1991 0x38000002, 1992 0x38000002, 1993 0x38000002, 1994 0x6, 1995 0x3, 1996 0x6, 1997 0x3, 1998 0x6, 1999 0x3, 2000 0x6, 2001 0x3, 2002 0x3, 2003 0x6, 2004 0x3, 2005 0x3, 2006 0x0, 2007 0x0, 2008 0x0, 2009 }, 2010 .uao_p_num = IPU8_PS_UAO_SRT_WR_PLANENUM, 2011 .uao_p2tlb = { 2012 0x00000000, 2013 0x00000001, 2014 0x00000002, 2015 0x00000003, 2016 0x00000004, 2017 0x00000005, 2018 0x00000006, 2019 0x00000007, 2020 0x00000008, 2021 0x00000009, 2022 0x0000000a, 2023 0x0000000b, 2024 0x0000000c, 2025 0x0000000d, 2026 0x0000000e, 2027 0x0000000f, 2028 0x00000010, 2029 0x00000011, 2030 0x00000012, 2031 0x00000013, 2032 0x00000014, 2033 0x00000015, 2034 0x00000016, 2035 0x00000000, 2036 0x00000000, 2037 0x00000000, 2038 }, 2039 }, 2040 }, 2041 .dmem_offset = IPU_PSYS_DMEM_OFFSET, 2042 }, 2043 }; 2044 2045 static const struct ipu_buttress_ctrl ipu7_isys_buttress_ctrl = { 2046 .subsys_id = IPU_IS, 2047 .ratio = IPU7_IS_FREQ_CTL_DEFAULT_RATIO, 2048 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT, 2049 .cdyn = IPU_FREQ_CTL_CDYN, 2050 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT, 2051 .freq_ctl = BUTTRESS_REG_IS_WORKPOINT_REQ, 2052 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT, 2053 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_IS_PWR_MASK, 2054 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE, 2055 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE, 2056 .ovrd_clk = BUTTRESS_OVERRIDE_IS_CLK, 2057 .own_clk_ack = BUTTRESS_OWN_ACK_IS_CLK, 2058 }; 2059 2060 static const struct ipu_buttress_ctrl ipu7_psys_buttress_ctrl = { 2061 .subsys_id = IPU_PS, 2062 .ratio = IPU7_PS_FREQ_CTL_DEFAULT_RATIO, 2063 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT, 2064 .cdyn = IPU_FREQ_CTL_CDYN, 2065 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT, 2066 .freq_ctl = BUTTRESS_REG_PS_WORKPOINT_REQ, 2067 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT, 2068 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_PS_PWR_MASK, 2069 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE, 2070 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE, 2071 .ovrd_clk = BUTTRESS_OVERRIDE_PS_CLK, 2072 .own_clk_ack = BUTTRESS_OWN_ACK_PS_CLK, 2073 }; 2074 2075 static const struct ipu_buttress_ctrl ipu8_isys_buttress_ctrl = { 2076 .subsys_id = IPU_IS, 2077 .ratio = IPU8_IS_FREQ_CTL_DEFAULT_RATIO, 2078 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT, 2079 .cdyn = IPU_FREQ_CTL_CDYN, 2080 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT, 2081 .freq_ctl = BUTTRESS_REG_IS_WORKPOINT_REQ, 2082 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT, 2083 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_IS_PWR_MASK, 2084 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE, 2085 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE, 2086 }; 2087 2088 static const struct ipu_buttress_ctrl ipu8_psys_buttress_ctrl = { 2089 .subsys_id = IPU_PS, 2090 .ratio = IPU8_PS_FREQ_CTL_DEFAULT_RATIO, 2091 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT, 2092 .cdyn = IPU_FREQ_CTL_CDYN, 2093 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT, 2094 .freq_ctl = BUTTRESS_REG_PS_WORKPOINT_REQ, 2095 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT, 2096 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_PS_PWR_MASK, 2097 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE, 2098 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE, 2099 .own_clk_ack = BUTTRESS_OWN_ACK_PS_PLL, 2100 }; 2101 2102 void ipu_internal_pdata_init(struct ipu_isys_internal_pdata *isys_ipdata, 2103 struct ipu_psys_internal_pdata *psys_ipdata) 2104 { 2105 isys_ipdata->csi2.nports = ARRAY_SIZE(ipu7_csi_offsets); 2106 isys_ipdata->csi2.offsets = ipu7_csi_offsets; 2107 isys_ipdata->num_parallel_streams = IPU7_ISYS_NUM_STREAMS; 2108 psys_ipdata->hw_variant.spc_offset = IPU7_PSYS_SPC_OFFSET; 2109 } 2110 2111 static int ipu7_isys_check_fwnode_graph(struct fwnode_handle *fwnode) 2112 { 2113 struct fwnode_handle *endpoint; 2114 2115 if (IS_ERR_OR_NULL(fwnode)) 2116 return -EINVAL; 2117 2118 endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); 2119 if (endpoint) { 2120 fwnode_handle_put(endpoint); 2121 return 0; 2122 } 2123 2124 return ipu7_isys_check_fwnode_graph(fwnode->secondary); 2125 } 2126 2127 static struct ipu7_bus_device * 2128 ipu7_isys_init(struct pci_dev *pdev, struct device *parent, 2129 const struct ipu_buttress_ctrl *ctrl, void __iomem *base, 2130 const struct ipu_isys_internal_pdata *ipdata, 2131 unsigned int nr) 2132 { 2133 struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev); 2134 struct ipu7_bus_device *isys_adev; 2135 struct device *dev = &pdev->dev; 2136 struct ipu7_isys_pdata *pdata; 2137 int ret; 2138 2139 ret = ipu7_isys_check_fwnode_graph(fwnode); 2140 if (ret) { 2141 if (fwnode && !IS_ERR_OR_NULL(fwnode->secondary)) { 2142 dev_err(dev, 2143 "fwnode graph has no endpoints connection\n"); 2144 return ERR_PTR(-EINVAL); 2145 } 2146 2147 ret = ipu_bridge_init(dev, ipu_bridge_parse_ssdb); 2148 if (ret) { 2149 dev_err_probe(dev, ret, "IPU bridge init failed\n"); 2150 return ERR_PTR(ret); 2151 } 2152 } 2153 2154 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 2155 if (!pdata) 2156 return ERR_PTR(-ENOMEM); 2157 2158 pdata->base = base; 2159 pdata->ipdata = ipdata; 2160 2161 isys_adev = ipu7_bus_initialize_device(pdev, parent, pdata, ctrl, 2162 IPU_ISYS_NAME); 2163 if (IS_ERR(isys_adev)) { 2164 dev_err_probe(dev, PTR_ERR(isys_adev), 2165 "ipu7_bus_initialize_device isys failed\n"); 2166 kfree(pdata); 2167 return ERR_CAST(isys_adev); 2168 } 2169 2170 isys_adev->mmu = ipu7_mmu_init(dev, base, ISYS_MMID, 2171 &ipdata->hw_variant); 2172 if (IS_ERR(isys_adev->mmu)) { 2173 dev_err_probe(dev, PTR_ERR(isys_adev->mmu), 2174 "ipu7_mmu_init(isys_adev->mmu) failed\n"); 2175 put_device(&isys_adev->auxdev.dev); 2176 kfree(pdata); 2177 return ERR_CAST(isys_adev->mmu); 2178 } 2179 2180 isys_adev->mmu->dev = &isys_adev->auxdev.dev; 2181 isys_adev->subsys = IPU_IS; 2182 2183 ret = ipu7_bus_add_device(isys_adev); 2184 if (ret) { 2185 kfree(pdata); 2186 return ERR_PTR(ret); 2187 } 2188 2189 return isys_adev; 2190 } 2191 2192 static struct ipu7_bus_device * 2193 ipu7_psys_init(struct pci_dev *pdev, struct device *parent, 2194 const struct ipu_buttress_ctrl *ctrl, void __iomem *base, 2195 const struct ipu_psys_internal_pdata *ipdata, unsigned int nr) 2196 { 2197 struct ipu7_bus_device *psys_adev; 2198 struct ipu7_psys_pdata *pdata; 2199 int ret; 2200 2201 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 2202 if (!pdata) 2203 return ERR_PTR(-ENOMEM); 2204 2205 pdata->base = base; 2206 pdata->ipdata = ipdata; 2207 2208 psys_adev = ipu7_bus_initialize_device(pdev, parent, pdata, ctrl, 2209 IPU_PSYS_NAME); 2210 if (IS_ERR(psys_adev)) { 2211 dev_err_probe(&pdev->dev, PTR_ERR(psys_adev), 2212 "ipu7_bus_initialize_device psys failed\n"); 2213 kfree(pdata); 2214 return ERR_CAST(psys_adev); 2215 } 2216 2217 psys_adev->mmu = ipu7_mmu_init(&pdev->dev, base, PSYS_MMID, 2218 &ipdata->hw_variant); 2219 if (IS_ERR(psys_adev->mmu)) { 2220 dev_err_probe(&pdev->dev, PTR_ERR(psys_adev->mmu), 2221 "ipu7_mmu_init(psys_adev->mmu) failed\n"); 2222 put_device(&psys_adev->auxdev.dev); 2223 kfree(pdata); 2224 return ERR_CAST(psys_adev->mmu); 2225 } 2226 2227 psys_adev->mmu->dev = &psys_adev->auxdev.dev; 2228 psys_adev->subsys = IPU_PS; 2229 2230 ret = ipu7_bus_add_device(psys_adev); 2231 if (ret) { 2232 kfree(pdata); 2233 return ERR_PTR(ret); 2234 } 2235 2236 return psys_adev; 2237 } 2238 2239 static struct ia_gofo_msg_log_info_ts fw_error_log[IPU_SUBSYS_NUM]; 2240 void ipu7_dump_fw_error_log(const struct ipu7_bus_device *adev) 2241 { 2242 void __iomem *reg = adev->isp->base + ((adev->subsys == IPU_IS) ? 2243 BUTTRESS_REG_FW_GP24 : 2244 BUTTRESS_REG_FW_GP8); 2245 2246 memcpy_fromio(&fw_error_log[adev->subsys], reg, 2247 sizeof(fw_error_log[adev->subsys])); 2248 } 2249 EXPORT_SYMBOL_NS_GPL(ipu7_dump_fw_error_log, "INTEL_IPU7"); 2250 2251 static int ipu7_pci_config_setup(struct pci_dev *dev) 2252 { 2253 u16 pci_command; 2254 int ret; 2255 2256 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 2257 pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 2258 pci_write_config_word(dev, PCI_COMMAND, pci_command); 2259 2260 ret = pci_enable_msi(dev); 2261 if (ret) 2262 dev_err(&dev->dev, "Failed to enable msi (%d)\n", ret); 2263 2264 return ret; 2265 } 2266 2267 static int ipu7_map_fw_code_region(struct ipu7_bus_device *sys, 2268 void *data, size_t size) 2269 { 2270 struct device *dev = &sys->auxdev.dev; 2271 struct ipu7_bus_device *adev = to_ipu7_bus_device(dev); 2272 struct sg_table *sgt = &sys->fw_sgt; 2273 struct ipu7_device *isp = adev->isp; 2274 struct pci_dev *pdev = isp->pdev; 2275 unsigned long n_pages, i; 2276 unsigned long attr = 0; 2277 struct page **pages; 2278 int ret; 2279 2280 n_pages = PFN_UP(size); 2281 2282 pages = kmalloc_array(n_pages, sizeof(*pages), GFP_KERNEL); 2283 if (!pages) 2284 return -ENOMEM; 2285 2286 for (i = 0; i < n_pages; i++) { 2287 struct page *p = vmalloc_to_page(data); 2288 2289 if (!p) { 2290 ret = -ENODEV; 2291 goto out; 2292 } 2293 2294 pages[i] = p; 2295 data += PAGE_SIZE; 2296 } 2297 2298 ret = sg_alloc_table_from_pages(sgt, pages, n_pages, 0, size, 2299 GFP_KERNEL); 2300 if (ret) { 2301 ret = -ENOMEM; 2302 goto out; 2303 } 2304 2305 if (!isp->secure_mode) 2306 attr |= DMA_ATTR_RESERVE_REGION; 2307 2308 ret = dma_map_sgtable(&pdev->dev, sgt, DMA_BIDIRECTIONAL, 0); 2309 if (ret < 0) { 2310 dev_err(dev, "map fw code[%lu pages %u nents] failed\n", 2311 n_pages, sgt->nents); 2312 ret = -ENOMEM; 2313 sg_free_table(sgt); 2314 goto out; 2315 } 2316 2317 ret = ipu7_dma_map_sgtable(sys, sgt, DMA_BIDIRECTIONAL, attr); 2318 if (ret) { 2319 dma_unmap_sgtable(&pdev->dev, sgt, DMA_BIDIRECTIONAL, 0); 2320 sg_free_table(sgt); 2321 goto out; 2322 } 2323 2324 ipu7_dma_sync_sgtable(sys, sgt); 2325 2326 dev_dbg(dev, "fw code region mapped at 0x%pad entries %d\n", 2327 &sgt->sgl->dma_address, sgt->nents); 2328 2329 out: 2330 kfree(pages); 2331 2332 return ret; 2333 } 2334 2335 static void ipu7_unmap_fw_code_region(struct ipu7_bus_device *sys) 2336 { 2337 struct pci_dev *pdev = sys->isp->pdev; 2338 struct sg_table *sgt = &sys->fw_sgt; 2339 2340 ipu7_dma_unmap_sgtable(sys, sgt, DMA_BIDIRECTIONAL, 0); 2341 dma_unmap_sgtable(&pdev->dev, sgt, DMA_BIDIRECTIONAL, 0); 2342 sg_free_table(sgt); 2343 } 2344 2345 static int ipu7_init_fw_code_region_by_sys(struct ipu7_bus_device *sys, 2346 const char *sys_name) 2347 { 2348 struct device *dev = &sys->auxdev.dev; 2349 struct ipu7_device *isp = sys->isp; 2350 int ret; 2351 2352 /* Copy FW binaries to specific location. */ 2353 ret = ipu7_cpd_copy_binary(isp->cpd_fw->data, sys_name, 2354 isp->fw_code_region, &sys->fw_entry); 2355 if (ret) { 2356 dev_err(dev, "%s binary not found.\n", sys_name); 2357 return ret; 2358 } 2359 2360 ret = pm_runtime_get_sync(dev); 2361 if (ret < 0) { 2362 dev_err(dev, "Failed to get runtime PM\n"); 2363 return ret; 2364 } 2365 2366 ret = ipu7_mmu_hw_init(sys->mmu); 2367 if (ret) { 2368 dev_err(dev, "Failed to set mmu hw\n"); 2369 pm_runtime_put(dev); 2370 return ret; 2371 } 2372 2373 /* Map code region. */ 2374 ret = ipu7_map_fw_code_region(sys, isp->fw_code_region, 2375 IPU_FW_CODE_REGION_SIZE); 2376 if (ret) 2377 dev_err(dev, "Failed to map fw code region for %s.\n", 2378 sys_name); 2379 2380 ipu7_mmu_hw_cleanup(sys->mmu); 2381 pm_runtime_put(dev); 2382 2383 return ret; 2384 } 2385 2386 static int ipu7_init_fw_code_region(struct ipu7_device *isp) 2387 { 2388 int ret; 2389 2390 /* 2391 * Allocate and map memory for FW execution. 2392 * Not required in secure mode, in which FW runs in IMR. 2393 */ 2394 isp->fw_code_region = vmalloc(IPU_FW_CODE_REGION_SIZE); 2395 if (!isp->fw_code_region) 2396 return -ENOMEM; 2397 2398 ret = ipu7_init_fw_code_region_by_sys(isp->isys, "isys"); 2399 if (ret) 2400 goto fail_init; 2401 2402 ret = ipu7_init_fw_code_region_by_sys(isp->psys, "psys"); 2403 if (ret) 2404 goto fail_init; 2405 2406 return 0; 2407 2408 fail_init: 2409 vfree(isp->fw_code_region); 2410 2411 return ret; 2412 } 2413 2414 static int ipu7_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2415 { 2416 struct ipu_buttress_ctrl *isys_ctrl = NULL, *psys_ctrl = NULL; 2417 struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev); 2418 const struct ipu_buttress_ctrl *isys_buttress_ctrl; 2419 const struct ipu_buttress_ctrl *psys_buttress_ctrl; 2420 struct ipu_isys_internal_pdata *isys_ipdata; 2421 struct ipu_psys_internal_pdata *psys_ipdata; 2422 unsigned int dma_mask = IPU_DMA_MASK; 2423 struct device *dev = &pdev->dev; 2424 void __iomem *isys_base = NULL; 2425 void __iomem *psys_base = NULL; 2426 phys_addr_t phys, pb_phys; 2427 struct ipu7_device *isp; 2428 u32 is_es; 2429 int ret; 2430 2431 if (!fwnode || fwnode_property_read_u32(fwnode, "is_es", &is_es)) 2432 is_es = 0; 2433 2434 isp = devm_kzalloc(dev, sizeof(*isp), GFP_KERNEL); 2435 if (!isp) 2436 return -ENOMEM; 2437 2438 dev_set_name(dev, "intel-ipu7"); 2439 isp->pdev = pdev; 2440 INIT_LIST_HEAD(&isp->devices); 2441 2442 ret = pcim_enable_device(pdev); 2443 if (ret) 2444 return dev_err_probe(dev, ret, "Enable PCI device failed\n"); 2445 2446 dev_info(dev, "Device 0x%x (rev: 0x%x)\n", 2447 pdev->device, pdev->revision); 2448 2449 phys = pci_resource_start(pdev, IPU_PCI_BAR); 2450 pb_phys = pci_resource_start(pdev, IPU_PCI_PBBAR); 2451 dev_info(dev, "IPU7 PCI BAR0 base %pap BAR2 base %pap\n", 2452 &phys, &pb_phys); 2453 2454 isp->base = pcim_iomap_region(pdev, IPU_PCI_BAR, IPU_NAME); 2455 if (IS_ERR(isp->base)) 2456 return dev_err_probe(dev, PTR_ERR(isp->base), 2457 "Failed to I/O memory remapping bar %u\n", 2458 IPU_PCI_BAR); 2459 2460 isp->pb_base = pcim_iomap_region(pdev, IPU_PCI_PBBAR, IPU_NAME); 2461 if (IS_ERR(isp->pb_base)) 2462 return dev_err_probe(dev, PTR_ERR(isp->pb_base), 2463 "Failed to I/O memory remapping bar %u\n", 2464 IPU_PCI_PBBAR); 2465 2466 dev_info(dev, "IPU7 PCI BAR0 mapped at %p\n BAR2 mapped at %p\n", 2467 isp->base, isp->pb_base); 2468 2469 pci_set_drvdata(pdev, isp); 2470 pci_set_master(pdev); 2471 2472 switch (id->device) { 2473 case IPU7_PCI_ID: 2474 isp->hw_ver = IPU_VER_7; 2475 isp->cpd_fw_name = IPU7_FIRMWARE_NAME; 2476 isys_ipdata = &ipu7_isys_ipdata; 2477 psys_ipdata = &ipu7_psys_ipdata; 2478 isys_buttress_ctrl = &ipu7_isys_buttress_ctrl; 2479 psys_buttress_ctrl = &ipu7_psys_buttress_ctrl; 2480 break; 2481 case IPU7P5_PCI_ID: 2482 isp->hw_ver = IPU_VER_7P5; 2483 isp->cpd_fw_name = IPU7P5_FIRMWARE_NAME; 2484 isys_ipdata = &ipu7p5_isys_ipdata; 2485 psys_ipdata = &ipu7p5_psys_ipdata; 2486 isys_buttress_ctrl = &ipu7_isys_buttress_ctrl; 2487 psys_buttress_ctrl = &ipu7_psys_buttress_ctrl; 2488 break; 2489 case IPU8_PCI_ID: 2490 isp->hw_ver = IPU_VER_8; 2491 isp->cpd_fw_name = IPU8_FIRMWARE_NAME; 2492 isys_ipdata = &ipu8_isys_ipdata; 2493 psys_ipdata = &ipu8_psys_ipdata; 2494 isys_buttress_ctrl = &ipu8_isys_buttress_ctrl; 2495 psys_buttress_ctrl = &ipu8_psys_buttress_ctrl; 2496 break; 2497 default: 2498 WARN(1, "Unsupported IPU device"); 2499 return -ENODEV; 2500 } 2501 2502 ipu_internal_pdata_init(isys_ipdata, psys_ipdata); 2503 2504 isys_base = isp->base + isys_ipdata->hw_variant.offset; 2505 psys_base = isp->base + psys_ipdata->hw_variant.offset; 2506 2507 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_mask)); 2508 if (ret) 2509 return dev_err_probe(dev, ret, "Failed to set DMA mask\n"); 2510 2511 dma_set_max_seg_size(dev, UINT_MAX); 2512 2513 ret = ipu7_pci_config_setup(pdev); 2514 if (ret) 2515 return ret; 2516 2517 ret = ipu_buttress_init(isp); 2518 if (ret) 2519 return ret; 2520 2521 dev_info(dev, "firmware cpd file: %s\n", isp->cpd_fw_name); 2522 2523 ret = request_firmware(&isp->cpd_fw, isp->cpd_fw_name, dev); 2524 if (ret) { 2525 dev_err_probe(dev, ret, 2526 "Requesting signed firmware %s failed\n", 2527 isp->cpd_fw_name); 2528 goto buttress_exit; 2529 } 2530 2531 ret = ipu7_cpd_validate_cpd_file(isp, isp->cpd_fw->data, 2532 isp->cpd_fw->size); 2533 if (ret) { 2534 dev_err_probe(dev, ret, "Failed to validate cpd\n"); 2535 goto out_ipu_bus_del_devices; 2536 } 2537 2538 isys_ctrl = devm_kmemdup(dev, isys_buttress_ctrl, 2539 sizeof(*isys_buttress_ctrl), GFP_KERNEL); 2540 if (!isys_ctrl) { 2541 ret = -ENOMEM; 2542 goto out_ipu_bus_del_devices; 2543 } 2544 2545 isp->isys = ipu7_isys_init(pdev, dev, isys_ctrl, isys_base, 2546 isys_ipdata, 0); 2547 if (IS_ERR(isp->isys)) { 2548 ret = PTR_ERR(isp->isys); 2549 goto out_ipu_bus_del_devices; 2550 } 2551 2552 psys_ctrl = devm_kmemdup(dev, psys_buttress_ctrl, 2553 sizeof(*psys_buttress_ctrl), GFP_KERNEL); 2554 if (!psys_ctrl) { 2555 ret = -ENOMEM; 2556 goto out_ipu_bus_del_devices; 2557 } 2558 2559 isp->psys = ipu7_psys_init(pdev, &isp->isys->auxdev.dev, 2560 psys_ctrl, psys_base, 2561 psys_ipdata, 0); 2562 if (IS_ERR(isp->psys)) { 2563 ret = PTR_ERR(isp->psys); 2564 goto out_ipu_bus_del_devices; 2565 } 2566 2567 ret = devm_request_threaded_irq(dev, pdev->irq, 2568 ipu_buttress_isr, 2569 ipu_buttress_isr_threaded, 2570 IRQF_SHARED, IPU_NAME, isp); 2571 if (ret) 2572 goto out_ipu_bus_del_devices; 2573 2574 if (!isp->secure_mode) { 2575 ret = ipu7_init_fw_code_region(isp); 2576 if (ret) 2577 goto out_ipu_bus_del_devices; 2578 } else { 2579 ret = pm_runtime_get_sync(&isp->psys->auxdev.dev); 2580 if (ret < 0) { 2581 dev_err(&isp->psys->auxdev.dev, 2582 "Failed to get runtime PM\n"); 2583 goto out_ipu_bus_del_devices; 2584 } 2585 2586 ret = ipu7_mmu_hw_init(isp->psys->mmu); 2587 if (ret) { 2588 dev_err_probe(&isp->pdev->dev, ret, 2589 "Failed to init MMU hardware\n"); 2590 goto out_ipu_bus_del_devices; 2591 } 2592 2593 ret = ipu7_map_fw_code_region(isp->psys, 2594 (void *)isp->cpd_fw->data, 2595 isp->cpd_fw->size); 2596 if (ret) { 2597 dev_err_probe(&isp->pdev->dev, ret, 2598 "failed to map fw image\n"); 2599 goto out_ipu_bus_del_devices; 2600 } 2601 2602 ret = ipu_buttress_authenticate(isp); 2603 if (ret) { 2604 dev_err_probe(&isp->pdev->dev, ret, 2605 "FW authentication failed\n"); 2606 goto out_ipu_bus_del_devices; 2607 } 2608 2609 ipu7_mmu_hw_cleanup(isp->psys->mmu); 2610 pm_runtime_put(&isp->psys->auxdev.dev); 2611 } 2612 2613 pm_runtime_put_noidle(dev); 2614 pm_runtime_allow(dev); 2615 2616 isp->ipu7_bus_ready_to_probe = true; 2617 2618 return 0; 2619 2620 out_ipu_bus_del_devices: 2621 if (!IS_ERR_OR_NULL(isp->isys) && isp->isys->fw_sgt.nents) 2622 ipu7_unmap_fw_code_region(isp->isys); 2623 if (!IS_ERR_OR_NULL(isp->psys) && isp->psys->fw_sgt.nents) 2624 ipu7_unmap_fw_code_region(isp->psys); 2625 if (!IS_ERR_OR_NULL(isp->psys) && !IS_ERR_OR_NULL(isp->psys->mmu)) 2626 ipu7_mmu_cleanup(isp->psys->mmu); 2627 if (!IS_ERR_OR_NULL(isp->isys) && !IS_ERR_OR_NULL(isp->isys->mmu)) 2628 ipu7_mmu_cleanup(isp->isys->mmu); 2629 if (!IS_ERR_OR_NULL(isp->psys)) 2630 pm_runtime_put(&isp->psys->auxdev.dev); 2631 ipu7_bus_del_devices(pdev); 2632 release_firmware(isp->cpd_fw); 2633 buttress_exit: 2634 ipu_buttress_exit(isp); 2635 2636 return ret; 2637 } 2638 2639 static void ipu7_pci_remove(struct pci_dev *pdev) 2640 { 2641 struct ipu7_device *isp = pci_get_drvdata(pdev); 2642 2643 if (!IS_ERR_OR_NULL(isp->isys) && isp->isys->fw_sgt.nents) 2644 ipu7_unmap_fw_code_region(isp->isys); 2645 if (!IS_ERR_OR_NULL(isp->psys) && isp->psys->fw_sgt.nents) 2646 ipu7_unmap_fw_code_region(isp->psys); 2647 2648 if (!IS_ERR_OR_NULL(isp->fw_code_region)) 2649 vfree(isp->fw_code_region); 2650 2651 ipu7_bus_del_devices(pdev); 2652 2653 pm_runtime_forbid(&pdev->dev); 2654 pm_runtime_get_noresume(&pdev->dev); 2655 2656 ipu_buttress_exit(isp); 2657 2658 release_firmware(isp->cpd_fw); 2659 2660 ipu7_mmu_cleanup(isp->psys->mmu); 2661 ipu7_mmu_cleanup(isp->isys->mmu); 2662 } 2663 2664 static void ipu7_pci_reset_prepare(struct pci_dev *pdev) 2665 { 2666 struct ipu7_device *isp = pci_get_drvdata(pdev); 2667 2668 dev_warn(&pdev->dev, "FLR prepare\n"); 2669 pm_runtime_forbid(&isp->pdev->dev); 2670 } 2671 2672 static void ipu7_pci_reset_done(struct pci_dev *pdev) 2673 { 2674 struct ipu7_device *isp = pci_get_drvdata(pdev); 2675 2676 ipu_buttress_restore(isp); 2677 if (isp->secure_mode) 2678 ipu_buttress_reset_authentication(isp); 2679 2680 isp->ipc_reinit = true; 2681 pm_runtime_allow(&isp->pdev->dev); 2682 2683 dev_warn(&pdev->dev, "FLR completed\n"); 2684 } 2685 2686 /* 2687 * PCI base driver code requires driver to provide these to enable 2688 * PCI device level PM state transitions (D0<->D3) 2689 */ 2690 static int ipu7_suspend(struct device *dev) 2691 { 2692 return 0; 2693 } 2694 2695 static int ipu7_resume(struct device *dev) 2696 { 2697 struct pci_dev *pdev = to_pci_dev(dev); 2698 struct ipu7_device *isp = pci_get_drvdata(pdev); 2699 struct ipu_buttress *b = &isp->buttress; 2700 int ret; 2701 2702 isp->secure_mode = ipu_buttress_get_secure_mode(isp); 2703 dev_info(dev, "IPU7 in %s mode\n", 2704 isp->secure_mode ? "secure" : "non-secure"); 2705 2706 ipu_buttress_restore(isp); 2707 2708 ret = ipu_buttress_ipc_reset(isp, &b->cse); 2709 if (ret) 2710 dev_err(dev, "IPC reset protocol failed!\n"); 2711 2712 ret = pm_runtime_get_sync(&isp->psys->auxdev.dev); 2713 if (ret < 0) { 2714 dev_err(dev, "Failed to get runtime PM\n"); 2715 return 0; 2716 } 2717 2718 ret = ipu_buttress_authenticate(isp); 2719 if (ret) 2720 dev_err(dev, "FW authentication failed(%d)\n", ret); 2721 2722 pm_runtime_put(&isp->psys->auxdev.dev); 2723 2724 return 0; 2725 } 2726 2727 static int ipu7_runtime_resume(struct device *dev) 2728 { 2729 struct pci_dev *pdev = to_pci_dev(dev); 2730 struct ipu7_device *isp = pci_get_drvdata(pdev); 2731 int ret; 2732 2733 ipu_buttress_restore(isp); 2734 2735 if (isp->ipc_reinit) { 2736 struct ipu_buttress *b = &isp->buttress; 2737 2738 isp->ipc_reinit = false; 2739 ret = ipu_buttress_ipc_reset(isp, &b->cse); 2740 if (ret) 2741 dev_err(dev, "IPC reset protocol failed!\n"); 2742 } 2743 2744 return 0; 2745 } 2746 2747 static const struct dev_pm_ops ipu7_pm_ops = { 2748 SYSTEM_SLEEP_PM_OPS(&ipu7_suspend, &ipu7_resume) 2749 RUNTIME_PM_OPS(&ipu7_suspend, &ipu7_runtime_resume, NULL) 2750 }; 2751 2752 static const struct pci_device_id ipu7_pci_tbl[] = { 2753 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IPU7_PCI_ID)}, 2754 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IPU7P5_PCI_ID)}, 2755 {0,} 2756 }; 2757 MODULE_DEVICE_TABLE(pci, ipu7_pci_tbl); 2758 2759 static const struct pci_error_handlers pci_err_handlers = { 2760 .reset_prepare = ipu7_pci_reset_prepare, 2761 .reset_done = ipu7_pci_reset_done, 2762 }; 2763 2764 static struct pci_driver ipu7_pci_driver = { 2765 .name = IPU_NAME, 2766 .id_table = ipu7_pci_tbl, 2767 .probe = ipu7_pci_probe, 2768 .remove = ipu7_pci_remove, 2769 .driver = { 2770 .pm = &ipu7_pm_ops, 2771 }, 2772 .err_handler = &pci_err_handlers, 2773 }; 2774 2775 module_pci_driver(ipu7_pci_driver); 2776 2777 MODULE_IMPORT_NS("INTEL_IPU_BRIDGE"); 2778 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 2779 MODULE_AUTHOR("Tianshu Qiu <tian.shu.qiu@intel.com>"); 2780 MODULE_AUTHOR("Qingwu Zhang <qingwu.zhang@intel.com>"); 2781 MODULE_AUTHOR("Intel"); 2782 MODULE_LICENSE("GPL"); 2783 MODULE_DESCRIPTION("Intel ipu7 pci driver"); 2784