1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 - 2025 Intel Corporation 4 */ 5 6 #ifndef IPU7_BUTTRESS_REGS_H 7 #define IPU7_BUTTRESS_REGS_H 8 9 #define BUTTRESS_REG_IRQ_STATUS 0x2000 10 #define BUTTRESS_REG_IRQ_STATUS_UNMASKED 0x2004 11 #define BUTTRESS_REG_IRQ_ENABLE 0x2008 12 #define BUTTRESS_REG_IRQ_CLEAR 0x200c 13 #define BUTTRESS_REG_IRQ_MASK 0x2010 14 #define BUTTRESS_REG_TSC_CMD 0x2014 15 #define BUTTRESS_REG_TSC_CTL 0x2018 16 #define BUTTRESS_REG_TSC_LO 0x201c 17 #define BUTTRESS_REG_TSC_HI 0x2020 18 19 /* valid for PTL */ 20 #define BUTTRESS_REG_PB_TIMESTAMP_LO 0x2030 21 #define BUTTRESS_REG_PB_TIMESTAMP_HI 0x2034 22 #define BUTTRESS_REG_PB_TIMESTAMP_VALID 0x2038 23 24 #define BUTTRESS_REG_PS_WORKPOINT_REQ 0x2100 25 #define BUTTRESS_REG_IS_WORKPOINT_REQ 0x2104 26 #define BUTTRESS_REG_PS_WORKPOINT_DOMAIN_REQ 0x2108 27 #define BUTTRESS_REG_PS_DOMAINS_STATUS 0x2110 28 #define BUTTRESS_REG_PWR_STATUS 0x2114 29 #define BUTTRESS_REG_PS_WORKPOINT_REQ_SHADOW 0x2120 30 #define BUTTRESS_REG_IS_WORKPOINT_REQ_SHADOW 0x2124 31 #define BUTTRESS_REG_PS_WORKPOINT_DOMAIN_REQ_SHADOW 0x2128 32 #define BUTTRESS_REG_ISPS_WORKPOINT_DOWNLOAD 0x212c 33 #define BUTTRESS_REG_PG_FLOW_OVERRIDE 0x2180 34 #define BUTTRESS_REG_GLOBAL_OVERRIDE_UNGATE_CTL 0x2184 35 #define BUTTRESS_REG_PWR_FSM_CTL 0x2188 36 #define BUTTRESS_REG_IDLE_WDT 0x218c 37 #define BUTTRESS_REG_PS_PWR_DOMAIN_EVENTQ_EN 0x2190 38 #define BUTTRESS_REG_PS_PWR_DOMAIN_EVENTQ_ADDR 0x2194 39 #define BUTTRESS_REG_PS_PWR_DOMAIN_EVENTQ_DATA 0x2198 40 #define BUTTRESS_REG_POWER_EN_DELAY 0x219c 41 #define IPU7_BUTTRESS_REG_LTR_CONTROL 0x21a0 42 #define IPU7_BUTTRESS_REG_NDE_CONTROL 0x21a4 43 #define IPU7_BUTTRESS_REG_INT_FRM_PUNIT 0x21a8 44 #define IPU8_BUTTRESS_REG_LTR_CONTROL 0x21a4 45 #define IPU8_BUTTRESS_REG_NDE_CONTROL 0x21a8 46 #define IPU8_BUTTRESS_REG_INT_FRM_PUNIT 0x21ac 47 #define BUTTRESS_REG_SLEEP_LEVEL_CFG 0x21b0 48 #define BUTTRESS_REG_SLEEP_LEVEL_STS 0x21b4 49 #define BUTTRESS_REG_DVFS_FSM_STATUS 0x21b8 50 #define BUTTRESS_REG_PS_PLL_ENABLE 0x21bc 51 #define BUTTRESS_REG_D2D_CTL 0x21d4 52 #define BUTTRESS_REG_IB_CLK_CTL 0x21d8 53 #define BUTTRESS_REG_IB_CRO_CLK_CTL 0x21dc 54 #define BUTTRESS_REG_FUNC_FUSES 0x21e0 55 #define BUTTRESS_REG_ISOCH_CTL 0x21e4 56 #define BUTTRESS_REG_WORKPOINT_CTL 0x21f0 57 #define BUTTRESS_REG_DRV_IS_UCX_CONTROL_STATUS 0x2200 58 #define BUTTRESS_REG_DRV_IS_UCX_START_ADDR 0x2204 59 #define BUTTRESS_REG_DRV_PS_UCX_CONTROL_STATUS 0x2208 60 #define BUTTRESS_REG_DRV_PS_UCX_START_ADDR 0x220c 61 #define BUTTRESS_REG_DRV_UCX_RESET_CFG 0x2210 62 63 /* configured by CSE */ 64 #define BUTTRESS_REG_CSE_IS_UCX_CONTROL_STATUS 0x2300 65 #define BUTTRESS_REG_CSE_IS_UCX_START_ADDR 0x2304 66 #define BUTTRESS_REG_CSE_PS_UCX_CONTROL_STATUS 0x2308 67 #define BUTTRESS_REG_CSE_PS_UCX_START_ADDR 0x230c 68 69 #define BUTTRESS_REG_CAMERA_MASK 0x2310 70 #define BUTTRESS_REG_FW_CTL 0x2314 71 #define BUTTRESS_REG_SECURITY_CTL 0x2318 72 #define BUTTRESS_REG_FUNCTIONAL_FW_SETUP 0x231c 73 #define BUTTRESS_REG_FW_BASE 0x2320 74 #define BUTTRESS_REG_FW_BASE_LIMIT 0x2324 75 #define BUTTRESS_REG_FW_SCRATCH_BASE 0x2328 76 #define BUTTRESS_REG_FW_SCRATCH_LIMIT 0x232c 77 #define BUTTRESS_REG_CSE_ACTION 0x2330 78 79 /* configured by SW */ 80 #define BUTTRESS_REG_FW_RESET_CTL 0x2334 81 #define BUTTRESS_REG_FW_SOURCE_SIZE 0x2338 82 #define BUTTRESS_REG_FW_SOURCE_BASE 0x233c 83 84 #define BUTTRESS_REG_IPU_SEC_CP_LSB 0x2400 85 #define BUTTRESS_REG_IPU_SEC_CP_MSB 0x2404 86 #define BUTTRESS_REG_IPU_SEC_WAC_LSB 0x2408 87 #define BUTTRESS_REG_IPU_SEC_WAC_MSB 0x240c 88 #define BUTTRESS_REG_IPU_SEC_RAC_LSB 0x2410 89 #define BUTTRESS_REG_IPU_SEC_RAC_MSB 0x2414 90 #define BUTTRESS_REG_IPU_DRV_CP_LSB 0x2418 91 #define BUTTRESS_REG_IPU_DRV_CP_MSB 0x241c 92 #define BUTTRESS_REG_IPU_DRV_WAC_LSB 0x2420 93 #define BUTTRESS_REG_IPU_DRV_WAC_MSB 0x2424 94 #define BUTTRESS_REG_IPU_DRV_RAC_LSB 0x2428 95 #define BUTTRESS_REG_IPU_DRV_RAC_MSB 0x242c 96 #define BUTTRESS_REG_IPU_FW_CP_LSB 0x2430 97 #define BUTTRESS_REG_IPU_FW_CP_MSB 0x2434 98 #define BUTTRESS_REG_IPU_FW_WAC_LSB 0x2438 99 #define BUTTRESS_REG_IPU_FW_WAC_MSB 0x243c 100 #define BUTTRESS_REG_IPU_FW_RAC_LSB 0x2440 101 #define BUTTRESS_REG_IPU_FW_RAC_MSB 0x2444 102 #define BUTTRESS_REG_IPU_BIOS_SEC_CP_LSB 0x2448 103 #define BUTTRESS_REG_IPU_BIOS_SEC_CP_MSB 0x244c 104 #define BUTTRESS_REG_IPU_BIOS_SEC_WAC_LSB 0x2450 105 #define BUTTRESS_REG_IPU_BIOS_SEC_WAC_MSB 0x2454 106 #define BUTTRESS_REG_IPU_BIOS_SEC_RAC_LSB 0x2458 107 #define BUTTRESS_REG_IPU_BIOS_SEC_RAC_MSB 0x245c 108 #define BUTTRESS_REG_IPU_DFD_CP_LSB 0x2460 109 #define BUTTRESS_REG_IPU_DFD_CP_MSB 0x2464 110 #define BUTTRESS_REG_IPU_DFD_WAC_LSB 0x2468 111 #define BUTTRESS_REG_IPU_DFD_WAC_MSB 0x246c 112 #define BUTTRESS_REG_IPU_DFD_RAC_LSB 0x2470 113 #define BUTTRESS_REG_IPU_DFD_RAC_MSB 0x2474 114 #define BUTTRESS_REG_CSE2IUDB0 0x2500 115 #define BUTTRESS_REG_CSE2IUDATA0 0x2504 116 #define BUTTRESS_REG_CSE2IUCSR 0x2508 117 #define BUTTRESS_REG_IU2CSEDB0 0x250c 118 #define BUTTRESS_REG_IU2CSEDATA0 0x2510 119 #define BUTTRESS_REG_IU2CSECSR 0x2514 120 #define BUTTRESS_REG_CSE2IUDB0_CR_SHADOW 0x2520 121 #define BUTTRESS_REG_CSE2IUDATA0_CR_SHADOW 0x2524 122 #define BUTTRESS_REG_CSE2IUCSR_CR_SHADOW 0x2528 123 #define BUTTRESS_REG_IU2CSEDB0_CR_SHADOW 0x252c 124 #define BUTTRESS_REG_DVFS_FSM_SURVIVABILITY 0x2900 125 #define BUTTRESS_REG_FLOWS_FSM_SURVIVABILITY 0x2904 126 #define BUTTRESS_REG_FABRICS_FSM_SURVIVABILITY 0x2908 127 #define BUTTRESS_REG_PS_SUB1_PM_FSM_SURVIVABILITY 0x290c 128 #define BUTTRESS_REG_PS_SUB0_PM_FSM_SURVIVABILITY 0x2910 129 #define BUTTRESS_REG_PS_PM_FSM_SURVIVABILITY 0x2914 130 #define BUTTRESS_REG_IS_PM_FSM_SURVIVABILITY 0x2918 131 #define BUTTRESS_REG_FLR_RST_FSM_SURVIVABILITY 0x291c 132 #define BUTTRESS_REG_FW_RST_FSM_SURVIVABILITY 0x2920 133 #define BUTTRESS_REG_RESETPREP_FSM_SURVIVABILITY 0x2924 134 #define BUTTRESS_REG_POWER_FSM_DOMAIN_STATUS 0x3000 135 #define BUTTRESS_REG_IDLEREQ_STATUS1 0x3004 136 #define BUTTRESS_REG_POWER_FSM_STATUS_IS_PS 0x3008 137 #define BUTTRESS_REG_POWER_ACK_B_STATUS 0x300c 138 #define BUTTRESS_REG_DOMAIN_RETENTION_CTL 0x3010 139 #define BUTTRESS_REG_CG_CTRL_BITS 0x3014 140 #define BUTTRESS_REG_IS_IFC_STATUS0 0x3018 141 #define BUTTRESS_REG_IS_IFC_STATUS1 0x301c 142 #define BUTTRESS_REG_PS_IFC_STATUS0 0x3020 143 #define BUTTRESS_REG_PS_IFC_STATUS1 0x3024 144 #define BUTTRESS_REG_BTRS_IFC_STATUS0 0x3028 145 #define BUTTRESS_REG_BTRS_IFC_STATUS1 0x302c 146 #define BUTTRESS_REG_IPU_SKU 0x3030 147 #define BUTTRESS_REG_PS_IDLEACK 0x3034 148 #define BUTTRESS_REG_IS_IDLEACK 0x3038 149 #define BUTTRESS_REG_SPARE_REGS_0 0x303c 150 #define BUTTRESS_REG_SPARE_REGS_1 0x3040 151 #define BUTTRESS_REG_SPARE_REGS_2 0x3044 152 #define BUTTRESS_REG_SPARE_REGS_3 0x3048 153 #define BUTTRESS_REG_IUNIT_ACV 0x304c 154 #define BUTTRESS_REG_CHICKEN_BITS 0x3050 155 #define BUTTRESS_REG_SBENDPOINT_CFG 0x3054 156 #define BUTTRESS_REG_ECC_ERR_LOG 0x3058 157 #define BUTTRESS_REG_POWER_FSM_STATUS 0x3070 158 #define BUTTRESS_REG_RESET_FSM_STATUS 0x3074 159 #define BUTTRESS_REG_IDLE_STATUS 0x3078 160 #define BUTTRESS_REG_IDLEACK_STATUS 0x307c 161 #define BUTTRESS_REG_IPU_DEBUG 0x3080 162 163 #define BUTTRESS_REG_FW_BOOT_PARAMS0 0x4000 164 #define BUTTRESS_REG_FW_BOOT_PARAMS1 0x4004 165 #define BUTTRESS_REG_FW_BOOT_PARAMS2 0x4008 166 #define BUTTRESS_REG_FW_BOOT_PARAMS3 0x400c 167 #define BUTTRESS_REG_FW_BOOT_PARAMS4 0x4010 168 #define BUTTRESS_REG_FW_BOOT_PARAMS5 0x4014 169 #define BUTTRESS_REG_FW_BOOT_PARAMS6 0x4018 170 #define BUTTRESS_REG_FW_BOOT_PARAMS7 0x401c 171 #define BUTTRESS_REG_FW_BOOT_PARAMS8 0x4020 172 #define BUTTRESS_REG_FW_BOOT_PARAMS9 0x4024 173 #define BUTTRESS_REG_FW_BOOT_PARAMS10 0x4028 174 #define BUTTRESS_REG_FW_BOOT_PARAMS11 0x402c 175 #define BUTTRESS_REG_FW_BOOT_PARAMS12 0x4030 176 #define BUTTRESS_REG_FW_BOOT_PARAMS13 0x4034 177 #define BUTTRESS_REG_FW_BOOT_PARAMS14 0x4038 178 #define BUTTRESS_REG_FW_BOOT_PARAMS15 0x403c 179 180 #define BUTTRESS_FW_BOOT_PARAMS_ENTRY(i) \ 181 (BUTTRESS_REG_FW_BOOT_PARAMS0 + ((i) * 4U)) 182 #define BUTTRESS_REG_FW_GP(i) (0x4040 + 0x4 * (i)) 183 #define BUTTRESS_REG_FPGA_SUPPORT(i) (0x40c0 + 0x4 * (i)) 184 185 #define BUTTRESS_REG_FW_GP8 0x4060 186 #define BUTTRESS_REG_FW_GP24 0x40a0 187 188 #define BUTTRESS_REG_GPIO_0_PADCFG_ADDR_CR 0x4100 189 #define BUTTRESS_REG_GPIO_1_PADCFG_ADDR_CR 0x4104 190 #define BUTTRESS_REG_GPIO_2_PADCFG_ADDR_CR 0x4108 191 #define BUTTRESS_REG_GPIO_3_PADCFG_ADDR_CR 0x410c 192 #define BUTTRESS_REG_GPIO_4_PADCFG_ADDR_CR 0x4110 193 #define BUTTRESS_REG_GPIO_5_PADCFG_ADDR_CR 0x4114 194 #define BUTTRESS_REG_GPIO_6_PADCFG_ADDR_CR 0x4118 195 #define BUTTRESS_REG_GPIO_7_PADCFG_ADDR_CR 0x411c 196 #define BUTTRESS_REG_GPIO_ENABLE 0x4140 197 #define BUTTRESS_REG_GPIO_VALUE_CR 0x4144 198 199 #define BUTTRESS_REG_IS_MEM_CORRECTABLE_ERROR_STATUS 0x5000 200 #define BUTTRESS_REG_IS_MEM_FATAL_ERROR_STATUS 0x5004 201 #define BUTTRESS_REG_IS_MEM_NON_FATAL_ERROR_STATUS 0x5008 202 #define BUTTRESS_REG_IS_MEM_CHECK_PASSED 0x500c 203 #define BUTTRESS_REG_IS_MEM_ERROR_INJECT 0x5010 204 #define BUTTRESS_REG_IS_MEM_ERROR_CLEAR 0x5014 205 #define BUTTRESS_REG_PS_MEM_CORRECTABLE_ERROR_STATUS 0x5040 206 #define BUTTRESS_REG_PS_MEM_FATAL_ERROR_STATUS 0x5044 207 #define BUTTRESS_REG_PS_MEM_NON_FATAL_ERROR_STATUS 0x5048 208 #define BUTTRESS_REG_PS_MEM_CHECK_PASSED 0x504c 209 #define BUTTRESS_REG_PS_MEM_ERROR_INJECT 0x5050 210 #define BUTTRESS_REG_PS_MEM_ERROR_CLEAR 0x5054 211 212 #define BUTTRESS_REG_IS_AB_REGION_MIN_ADDRESS(i) (0x6000 + 0x8 * (i)) 213 #define BUTTRESS_REG_IS_AB_REGION_MAX_ADDRESS(i) (0x6004 + 0x8 * (i)) 214 #define BUTTRESS_REG_IS_AB_VIOLATION_LOG0 0x6080 215 #define BUTTRESS_REG_IS_AB_VIOLATION_LOG1 0x6084 216 #define BUTTRESS_REG_PS_AB_REGION_MIN_ADDRESS(i) (0x6100 + 0x8 * (i)) 217 #define BUTTRESS_REG_PS_AB_REGION_MAX_ADDRESS0 (0x6104 + 0x8 * (i)) 218 #define BUTTRESS_REG_PS_AB_VIOLATION_LOG0 0x6180 219 #define BUTTRESS_REG_PS_AB_VIOLATION_LOG1 0x6184 220 #define BUTTRESS_REG_PS_DEBUG_AB_VIOLATION_LOG0 0x6200 221 #define BUTTRESS_REG_PS_DEBUG_AB_VIOLATION_LOG1 0x6204 222 #define BUTTRESS_REG_IS_DEBUG_AB_VIOLATION_LOG0 0x6208 223 #define BUTTRESS_REG_IS_DEBUG_AB_VIOLATION_LOG1 0x620c 224 #define BUTTRESS_REG_IB_DVP_AB_VIOLATION_LOG0 0x6210 225 #define BUTTRESS_REG_IB_DVP_AB_VIOLATION_LOG1 0x6214 226 #define BUTTRESS_REG_IB_ATB2DTF_AB_VIOLATION_LOG0 0x6218 227 #define BUTTRESS_REG_IB_ATB2DTF_AB_VIOLATION_LOG1 0x621c 228 #define BUTTRESS_REG_AB_ENABLE 0x6220 229 #define BUTTRESS_REG_AB_DEFAULT_ACCESS 0x6230 230 231 /* Indicates CSE has received an IPU driver IPC transaction */ 232 #define BUTTRESS_IRQ_IPC_EXEC_DONE_BY_CSE BIT(0) 233 /* Indicates an IPC transaction from CSE has arrived */ 234 #define BUTTRESS_IRQ_IPC_FROM_CSE_IS_WAITING BIT(1) 235 /* Indicates a CSR update from CSE has arrived */ 236 #define BUTTRESS_IRQ_CSE_CSR_SET BIT(2) 237 /* Indicates an interrupt set by Punit (not in use at this time) */ 238 #define BUTTRESS_IRQ_PUNIT_2_IUNIT_IRQ BIT(3) 239 /* Indicates an SAI violation was detected on access to IB registers */ 240 #define BUTTRESS_IRQ_SAI_VIOLATION BIT(4) 241 /* Indicates a transaction to IS was not able to pass the access blocker */ 242 #define BUTTRESS_IRQ_IS_AB_VIOLATION BIT(5) 243 /* Indicates a transaction to PS was not able to pass the access blocker */ 244 #define BUTTRESS_IRQ_PS_AB_VIOLATION BIT(6) 245 /* Indicates an error response was detected by the IB config NoC */ 246 #define BUTTRESS_IRQ_IB_CFG_NOC_ERR_IRQ BIT(7) 247 /* Indicates an error response was detected by the IB data NoC */ 248 #define BUTTRESS_IRQ_IB_DATA_NOC_ERR_IRQ BIT(8) 249 /* Transaction to DVP regs was not able to pass the access blocker */ 250 #define BUTTRESS_IRQ_IB_DVP_AB_VIOLATION BIT(9) 251 /* Transaction to ATB2DTF regs was not able to pass the access blocker */ 252 #define BUTTRESS_IRQ_ATB2DTF_AB_VIOLATION BIT(10) 253 /* Transaction to IS debug regs was not able to pass the access blocker */ 254 #define BUTTRESS_IRQ_IS_DEBUG_AB_VIOLATION BIT(11) 255 /* Transaction to PS debug regs was not able to pass the access blocker */ 256 #define BUTTRESS_IRQ_PS_DEBUG_AB_VIOLATION BIT(12) 257 /* Indicates timeout occurred waiting for a response from a target */ 258 #define BUTTRESS_IRQ_IB_CFG_NOC_TIMEOUT_IRQ BIT(13) 259 /* Set when any correctable ECC error input wire to buttress is set */ 260 #define BUTTRESS_IRQ_ECC_CORRECTABLE BIT(14) 261 /* Any noncorrectable-nonfatal ECC error input wire to buttress is set */ 262 #define BUTTRESS_IRQ_ECC_NONCORRECTABLE_NONFATAL BIT(15) 263 /* Set when any noncorrectable-fatal ECC error input wire to buttress is set */ 264 #define BUTTRESS_IRQ_ECC_NONCORRECTABLE_FATAL BIT(16) 265 /* Set when timeout occurred waiting for a response from a target */ 266 #define BUTTRESS_IRQ_IS_CFG_NOC_TIMEOUT_IRQ BIT(17) 267 #define BUTTRESS_IRQ_PS_CFG_NOC_TIMEOUT_IRQ BIT(18) 268 #define BUTTRESS_IRQ_LB_CFG_NOC_TIMEOUT_IRQ BIT(19) 269 /* IS FW double exception event */ 270 #define BUTTRESS_IRQ_IS_UC_PFATAL_ERROR BIT(26) 271 /* PS FW double exception event */ 272 #define BUTTRESS_IRQ_PS_UC_PFATAL_ERROR BIT(27) 273 /* IS FW watchdog event */ 274 #define BUTTRESS_IRQ_IS_WATCHDOG BIT(28) 275 /* PS FW watchdog event */ 276 #define BUTTRESS_IRQ_PS_WATCHDOG BIT(29) 277 /* IS IRC irq out */ 278 #define BUTTRESS_IRQ_IS_IRQ BIT(30) 279 /* PS IRC irq out */ 280 #define BUTTRESS_IRQ_PS_IRQ BIT(31) 281 282 /* buttress irq */ 283 #define BUTTRESS_PWR_STATUS_HH_STATE_IDLE 0U 284 #define BUTTRESS_PWR_STATUS_HH_STATE_IN_PRGS 1U 285 #define BUTTRESS_PWR_STATUS_HH_STATE_DONE 2U 286 #define BUTTRESS_PWR_STATUS_HH_STATE_ERR 3U 287 288 #define BUTTRESS_TSC_CMD_START_TSC_SYNC BIT(0) 289 #define BUTTRESS_PWR_STATUS_HH_STATUS_SHIFT 11 290 #define BUTTRESS_PWR_STATUS_HH_STATUS_MASK (0x3U << 11) 291 #define BUTTRESS_TSW_WA_SOFT_RESET BIT(8) 292 /* new for PTL */ 293 #define BUTTRESS_SEL_PB_TIMESTAMP BIT(9) 294 #define BUTTRESS_IRQS (BUTTRESS_IRQ_IS_IRQ | \ 295 BUTTRESS_IRQ_PS_IRQ | \ 296 BUTTRESS_IRQ_IPC_FROM_CSE_IS_WAITING | \ 297 BUTTRESS_IRQ_CSE_CSR_SET | \ 298 BUTTRESS_IRQ_IPC_EXEC_DONE_BY_CSE | \ 299 BUTTRESS_IRQ_PUNIT_2_IUNIT_IRQ) 300 301 /* Iunit to CSE regs */ 302 #define BUTTRESS_IU2CSEDB0_BUSY BIT(31) 303 #define BUTTRESS_IU2CSEDB0_SHORT_FORMAT_SHIFT 27 304 #define BUTTRESS_IU2CSEDB0_CLIENT_ID_SHIFT 10 305 #define BUTTRESS_IU2CSEDB0_IPC_CLIENT_ID_VAL 2 306 307 #define BUTTRESS_IU2CSEDATA0_IPC_BOOT_LOAD 1 308 #define BUTTRESS_IU2CSEDATA0_IPC_AUTH_RUN 2 309 #define BUTTRESS_IU2CSEDATA0_IPC_AUTH_REPLACE 3 310 #define BUTTRESS_IU2CSEDATA0_IPC_UPDATE_SECURE_TOUCH 16 311 312 #define BUTTRESS_CSE2IUDATA0_IPC_BOOT_LOAD_DONE BIT(0) 313 #define BUTTRESS_CSE2IUDATA0_IPC_AUTH_RUN_DONE BIT(1) 314 #define BUTTRESS_CSE2IUDATA0_IPC_AUTH_REPLACE_DONE BIT(2) 315 #define BUTTRESS_CSE2IUDATA0_IPC_UPDATE_SECURE_TOUCH_DONE BIT(4) 316 317 #define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE1 BIT(0) 318 #define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE2 BIT(1) 319 #define BUTTRESS_IU2CSECSR_IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE BIT(2) 320 #define BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ BIT(3) 321 #define BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID BIT(4) 322 #define BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ BIT(5) 323 324 /* 0x20 == NACK, 0xf == unknown command */ 325 #define BUTTRESS_CSE2IUDATA0_IPC_NACK 0xf20 326 #define BUTTRESS_CSE2IUDATA0_IPC_NACK_MASK 0xffff 327 328 /* IS/PS freq control */ 329 #define BUTTRESS_IS_FREQ_CTL_RATIO_MASK 0xffU 330 #define BUTTRESS_PS_FREQ_CTL_RATIO_MASK 0xffU 331 332 #define IPU7_IS_FREQ_MAX 450 333 #define IPU7_IS_FREQ_MIN 50 334 #define IPU7_PS_FREQ_MAX 750 335 #define BUTTRESS_PS_FREQ_RATIO_STEP 25U 336 /* valid for IPU8 */ 337 #define BUTTRESS_IS_FREQ_RATIO_STEP 25U 338 339 /* IS: 400mhz, PS: 500mhz */ 340 #define IPU7_IS_FREQ_CTL_DEFAULT_RATIO 0x1b 341 #define IPU7_PS_FREQ_CTL_DEFAULT_RATIO 0x14 342 /* IS: 400mhz, PS: 400mhz */ 343 #define IPU8_IS_FREQ_CTL_DEFAULT_RATIO 0x10 344 #define IPU8_PS_FREQ_CTL_DEFAULT_RATIO 0x10 345 346 #define IPU_FREQ_CTL_CDYN 0x80 347 #define IPU_FREQ_CTL_RATIO_SHIFT 0x0 348 #define IPU_FREQ_CTL_CDYN_SHIFT 0x8 349 350 /* buttree power status */ 351 #define IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT 0 352 #define IPU_BUTTRESS_PWR_STATE_IS_PWR_MASK \ 353 (0x3U << IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT) 354 355 #define IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT 4 356 #define IPU_BUTTRESS_PWR_STATE_PS_PWR_MASK \ 357 (0x3U << IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT) 358 359 #define IPU_BUTTRESS_PWR_STATE_DN_DONE 0x0 360 #define IPU_BUTTRESS_PWR_STATE_UP_PROCESS 0x1 361 #define IPU_BUTTRESS_PWR_STATE_DN_PROCESS 0x2 362 #define IPU_BUTTRESS_PWR_STATE_UP_DONE 0x3 363 364 #define BUTTRESS_PWR_STATE_IS_PWR_SHIFT 3 365 #define BUTTRESS_PWR_STATE_IS_PWR_MASK (0x3 << 3) 366 367 #define BUTTRESS_PWR_STATE_PS_PWR_SHIFT 6 368 #define BUTTRESS_PWR_STATE_PS_PWR_MASK (0x3 << 6) 369 370 #define PS_FSM_CG BIT(3) 371 372 #define BUTTRESS_OVERRIDE_IS_CLK BIT(1) 373 #define BUTTRESS_OVERRIDE_PS_CLK BIT(2) 374 /* ps_pll only valid for ipu8 */ 375 #define BUTTRESS_OWN_ACK_PS_PLL BIT(8) 376 #define BUTTRESS_OWN_ACK_IS_CLK BIT(9) 377 #define BUTTRESS_OWN_ACK_PS_CLK BIT(10) 378 379 /* FW reset ctrl */ 380 #define BUTTRESS_FW_RESET_CTL_START BIT(0) 381 #define BUTTRESS_FW_RESET_CTL_DONE BIT(1) 382 383 /* security */ 384 #define BUTTRESS_SECURITY_CTL_FW_SECURE_MODE BIT(16) 385 #define BUTTRESS_SECURITY_CTL_FW_SETUP_MASK GENMASK(4, 0) 386 387 #define BUTTRESS_SECURITY_CTL_FW_SETUP_DONE BIT(0) 388 #define BUTTRESS_SECURITY_CTL_AUTH_DONE BIT(1) 389 #define BUTTRESS_SECURITY_CTL_AUTH_FAILED BIT(3) 390 391 /* D2D */ 392 #define BUTTRESS_D2D_PWR_EN BIT(0) 393 #define BUTTRESS_D2D_PWR_ACK BIT(4) 394 395 /* NDE */ 396 #define NDE_VAL_MASK GENMASK(9, 0) 397 #define NDE_SCALE_MASK GENMASK(12, 10) 398 #define NDE_VALID_MASK BIT(13) 399 #define NDE_RESVEC_MASK GENMASK(19, 16) 400 #define NDE_IN_VBLANK_DIS_MASK BIT(31) 401 402 #define BUTTRESS_NDE_VAL_ACTIVE 48 403 #define BUTTRESS_NDE_SCALE_ACTIVE 2 404 #define BUTTRESS_NDE_VALID_ACTIVE 1 405 406 #define BUTTRESS_NDE_VAL_DEFAULT 1023 407 #define BUTTRESS_NDE_SCALE_DEFAULT 2 408 #define BUTTRESS_NDE_VALID_DEFAULT 0 409 410 /* IS and PS UCX control */ 411 #define UCX_CTL_RESET BIT(0) 412 #define UCX_CTL_RUN BIT(1) 413 #define UCX_CTL_WAKEUP BIT(2) 414 #define UCX_CTL_SPARE GENMASK(7, 3) 415 #define UCX_STS_PWR GENMASK(17, 16) 416 #define UCX_STS_SLEEPING BIT(18) 417 418 /* offset from PHY base */ 419 #define PHY_CSI_CFG 0xc0 420 #define PHY_CSI_RCOMP_CONTROL 0xc8 421 #define PHY_CSI_BSCAN_EXCLUDE 0xd8 422 423 #define PHY_CPHY_DLL_OVRD(x) (0x100 + 0x100 * (x)) 424 #define PHY_DPHY_DLL_OVRD(x) (0x14c + 0x100 * (x)) 425 #define PHY_CPHY_RX_CONTROL1(x) (0x110 + 0x100 * (x)) 426 #define PHY_CPHY_RX_CONTROL2(x) (0x114 + 0x100 * (x)) 427 #define PHY_DPHY_CFG(x) (0x148 + 0x100 * (x)) 428 #define PHY_BB_AFE_CONFIG(x) (0x174 + 0x100 * (x)) 429 430 /* PB registers */ 431 #define INTERRUPT_STATUS 0x0 432 #define BTRS_LOCAL_INTERRUPT_MASK 0x4 433 #define GLOBAL_INTERRUPT_MASK 0x8 434 #define HM_ATS 0xc 435 #define ATS_ERROR_LOG1 0x10 436 #define ATS_ERROR_LOG2 0x14 437 #define ATS_ERROR_CLEAR 0x18 438 #define CFI_0_ERROR_LOG 0x1c 439 #define CFI_0_ERROR_CLEAR 0x20 440 #define HASH_CONFIG 0x2c 441 #define TLBID_HASH_ENABLE_31_0 0x30 442 #define TLBID_HASH_ENABLE_63_32 0x34 443 #define TLBID_HASH_ENABLE_95_64 0x38 444 #define TLBID_HASH_ENABLE_127_96 0x3c 445 #define CFI_1_ERROR_LOGGING 0x40 446 #define CFI_1_ERROR_CLEAR 0x44 447 #define IMR_ERROR_LOGGING_LOW 0x48 448 #define IMR_ERROR_LOGGING_HIGH 0x4c 449 #define IMR_ERROR_CLEAR 0x50 450 #define PORT_ARBITRATION_WEIGHTS 0x54 451 #define IMR_ERROR_LOGGING_CFI_1_LOW 0x58 452 #define IMR_ERROR_LOGGING_CFI_1_HIGH 0x5c 453 #define IMR_ERROR_CLEAR_CFI_1 0x60 454 #define BAR2_MISC_CONFIG 0x64 455 #define RSP_ID_CONFIG_AXI2CFI_0 0x68 456 #define RSP_ID_CONFIG_AXI2CFI_1 0x6c 457 #define PB_DRIVER_PCODE_MAILBOX_STATUS 0x70 458 #define PB_DRIVER_PCODE_MAILBOX_INTERFACE 0x74 459 #define PORT_ARBITRATION_WEIGHTS_ATS 0x78 460 461 #endif /* IPU7_BUTTRESS_REGS_H */ 462