1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // SpacemiT K1 SPI controller driver 4 // 5 // Copyright (C) 2026, RISCstar Solutions Corporation 6 // Copyright (C) 2023, SpacemiT Corporation 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset.h> 18 #include <linux/scatterlist.h> 19 #include <linux/sizes.h> 20 #include <linux/spi/spi.h> 21 #include <linux/units.h> 22 23 #include "internals.h" 24 25 /* This is the range of transfer rates supported by the K1 SoC */ 26 #define K1_SPI_MIN_SPEED_HZ 6250 27 #define K1_SPI_MAX_SPEED_HZ 51200000 28 29 /* DMA constraints */ 30 #define K1_SPI_DMA_ALIGNMENT 64 31 #define K1_SPI_MAX_DMA_LEN SZ_512K 32 33 /* SSP Top Control Register */ 34 #define SSP_TOP_CTRL 0x00 35 #define TOP_SSE BIT(0) /* Enable port */ 36 #define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */ 37 #define TOP_FRF_MOTOROLA 0 /* Motorola SPI */ 38 #define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */ 39 #define TOP_SPO BIT(10) /* Polarity: 0=low */ 40 #define TOP_SPH BIT(11) /* Half-cycle phase */ 41 #define TOP_LBM BIT(12) /* Loopback mode */ 42 #define TOP_TRAIL BIT(13) /* Trailing bytes */ 43 #define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */ 44 45 /* SSP FIFO Control Register */ 46 #define SSP_FIFO_CTRL 0x04 47 #define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */ 48 #define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */ 49 #define FIFO_TSRE BIT(10) /* TX service request */ 50 #define FIFO_RSRE BIT(11) /* RX service request */ 51 52 /* SSP Interrupt Enable Register */ 53 #define SSP_INT_EN 0x08 54 #define SSP_INT_EN_TINTE BIT(1) /* RX timeout */ 55 #define SSP_INT_EN_RIE BIT(2) /* RX FIFO */ 56 #define SSP_INT_EN_TIE BIT(3) /* TX FIFO */ 57 #define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */ 58 #define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */ 59 #define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */ 60 61 /* TX interrupts, RX interrupts, and error interrupts */ 62 #define SSP_INT_EN_TX SSP_INT_EN_TIE 63 #define SSP_INT_EN_RX \ 64 (SSP_INT_EN_TINTE | SSP_INT_EN_RIE) 65 #define SSP_INT_EN_ERROR \ 66 (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI) 67 68 /* SSP Time Out Register */ 69 #define SSP_TIMEOUT 0x0c 70 #define SSP_TIMEOUT_MASK GENMASK(23, 0) 71 72 /* SSP Data Register */ 73 #define SSP_DATAR 0x10 74 75 /* SSP Status Register */ 76 #define SSP_STATUS 0x14 77 #define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */ 78 #define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */ 79 #define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */ 80 #define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */ 81 #define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */ 82 #define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */ 83 #define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */ 84 #define SSP_STATUS_BCE BIT(21) /* Bit count error */ 85 86 /* Error status mask */ 87 #define SSP_STATUS_ERROR \ 88 (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE) 89 90 /* The FIFO sizes and thresholds are the same for RX and TX */ 91 #define K1_SPI_FIFO_SIZE 32 92 #define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2) 93 94 struct k1_spi_driver_data { 95 struct spi_controller *host; 96 void __iomem *base; 97 phys_addr_t base_addr; 98 unsigned long bus_rate; 99 struct clk *clk; 100 unsigned long rate; 101 int irq; 102 103 /* Current transfer information; not valid if message is null */ 104 u32 bytes; /* Bytes used for bits_per_word */ 105 unsigned int rx_resid; /* RX bytes left in transfer */ 106 unsigned int tx_resid; /* TX bytes left in transfer */ 107 struct spi_transfer *transfer; /* Current transfer */ 108 109 bool dma_enabled; 110 }; 111 112 /* Set our registers to a known initial state */ 113 static void 114 k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial) 115 { 116 u32 val = 0; 117 118 writel(0, drv_data->base + SSP_TOP_CTRL); 119 120 if (initial) { 121 /* 122 * The TX and RX FIFO thresholds are the same no matter 123 * what the speed or bits per word, so we can just set 124 * them once. The thresholds are one more than the values 125 * in the register. 126 */ 127 val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1); 128 val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1); 129 } 130 writel(val, drv_data->base + SSP_FIFO_CTRL); 131 132 writel(0, drv_data->base + SSP_INT_EN); 133 writel(0, drv_data->base + SSP_TIMEOUT); 134 135 /* Clear any pending interrupt conditions */ 136 writel(~0, drv_data->base + SSP_STATUS); 137 } 138 139 /* 140 * The client can call the setup function multiple times, and each call 141 * can specify a different SPI mode (and transfer speed). Each transfer 142 * can specify its own speed though, and the core code ensures each 143 * transfer's speed is set to something nonzero and supported by both 144 * the controller and the device. We just set the speed for each transfer. 145 */ 146 static int k1_spi_setup(struct spi_device *spi) 147 { 148 struct k1_spi_driver_data *drv_data; 149 u32 val; 150 151 drv_data = spi_controller_get_devdata(spi->controller); 152 153 /* 154 * Configure the message format for this device. We only 155 * support Motorola SPI format in master mode. 156 */ 157 val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA); 158 159 /* Translate the mode into the value used to program the hardware. */ 160 if (spi->mode & SPI_CPHA) 161 val |= TOP_SPH; /* 1/2 cycle */ 162 if (spi->mode & SPI_CPOL) 163 val |= TOP_SPO; /* active low */ 164 if (spi->mode & SPI_LOOP) 165 val |= TOP_LBM; /* enable loopback */ 166 writel(val, drv_data->base + SSP_TOP_CTRL); 167 168 return 0; 169 } 170 171 static void k1_spi_cleanup(struct spi_device *spi) 172 { 173 struct k1_spi_driver_data *drv_data; 174 175 drv_data = spi_controller_get_devdata(spi->controller); 176 k1_spi_register_reset(drv_data, false); 177 } 178 179 static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi, 180 struct spi_transfer *transfer) 181 { 182 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); 183 u32 burst_size; 184 185 if (!drv_data->dma_enabled) 186 return false; 187 188 if (transfer->len > SZ_2K) 189 return false; 190 191 /* Don't bother with DMA if we can't do even a single burst */ 192 burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word); 193 194 return transfer->len >= burst_size; 195 } 196 197 static void k1_spi_dma_callback(void *param) 198 { 199 struct k1_spi_driver_data *drv_data = param; 200 u32 val; 201 202 val = readl(drv_data->base + SSP_FIFO_CTRL); 203 val &= ~(FIFO_TSRE | FIFO_RSRE); 204 writel(val, drv_data->base + SSP_FIFO_CTRL); 205 206 val = readl(drv_data->base + SSP_TOP_CTRL); 207 val &= ~TOP_TRAIL; 208 writel(val, drv_data->base + SSP_TOP_CTRL); 209 210 /* Check for any error conditions */ 211 val = readl(drv_data->base + SSP_STATUS); 212 if (val & SSP_STATUS_ERROR) 213 drv_data->transfer->error |= SPI_TRANS_FAIL_IO; 214 215 /* Disable the port */ 216 val = readl(drv_data->base + SSP_TOP_CTRL); 217 val &= ~TOP_SSE; 218 writel(val, drv_data->base + SSP_TOP_CTRL); 219 220 drv_data->transfer = NULL; 221 222 spi_finalize_current_transfer(drv_data->host); 223 } 224 225 /* Prepare a descriptor for TX or RX DMA */ 226 static struct dma_async_tx_descriptor * 227 k1_spi_dma_prep(struct k1_spi_driver_data *drv_data, 228 struct spi_transfer *transfer, bool tx) 229 { 230 phys_addr_t addr = drv_data->base_addr + SSP_DATAR; 231 u32 burst_size = K1_SPI_THRESH * drv_data->bytes; 232 struct dma_slave_config cfg = { }; 233 enum dma_transfer_direction dir; 234 enum dma_slave_buswidth width; 235 struct dma_chan *chan; 236 struct sg_table *sgt; 237 238 switch (drv_data->bytes) { 239 case 1: 240 width = DMA_SLAVE_BUSWIDTH_1_BYTE; 241 break; 242 case 2: 243 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 244 break; 245 default: /* bytes == 4 */ 246 width = DMA_SLAVE_BUSWIDTH_4_BYTES; 247 break; 248 } 249 250 if (tx) { 251 chan = drv_data->host->dma_tx; 252 sgt = &transfer->tx_sg; 253 dir = DMA_MEM_TO_DEV; 254 255 cfg.dst_addr = addr; 256 cfg.dst_addr_width = width; 257 cfg.dst_maxburst = burst_size; 258 } else { 259 chan = drv_data->host->dma_rx; 260 sgt = &transfer->rx_sg; 261 dir = DMA_DEV_TO_MEM; 262 263 cfg.src_addr = addr; 264 cfg.src_addr_width = width; 265 cfg.src_maxburst = burst_size; 266 } 267 cfg.direction = dir; 268 269 if (dmaengine_slave_config(chan, &cfg)) 270 return NULL; 271 272 return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, 273 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 274 275 } 276 277 static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi, 278 struct spi_transfer *transfer) 279 { 280 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); 281 struct dma_async_tx_descriptor *txdesc, *rxdesc; 282 u32 val; 283 284 /* Prepare the TX descriptor */ 285 txdesc = k1_spi_dma_prep(drv_data, transfer, true); 286 if (!txdesc) 287 goto fallback; 288 289 /* Prepare the RX descriptor */ 290 rxdesc = k1_spi_dma_prep(drv_data, transfer, false); 291 if (!rxdesc) 292 goto fallback; 293 294 /* When RX is complete we also know TX has completed */ 295 rxdesc->callback = k1_spi_dma_callback; 296 rxdesc->callback_param = drv_data; 297 298 dmaengine_submit(txdesc); 299 dmaengine_submit(rxdesc); 300 301 val = readl(drv_data->base + SSP_TOP_CTRL); 302 val |= TOP_TRAIL; /* Trailing bytes handled by DMA */ 303 writel(val, drv_data->base + SSP_TOP_CTRL); 304 305 val = readl(drv_data->base + SSP_FIFO_CTRL); 306 val |= FIFO_TSRE | FIFO_RSRE; 307 writel(val, drv_data->base + SSP_FIFO_CTRL); 308 309 /* Start RX first so we're ready the instant we start transmitting */ 310 dma_async_issue_pending(host->dma_rx); 311 dma_async_issue_pending(host->dma_tx); 312 313 return 1; 314 fallback: 315 transfer->error |= SPI_TRANS_FAIL_NO_START; 316 317 return -EAGAIN; 318 } 319 320 /* Flush the RX FIFO of any leftover data before processing a message */ 321 static int k1_spi_prepare_message(struct spi_controller *host, 322 struct spi_message *message) 323 { 324 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); 325 u32 val = readl(drv_data->base + SSP_STATUS); 326 u32 count; 327 328 /* If there's nothing in the FIFO, we're done */ 329 if (!(val & SSP_STATUS_RNE)) 330 return 0; 331 332 /* Read and discard what's there (one more than what the field says) */ 333 count = FIELD_GET(SSP_STATUS_RFL, val) + 1; 334 do 335 (void)readl(drv_data->base + SSP_DATAR); 336 while (--count); 337 338 return 0; 339 } 340 341 /* Set logic level of chip select line (high=true means CS deasserted) */ 342 static void k1_spi_set_cs(struct spi_device *spi, bool high) 343 { 344 struct k1_spi_driver_data *drv_data; 345 u32 val; 346 347 drv_data = spi_controller_get_devdata(spi->controller); 348 349 val = readl(drv_data->base + SSP_TOP_CTRL); 350 if (high) 351 val &= ~TOP_HOLD_FRAME_LOW; 352 else 353 val |= TOP_HOLD_FRAME_LOW; 354 writel(val, drv_data->base + SSP_TOP_CTRL); 355 } 356 357 /* Set the transfer speed; the SPI core code ensures it is supported */ 358 static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, 359 struct spi_transfer *transfer) 360 { 361 struct clk *clk = drv_data->clk; 362 u64 nsec_per_word; 363 u64 bus_ticks; 364 u32 timeout; 365 u32 val; 366 int ret; 367 368 ret = clk_set_rate(clk, transfer->speed_hz); 369 if (ret) 370 return ret; 371 372 drv_data->rate = clk_get_rate(clk); 373 374 /* No need for RX FIFO timeout if we're not receiving anything */ 375 if (!transfer->rx_buf) 376 return 0; 377 378 /* 379 * Compute the RX FIFO inactivity timeout value that should be used. 380 * The inactivity timer restarts with each word that lands in the 381 * FIFO. If several "word transfer times" pass without any new data 382 * in the RX FIFO, we might as well read what's there. 383 * 384 * The rate at which words land in the FIFO is determined by the 385 * word size and the transfer rate. One bit is transferred per 386 * clock tick, and 8 (or 16 or 32) bits are transferred per word. 387 * 388 * So we can get word transfer time (in nanoseconds) from: 389 * nsec_per_tick = NSEC_PER_SEC / drv_data->rate; 390 * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; 391 * We do the divide last for better accuracy. 392 */ 393 nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; 394 nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); 395 396 /* 397 * The timeout (which we'll set to three word transfer times) is 398 * expressed as a number of APB clock ticks. 399 * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC) 400 */ 401 bus_ticks = 3 * nsec_per_word * drv_data->bus_rate; 402 timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC); 403 404 /* Set the RX timeout period (required for both DMA and PIO) */ 405 val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout); 406 writel(val, drv_data->base + SSP_TIMEOUT); 407 408 return 0; 409 } 410 411 static int k1_spi_transfer_one(struct spi_controller *host, 412 struct spi_device *spi, 413 struct spi_transfer *transfer) 414 { 415 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); 416 u32 ctrl; 417 u32 val; 418 int ret; 419 420 /* Bits per word can change on a per-transfer basis */ 421 drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word); 422 423 /* Each transfer can also specify a different rate */ 424 ret = k1_spi_set_speed(drv_data, transfer); 425 if (ret) { 426 dev_err(&host->dev, 427 "failed to set transfer speed: %d\n", ret); 428 return ret; 429 } 430 431 drv_data->rx_resid = transfer->len; 432 drv_data->tx_resid = transfer->len; 433 434 drv_data->transfer = transfer; 435 436 /* Clear any existing interrupt conditions */ 437 writel(~0, drv_data->base + SSP_STATUS); 438 439 /* Set the data (word) size, and enable the port */ 440 ctrl = readl(drv_data->base + SSP_TOP_CTRL); 441 ctrl &= ~TOP_DSS_MASK; 442 ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1); 443 ctrl |= TOP_SSE; 444 writel(ctrl, drv_data->base + SSP_TOP_CTRL); 445 446 if (spi_xfer_is_dma_mapped(host, spi, transfer)) 447 return k1_spi_dma_one(host, spi, transfer); 448 449 /* An interrupt will initiate the transfer */ 450 val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR; 451 writel(val, drv_data->base + SSP_INT_EN); 452 453 return 1; /* We will call spi_finalize_current_transfer() */ 454 } 455 456 static void 457 k1_spi_handle_err(struct spi_controller *host, struct spi_message *message) 458 { 459 struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); 460 461 if (drv_data->dma_enabled) { 462 dmaengine_terminate_sync(host->dma_rx); 463 dmaengine_terminate_sync(host->dma_tx); 464 } 465 } 466 467 static void k1_spi_write_word(struct k1_spi_driver_data *drv_data) 468 { 469 struct spi_transfer *transfer = drv_data->transfer; 470 u32 bytes = drv_data->bytes; 471 u32 val; 472 473 if (transfer->tx_buf) { 474 const void *buf; 475 476 buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid); 477 if (bytes == 1) 478 val = *(u8 *)buf; 479 else if (bytes == 2) 480 val = *(u16 *)buf; 481 else /* bytes == 4 */ 482 val = *(u32 *)buf; 483 } else { 484 val = 0; /* Null writer; write 1, 2, or 4 zero bytes */ 485 } 486 /* Fill the next TX FIFO entry */ 487 writel(val, drv_data->base + SSP_DATAR); 488 489 drv_data->tx_resid -= bytes; 490 } 491 492 /* The last-read status value is provided; we know SSP_STATUS_TNF is set */ 493 static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val) 494 { 495 unsigned int count; 496 497 /* Get the number of free slots in the FIFO */ 498 count = K1_SPI_FIFO_SIZE - FIELD_GET(SSP_STATUS_TFL, val); 499 500 /* 501 * Limit how much we try to send at a time, to reduce the 502 * chance the other side can overrun our RX FIFO. 503 */ 504 count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes); 505 do 506 k1_spi_write_word(drv_data); 507 while (--count); 508 509 return !drv_data->tx_resid; 510 } 511 512 static void k1_spi_read_word(struct k1_spi_driver_data *drv_data) 513 { 514 struct spi_transfer *transfer = drv_data->transfer; 515 u32 bytes = drv_data->bytes; 516 u32 val; 517 518 /* Consume the next RX FIFO entry */ 519 val = readl(drv_data->base + SSP_DATAR); 520 if (transfer->rx_buf) { 521 void *buf; 522 523 buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid); 524 525 if (bytes == 1) 526 *(u8 *)buf = val; 527 else if (bytes == 2) 528 *(u16 *)buf = val; 529 else /* bytes == 4 */ 530 *(u32 *)buf = val; 531 } /* Otherwise null reader: discard the data */ 532 533 drv_data->rx_resid -= bytes; 534 } 535 536 /* The last-read status value is provided; we know SSP_STATUS_RNE is set */ 537 static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val) 538 { 539 do { 540 unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1; 541 542 /* Only read what we need */ 543 count = min(count, drv_data->rx_resid / drv_data->bytes); 544 do 545 k1_spi_read_word(drv_data); 546 while (--count); 547 548 /* If there's no more to read, we're done */ 549 if (!drv_data->rx_resid) 550 return true; 551 552 /* Check again in case more became available to read */ 553 val = readl(drv_data->base + SSP_STATUS); 554 if (val & SSP_STATUS_RNE) 555 writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS); 556 else 557 return false; 558 } while (true); 559 } 560 561 static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id) 562 { 563 struct k1_spi_driver_data *drv_data = dev_id; 564 u32 status; 565 u32 top_ctrl; 566 567 /* Get status and clear pending interrupts */ 568 status = readl(drv_data->base + SSP_STATUS); 569 writel(status, drv_data->base + SSP_STATUS); 570 571 /* If no actionable status bits are set, this is not our interrupt */ 572 if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE))) 573 return IRQ_NONE; 574 575 /* Check for any error conditions first */ 576 if (status & SSP_STATUS_ERROR) { 577 if (drv_data->transfer) 578 drv_data->transfer->error |= SPI_TRANS_FAIL_IO; 579 goto done; 580 } 581 582 /* 583 * For SPI, bytes are transferred in both directions equally, and 584 * RX always follows TX. Start by writing if there is anything to 585 * write, then read. Once there's no more to read, we're done. 586 */ 587 if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) { 588 /* If we finish writing, disable TX interrupts */ 589 if (k1_spi_write(drv_data, status)) 590 writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR, 591 drv_data->base + SSP_INT_EN); 592 } 593 594 /* We're not done unless we've read all that was requested */ 595 if (drv_data->rx_resid) { 596 /* Read more if the FIFO is not empty */ 597 if (status & SSP_STATUS_RNE) 598 if (k1_spi_read(drv_data, status)) 599 goto done; 600 601 return IRQ_HANDLED; 602 } 603 done: 604 /* Disable the port */ 605 top_ctrl = readl(drv_data->base + SSP_TOP_CTRL); 606 top_ctrl &= ~TOP_SSE; 607 writel(top_ctrl, drv_data->base + SSP_TOP_CTRL); 608 609 /* Disable all interrupts */ 610 writel(0, drv_data->base + SSP_INT_EN); 611 612 if (drv_data->transfer) { 613 drv_data->transfer = NULL; 614 spi_finalize_current_transfer(drv_data->host); 615 } 616 617 return IRQ_HANDLED; 618 } 619 620 static int 621 k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) 622 { 623 struct spi_controller *host = drv_data->host; 624 struct dma_chan *chan; 625 626 chan = dma_request_chan(dev, "tx"); 627 if (IS_ERR(chan)) 628 return PTR_ERR(chan); 629 host->dma_tx = chan; 630 631 chan = dma_request_chan(dev, "rx"); 632 if (IS_ERR(chan)) { 633 dma_release_channel(host->dma_tx); 634 host->dma_tx = NULL; 635 return PTR_ERR(chan); 636 } 637 host->dma_rx = chan; 638 639 drv_data->dma_enabled = true; 640 641 return 0; 642 } 643 644 static void k1_spi_dma_cleanup(struct device *dev, void *res) 645 { 646 struct k1_spi_driver_data **ptr = res; 647 struct k1_spi_driver_data *drv_data = *ptr; 648 struct spi_controller *host = drv_data->host; 649 650 if (!drv_data->dma_enabled) 651 return; 652 653 drv_data->dma_enabled = false; 654 655 dma_release_channel(host->dma_rx); 656 host->dma_rx = NULL; 657 dma_release_channel(host->dma_tx); 658 host->dma_tx = NULL; 659 } 660 661 static int 662 devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) 663 { 664 struct k1_spi_driver_data **ptr; 665 int ret; 666 667 if (!IS_ENABLED(CONFIG_MMP_PDMA)) { 668 dev_info(dev, "DMA not available; using PIO\n"); 669 return 0; 670 } 671 672 ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL); 673 if (!ptr) 674 return -ENOMEM; 675 676 ret = k1_spi_dma_setup(drv_data, dev); 677 if (ret) { 678 devres_free(ptr); 679 return ret; 680 } 681 682 *ptr = drv_data; 683 devres_add(dev, ptr); 684 685 return 0; 686 } 687 688 static int k1_spi_probe(struct platform_device *pdev) 689 { 690 struct k1_spi_driver_data *drv_data; 691 struct device *dev = &pdev->dev; 692 struct reset_control *reset; 693 struct spi_controller *host; 694 struct resource *iores; 695 struct clk *clk_bus; 696 int ret; 697 698 host = devm_spi_alloc_host(dev, sizeof(*drv_data)); 699 if (!host) 700 return -ENOMEM; 701 drv_data = spi_controller_get_devdata(host); 702 drv_data->host = host; 703 platform_set_drvdata(pdev, drv_data); 704 705 ret = devm_k1_spi_dma_setup(drv_data, dev); 706 if (ret == -EPROBE_DEFER) 707 return ret; 708 if (ret) 709 dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret); 710 711 drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, 712 &iores); 713 if (IS_ERR(drv_data->base)) 714 return dev_err_probe(dev, PTR_ERR(drv_data->base), 715 "error mapping memory\n"); 716 drv_data->base_addr = iores->start; 717 718 clk_bus = devm_clk_get_enabled(dev, "bus"); 719 if (IS_ERR(clk_bus)) 720 return dev_err_probe(dev, PTR_ERR(clk_bus), 721 "error getting/enabling bus clock\n"); 722 drv_data->bus_rate = clk_get_rate(clk_bus); 723 724 drv_data->clk = devm_clk_get_enabled(dev, "core"); 725 if (IS_ERR(drv_data->clk)) 726 return dev_err_probe(dev, PTR_ERR(drv_data->clk), 727 "error getting/enabling core clock\n"); 728 729 reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); 730 if (IS_ERR(reset)) 731 return dev_err_probe(dev, PTR_ERR(reset), 732 "error getting/deasserting reset\n"); 733 734 k1_spi_register_reset(drv_data, true); 735 736 drv_data->irq = platform_get_irq(pdev, 0); 737 if (drv_data->irq < 0) 738 return dev_err_probe(dev, drv_data->irq, "error getting IRQ\n"); 739 740 ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr, 741 IRQF_SHARED, dev_name(dev), drv_data); 742 if (ret < 0) 743 return dev_err_probe(dev, ret, "error requesting IRQ\n"); 744 745 /* Initialize the host structure, then register it */ 746 host->dev.of_node = dev_of_node(dev); 747 host->dev.parent = dev; 748 host->num_chipselect = 1; 749 if (drv_data->dma_enabled) 750 host->dma_alignment = K1_SPI_DMA_ALIGNMENT; 751 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; 752 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 753 host->min_speed_hz = K1_SPI_MIN_SPEED_HZ; 754 host->max_speed_hz = K1_SPI_MAX_SPEED_HZ; 755 host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 756 host->max_dma_len = K1_SPI_MAX_DMA_LEN; 757 758 host->setup = k1_spi_setup; 759 host->cleanup = k1_spi_cleanup; 760 host->can_dma = k1_spi_can_dma; 761 host->prepare_message = k1_spi_prepare_message; 762 host->set_cs = k1_spi_set_cs; 763 host->transfer_one = k1_spi_transfer_one; 764 host->handle_err = k1_spi_handle_err; 765 766 ret = devm_spi_register_controller(dev, host); 767 if (ret) 768 dev_err(dev, "error registering controller\n"); 769 770 return ret; 771 } 772 773 static const struct of_device_id k1_spi_dt_ids[] = { 774 { .compatible = "spacemit,k1-spi", }, 775 {} 776 }; 777 MODULE_DEVICE_TABLE(of, k1_spi_dt_ids); 778 779 static struct platform_driver k1_spi_driver = { 780 .probe = k1_spi_probe, 781 .driver = { 782 .name = "k1-spi", 783 .of_match_table = k1_spi_dt_ids, 784 }, 785 }; 786 module_platform_driver(k1_spi_driver); 787 788 MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver"); 789 MODULE_LICENSE("GPL"); 790