1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // 3 // Nuvoton MA35D1 QSPI controller driver 4 // 5 // Copyright (c) 2026 Nuvoton Technology Corp. 6 // Author: Chi-Wen Weng <cwweng@nuvoton.com> 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/reset.h> 19 #include <linux/sizes.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi-mem.h> 22 #include <linux/spinlock.h> 23 24 /* Register offset definitions */ 25 #define NUVOTON_QSPI_CTL_OFFSET 0x00 /* Control Register, RW */ 26 #define NUVOTON_QSPI_CLKDIV_OFFSET 0x04 /* Clock Divider Register, RW */ 27 #define NUVOTON_QSPI_SSCTL_OFFSET 0x08 /* Slave Select Register, RW */ 28 #define NUVOTON_QSPI_FIFOCTL_OFFSET 0x10 /* FIFO Control Register, RW */ 29 #define NUVOTON_QSPI_STATUS_OFFSET 0x14 /* Status Register, RW */ 30 #define NUVOTON_QSPI_TX_OFFSET 0x20 /* Data Transmit Register, WO */ 31 #define NUVOTON_QSPI_RX_OFFSET 0x30 /* Data Receive Register, RO */ 32 33 /* QSPI Control Register bit masks */ 34 #define NUVOTON_QSPI_CTL_DTREN_MASK BIT(23) /* DTR I/O Mode Enable */ 35 #define NUVOTON_QSPI_CTL_QUADIOEN_MASK BIT(22) /* Quad I/O Mode Enable */ 36 #define NUVOTON_QSPI_CTL_DUALIOEN_MASK BIT(21) /* Dual I/O Mode Enable */ 37 #define NUVOTON_QSPI_CTL_DATDIR_MASK BIT(20) /* Data Port Direction Control */ 38 #define NUVOTON_QSPI_CTL_REORDER_MASK BIT(19) /* Byte Reorder Function Enable */ 39 #define NUVOTON_QSPI_CTL_LSB_MASK BIT(13) /* Send LSB First */ 40 #define NUVOTON_QSPI_CTL_DWIDTH_MASK GENMASK(12, 8) /* Data Width */ 41 #define NUVOTON_QSPI_CTL_SUSPITV_MASK GENMASK(7, 4) /* Suspend Interval */ 42 #define NUVOTON_QSPI_CTL_CLKPOL_MASK BIT(3) /* Clock Polarity */ 43 #define NUVOTON_QSPI_CTL_TXNEG_MASK BIT(2) /* Transmit on Negative Edge */ 44 #define NUVOTON_QSPI_CTL_RXNEG_MASK BIT(1) /* Receive on Negative Edge */ 45 #define NUVOTON_QSPI_CTL_SPIEN_MASK BIT(0) /* QSPI Transfer Control Enable */ 46 47 /* QSPI Clock Divider Register bit masks */ 48 #define NUVOTON_QSPI_CLKDIV_MASK GENMASK(8, 0) /* Clock Divider */ 49 50 /* QSPI Slave Select Control Register bit masks */ 51 #define NUVOTON_QSPI_SSCTL_SS1_MASK BIT(1) /* Slave Selection 1 Control */ 52 #define NUVOTON_QSPI_SSCTL_SS0_MASK BIT(0) /* Slave Selection 0 Control */ 53 54 /* QSPI FIFO Control Register bit masks */ 55 #define NUVOTON_QSPI_FIFOCTL_TXRST_MASK BIT(1) /* Transmit Reset */ 56 #define NUVOTON_QSPI_FIFOCTL_RXRST_MASK BIT(0) /* Receive Reset */ 57 58 /* QSPI Status Register bit masks */ 59 #define NUVOTON_QSPI_STATUS_TXRXRST_MASK BIT(23) /* TX or RX Reset Status */ 60 #define NUVOTON_QSPI_STATUS_TXFULL_MASK BIT(17) /* Transmit FIFO Full */ 61 #define NUVOTON_QSPI_STATUS_SPIENSTS_MASK BIT(15) /* QSPI Enable Status */ 62 #define NUVOTON_QSPI_STATUS_RXEMPTY_MASK BIT(8) /* Receive FIFO Empty */ 63 #define NUVOTON_QSPI_STATUS_BUSY_MASK BIT(0) /* Busy Status */ 64 65 #define NUVOTON_QSPI_MAX_NUM_CS 2 66 #define NUVOTON_QSPI_DEFAULT_NUM_CS 2 67 #define NUVOTON_QSPI_DEFAULT_BPW 8 68 /* Bound PIO operations to avoid long atomic polling loops. */ 69 #define NUVOTON_QSPI_MAX_TRANSFER_SIZE SZ_4K 70 #define NUVOTON_QSPI_MAX_MESSAGE_SIZE SZ_8K 71 #define NUVOTON_QSPI_TIMEOUT_US 10000 72 73 struct nuvoton_qspi { 74 void __iomem *regs; 75 struct clk *clk; 76 struct device *dev; 77 78 /* Protects read-modify-write accesses to the SSCTL register. */ 79 spinlock_t ssctl_lock; 80 u32 speed_hz; 81 }; 82 83 static u32 nuvoton_qspi_read(struct nuvoton_qspi *qspi, u32 reg) 84 { 85 return readl(qspi->regs + reg); 86 } 87 88 static void nuvoton_qspi_write(struct nuvoton_qspi *qspi, u32 val, u32 reg) 89 { 90 writel(val, qspi->regs + reg); 91 } 92 93 static void nuvoton_qspi_update_bits(struct nuvoton_qspi *qspi, u32 reg, 94 u32 mask, u32 val) 95 { 96 u32 tmp; 97 98 tmp = nuvoton_qspi_read(qspi, reg); 99 tmp &= ~mask; 100 tmp |= val & mask; 101 nuvoton_qspi_write(qspi, tmp, reg); 102 } 103 104 static int nuvoton_qspi_wait_ready(struct nuvoton_qspi *qspi) 105 { 106 u32 val; 107 108 return readl_poll_timeout(qspi->regs + NUVOTON_QSPI_STATUS_OFFSET, 109 val, 110 !(val & NUVOTON_QSPI_STATUS_BUSY_MASK), 111 0, NUVOTON_QSPI_TIMEOUT_US); 112 } 113 114 static int nuvoton_qspi_reset_fifo(struct nuvoton_qspi *qspi) 115 { 116 u32 val; 117 118 nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_FIFOCTL_OFFSET, 119 NUVOTON_QSPI_FIFOCTL_TXRST_MASK | 120 NUVOTON_QSPI_FIFOCTL_RXRST_MASK, 121 NUVOTON_QSPI_FIFOCTL_TXRST_MASK | 122 NUVOTON_QSPI_FIFOCTL_RXRST_MASK); 123 124 /* 125 * Give the controller a short time to latch the FIFO reset request 126 * before polling the reset status bit. 127 */ 128 udelay(1); 129 130 return readl_poll_timeout_atomic(qspi->regs + NUVOTON_QSPI_STATUS_OFFSET, 131 val, 132 !(val & NUVOTON_QSPI_STATUS_TXRXRST_MASK), 133 1, NUVOTON_QSPI_TIMEOUT_US); 134 } 135 136 static int nuvoton_qspi_set_speed(struct spi_device *spi, u32 speed_hz, bool dtr) 137 { 138 struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); 139 unsigned long clk_rate; 140 u32 div; 141 142 if (!speed_hz) 143 speed_hz = spi->max_speed_hz; 144 145 if (!speed_hz) 146 return -EINVAL; 147 148 /* Experimentally, when enabling DTR the frequency is cut in half */ 149 if (dtr) 150 speed_hz *= 2; 151 152 if (qspi->speed_hz == speed_hz) 153 return 0; 154 155 clk_rate = clk_get_rate(qspi->clk); 156 if (!clk_rate) { 157 dev_err(qspi->dev, "failed to get clock rate\n"); 158 return -EINVAL; 159 } 160 161 div = DIV_ROUND_UP(clk_rate, speed_hz) - 1; 162 if (div > FIELD_MAX(NUVOTON_QSPI_CLKDIV_MASK)) { 163 dev_err(qspi->dev, "unsupported SPI clock %u Hz\n", speed_hz); 164 return -EINVAL; 165 } 166 167 nuvoton_qspi_write(qspi, FIELD_PREP(NUVOTON_QSPI_CLKDIV_MASK, div), 168 NUVOTON_QSPI_CLKDIV_OFFSET); 169 qspi->speed_hz = speed_hz; 170 171 return 0; 172 } 173 174 static int nuvoton_qspi_set_bits_per_word(struct nuvoton_qspi *qspi, u8 bpw) 175 { 176 if (bpw != NUVOTON_QSPI_DEFAULT_BPW) 177 return -EINVAL; 178 179 nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_CTL_OFFSET, 180 NUVOTON_QSPI_CTL_DWIDTH_MASK | 181 NUVOTON_QSPI_CTL_REORDER_MASK, 182 FIELD_PREP(NUVOTON_QSPI_CTL_DWIDTH_MASK, bpw)); 183 184 return 0; 185 } 186 187 static int nuvoton_qspi_setup_transfer(struct spi_device *spi, u8 bpw) 188 { 189 struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); 190 u32 mode = spi->mode & SPI_MODE_X_MASK; 191 u32 ctl = 0; 192 int ret; 193 194 if (!bpw) 195 bpw = NUVOTON_QSPI_DEFAULT_BPW; 196 197 ret = nuvoton_qspi_set_bits_per_word(qspi, bpw); 198 if (ret) 199 return ret; 200 201 if (mode == SPI_MODE_0 || mode == SPI_MODE_3) 202 ctl |= NUVOTON_QSPI_CTL_TXNEG_MASK; 203 else 204 ctl |= NUVOTON_QSPI_CTL_RXNEG_MASK; 205 206 if (spi->mode & SPI_CPOL) 207 ctl |= NUVOTON_QSPI_CTL_CLKPOL_MASK; 208 209 if (spi->mode & SPI_LSB_FIRST) 210 ctl |= NUVOTON_QSPI_CTL_LSB_MASK; 211 212 nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_CTL_OFFSET, 213 NUVOTON_QSPI_CTL_TXNEG_MASK | 214 NUVOTON_QSPI_CTL_RXNEG_MASK | 215 NUVOTON_QSPI_CTL_CLKPOL_MASK | 216 NUVOTON_QSPI_CTL_LSB_MASK, ctl); 217 218 return 0; 219 } 220 221 static int nuvoton_qspi_configure_bus(struct spi_device *spi, 222 unsigned int buswidth, 223 enum spi_mem_data_dir dir, 224 u32 speed_hz, bool dtr) 225 { 226 struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); 227 u32 ctl = 0; 228 int ret; 229 230 ret = nuvoton_qspi_set_speed(spi, speed_hz, dtr); 231 if (ret) 232 return ret; 233 234 if (dtr) 235 ctl |= NUVOTON_QSPI_CTL_DTREN_MASK; 236 237 if (buswidth == 4) 238 ctl |= NUVOTON_QSPI_CTL_QUADIOEN_MASK; 239 else if (buswidth == 2) 240 ctl |= NUVOTON_QSPI_CTL_DUALIOEN_MASK; 241 242 if (buswidth > 1 && dir == SPI_MEM_DATA_OUT) 243 ctl |= NUVOTON_QSPI_CTL_DATDIR_MASK; 244 245 nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_CTL_OFFSET, 246 NUVOTON_QSPI_CTL_DTREN_MASK | 247 NUVOTON_QSPI_CTL_QUADIOEN_MASK | 248 NUVOTON_QSPI_CTL_DUALIOEN_MASK | 249 NUVOTON_QSPI_CTL_DATDIR_MASK, ctl); 250 251 return 0; 252 } 253 254 static u32 nuvoton_qspi_tx_byte(const void *txbuf, unsigned int idx) 255 { 256 if (!txbuf) 257 return 0; 258 259 return ((const u8 *)txbuf)[idx]; 260 } 261 262 static void nuvoton_qspi_rx_byte(void *rxbuf, unsigned int idx, u32 val) 263 { 264 if (rxbuf) 265 ((u8 *)rxbuf)[idx] = val; 266 } 267 268 static int nuvoton_qspi_wait_tx_not_full(struct nuvoton_qspi *qspi) 269 { 270 u32 val; 271 272 return readl_poll_timeout_atomic(qspi->regs + NUVOTON_QSPI_STATUS_OFFSET, 273 val, 274 !(val & NUVOTON_QSPI_STATUS_TXFULL_MASK), 275 0, NUVOTON_QSPI_TIMEOUT_US); 276 } 277 278 static int nuvoton_qspi_wait_rx_not_empty(struct nuvoton_qspi *qspi) 279 { 280 u32 val; 281 282 return readl_poll_timeout_atomic(qspi->regs + NUVOTON_QSPI_STATUS_OFFSET, 283 val, 284 !(val & NUVOTON_QSPI_STATUS_RXEMPTY_MASK), 285 0, NUVOTON_QSPI_TIMEOUT_US); 286 } 287 288 static int nuvoton_qspi_txrx(struct nuvoton_qspi *qspi, const void *txbuf, 289 void *rxbuf, unsigned int len) 290 { 291 unsigned int i; 292 u32 val; 293 int ret; 294 295 if (!len) 296 return 0; 297 298 if (len > NUVOTON_QSPI_MAX_TRANSFER_SIZE) 299 return -EMSGSIZE; 300 301 ret = nuvoton_qspi_reset_fifo(qspi); 302 if (ret) { 303 dev_err(qspi->dev, "FIFO reset timed out\n"); 304 return ret; 305 } 306 307 /* 308 * Use conservative byte-by-byte PIO access. This keeps the initial driver 309 * simple and avoids relying on FIFO threshold interrupts or DMA support. 310 * 311 * The MA35D1 QSPI controller pushes one RX FIFO entry for each TX byte in 312 * single, dual-output and quad-output modes. Drain RX after every TX byte 313 * and discard the value for TX-only transfers to avoid RX FIFO overflow. 314 */ 315 for (i = 0; i < len; i++) { 316 ret = nuvoton_qspi_wait_tx_not_full(qspi); 317 if (ret) { 318 dev_err(qspi->dev, "TX FIFO full timeout\n"); 319 return ret; 320 } 321 322 nuvoton_qspi_write(qspi, nuvoton_qspi_tx_byte(txbuf, i), 323 NUVOTON_QSPI_TX_OFFSET); 324 325 ret = nuvoton_qspi_wait_rx_not_empty(qspi); 326 if (ret) { 327 dev_err(qspi->dev, "RX FIFO empty timeout\n"); 328 return ret; 329 } 330 331 val = nuvoton_qspi_read(qspi, NUVOTON_QSPI_RX_OFFSET); 332 if (rxbuf) 333 nuvoton_qspi_rx_byte(rxbuf, i, val); 334 } 335 336 ret = nuvoton_qspi_wait_ready(qspi); 337 if (ret) 338 dev_err(qspi->dev, "controller busy timeout\n"); 339 340 return ret; 341 } 342 343 static int nuvoton_qspi_hw_init(struct nuvoton_qspi *qspi) 344 { 345 u32 val; 346 int ret; 347 348 ret = nuvoton_qspi_set_bits_per_word(qspi, NUVOTON_QSPI_DEFAULT_BPW); 349 if (ret) 350 return ret; 351 352 nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_CTL_OFFSET, 353 NUVOTON_QSPI_CTL_SUSPITV_MASK | 354 NUVOTON_QSPI_CTL_TXNEG_MASK | 355 NUVOTON_QSPI_CTL_RXNEG_MASK | 356 NUVOTON_QSPI_CTL_CLKPOL_MASK | 357 NUVOTON_QSPI_CTL_LSB_MASK, 358 NUVOTON_QSPI_CTL_TXNEG_MASK); 359 360 nuvoton_qspi_update_bits(qspi, NUVOTON_QSPI_CTL_OFFSET, 361 NUVOTON_QSPI_CTL_SPIEN_MASK, 362 NUVOTON_QSPI_CTL_SPIEN_MASK); 363 364 ret = readl_poll_timeout(qspi->regs + NUVOTON_QSPI_STATUS_OFFSET, val, 365 (val & NUVOTON_QSPI_STATUS_SPIENSTS_MASK), 366 1, NUVOTON_QSPI_TIMEOUT_US); 367 if (ret) { 368 dev_err(qspi->dev, "failed to enable controller\n"); 369 return ret; 370 } 371 372 ret = nuvoton_qspi_reset_fifo(qspi); 373 if (ret) 374 dev_err(qspi->dev, "FIFO reset timed out\n"); 375 376 return ret; 377 } 378 379 static size_t nuvoton_qspi_max_transfer_size(struct spi_device *spi) 380 { 381 return NUVOTON_QSPI_MAX_TRANSFER_SIZE; 382 } 383 384 static size_t nuvoton_qspi_max_message_size(struct spi_device *spi) 385 { 386 return NUVOTON_QSPI_MAX_MESSAGE_SIZE; 387 } 388 389 static int nuvoton_qspi_mem_adjust_op_size(struct spi_mem *mem, 390 struct spi_mem_op *op) 391 { 392 if (op->data.nbytes > NUVOTON_QSPI_MAX_TRANSFER_SIZE) 393 op->data.nbytes = NUVOTON_QSPI_MAX_TRANSFER_SIZE; 394 395 return 0; 396 } 397 398 static bool nuvoton_qspi_mem_supports_op(struct spi_mem *mem, 399 const struct spi_mem_op *op) 400 { 401 if (!spi_mem_default_supports_op(mem, op)) 402 return false; 403 404 if (op->cmd.buswidth > 4 || op->addr.buswidth > 4 || 405 op->dummy.buswidth > 4 || op->data.buswidth > 4) 406 return false; 407 408 if (op->addr.nbytes > 4) 409 return false; 410 411 return true; 412 } 413 414 static void nuvoton_qspi_set_cs_level(struct nuvoton_qspi *qspi, 415 unsigned int cs, bool assert) 416 { 417 unsigned long flags; 418 u32 mask; 419 u32 val; 420 421 switch (cs) { 422 case 0: 423 mask = NUVOTON_QSPI_SSCTL_SS0_MASK; 424 break; 425 case 1: 426 mask = NUVOTON_QSPI_SSCTL_SS1_MASK; 427 break; 428 default: 429 dev_warn(qspi->dev, "invalid chip select %u\n", cs); 430 return; 431 } 432 433 spin_lock_irqsave(&qspi->ssctl_lock, flags); 434 435 val = nuvoton_qspi_read(qspi, NUVOTON_QSPI_SSCTL_OFFSET); 436 if (assert) 437 val |= mask; 438 else 439 val &= ~mask; 440 nuvoton_qspi_write(qspi, val, NUVOTON_QSPI_SSCTL_OFFSET); 441 442 spin_unlock_irqrestore(&qspi->ssctl_lock, flags); 443 } 444 445 static void nuvoton_qspi_set_cs(struct spi_device *spi, bool level) 446 { 447 struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); 448 449 /* 450 * The SPI core passes the physical CS level to ->set_cs(). This 451 * initial driver only supports active-low native chip selects. 452 */ 453 nuvoton_qspi_set_cs_level(qspi, spi_get_chipselect(spi, 0), !level); 454 } 455 456 static void nuvoton_qspi_mem_set_cs(struct spi_device *spi, bool assert) 457 { 458 struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); 459 460 /* The direct spi-mem path passes a logical assertion state. */ 461 nuvoton_qspi_set_cs_level(qspi, spi_get_chipselect(spi, 0), assert); 462 } 463 464 static int nuvoton_qspi_mem_exec_op(struct spi_mem *mem, 465 const struct spi_mem_op *op) 466 { 467 struct spi_device *spi = mem->spi; 468 struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); 469 u8 cmd[2], addr[4]; 470 int ret; 471 int i; 472 473 ret = nuvoton_qspi_setup_transfer(spi, NUVOTON_QSPI_DEFAULT_BPW); 474 if (ret) 475 return ret; 476 477 nuvoton_qspi_mem_set_cs(spi, true); 478 479 for (i = 0; i < op->cmd.nbytes; i++) 480 cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1)); 481 482 ret = nuvoton_qspi_configure_bus(spi, op->cmd.buswidth, SPI_MEM_DATA_OUT, 483 op->max_freq, op->cmd.dtr); 484 if (ret) 485 goto out_deassert_cs; 486 487 ret = nuvoton_qspi_txrx(qspi, cmd, NULL, op->cmd.nbytes); 488 if (ret) 489 goto out_deassert_cs; 490 491 if (op->addr.nbytes) { 492 for (i = 0; i < op->addr.nbytes; i++) 493 addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); 494 495 ret = nuvoton_qspi_configure_bus(spi, op->addr.buswidth, SPI_MEM_DATA_OUT, 496 op->max_freq, op->addr.dtr); 497 if (ret) 498 goto out_deassert_cs; 499 500 ret = nuvoton_qspi_txrx(qspi, addr, NULL, op->addr.nbytes); 501 if (ret) 502 goto out_deassert_cs; 503 } 504 505 if (op->dummy.nbytes) { 506 ret = nuvoton_qspi_configure_bus(spi, op->dummy.buswidth, SPI_MEM_DATA_OUT, 507 op->max_freq, op->dummy.dtr); 508 if (ret) 509 goto out_deassert_cs; 510 511 ret = nuvoton_qspi_txrx(qspi, NULL, NULL, op->dummy.nbytes); 512 if (ret) 513 goto out_deassert_cs; 514 } 515 516 if (op->data.nbytes) { 517 ret = nuvoton_qspi_configure_bus(spi, op->data.buswidth, op->data.dir, 518 op->max_freq, op->data.dtr); 519 if (ret) 520 goto out_deassert_cs; 521 522 ret = nuvoton_qspi_txrx(qspi, 523 op->data.dir == SPI_MEM_DATA_OUT ? 524 op->data.buf.out : NULL, 525 op->data.dir == SPI_MEM_DATA_IN ? 526 op->data.buf.in : NULL, 527 op->data.nbytes); 528 } 529 530 out_deassert_cs: 531 nuvoton_qspi_mem_set_cs(spi, false); 532 533 return ret; 534 } 535 536 static const struct spi_controller_mem_ops nuvoton_qspi_mem_ops = { 537 .adjust_op_size = nuvoton_qspi_mem_adjust_op_size, 538 .supports_op = nuvoton_qspi_mem_supports_op, 539 .exec_op = nuvoton_qspi_mem_exec_op, 540 }; 541 542 static const struct spi_controller_mem_caps nuvoton_qspi_mem_caps = { 543 .per_op_freq = true, 544 .dtr = true, 545 }; 546 547 static int nuvoton_qspi_transfer_one(struct spi_controller *ctlr, 548 struct spi_device *spi, 549 struct spi_transfer *xfer) 550 { 551 struct nuvoton_qspi *qspi = spi_controller_get_devdata(ctlr); 552 unsigned int tx_nbits = xfer->tx_nbits ?: SPI_NBITS_SINGLE; 553 unsigned int rx_nbits = xfer->rx_nbits ?: SPI_NBITS_SINGLE; 554 enum spi_mem_data_dir dir = SPI_MEM_DATA_IN; 555 unsigned int buswidth = 1; 556 int ret; 557 558 ret = nuvoton_qspi_setup_transfer(spi, xfer->bits_per_word); 559 if (ret) 560 return ret; 561 562 if (xfer->tx_buf && xfer->rx_buf && 563 (tx_nbits != SPI_NBITS_SINGLE || 564 rx_nbits != SPI_NBITS_SINGLE)) 565 return -EOPNOTSUPP; 566 567 if (xfer->tx_buf) { 568 dir = SPI_MEM_DATA_OUT; 569 570 if (tx_nbits == SPI_NBITS_QUAD) 571 buswidth = 4; 572 else if (tx_nbits == SPI_NBITS_DUAL) 573 buswidth = 2; 574 } else if (xfer->rx_buf) { 575 if (rx_nbits == SPI_NBITS_QUAD) 576 buswidth = 4; 577 else if (rx_nbits == SPI_NBITS_DUAL) 578 buswidth = 2; 579 } 580 581 ret = nuvoton_qspi_configure_bus(spi, buswidth, dir, xfer->speed_hz, 582 xfer->dtr_mode); 583 if (ret) 584 return ret; 585 586 ret = nuvoton_qspi_txrx(qspi, xfer->tx_buf, xfer->rx_buf, 587 xfer->len); 588 589 return ret; 590 } 591 592 static int nuvoton_qspi_probe(struct platform_device *pdev) 593 { 594 struct device *dev = &pdev->dev; 595 struct spi_controller *ctlr; 596 struct nuvoton_qspi *qspi; 597 struct reset_control *rst; 598 u32 num_cs = NUVOTON_QSPI_DEFAULT_NUM_CS; 599 int ret; 600 601 ctlr = devm_spi_alloc_host(dev, sizeof(*qspi)); 602 if (!ctlr) 603 return -ENOMEM; 604 605 platform_set_drvdata(pdev, ctlr); 606 607 qspi = spi_controller_get_devdata(ctlr); 608 qspi->dev = dev; 609 spin_lock_init(&qspi->ssctl_lock); 610 611 qspi->regs = devm_platform_ioremap_resource(pdev, 0); 612 if (IS_ERR(qspi->regs)) 613 return PTR_ERR(qspi->regs); 614 615 rst = devm_reset_control_get_exclusive(dev, NULL); 616 if (IS_ERR(rst)) 617 return dev_err_probe(dev, PTR_ERR(rst), 618 "failed to get reset\n"); 619 620 qspi->clk = devm_clk_get_enabled(dev, NULL); 621 if (IS_ERR(qspi->clk)) 622 return dev_err_probe(dev, PTR_ERR(qspi->clk), 623 "failed to get and enable clock\n"); 624 625 ret = reset_control_assert(rst); 626 if (ret) 627 return dev_err_probe(dev, ret, "failed to assert reset\n"); 628 629 udelay(2); 630 631 ret = reset_control_deassert(rst); 632 if (ret) 633 return dev_err_probe(dev, ret, "failed to deassert reset\n"); 634 635 ret = device_property_read_u32(dev, "num-cs", &num_cs); 636 if (ret && ret != -EINVAL) 637 return dev_err_probe(dev, ret, "failed to read num-cs\n"); 638 639 if (!num_cs || num_cs > NUVOTON_QSPI_MAX_NUM_CS) 640 return dev_err_probe(dev, -EINVAL, "invalid num-cs %u\n", 641 num_cs); 642 643 ctlr->num_chipselect = num_cs; 644 ctlr->max_transfer_size = nuvoton_qspi_max_transfer_size; 645 ctlr->max_message_size = nuvoton_qspi_max_message_size; 646 ctlr->mem_ops = &nuvoton_qspi_mem_ops; 647 ctlr->mem_caps = &nuvoton_qspi_mem_caps; 648 ctlr->set_cs = nuvoton_qspi_set_cs; 649 ctlr->transfer_one = nuvoton_qspi_transfer_one; 650 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); 651 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | 652 SPI_RX_DUAL | SPI_TX_DUAL | 653 SPI_RX_QUAD | SPI_TX_QUAD; 654 ctlr->dev.of_node = dev->of_node; 655 656 ret = nuvoton_qspi_hw_init(qspi); 657 if (ret) 658 return ret; 659 660 ret = devm_spi_register_controller(dev, ctlr); 661 if (ret) 662 return dev_err_probe(dev, ret, 663 "failed to register spi controller\n"); 664 665 return 0; 666 } 667 668 static const struct of_device_id nuvoton_qspi_of_match[] = { 669 { .compatible = "nuvoton,ma35d1-qspi" }, 670 { } 671 }; 672 MODULE_DEVICE_TABLE(of, nuvoton_qspi_of_match); 673 674 static struct platform_driver nuvoton_qspi_driver = { 675 .driver = { 676 .name = "ma35d1-qspi", 677 .of_match_table = nuvoton_qspi_of_match, 678 }, 679 .probe = nuvoton_qspi_probe, 680 }; 681 module_platform_driver(nuvoton_qspi_driver); 682 683 MODULE_DESCRIPTION("Nuvoton MA35D1 QSPI controller driver"); 684 MODULE_AUTHOR("Chi-Wen Weng <cwweng@nuvoton.com>"); 685 MODULE_LICENSE("GPL"); 686