1*b1de9823SBiju Das // SPDX-License-Identifier: GPL-2.0 2*b1de9823SBiju Das /* 3*b1de9823SBiju Das * RZ/G3L System controller (SYSC) driver 4*b1de9823SBiju Das * 5*b1de9823SBiju Das * Copyright (C) 2026 Renesas Electronics Corp. 6*b1de9823SBiju Das */ 7*b1de9823SBiju Das 8*b1de9823SBiju Das #include <linux/bits.h> 9*b1de9823SBiju Das #include <linux/device.h> 10*b1de9823SBiju Das #include <linux/init.h> 11*b1de9823SBiju Das 12*b1de9823SBiju Das #include "rz-sysc.h" 13*b1de9823SBiju Das 14*b1de9823SBiju Das #define SYS_XSPI_MAP_STAADD_CS0 0x348 15*b1de9823SBiju Das #define SYS_XSPI_MAP_ENDADD_CS0 0x34c 16*b1de9823SBiju Das #define SYS_XSPI_MAP_STAADD_CS1 0x350 17*b1de9823SBiju Das #define SYS_XSPI_MAP_ENDADD_CS1 0x354 18*b1de9823SBiju Das #define SYS_GETH0_CFG 0x380 19*b1de9823SBiju Das #define SYS_GETH1_CFG 0x390 20*b1de9823SBiju Das #define SYS_PCIE_CFG 0x3a0 21*b1de9823SBiju Das #define SYS_PCIE_MON 0x3a4 22*b1de9823SBiju Das #define SYS_PCIE_PHY 0x3b4 23*b1de9823SBiju Das #define SYS_I2C0_CFG 0x400 24*b1de9823SBiju Das #define SYS_I2C1_CFG 0x410 25*b1de9823SBiju Das #define SYS_I2C2_CFG 0x420 26*b1de9823SBiju Das #define SYS_I2C3_CFG 0x430 27*b1de9823SBiju Das #define SYS_I3C_CFG 0x440 28*b1de9823SBiju Das #define SYS_PWRRDY_N 0xd70 29*b1de9823SBiju Das #define SYS_IPCONT_SEL_CLONECH 0xe2c 30*b1de9823SBiju Das 31*b1de9823SBiju Das static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg) 32*b1de9823SBiju Das { 33*b1de9823SBiju Das switch (reg) { 34*b1de9823SBiju Das case SYS_XSPI_MAP_STAADD_CS0: 35*b1de9823SBiju Das case SYS_XSPI_MAP_ENDADD_CS0: 36*b1de9823SBiju Das case SYS_XSPI_MAP_STAADD_CS1: 37*b1de9823SBiju Das case SYS_XSPI_MAP_ENDADD_CS1: 38*b1de9823SBiju Das case SYS_GETH0_CFG: 39*b1de9823SBiju Das case SYS_GETH1_CFG: 40*b1de9823SBiju Das case SYS_PCIE_CFG: 41*b1de9823SBiju Das case SYS_PCIE_MON: 42*b1de9823SBiju Das case SYS_PCIE_PHY: 43*b1de9823SBiju Das case SYS_I2C0_CFG: 44*b1de9823SBiju Das case SYS_I2C1_CFG: 45*b1de9823SBiju Das case SYS_I2C2_CFG: 46*b1de9823SBiju Das case SYS_I2C3_CFG: 47*b1de9823SBiju Das case SYS_I3C_CFG: 48*b1de9823SBiju Das case SYS_PWRRDY_N: 49*b1de9823SBiju Das case SYS_IPCONT_SEL_CLONECH: 50*b1de9823SBiju Das return true; 51*b1de9823SBiju Das default: 52*b1de9823SBiju Das return false; 53*b1de9823SBiju Das } 54*b1de9823SBiju Das } 55*b1de9823SBiju Das 56*b1de9823SBiju Das static bool rzg3l_regmap_writeable_reg(struct device *dev, unsigned int reg) 57*b1de9823SBiju Das { 58*b1de9823SBiju Das switch (reg) { 59*b1de9823SBiju Das case SYS_XSPI_MAP_STAADD_CS0: 60*b1de9823SBiju Das case SYS_XSPI_MAP_ENDADD_CS0: 61*b1de9823SBiju Das case SYS_XSPI_MAP_STAADD_CS1: 62*b1de9823SBiju Das case SYS_XSPI_MAP_ENDADD_CS1: 63*b1de9823SBiju Das case SYS_PCIE_CFG: 64*b1de9823SBiju Das case SYS_PCIE_PHY: 65*b1de9823SBiju Das case SYS_I2C0_CFG: 66*b1de9823SBiju Das case SYS_I2C1_CFG: 67*b1de9823SBiju Das case SYS_I2C2_CFG: 68*b1de9823SBiju Das case SYS_I2C3_CFG: 69*b1de9823SBiju Das case SYS_I3C_CFG: 70*b1de9823SBiju Das case SYS_PWRRDY_N: 71*b1de9823SBiju Das case SYS_IPCONT_SEL_CLONECH: 72*b1de9823SBiju Das return true; 73*b1de9823SBiju Das default: 74*b1de9823SBiju Das return false; 75*b1de9823SBiju Das } 76*b1de9823SBiju Das } 77*b1de9823SBiju Das 78*b1de9823SBiju Das static const struct rz_sysc_soc_id_init_data rzg3l_sysc_soc_id_init_data __initconst = { 79*b1de9823SBiju Das .family = "RZ/G3L", 80*b1de9823SBiju Das .id = 0x87d9447, 81*b1de9823SBiju Das .devid_offset = 0xa04, 82*b1de9823SBiju Das .revision_mask = GENMASK(31, 28), 83*b1de9823SBiju Das .specific_id_mask = GENMASK(27, 0), 84*b1de9823SBiju Das }; 85*b1de9823SBiju Das 86*b1de9823SBiju Das const struct rz_sysc_init_data rzg3l_sysc_init_data __initconst = { 87*b1de9823SBiju Das .soc_id_init_data = &rzg3l_sysc_soc_id_init_data, 88*b1de9823SBiju Das .readable_reg = rzg3l_regmap_readable_reg, 89*b1de9823SBiju Das .writeable_reg = rzg3l_regmap_writeable_reg, 90*b1de9823SBiju Das .max_register = 0xe2c, 91*b1de9823SBiju Das }; 92