1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G3L System controller (SYSC) driver 4 * 5 * Copyright (C) 2026 Renesas Electronics Corp. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 12 #include "rz-sysc.h" 13 14 #define SYS_XSPI_MAP_STAADD_CS0 0x348 15 #define SYS_XSPI_MAP_ENDADD_CS0 0x34c 16 #define SYS_XSPI_MAP_STAADD_CS1 0x350 17 #define SYS_XSPI_MAP_ENDADD_CS1 0x354 18 #define SYS_GETH0_CFG 0x380 19 #define SYS_GETH1_CFG 0x390 20 #define SYS_PCIE_CFG 0x3a0 21 #define SYS_PCIE_MON 0x3a4 22 #define SYS_PCIE_PHY 0x3b4 23 #define SYS_I2C0_CFG 0x400 24 #define SYS_I2C1_CFG 0x410 25 #define SYS_I2C2_CFG 0x420 26 #define SYS_I2C3_CFG 0x430 27 #define SYS_I3C_CFG 0x440 28 #define SYS_PWRRDY_N 0xd70 29 #define SYS_IPCONT_SEL_CLONECH 0xe2c 30 31 static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg) 32 { 33 switch (reg) { 34 case SYS_XSPI_MAP_STAADD_CS0: 35 case SYS_XSPI_MAP_ENDADD_CS0: 36 case SYS_XSPI_MAP_STAADD_CS1: 37 case SYS_XSPI_MAP_ENDADD_CS1: 38 case SYS_GETH0_CFG: 39 case SYS_GETH1_CFG: 40 case SYS_PCIE_CFG: 41 case SYS_PCIE_MON: 42 case SYS_PCIE_PHY: 43 case SYS_I2C0_CFG: 44 case SYS_I2C1_CFG: 45 case SYS_I2C2_CFG: 46 case SYS_I2C3_CFG: 47 case SYS_I3C_CFG: 48 case SYS_PWRRDY_N: 49 case SYS_IPCONT_SEL_CLONECH: 50 return true; 51 default: 52 return false; 53 } 54 } 55 56 static bool rzg3l_regmap_writeable_reg(struct device *dev, unsigned int reg) 57 { 58 switch (reg) { 59 case SYS_XSPI_MAP_STAADD_CS0: 60 case SYS_XSPI_MAP_ENDADD_CS0: 61 case SYS_XSPI_MAP_STAADD_CS1: 62 case SYS_XSPI_MAP_ENDADD_CS1: 63 case SYS_PCIE_CFG: 64 case SYS_PCIE_PHY: 65 case SYS_I2C0_CFG: 66 case SYS_I2C1_CFG: 67 case SYS_I2C2_CFG: 68 case SYS_I2C3_CFG: 69 case SYS_I3C_CFG: 70 case SYS_PWRRDY_N: 71 case SYS_IPCONT_SEL_CLONECH: 72 return true; 73 default: 74 return false; 75 } 76 } 77 78 static const struct rz_sysc_soc_id_init_data rzg3l_sysc_soc_id_init_data __initconst = { 79 .family = "RZ/G3L", 80 .id = 0x87d9447, 81 .devid_offset = 0xa04, 82 .revision_mask = GENMASK(31, 28), 83 .specific_id_mask = GENMASK(27, 0), 84 }; 85 86 const struct rz_sysc_init_data rzg3l_sysc_init_data __initconst = { 87 .soc_id_init_data = &rzg3l_sysc_soc_id_init_data, 88 .readable_reg = rzg3l_regmap_readable_reg, 89 .writeable_reg = rzg3l_regmap_writeable_reg, 90 .max_register = 0xe2c, 91 }; 92