1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Largely copied from rzn1_irqmux.c 4 */ 5 6 #include <linux/bitmap.h> 7 #include <linux/bitops.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_irq.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #define MPFS_IRQMUX_CR 0x54 16 #define MPFS_IRQMUX_NUM_CHILDREN 96 17 #define MPFS_IRQMUX_NUM_DIRECT 38 18 #define MPFS_IRQMUX_DIRECT_START 13 19 #define MPFS_IRQMUX_DIRECT_END 50 20 #define MPFS_IRQMUX_NONDIRECT_END 53 21 22 static int mpfs_irqmux_is_direct_mode(struct device *dev, 23 const struct of_phandle_args *parent_args) 24 { 25 if (parent_args->args_count != 1) { 26 dev_err(dev, "Invalid interrupt-map item\n"); 27 return -EINVAL; 28 } 29 30 if (parent_args->args[0] < MPFS_IRQMUX_DIRECT_START || 31 parent_args->args[0] > MPFS_IRQMUX_NONDIRECT_END) { 32 dev_err(dev, "Invalid interrupt %u\n", parent_args->args[0]); 33 return -EINVAL; 34 } 35 36 if (parent_args->args[0] > MPFS_IRQMUX_DIRECT_END) 37 return 0; 38 39 return 1; 40 } 41 42 static int mpfs_irqmux_probe(struct platform_device *pdev) 43 { 44 DECLARE_BITMAP(child_done, MPFS_IRQMUX_NUM_CHILDREN) = {}; 45 DECLARE_BITMAP(parent_done, MPFS_IRQMUX_NUM_DIRECT) = {}; 46 struct device *dev = &pdev->dev; 47 struct device_node *np = dev->of_node; 48 struct of_imap_parser imap_parser; 49 struct of_imap_item imap_item; 50 struct regmap *regmap; 51 int ret, direct_mode, line, controller, gpio, parent_line; 52 u32 tmp, val = 0, old; 53 54 regmap = device_node_to_regmap(pdev->dev.parent->of_node); 55 if (IS_ERR(regmap)) 56 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to find syscon regmap\n"); 57 58 /* We support only #interrupt-cells = <1> and #address-cells = <0> */ 59 ret = of_property_read_u32(np, "#interrupt-cells", &tmp); 60 if (ret) 61 return ret; 62 if (tmp != 1) 63 return -EINVAL; 64 65 ret = of_property_read_u32(np, "#address-cells", &tmp); 66 if (ret) 67 return ret; 68 if (tmp != 0) 69 return -EINVAL; 70 71 ret = of_imap_parser_init(&imap_parser, np, &imap_item); 72 if (ret) 73 return ret; 74 75 for_each_of_imap_item(&imap_parser, &imap_item) { 76 77 direct_mode = mpfs_irqmux_is_direct_mode(dev, &imap_item.parent_args); 78 if (direct_mode < 0) { 79 of_node_put(imap_item.parent_args.np); 80 return direct_mode; 81 } 82 83 line = imap_item.child_imap[0]; 84 gpio = line % 32; 85 controller = line / 32; 86 87 if (controller > 2) { 88 of_node_put(imap_item.parent_args.np); 89 dev_err(dev, "child interrupt number too large: %d\n", line); 90 return -EINVAL; 91 } 92 93 if (test_and_set_bit(line, child_done)) { 94 of_node_put(imap_item.parent_args.np); 95 dev_err(dev, "mux child line %d already defined in interrupt-map\n", 96 line); 97 return -EINVAL; 98 } 99 100 parent_line = imap_item.parent_args.args[0] - MPFS_IRQMUX_DIRECT_START; 101 if (direct_mode && test_and_set_bit(parent_line, parent_done)) { 102 of_node_put(imap_item.parent_args.np); 103 dev_err(dev, "mux parent line %d already defined in interrupt-map\n", 104 line); 105 return -EINVAL; 106 } 107 108 /* 109 * There are 41 interrupts assigned to GPIOs, of which 38 are "direct". Since the 110 * mux has 32 bits only, 6 of these exclusive/"direct" interrupts remain. These 111 * are used by GPIO controller 1's lines 18 to 23. Nothing needs to be done 112 * for these interrupts. 113 */ 114 if (controller == 1 && gpio >= 18) 115 continue; 116 117 /* 118 * The mux has a single register, where bits 0 to 13 mux between GPIO controller 119 * 1's 14 GPIOs and GPIO controller 2's first 14 GPIOs. The remaining bits mux 120 * between the first 18 GPIOs of controller 1 and the last 18 GPIOS of 121 * controller 2. If a bit in the mux's control register is set, the 122 * corresponding interrupt line for GPIO controller 0 or 1 will be put in 123 * "non-direct" mode. If cleared, the "fabric" controller's will. 124 * 125 * Register layout: 126 * GPIO 1 interrupt line 17 | mux bit 31 | GPIO 2 interrupt line 31 127 * ... | ... | ... 128 * ... | ... | ... 129 * GPIO 1 interrupt line 0 | mux bit 14 | GPIO 2 interrupt line 14 130 * GPIO 0 interrupt line 13 | mux bit 13 | GPIO 2 interrupt line 13 131 * ... | ... | ... 132 * ... | ... | ... 133 * GPIO 0 interrupt line 0 | mux bit 0 | GPIO 2 interrupt line 0 134 * 135 * As the binding mandates 70 items, one for each GPIO line, there's no need to 136 * handle anything for GPIO controller 2, since the bit will be set for the 137 * corresponding line in GPIO controller 0 or 1. 138 */ 139 if (controller == 2) 140 continue; 141 142 /* 143 * If in direct mode, the bit is cleared, nothing needs to be done as val is zero 144 * initialised and that's the direct mode setting for GPIO controller 0 and 1. 145 */ 146 if (direct_mode) 147 continue; 148 149 if (controller == 0) 150 val |= 1U << gpio; 151 else 152 val |= 1U << (gpio + 14); 153 } 154 155 regmap_read(regmap, MPFS_IRQMUX_CR, &old); 156 regmap_write(regmap, MPFS_IRQMUX_CR, val); 157 158 if (val != old) 159 dev_info(dev, "firmware mux setting of 0x%x overwritten to 0x%x\n", old, val); 160 161 return 0; 162 } 163 164 static const struct of_device_id mpfs_irqmux_of_match[] = { 165 { .compatible = "microchip,mpfs-irqmux", }, 166 { } 167 }; 168 MODULE_DEVICE_TABLE(of, mpfs_irqmux_of_match); 169 170 static struct platform_driver mpfs_irqmux_driver = { 171 .probe = mpfs_irqmux_probe, 172 .driver = { 173 .name = "mpfs_irqmux", 174 .of_match_table = mpfs_irqmux_of_match, 175 }, 176 }; 177 module_platform_driver(mpfs_irqmux_driver); 178 179 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); 180 MODULE_DESCRIPTION("Polarfire SoC interrupt mux driver"); 181 MODULE_LICENSE("GPL"); 182