1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #include "mpi3mr.h" 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 13 static int 14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason); 15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc); 16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 17 struct mpi3_ioc_facts_data *facts_data); 18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 19 struct mpi3mr_drv_cmd *drv_cmd); 20 21 static int poll_queues; 22 module_param(poll_queues, int, 0444); 23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); 24 25 #if defined(writeq) && defined(CONFIG_64BIT) 26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 27 { 28 writeq(b, addr); 29 } 30 #else 31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 32 { 33 __u64 data_out = b; 34 35 writel((u32)(data_out), addr); 36 writel((u32)(data_out >> 32), (addr + 4)); 37 } 38 #endif 39 40 static inline bool 41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q) 42 { 43 u16 pi, ci, max_entries; 44 bool is_qfull = false; 45 46 pi = op_req_q->pi; 47 ci = READ_ONCE(op_req_q->ci); 48 max_entries = op_req_q->num_requests; 49 50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 51 is_qfull = true; 52 53 return is_qfull; 54 } 55 56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc) 57 { 58 u16 i, max_vectors; 59 60 max_vectors = mrioc->intr_info_count; 61 62 for (i = 0; i < max_vectors; i++) 63 synchronize_irq(pci_irq_vector(mrioc->pdev, i)); 64 } 65 66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc) 67 { 68 mrioc->intr_enabled = 0; 69 mpi3mr_sync_irqs(mrioc); 70 } 71 72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc) 73 { 74 mrioc->intr_enabled = 1; 75 } 76 77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) 78 { 79 u16 i; 80 81 mpi3mr_ioc_disable_intr(mrioc); 82 83 if (!mrioc->intr_info) 84 return; 85 86 for (i = 0; i < mrioc->intr_info_count; i++) 87 free_irq(pci_irq_vector(mrioc->pdev, i), 88 (mrioc->intr_info + i)); 89 90 kfree(mrioc->intr_info); 91 mrioc->intr_info = NULL; 92 mrioc->intr_info_count = 0; 93 mrioc->is_intr_info_set = false; 94 pci_free_irq_vectors(mrioc->pdev); 95 } 96 97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 98 dma_addr_t dma_addr) 99 { 100 struct mpi3_sge_common *sgel = paddr; 101 102 sgel->flags = flags; 103 sgel->length = cpu_to_le32(length); 104 sgel->address = cpu_to_le64(dma_addr); 105 } 106 107 void mpi3mr_build_zero_len_sge(void *paddr) 108 { 109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 110 111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 112 } 113 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 115 dma_addr_t phys_addr) 116 { 117 if (!phys_addr) 118 return NULL; 119 120 if ((phys_addr < mrioc->reply_buf_dma) || 121 (phys_addr > mrioc->reply_buf_dma_max_address)) 122 return NULL; 123 124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma); 125 } 126 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 128 dma_addr_t phys_addr) 129 { 130 if (!phys_addr) 131 return NULL; 132 133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma); 134 } 135 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, 137 u64 reply_dma) 138 { 139 u32 old_idx = 0; 140 unsigned long flags; 141 142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags); 143 old_idx = mrioc->reply_free_queue_host_index; 144 mrioc->reply_free_queue_host_index = ( 145 (mrioc->reply_free_queue_host_index == 146 (mrioc->reply_free_qsz - 1)) ? 0 : 147 (mrioc->reply_free_queue_host_index + 1)); 148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma); 149 writel(mrioc->reply_free_queue_host_index, 150 &mrioc->sysif_regs->reply_free_host_index); 151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags); 152 } 153 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 155 u64 sense_buf_dma) 156 { 157 u32 old_idx = 0; 158 unsigned long flags; 159 160 spin_lock_irqsave(&mrioc->sbq_lock, flags); 161 old_idx = mrioc->sbq_host_index; 162 mrioc->sbq_host_index = ((mrioc->sbq_host_index == 163 (mrioc->sense_buf_q_sz - 1)) ? 0 : 164 (mrioc->sbq_host_index + 1)); 165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma); 166 writel(mrioc->sbq_host_index, 167 &mrioc->sysif_regs->sense_buffer_free_host_index); 168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags); 169 } 170 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc, 172 struct mpi3_event_notification_reply *event_reply) 173 { 174 char *desc = NULL; 175 u16 event; 176 177 event = event_reply->event; 178 179 switch (event) { 180 case MPI3_EVENT_LOG_DATA: 181 desc = "Log Data"; 182 break; 183 case MPI3_EVENT_CHANGE: 184 desc = "Event Change"; 185 break; 186 case MPI3_EVENT_GPIO_INTERRUPT: 187 desc = "GPIO Interrupt"; 188 break; 189 case MPI3_EVENT_CABLE_MGMT: 190 desc = "Cable Management"; 191 break; 192 case MPI3_EVENT_ENERGY_PACK_CHANGE: 193 desc = "Energy Pack Change"; 194 break; 195 case MPI3_EVENT_DEVICE_ADDED: 196 { 197 struct mpi3_device_page0 *event_data = 198 (struct mpi3_device_page0 *)event_reply->event_data; 199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n", 200 event_data->dev_handle, event_data->device_form); 201 return; 202 } 203 case MPI3_EVENT_DEVICE_INFO_CHANGED: 204 { 205 struct mpi3_device_page0 *event_data = 206 (struct mpi3_device_page0 *)event_reply->event_data; 207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n", 208 event_data->dev_handle, event_data->device_form); 209 return; 210 } 211 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 212 { 213 struct mpi3_event_data_device_status_change *event_data = 214 (struct mpi3_event_data_device_status_change *)event_reply->event_data; 215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n", 216 event_data->dev_handle, event_data->reason_code); 217 return; 218 } 219 case MPI3_EVENT_SAS_DISCOVERY: 220 { 221 struct mpi3_event_data_sas_discovery *event_data = 222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data; 223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n", 224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 225 "start" : "stop", 226 le32_to_cpu(event_data->discovery_status)); 227 return; 228 } 229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 230 desc = "SAS Broadcast Primitive"; 231 break; 232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 233 desc = "SAS Notify Primitive"; 234 break; 235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 236 desc = "SAS Init Device Status Change"; 237 break; 238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 239 desc = "SAS Init Table Overflow"; 240 break; 241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 242 desc = "SAS Topology Change List"; 243 break; 244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 245 desc = "Enclosure Device Status Change"; 246 break; 247 case MPI3_EVENT_ENCL_DEVICE_ADDED: 248 desc = "Enclosure Added"; 249 break; 250 case MPI3_EVENT_HARD_RESET_RECEIVED: 251 desc = "Hard Reset Received"; 252 break; 253 case MPI3_EVENT_SAS_PHY_COUNTER: 254 desc = "SAS PHY Counter"; 255 break; 256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 257 desc = "SAS Device Discovery Error"; 258 break; 259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 260 desc = "PCIE Topology Change List"; 261 break; 262 case MPI3_EVENT_PCIE_ENUMERATION: 263 { 264 struct mpi3_event_data_pcie_enumeration *event_data = 265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data; 266 ioc_info(mrioc, "PCIE Enumeration: (%s)", 267 (event_data->reason_code == 268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop"); 269 if (event_data->enumeration_status) 270 ioc_info(mrioc, "enumeration_status(0x%08x)\n", 271 le32_to_cpu(event_data->enumeration_status)); 272 return; 273 } 274 case MPI3_EVENT_PREPARE_FOR_RESET: 275 desc = "Prepare For Reset"; 276 break; 277 case MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE: 278 desc = "Diagnostic Buffer Status Change"; 279 break; 280 } 281 282 if (!desc) 283 return; 284 285 ioc_info(mrioc, "%s\n", desc); 286 } 287 288 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc, 289 struct mpi3_default_reply *def_reply) 290 { 291 struct mpi3_event_notification_reply *event_reply = 292 (struct mpi3_event_notification_reply *)def_reply; 293 294 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count); 295 mpi3mr_print_event_data(mrioc, event_reply); 296 mpi3mr_os_handle_events(mrioc, event_reply); 297 } 298 299 static struct mpi3mr_drv_cmd * 300 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, 301 struct mpi3_default_reply *def_reply) 302 { 303 u16 idx; 304 305 switch (host_tag) { 306 case MPI3MR_HOSTTAG_INITCMDS: 307 return &mrioc->init_cmds; 308 case MPI3MR_HOSTTAG_CFG_CMDS: 309 return &mrioc->cfg_cmds; 310 case MPI3MR_HOSTTAG_BSG_CMDS: 311 return &mrioc->bsg_cmds; 312 case MPI3MR_HOSTTAG_BLK_TMS: 313 return &mrioc->host_tm_cmds; 314 case MPI3MR_HOSTTAG_PEL_ABORT: 315 return &mrioc->pel_abort_cmd; 316 case MPI3MR_HOSTTAG_PEL_WAIT: 317 return &mrioc->pel_cmds; 318 case MPI3MR_HOSTTAG_TRANSPORT_CMDS: 319 return &mrioc->transport_cmds; 320 case MPI3MR_HOSTTAG_INVALID: 321 if (def_reply && def_reply->function == 322 MPI3_FUNCTION_EVENT_NOTIFICATION) 323 mpi3mr_handle_events(mrioc, def_reply); 324 return NULL; 325 default: 326 break; 327 } 328 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 329 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) { 330 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 331 return &mrioc->dev_rmhs_cmds[idx]; 332 } 333 334 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 335 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 336 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 337 return &mrioc->evtack_cmds[idx]; 338 } 339 340 return NULL; 341 } 342 343 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, 344 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma) 345 { 346 u16 reply_desc_type, host_tag = 0; 347 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 348 u16 masked_ioc_status = MPI3_IOCSTATUS_SUCCESS; 349 u32 ioc_loginfo = 0, sense_count = 0; 350 struct mpi3_status_reply_descriptor *status_desc; 351 struct mpi3_address_reply_descriptor *addr_desc; 352 struct mpi3_success_reply_descriptor *success_desc; 353 struct mpi3_default_reply *def_reply = NULL; 354 struct mpi3mr_drv_cmd *cmdptr = NULL; 355 struct mpi3_scsi_io_reply *scsi_reply; 356 struct scsi_sense_hdr sshdr; 357 u8 *sense_buf = NULL; 358 359 *reply_dma = 0; 360 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) & 361 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 362 switch (reply_desc_type) { 363 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 364 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc; 365 host_tag = le16_to_cpu(status_desc->host_tag); 366 ioc_status = le16_to_cpu(status_desc->ioc_status); 367 if (ioc_status & 368 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 369 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info); 370 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 371 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo); 372 break; 373 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 374 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc; 375 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address); 376 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma); 377 if (!def_reply) 378 goto out; 379 host_tag = le16_to_cpu(def_reply->host_tag); 380 ioc_status = le16_to_cpu(def_reply->ioc_status); 381 if (ioc_status & 382 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 383 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info); 384 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 385 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) { 386 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply; 387 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc, 388 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 389 sense_count = le32_to_cpu(scsi_reply->sense_count); 390 if (sense_buf) { 391 scsi_normalize_sense(sense_buf, sense_count, 392 &sshdr); 393 mpi3mr_scsisense_trigger(mrioc, sshdr.sense_key, 394 sshdr.asc, sshdr.ascq); 395 } 396 } 397 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo); 398 break; 399 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 400 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc; 401 host_tag = le16_to_cpu(success_desc->host_tag); 402 break; 403 default: 404 break; 405 } 406 407 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply); 408 if (cmdptr) { 409 if (cmdptr->state & MPI3MR_CMD_PENDING) { 410 cmdptr->state |= MPI3MR_CMD_COMPLETE; 411 cmdptr->ioc_loginfo = ioc_loginfo; 412 if (host_tag == MPI3MR_HOSTTAG_BSG_CMDS) 413 cmdptr->ioc_status = ioc_status; 414 else 415 cmdptr->ioc_status = masked_ioc_status; 416 cmdptr->state &= ~MPI3MR_CMD_PENDING; 417 if (def_reply) { 418 cmdptr->state |= MPI3MR_CMD_REPLY_VALID; 419 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply, 420 mrioc->reply_sz); 421 } 422 if (sense_buf && cmdptr->sensebuf) { 423 cmdptr->is_sense = 1; 424 memcpy(cmdptr->sensebuf, sense_buf, 425 MPI3MR_SENSE_BUF_SZ); 426 } 427 if (cmdptr->is_waiting) { 428 complete(&cmdptr->done); 429 cmdptr->is_waiting = 0; 430 } else if (cmdptr->callback) 431 cmdptr->callback(mrioc, cmdptr); 432 } 433 } 434 out: 435 if (sense_buf) 436 mpi3mr_repost_sense_buf(mrioc, 437 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 438 } 439 440 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc) 441 { 442 u32 exp_phase = mrioc->admin_reply_ephase; 443 u32 admin_reply_ci = mrioc->admin_reply_ci; 444 u32 num_admin_replies = 0; 445 u64 reply_dma = 0; 446 u16 threshold_comps = 0; 447 struct mpi3_default_reply_descriptor *reply_desc; 448 449 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1)) 450 return 0; 451 452 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 453 admin_reply_ci; 454 455 if ((le16_to_cpu(reply_desc->reply_flags) & 456 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 457 atomic_dec(&mrioc->admin_reply_q_in_use); 458 return 0; 459 } 460 461 do { 462 if (mrioc->unrecoverable) 463 break; 464 465 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci); 466 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma); 467 if (reply_dma) 468 mpi3mr_repost_reply_buf(mrioc, reply_dma); 469 num_admin_replies++; 470 threshold_comps++; 471 if (++admin_reply_ci == mrioc->num_admin_replies) { 472 admin_reply_ci = 0; 473 exp_phase ^= 1; 474 } 475 reply_desc = 476 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 477 admin_reply_ci; 478 if ((le16_to_cpu(reply_desc->reply_flags) & 479 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 480 break; 481 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) { 482 writel(admin_reply_ci, 483 &mrioc->sysif_regs->admin_reply_queue_ci); 484 threshold_comps = 0; 485 } 486 } while (1); 487 488 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 489 mrioc->admin_reply_ci = admin_reply_ci; 490 mrioc->admin_reply_ephase = exp_phase; 491 atomic_dec(&mrioc->admin_reply_q_in_use); 492 493 return num_admin_replies; 494 } 495 496 /** 497 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to 498 * queue's consumer index from operational reply descriptor queue. 499 * @op_reply_q: op_reply_qinfo object 500 * @reply_ci: operational reply descriptor's queue consumer index 501 * 502 * Returns: reply descriptor frame address 503 */ 504 static inline struct mpi3_default_reply_descriptor * 505 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) 506 { 507 void *segment_base_addr; 508 struct segments *segments = op_reply_q->q_segments; 509 struct mpi3_default_reply_descriptor *reply_desc = NULL; 510 511 segment_base_addr = 512 segments[reply_ci / op_reply_q->segment_qd].segment; 513 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr + 514 (reply_ci % op_reply_q->segment_qd); 515 return reply_desc; 516 } 517 518 /** 519 * mpi3mr_process_op_reply_q - Operational reply queue handler 520 * @mrioc: Adapter instance reference 521 * @op_reply_q: Operational reply queue info 522 * 523 * Checks the specific operational reply queue and drains the 524 * reply queue entries until the queue is empty and process the 525 * individual reply descriptors. 526 * 527 * Return: 0 if queue is already processed,or number of reply 528 * descriptors processed. 529 */ 530 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 531 struct op_reply_qinfo *op_reply_q) 532 { 533 struct op_req_qinfo *op_req_q; 534 u32 exp_phase; 535 u32 reply_ci; 536 u32 num_op_reply = 0; 537 u64 reply_dma = 0; 538 struct mpi3_default_reply_descriptor *reply_desc; 539 u16 req_q_idx = 0, reply_qidx, threshold_comps = 0; 540 541 reply_qidx = op_reply_q->qid - 1; 542 543 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1)) 544 return 0; 545 546 exp_phase = op_reply_q->ephase; 547 reply_ci = op_reply_q->ci; 548 549 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 550 if ((le16_to_cpu(reply_desc->reply_flags) & 551 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 552 atomic_dec(&op_reply_q->in_use); 553 return 0; 554 } 555 556 do { 557 if (mrioc->unrecoverable) 558 break; 559 560 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1; 561 op_req_q = &mrioc->req_qinfo[req_q_idx]; 562 563 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci)); 564 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma, 565 reply_qidx); 566 atomic_dec(&op_reply_q->pend_ios); 567 if (reply_dma) 568 mpi3mr_repost_reply_buf(mrioc, reply_dma); 569 num_op_reply++; 570 threshold_comps++; 571 572 if (++reply_ci == op_reply_q->num_replies) { 573 reply_ci = 0; 574 exp_phase ^= 1; 575 } 576 577 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 578 579 if ((le16_to_cpu(reply_desc->reply_flags) & 580 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 581 break; 582 #ifndef CONFIG_PREEMPT_RT 583 /* 584 * Exit completion loop to avoid CPU lockup 585 * Ensure remaining completion happens from threaded ISR. 586 */ 587 if (num_op_reply > mrioc->max_host_ios) { 588 op_reply_q->enable_irq_poll = true; 589 break; 590 } 591 #endif 592 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) { 593 writel(reply_ci, 594 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 595 atomic_sub(threshold_comps, &op_reply_q->pend_ios); 596 threshold_comps = 0; 597 } 598 } while (1); 599 600 writel(reply_ci, 601 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 602 op_reply_q->ci = reply_ci; 603 op_reply_q->ephase = exp_phase; 604 atomic_sub(threshold_comps, &op_reply_q->pend_ios); 605 atomic_dec(&op_reply_q->in_use); 606 return num_op_reply; 607 } 608 609 /** 610 * mpi3mr_blk_mq_poll - Operational reply queue handler 611 * @shost: SCSI Host reference 612 * @queue_num: Request queue number (w.r.t OS it is hardware context number) 613 * 614 * Checks the specific operational reply queue and drains the 615 * reply queue entries until the queue is empty and process the 616 * individual reply descriptors. 617 * 618 * Return: 0 if queue is already processed,or number of reply 619 * descriptors processed. 620 */ 621 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 622 { 623 int num_entries = 0; 624 struct mpi3mr_ioc *mrioc; 625 626 mrioc = (struct mpi3mr_ioc *)shost->hostdata; 627 628 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset || 629 mrioc->unrecoverable || mrioc->pci_err_recovery)) 630 return 0; 631 632 num_entries = mpi3mr_process_op_reply_q(mrioc, 633 &mrioc->op_reply_qinfo[queue_num]); 634 635 return num_entries; 636 } 637 638 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) 639 { 640 struct mpi3mr_intr_info *intr_info = privdata; 641 struct mpi3mr_ioc *mrioc; 642 u16 midx; 643 u32 num_admin_replies = 0, num_op_reply = 0; 644 645 if (!intr_info) 646 return IRQ_NONE; 647 648 mrioc = intr_info->mrioc; 649 650 if (!mrioc->intr_enabled) 651 return IRQ_NONE; 652 653 midx = intr_info->msix_index; 654 655 if (!midx) 656 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc); 657 if (intr_info->op_reply_q) 658 num_op_reply = mpi3mr_process_op_reply_q(mrioc, 659 intr_info->op_reply_q); 660 661 if (num_admin_replies || num_op_reply) 662 return IRQ_HANDLED; 663 else 664 return IRQ_NONE; 665 } 666 667 #ifndef CONFIG_PREEMPT_RT 668 669 static irqreturn_t mpi3mr_isr(int irq, void *privdata) 670 { 671 struct mpi3mr_intr_info *intr_info = privdata; 672 int ret; 673 674 if (!intr_info) 675 return IRQ_NONE; 676 677 /* Call primary ISR routine */ 678 ret = mpi3mr_isr_primary(irq, privdata); 679 680 /* 681 * If more IOs are expected, schedule IRQ polling thread. 682 * Otherwise exit from ISR. 683 */ 684 if (!intr_info->op_reply_q) 685 return ret; 686 687 if (!intr_info->op_reply_q->enable_irq_poll || 688 !atomic_read(&intr_info->op_reply_q->pend_ios)) 689 return ret; 690 691 disable_irq_nosync(intr_info->os_irq); 692 693 return IRQ_WAKE_THREAD; 694 } 695 696 /** 697 * mpi3mr_isr_poll - Reply queue polling routine 698 * @irq: IRQ 699 * @privdata: Interrupt info 700 * 701 * poll for pending I/O completions in a loop until pending I/Os 702 * present or controller queue depth I/Os are processed. 703 * 704 * Return: IRQ_NONE or IRQ_HANDLED 705 */ 706 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) 707 { 708 struct mpi3mr_intr_info *intr_info = privdata; 709 struct mpi3mr_ioc *mrioc; 710 u16 midx; 711 u32 num_op_reply = 0; 712 713 if (!intr_info || !intr_info->op_reply_q) 714 return IRQ_NONE; 715 716 mrioc = intr_info->mrioc; 717 midx = intr_info->msix_index; 718 719 /* Poll for pending IOs completions */ 720 do { 721 if (!mrioc->intr_enabled || mrioc->unrecoverable) 722 break; 723 724 if (!midx) 725 mpi3mr_process_admin_reply_q(mrioc); 726 if (intr_info->op_reply_q) 727 num_op_reply += 728 mpi3mr_process_op_reply_q(mrioc, 729 intr_info->op_reply_q); 730 731 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP); 732 733 } while (atomic_read(&intr_info->op_reply_q->pend_ios) && 734 (num_op_reply < mrioc->max_host_ios)); 735 736 intr_info->op_reply_q->enable_irq_poll = false; 737 enable_irq(intr_info->os_irq); 738 739 return IRQ_HANDLED; 740 } 741 742 #endif 743 744 /** 745 * mpi3mr_request_irq - Request IRQ and register ISR 746 * @mrioc: Adapter instance reference 747 * @index: IRQ vector index 748 * 749 * Request threaded ISR with primary ISR and secondary 750 * 751 * Return: 0 on success and non zero on failures. 752 */ 753 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) 754 { 755 struct pci_dev *pdev = mrioc->pdev; 756 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index; 757 int retval = 0; 758 759 intr_info->mrioc = mrioc; 760 intr_info->msix_index = index; 761 intr_info->op_reply_q = NULL; 762 763 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", 764 mrioc->driver_name, mrioc->id, index); 765 766 #ifndef CONFIG_PREEMPT_RT 767 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, 768 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); 769 #else 770 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary, 771 NULL, IRQF_SHARED, intr_info->name, intr_info); 772 #endif 773 if (retval) { 774 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", 775 intr_info->name, pci_irq_vector(pdev, index)); 776 return retval; 777 } 778 779 intr_info->os_irq = pci_irq_vector(pdev, index); 780 return retval; 781 } 782 783 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors) 784 { 785 if (!mrioc->requested_poll_qcount) 786 return; 787 788 /* Reserved for Admin and Default Queue */ 789 if (max_vectors > 2 && 790 (mrioc->requested_poll_qcount < max_vectors - 2)) { 791 ioc_info(mrioc, 792 "enabled polled queues (%d) msix (%d)\n", 793 mrioc->requested_poll_qcount, max_vectors); 794 } else { 795 ioc_info(mrioc, 796 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n", 797 mrioc->requested_poll_qcount, max_vectors); 798 mrioc->requested_poll_qcount = 0; 799 } 800 } 801 802 /** 803 * mpi3mr_setup_isr - Setup ISR for the controller 804 * @mrioc: Adapter instance reference 805 * @setup_one: Request one IRQ or more 806 * 807 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR 808 * 809 * Return: 0 on success and non zero on failures. 810 */ 811 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) 812 { 813 unsigned int irq_flags = PCI_IRQ_MSIX; 814 int max_vectors, min_vec; 815 int retval; 816 int i; 817 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 }; 818 819 if (mrioc->is_intr_info_set) 820 return 0; 821 822 mpi3mr_cleanup_isr(mrioc); 823 824 if (setup_one || reset_devices) { 825 max_vectors = 1; 826 retval = pci_alloc_irq_vectors(mrioc->pdev, 827 1, max_vectors, irq_flags); 828 if (retval < 0) { 829 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 830 retval); 831 goto out_failed; 832 } 833 } else { 834 max_vectors = 835 min_t(int, mrioc->cpu_count + 1 + 836 mrioc->requested_poll_qcount, mrioc->msix_count); 837 838 mpi3mr_calc_poll_queues(mrioc, max_vectors); 839 840 ioc_info(mrioc, 841 "MSI-X vectors supported: %d, no of cores: %d,", 842 mrioc->msix_count, mrioc->cpu_count); 843 ioc_info(mrioc, 844 "MSI-x vectors requested: %d poll_queues %d\n", 845 max_vectors, mrioc->requested_poll_qcount); 846 847 desc.post_vectors = mrioc->requested_poll_qcount; 848 min_vec = desc.pre_vectors + desc.post_vectors; 849 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 850 851 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev, 852 min_vec, max_vectors, irq_flags, &desc); 853 854 if (retval < 0) { 855 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 856 retval); 857 goto out_failed; 858 } 859 860 861 /* 862 * If only one MSI-x is allocated, then MSI-x 0 will be shared 863 * between Admin queue and operational queue 864 */ 865 if (retval == min_vec) 866 mrioc->op_reply_q_offset = 0; 867 else if (retval != (max_vectors)) { 868 ioc_info(mrioc, 869 "allocated vectors (%d) are less than configured (%d)\n", 870 retval, max_vectors); 871 } 872 873 max_vectors = retval; 874 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0; 875 876 mpi3mr_calc_poll_queues(mrioc, max_vectors); 877 878 } 879 880 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors, 881 GFP_KERNEL); 882 if (!mrioc->intr_info) { 883 retval = -ENOMEM; 884 pci_free_irq_vectors(mrioc->pdev); 885 goto out_failed; 886 } 887 for (i = 0; i < max_vectors; i++) { 888 retval = mpi3mr_request_irq(mrioc, i); 889 if (retval) { 890 mrioc->intr_info_count = i; 891 goto out_failed; 892 } 893 } 894 if (reset_devices || !setup_one) 895 mrioc->is_intr_info_set = true; 896 mrioc->intr_info_count = max_vectors; 897 mpi3mr_ioc_enable_intr(mrioc); 898 return 0; 899 900 out_failed: 901 mpi3mr_cleanup_isr(mrioc); 902 903 return retval; 904 } 905 906 static const struct { 907 enum mpi3mr_iocstate value; 908 char *name; 909 } mrioc_states[] = { 910 { MRIOC_STATE_READY, "ready" }, 911 { MRIOC_STATE_FAULT, "fault" }, 912 { MRIOC_STATE_RESET, "reset" }, 913 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 914 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 915 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" }, 916 }; 917 918 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 919 { 920 int i; 921 char *name = NULL; 922 923 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) { 924 if (mrioc_states[i].value == mrioc_state) { 925 name = mrioc_states[i].name; 926 break; 927 } 928 } 929 return name; 930 } 931 932 /* Reset reason to name mapper structure*/ 933 static const struct { 934 enum mpi3mr_reset_reason value; 935 char *name; 936 } mpi3mr_reset_reason_codes[] = { 937 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 938 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 939 { MPI3MR_RESET_FROM_APP, "application invocation" }, 940 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 941 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 942 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" }, 943 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 944 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 945 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 946 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 947 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 948 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 949 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 950 { 951 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 952 "create request queue timeout" 953 }, 954 { 955 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 956 "create reply queue timeout" 957 }, 958 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 959 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 960 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 961 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 962 { 963 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 964 "component image activation timeout" 965 }, 966 { 967 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 968 "get package version timeout" 969 }, 970 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 971 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 972 { 973 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT, 974 "diagnostic buffer post timeout" 975 }, 976 { 977 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT, 978 "diagnostic buffer release timeout" 979 }, 980 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" }, 981 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"}, 982 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" }, 983 }; 984 985 /** 986 * mpi3mr_reset_rc_name - get reset reason code name 987 * @reason_code: reset reason code value 988 * 989 * Map reset reason to an NULL terminated ASCII string 990 * 991 * Return: name corresponding to reset reason value or NULL. 992 */ 993 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 994 { 995 int i; 996 char *name = NULL; 997 998 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) { 999 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 1000 name = mpi3mr_reset_reason_codes[i].name; 1001 break; 1002 } 1003 } 1004 return name; 1005 } 1006 1007 /* Reset type to name mapper structure*/ 1008 static const struct { 1009 u16 reset_type; 1010 char *name; 1011 } mpi3mr_reset_types[] = { 1012 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 1013 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 1014 }; 1015 1016 /** 1017 * mpi3mr_reset_type_name - get reset type name 1018 * @reset_type: reset type value 1019 * 1020 * Map reset type to an NULL terminated ASCII string 1021 * 1022 * Return: name corresponding to reset type value or NULL. 1023 */ 1024 static const char *mpi3mr_reset_type_name(u16 reset_type) 1025 { 1026 int i; 1027 char *name = NULL; 1028 1029 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) { 1030 if (mpi3mr_reset_types[i].reset_type == reset_type) { 1031 name = mpi3mr_reset_types[i].name; 1032 break; 1033 } 1034 } 1035 return name; 1036 } 1037 1038 /** 1039 * mpi3mr_print_fault_info - Display fault information 1040 * @mrioc: Adapter instance reference 1041 * 1042 * Display the controller fault information if there is a 1043 * controller fault. 1044 * 1045 * Return: Nothing. 1046 */ 1047 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc) 1048 { 1049 u32 ioc_status, code, code1, code2, code3; 1050 1051 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1052 1053 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1054 code = readl(&mrioc->sysif_regs->fault); 1055 code1 = readl(&mrioc->sysif_regs->fault_info[0]); 1056 code2 = readl(&mrioc->sysif_regs->fault_info[1]); 1057 code3 = readl(&mrioc->sysif_regs->fault_info[2]); 1058 1059 ioc_info(mrioc, 1060 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n", 1061 code, code1, code2, code3); 1062 } 1063 } 1064 1065 /** 1066 * mpi3mr_get_iocstate - Get IOC State 1067 * @mrioc: Adapter instance reference 1068 * 1069 * Return a proper IOC state enum based on the IOC status and 1070 * IOC configuration and unrcoverable state of the controller. 1071 * 1072 * Return: Current IOC state. 1073 */ 1074 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc) 1075 { 1076 u32 ioc_status, ioc_config; 1077 u8 ready, enabled; 1078 1079 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1080 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1081 1082 if (mrioc->unrecoverable) 1083 return MRIOC_STATE_UNRECOVERABLE; 1084 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1085 return MRIOC_STATE_FAULT; 1086 1087 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1088 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1089 1090 if (ready && enabled) 1091 return MRIOC_STATE_READY; 1092 if ((!ready) && (!enabled)) 1093 return MRIOC_STATE_RESET; 1094 if ((!ready) && (enabled)) 1095 return MRIOC_STATE_BECOMING_READY; 1096 1097 return MRIOC_STATE_RESET_REQUESTED; 1098 } 1099 1100 /** 1101 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma 1102 * @mrioc: Adapter instance reference 1103 * 1104 * Free the DMA memory allocated for IOCTL handling purpose. 1105 * 1106 * Return: None 1107 */ 1108 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc) 1109 { 1110 struct dma_memory_desc *mem_desc; 1111 u16 i; 1112 1113 if (!mrioc->ioctl_dma_pool) 1114 return; 1115 1116 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) { 1117 mem_desc = &mrioc->ioctl_sge[i]; 1118 if (mem_desc->addr) { 1119 dma_pool_free(mrioc->ioctl_dma_pool, 1120 mem_desc->addr, 1121 mem_desc->dma_addr); 1122 mem_desc->addr = NULL; 1123 } 1124 } 1125 dma_pool_destroy(mrioc->ioctl_dma_pool); 1126 mrioc->ioctl_dma_pool = NULL; 1127 mem_desc = &mrioc->ioctl_chain_sge; 1128 1129 if (mem_desc->addr) { 1130 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 1131 mem_desc->addr, mem_desc->dma_addr); 1132 mem_desc->addr = NULL; 1133 } 1134 mem_desc = &mrioc->ioctl_resp_sge; 1135 if (mem_desc->addr) { 1136 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 1137 mem_desc->addr, mem_desc->dma_addr); 1138 mem_desc->addr = NULL; 1139 } 1140 1141 mrioc->ioctl_sges_allocated = false; 1142 } 1143 1144 /** 1145 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma 1146 * @mrioc: Adapter instance reference 1147 * 1148 * This function allocates dmaable memory required to handle the 1149 * application issued MPI3 IOCTL requests. 1150 * 1151 * Return: None 1152 */ 1153 static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc) 1154 1155 { 1156 struct dma_memory_desc *mem_desc; 1157 u16 i; 1158 1159 mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool", 1160 &mrioc->pdev->dev, 1161 MPI3MR_IOCTL_SGE_SIZE, 1162 MPI3MR_PAGE_SIZE_4K, 0); 1163 1164 if (!mrioc->ioctl_dma_pool) { 1165 ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n"); 1166 goto out_failed; 1167 } 1168 1169 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) { 1170 mem_desc = &mrioc->ioctl_sge[i]; 1171 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE; 1172 mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool, 1173 GFP_KERNEL, 1174 &mem_desc->dma_addr); 1175 if (!mem_desc->addr) 1176 goto out_failed; 1177 } 1178 1179 mem_desc = &mrioc->ioctl_chain_sge; 1180 mem_desc->size = MPI3MR_PAGE_SIZE_4K; 1181 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 1182 mem_desc->size, 1183 &mem_desc->dma_addr, 1184 GFP_KERNEL); 1185 if (!mem_desc->addr) 1186 goto out_failed; 1187 1188 mem_desc = &mrioc->ioctl_resp_sge; 1189 mem_desc->size = MPI3MR_PAGE_SIZE_4K; 1190 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 1191 mem_desc->size, 1192 &mem_desc->dma_addr, 1193 GFP_KERNEL); 1194 if (!mem_desc->addr) 1195 goto out_failed; 1196 1197 mrioc->ioctl_sges_allocated = true; 1198 1199 return; 1200 out_failed: 1201 ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n" 1202 "from the applications, application interface for MPT command is disabled\n"); 1203 mpi3mr_free_ioctl_dma_memory(mrioc); 1204 } 1205 1206 /** 1207 * mpi3mr_clear_reset_history - clear reset history 1208 * @mrioc: Adapter instance reference 1209 * 1210 * Write the reset history bit in IOC status to clear the bit, 1211 * if it is already set. 1212 * 1213 * Return: Nothing. 1214 */ 1215 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) 1216 { 1217 u32 ioc_status; 1218 1219 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1220 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1221 writel(ioc_status, &mrioc->sysif_regs->ioc_status); 1222 } 1223 1224 /** 1225 * mpi3mr_issue_and_process_mur - Message unit Reset handler 1226 * @mrioc: Adapter instance reference 1227 * @reset_reason: Reset reason code 1228 * 1229 * Issue Message unit Reset to the controller and wait for it to 1230 * be complete. 1231 * 1232 * Return: 0 on success, -1 on failure. 1233 */ 1234 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, 1235 u32 reset_reason) 1236 { 1237 u32 ioc_config, timeout, ioc_status, scratch_pad0; 1238 int retval = -1; 1239 1240 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); 1241 if (mrioc->unrecoverable) { 1242 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n"); 1243 return retval; 1244 } 1245 mpi3mr_clear_reset_history(mrioc); 1246 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX << 1247 MPI3MR_RESET_REASON_OSTYPE_SHIFT) | 1248 (mrioc->facts.ioc_num << 1249 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason); 1250 writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]); 1251 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1252 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1253 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1254 1255 timeout = MPI3MR_MUR_TIMEOUT * 10; 1256 do { 1257 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1258 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1259 mpi3mr_clear_reset_history(mrioc); 1260 break; 1261 } 1262 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1263 mpi3mr_print_fault_info(mrioc); 1264 break; 1265 } 1266 msleep(100); 1267 } while (--timeout); 1268 1269 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1270 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1271 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1272 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1273 retval = 0; 1274 1275 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n", 1276 (!retval) ? "successful" : "failed", ioc_status, ioc_config); 1277 return retval; 1278 } 1279 1280 /** 1281 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters 1282 * during reset/resume 1283 * @mrioc: Adapter instance reference 1284 * 1285 * Return: zero if the new IOCFacts parameters value is compatible with 1286 * older values else return -EPERM 1287 */ 1288 static int 1289 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc) 1290 { 1291 unsigned long *removepend_bitmap; 1292 1293 if (mrioc->facts.reply_sz > mrioc->reply_sz) { 1294 ioc_err(mrioc, 1295 "cannot increase reply size from %d to %d\n", 1296 mrioc->reply_sz, mrioc->facts.reply_sz); 1297 return -EPERM; 1298 } 1299 1300 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) { 1301 ioc_err(mrioc, 1302 "cannot reduce number of operational reply queues from %d to %d\n", 1303 mrioc->num_op_reply_q, 1304 mrioc->facts.max_op_reply_q); 1305 return -EPERM; 1306 } 1307 1308 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) { 1309 ioc_err(mrioc, 1310 "cannot reduce number of operational request queues from %d to %d\n", 1311 mrioc->num_op_req_q, mrioc->facts.max_op_req_q); 1312 return -EPERM; 1313 } 1314 1315 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512)) 1316 ioc_err(mrioc, "Warning: The maximum data transfer length\n" 1317 "\tchanged after reset: previous(%d), new(%d),\n" 1318 "the driver cannot change this at run time\n", 1319 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length); 1320 1321 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities & 1322 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) 1323 ioc_err(mrioc, 1324 "critical error: multipath capability is enabled at the\n" 1325 "\tcontroller while sas transport support is enabled at the\n" 1326 "\tdriver, please reboot the system or reload the driver\n"); 1327 1328 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) { 1329 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle, 1330 GFP_KERNEL); 1331 if (!removepend_bitmap) { 1332 ioc_err(mrioc, 1333 "failed to increase removepend_bitmap bits from %d to %d\n", 1334 mrioc->dev_handle_bitmap_bits, 1335 mrioc->facts.max_devhandle); 1336 return -EPERM; 1337 } 1338 bitmap_free(mrioc->removepend_bitmap); 1339 mrioc->removepend_bitmap = removepend_bitmap; 1340 ioc_info(mrioc, 1341 "increased bits of dev_handle_bitmap from %d to %d\n", 1342 mrioc->dev_handle_bitmap_bits, 1343 mrioc->facts.max_devhandle); 1344 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 1345 } 1346 1347 return 0; 1348 } 1349 1350 /** 1351 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1352 * @mrioc: Adapter instance reference 1353 * 1354 * Set Enable IOC bit in IOC configuration register and wait for 1355 * the controller to become ready. 1356 * 1357 * Return: 0 on success, appropriate error on failure. 1358 */ 1359 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc) 1360 { 1361 u32 ioc_config, ioc_status, timeout, host_diagnostic; 1362 int retval = 0; 1363 enum mpi3mr_iocstate ioc_state; 1364 u64 base_info; 1365 1366 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1367 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1368 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information); 1369 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n", 1370 ioc_status, ioc_config, base_info); 1371 1372 /*The timeout value is in 2sec unit, changing it to seconds*/ 1373 mrioc->ready_timeout = 1374 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 1375 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 1376 1377 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout); 1378 1379 ioc_state = mpi3mr_get_iocstate(mrioc); 1380 ioc_info(mrioc, "controller is in %s state during detection\n", 1381 mpi3mr_iocstate_name(ioc_state)); 1382 1383 if (ioc_state == MRIOC_STATE_BECOMING_READY || 1384 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 1385 timeout = mrioc->ready_timeout * 10; 1386 do { 1387 msleep(100); 1388 } while (--timeout); 1389 1390 if (!pci_device_is_present(mrioc->pdev)) { 1391 mrioc->unrecoverable = 1; 1392 ioc_err(mrioc, 1393 "controller is not present while waiting to reset\n"); 1394 retval = -1; 1395 goto out_device_not_present; 1396 } 1397 1398 ioc_state = mpi3mr_get_iocstate(mrioc); 1399 ioc_info(mrioc, 1400 "controller is in %s state after waiting to reset\n", 1401 mpi3mr_iocstate_name(ioc_state)); 1402 } 1403 1404 if (ioc_state == MRIOC_STATE_READY) { 1405 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n"); 1406 retval = mpi3mr_issue_and_process_mur(mrioc, 1407 MPI3MR_RESET_FROM_BRINGUP); 1408 ioc_state = mpi3mr_get_iocstate(mrioc); 1409 if (retval) 1410 ioc_err(mrioc, 1411 "message unit reset failed with error %d current state %s\n", 1412 retval, mpi3mr_iocstate_name(ioc_state)); 1413 } 1414 if (ioc_state != MRIOC_STATE_RESET) { 1415 if (ioc_state == MRIOC_STATE_FAULT) { 1416 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 1417 mpi3mr_print_fault_info(mrioc); 1418 do { 1419 host_diagnostic = 1420 readl(&mrioc->sysif_regs->host_diagnostic); 1421 if (!(host_diagnostic & 1422 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 1423 break; 1424 if (!pci_device_is_present(mrioc->pdev)) { 1425 mrioc->unrecoverable = 1; 1426 ioc_err(mrioc, "controller is not present at the bringup\n"); 1427 goto out_device_not_present; 1428 } 1429 msleep(100); 1430 } while (--timeout); 1431 } 1432 mpi3mr_print_fault_info(mrioc); 1433 ioc_info(mrioc, "issuing soft reset to bring to reset state\n"); 1434 retval = mpi3mr_issue_reset(mrioc, 1435 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 1436 MPI3MR_RESET_FROM_BRINGUP); 1437 if (retval) { 1438 ioc_err(mrioc, 1439 "soft reset failed with error %d\n", retval); 1440 goto out_failed; 1441 } 1442 } 1443 ioc_state = mpi3mr_get_iocstate(mrioc); 1444 if (ioc_state != MRIOC_STATE_RESET) { 1445 ioc_err(mrioc, 1446 "cannot bring controller to reset state, current state: %s\n", 1447 mpi3mr_iocstate_name(ioc_state)); 1448 goto out_failed; 1449 } 1450 mpi3mr_clear_reset_history(mrioc); 1451 retval = mpi3mr_setup_admin_qpair(mrioc); 1452 if (retval) { 1453 ioc_err(mrioc, "failed to setup admin queues: error %d\n", 1454 retval); 1455 goto out_failed; 1456 } 1457 1458 ioc_info(mrioc, "bringing controller to ready state\n"); 1459 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1460 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1461 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1462 1463 timeout = mrioc->ready_timeout * 10; 1464 do { 1465 ioc_state = mpi3mr_get_iocstate(mrioc); 1466 if (ioc_state == MRIOC_STATE_READY) { 1467 ioc_info(mrioc, 1468 "successfully transitioned to %s state\n", 1469 mpi3mr_iocstate_name(ioc_state)); 1470 return 0; 1471 } 1472 if (!pci_device_is_present(mrioc->pdev)) { 1473 mrioc->unrecoverable = 1; 1474 ioc_err(mrioc, 1475 "controller is not present at the bringup\n"); 1476 retval = -1; 1477 goto out_device_not_present; 1478 } 1479 msleep(100); 1480 } while (--timeout); 1481 1482 out_failed: 1483 ioc_state = mpi3mr_get_iocstate(mrioc); 1484 ioc_err(mrioc, 1485 "failed to bring to ready state, current state: %s\n", 1486 mpi3mr_iocstate_name(ioc_state)); 1487 out_device_not_present: 1488 return retval; 1489 } 1490 1491 /** 1492 * mpi3mr_soft_reset_success - Check softreset is success or not 1493 * @ioc_status: IOC status register value 1494 * @ioc_config: IOC config register value 1495 * 1496 * Check whether the soft reset is successful or not based on 1497 * IOC status and IOC config register values. 1498 * 1499 * Return: True when the soft reset is success, false otherwise. 1500 */ 1501 static inline bool 1502 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config) 1503 { 1504 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1505 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1506 return true; 1507 return false; 1508 } 1509 1510 /** 1511 * mpi3mr_diagfault_success - Check diag fault is success or not 1512 * @mrioc: Adapter reference 1513 * @ioc_status: IOC status register value 1514 * 1515 * Check whether the controller hit diag reset fault code. 1516 * 1517 * Return: True when there is diag fault, false otherwise. 1518 */ 1519 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc, 1520 u32 ioc_status) 1521 { 1522 u32 fault; 1523 1524 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1525 return false; 1526 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 1527 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) { 1528 mpi3mr_print_fault_info(mrioc); 1529 return true; 1530 } 1531 return false; 1532 } 1533 1534 /** 1535 * mpi3mr_set_diagsave - Set diag save bit for snapdump 1536 * @mrioc: Adapter reference 1537 * 1538 * Set diag save bit in IOC configuration register to enable 1539 * snapdump. 1540 * 1541 * Return: Nothing. 1542 */ 1543 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) 1544 { 1545 u32 ioc_config; 1546 1547 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1548 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 1549 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1550 } 1551 1552 /** 1553 * mpi3mr_issue_reset - Issue reset to the controller 1554 * @mrioc: Adapter reference 1555 * @reset_type: Reset type 1556 * @reset_reason: Reset reason code 1557 * 1558 * Unlock the host diagnostic registers and write the specific 1559 * reset type to that, wait for reset acknowledgment from the 1560 * controller, if the reset is not successful retry for the 1561 * predefined number of times. 1562 * 1563 * Return: 0 on success, non-zero on failure. 1564 */ 1565 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, 1566 u16 reset_reason) 1567 { 1568 int retval = -1; 1569 u8 unlock_retry_count = 0; 1570 u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0; 1571 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1572 1573 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 1574 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 1575 return retval; 1576 if (mrioc->unrecoverable) 1577 return retval; 1578 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 1579 retval = 0; 1580 return retval; 1581 } 1582 1583 ioc_info(mrioc, "%s reset due to %s(0x%x)\n", 1584 mpi3mr_reset_type_name(reset_type), 1585 mpi3mr_reset_rc_name(reset_reason), reset_reason); 1586 1587 mpi3mr_clear_reset_history(mrioc); 1588 do { 1589 ioc_info(mrioc, 1590 "Write magic sequence to unlock host diag register (retry=%d)\n", 1591 ++unlock_retry_count); 1592 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 1593 ioc_err(mrioc, 1594 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n", 1595 mpi3mr_reset_type_name(reset_type), 1596 host_diagnostic); 1597 mrioc->unrecoverable = 1; 1598 return retval; 1599 } 1600 1601 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH, 1602 &mrioc->sysif_regs->write_sequence); 1603 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST, 1604 &mrioc->sysif_regs->write_sequence); 1605 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1606 &mrioc->sysif_regs->write_sequence); 1607 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD, 1608 &mrioc->sysif_regs->write_sequence); 1609 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH, 1610 &mrioc->sysif_regs->write_sequence); 1611 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH, 1612 &mrioc->sysif_regs->write_sequence); 1613 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH, 1614 &mrioc->sysif_regs->write_sequence); 1615 usleep_range(1000, 1100); 1616 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 1617 ioc_info(mrioc, 1618 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 1619 unlock_retry_count, host_diagnostic); 1620 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 1621 1622 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX << 1623 MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num << 1624 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason); 1625 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1626 writel(host_diagnostic | reset_type, 1627 &mrioc->sysif_regs->host_diagnostic); 1628 switch (reset_type) { 1629 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET: 1630 do { 1631 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1632 ioc_config = 1633 readl(&mrioc->sysif_regs->ioc_configuration); 1634 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1635 && mpi3mr_soft_reset_success(ioc_status, ioc_config) 1636 ) { 1637 mpi3mr_clear_reset_history(mrioc); 1638 retval = 0; 1639 break; 1640 } 1641 msleep(100); 1642 } while (--timeout); 1643 mpi3mr_print_fault_info(mrioc); 1644 break; 1645 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT: 1646 do { 1647 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1648 if (mpi3mr_diagfault_success(mrioc, ioc_status)) { 1649 retval = 0; 1650 break; 1651 } 1652 msleep(100); 1653 } while (--timeout); 1654 break; 1655 default: 1656 break; 1657 } 1658 1659 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1660 &mrioc->sysif_regs->write_sequence); 1661 1662 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1663 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1664 ioc_info(mrioc, 1665 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n", 1666 (!retval)?"successful":"failed", ioc_status, 1667 ioc_config); 1668 if (retval) 1669 mrioc->unrecoverable = 1; 1670 return retval; 1671 } 1672 1673 /** 1674 * mpi3mr_admin_request_post - Post request to admin queue 1675 * @mrioc: Adapter reference 1676 * @admin_req: MPI3 request 1677 * @admin_req_sz: Request size 1678 * @ignore_reset: Ignore reset in process 1679 * 1680 * Post the MPI3 request into admin request queue and 1681 * inform the controller, if the queue is full return 1682 * appropriate error. 1683 * 1684 * Return: 0 on success, non-zero on failure. 1685 */ 1686 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1687 u16 admin_req_sz, u8 ignore_reset) 1688 { 1689 u16 areq_pi = 0, areq_ci = 0, max_entries = 0; 1690 int retval = 0; 1691 unsigned long flags; 1692 u8 *areq_entry; 1693 1694 if (mrioc->unrecoverable) { 1695 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__); 1696 return -EFAULT; 1697 } 1698 1699 spin_lock_irqsave(&mrioc->admin_req_lock, flags); 1700 areq_pi = mrioc->admin_req_pi; 1701 areq_ci = mrioc->admin_req_ci; 1702 max_entries = mrioc->num_admin_req; 1703 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 1704 (areq_pi == (max_entries - 1)))) { 1705 ioc_err(mrioc, "AdminReqQ full condition detected\n"); 1706 retval = -EAGAIN; 1707 goto out; 1708 } 1709 if (!ignore_reset && mrioc->reset_in_progress) { 1710 ioc_err(mrioc, "AdminReqQ submit reset in progress\n"); 1711 retval = -EAGAIN; 1712 goto out; 1713 } 1714 if (mrioc->pci_err_recovery) { 1715 ioc_err(mrioc, "admin request queue submission failed due to pci error recovery in progress\n"); 1716 retval = -EAGAIN; 1717 goto out; 1718 } 1719 1720 areq_entry = (u8 *)mrioc->admin_req_base + 1721 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ); 1722 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ); 1723 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz); 1724 1725 if (++areq_pi == max_entries) 1726 areq_pi = 0; 1727 mrioc->admin_req_pi = areq_pi; 1728 1729 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 1730 1731 out: 1732 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags); 1733 1734 return retval; 1735 } 1736 1737 /** 1738 * mpi3mr_free_op_req_q_segments - free request memory segments 1739 * @mrioc: Adapter instance reference 1740 * @q_idx: operational request queue index 1741 * 1742 * Free memory segments allocated for operational request queue 1743 * 1744 * Return: Nothing. 1745 */ 1746 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1747 { 1748 u16 j; 1749 int size; 1750 struct segments *segments; 1751 1752 segments = mrioc->req_qinfo[q_idx].q_segments; 1753 if (!segments) 1754 return; 1755 1756 if (mrioc->enable_segqueue) { 1757 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1758 if (mrioc->req_qinfo[q_idx].q_segment_list) { 1759 dma_free_coherent(&mrioc->pdev->dev, 1760 MPI3MR_MAX_SEG_LIST_SIZE, 1761 mrioc->req_qinfo[q_idx].q_segment_list, 1762 mrioc->req_qinfo[q_idx].q_segment_list_dma); 1763 mrioc->req_qinfo[q_idx].q_segment_list = NULL; 1764 } 1765 } else 1766 size = mrioc->req_qinfo[q_idx].segment_qd * 1767 mrioc->facts.op_req_sz; 1768 1769 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) { 1770 if (!segments[j].segment) 1771 continue; 1772 dma_free_coherent(&mrioc->pdev->dev, 1773 size, segments[j].segment, segments[j].segment_dma); 1774 segments[j].segment = NULL; 1775 } 1776 kfree(mrioc->req_qinfo[q_idx].q_segments); 1777 mrioc->req_qinfo[q_idx].q_segments = NULL; 1778 mrioc->req_qinfo[q_idx].qid = 0; 1779 } 1780 1781 /** 1782 * mpi3mr_free_op_reply_q_segments - free reply memory segments 1783 * @mrioc: Adapter instance reference 1784 * @q_idx: operational reply queue index 1785 * 1786 * Free memory segments allocated for operational reply queue 1787 * 1788 * Return: Nothing. 1789 */ 1790 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1791 { 1792 u16 j; 1793 int size; 1794 struct segments *segments; 1795 1796 segments = mrioc->op_reply_qinfo[q_idx].q_segments; 1797 if (!segments) 1798 return; 1799 1800 if (mrioc->enable_segqueue) { 1801 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1802 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) { 1803 dma_free_coherent(&mrioc->pdev->dev, 1804 MPI3MR_MAX_SEG_LIST_SIZE, 1805 mrioc->op_reply_qinfo[q_idx].q_segment_list, 1806 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma); 1807 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 1808 } 1809 } else 1810 size = mrioc->op_reply_qinfo[q_idx].segment_qd * 1811 mrioc->op_reply_desc_sz; 1812 1813 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) { 1814 if (!segments[j].segment) 1815 continue; 1816 dma_free_coherent(&mrioc->pdev->dev, 1817 size, segments[j].segment, segments[j].segment_dma); 1818 segments[j].segment = NULL; 1819 } 1820 1821 kfree(mrioc->op_reply_qinfo[q_idx].q_segments); 1822 mrioc->op_reply_qinfo[q_idx].q_segments = NULL; 1823 mrioc->op_reply_qinfo[q_idx].qid = 0; 1824 } 1825 1826 /** 1827 * mpi3mr_delete_op_reply_q - delete operational reply queue 1828 * @mrioc: Adapter instance reference 1829 * @qidx: operational reply queue index 1830 * 1831 * Delete operatinal reply queue by issuing MPI request 1832 * through admin queue. 1833 * 1834 * Return: 0 on success, non-zero on failure. 1835 */ 1836 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1837 { 1838 struct mpi3_delete_reply_queue_request delq_req; 1839 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1840 int retval = 0; 1841 u16 reply_qid = 0, midx; 1842 1843 reply_qid = op_reply_q->qid; 1844 1845 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1846 1847 if (!reply_qid) { 1848 retval = -1; 1849 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n"); 1850 goto out; 1851 } 1852 1853 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- : 1854 mrioc->active_poll_qcount--; 1855 1856 memset(&delq_req, 0, sizeof(delq_req)); 1857 mutex_lock(&mrioc->init_cmds.mutex); 1858 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1859 retval = -1; 1860 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n"); 1861 mutex_unlock(&mrioc->init_cmds.mutex); 1862 goto out; 1863 } 1864 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1865 mrioc->init_cmds.is_waiting = 1; 1866 mrioc->init_cmds.callback = NULL; 1867 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1868 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 1869 delq_req.queue_id = cpu_to_le16(reply_qid); 1870 1871 init_completion(&mrioc->init_cmds.done); 1872 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req), 1873 1); 1874 if (retval) { 1875 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n"); 1876 goto out_unlock; 1877 } 1878 wait_for_completion_timeout(&mrioc->init_cmds.done, 1879 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1880 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1881 ioc_err(mrioc, "delete reply queue timed out\n"); 1882 mpi3mr_check_rh_fault_ioc(mrioc, 1883 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 1884 retval = -1; 1885 goto out_unlock; 1886 } 1887 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1888 != MPI3_IOCSTATUS_SUCCESS) { 1889 ioc_err(mrioc, 1890 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1891 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1892 mrioc->init_cmds.ioc_loginfo); 1893 retval = -1; 1894 goto out_unlock; 1895 } 1896 mrioc->intr_info[midx].op_reply_q = NULL; 1897 1898 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1899 out_unlock: 1900 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1901 mutex_unlock(&mrioc->init_cmds.mutex); 1902 out: 1903 1904 return retval; 1905 } 1906 1907 /** 1908 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool 1909 * @mrioc: Adapter instance reference 1910 * @qidx: request queue index 1911 * 1912 * Allocate segmented memory pools for operational reply 1913 * queue. 1914 * 1915 * Return: 0 on success, non-zero on failure. 1916 */ 1917 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1918 { 1919 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1920 int i, size; 1921 u64 *q_segment_list_entry = NULL; 1922 struct segments *segments; 1923 1924 if (mrioc->enable_segqueue) { 1925 op_reply_q->segment_qd = 1926 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz; 1927 1928 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1929 1930 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1931 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma, 1932 GFP_KERNEL); 1933 if (!op_reply_q->q_segment_list) 1934 return -ENOMEM; 1935 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list; 1936 } else { 1937 op_reply_q->segment_qd = op_reply_q->num_replies; 1938 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz; 1939 } 1940 1941 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies, 1942 op_reply_q->segment_qd); 1943 1944 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments, 1945 sizeof(struct segments), GFP_KERNEL); 1946 if (!op_reply_q->q_segments) 1947 return -ENOMEM; 1948 1949 segments = op_reply_q->q_segments; 1950 for (i = 0; i < op_reply_q->num_segments; i++) { 1951 segments[i].segment = 1952 dma_alloc_coherent(&mrioc->pdev->dev, 1953 size, &segments[i].segment_dma, GFP_KERNEL); 1954 if (!segments[i].segment) 1955 return -ENOMEM; 1956 if (mrioc->enable_segqueue) 1957 q_segment_list_entry[i] = 1958 (unsigned long)segments[i].segment_dma; 1959 } 1960 1961 return 0; 1962 } 1963 1964 /** 1965 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool. 1966 * @mrioc: Adapter instance reference 1967 * @qidx: request queue index 1968 * 1969 * Allocate segmented memory pools for operational request 1970 * queue. 1971 * 1972 * Return: 0 on success, non-zero on failure. 1973 */ 1974 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1975 { 1976 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 1977 int i, size; 1978 u64 *q_segment_list_entry = NULL; 1979 struct segments *segments; 1980 1981 if (mrioc->enable_segqueue) { 1982 op_req_q->segment_qd = 1983 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz; 1984 1985 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1986 1987 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1988 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma, 1989 GFP_KERNEL); 1990 if (!op_req_q->q_segment_list) 1991 return -ENOMEM; 1992 q_segment_list_entry = (u64 *)op_req_q->q_segment_list; 1993 1994 } else { 1995 op_req_q->segment_qd = op_req_q->num_requests; 1996 size = op_req_q->num_requests * mrioc->facts.op_req_sz; 1997 } 1998 1999 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests, 2000 op_req_q->segment_qd); 2001 2002 op_req_q->q_segments = kcalloc(op_req_q->num_segments, 2003 sizeof(struct segments), GFP_KERNEL); 2004 if (!op_req_q->q_segments) 2005 return -ENOMEM; 2006 2007 segments = op_req_q->q_segments; 2008 for (i = 0; i < op_req_q->num_segments; i++) { 2009 segments[i].segment = 2010 dma_alloc_coherent(&mrioc->pdev->dev, 2011 size, &segments[i].segment_dma, GFP_KERNEL); 2012 if (!segments[i].segment) 2013 return -ENOMEM; 2014 if (mrioc->enable_segqueue) 2015 q_segment_list_entry[i] = 2016 (unsigned long)segments[i].segment_dma; 2017 } 2018 2019 return 0; 2020 } 2021 2022 /** 2023 * mpi3mr_create_op_reply_q - create operational reply queue 2024 * @mrioc: Adapter instance reference 2025 * @qidx: operational reply queue index 2026 * 2027 * Create operatinal reply queue by issuing MPI request 2028 * through admin queue. 2029 * 2030 * Return: 0 on success, non-zero on failure. 2031 */ 2032 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 2033 { 2034 struct mpi3_create_reply_queue_request create_req; 2035 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 2036 int retval = 0; 2037 u16 reply_qid = 0, midx; 2038 2039 reply_qid = op_reply_q->qid; 2040 2041 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 2042 2043 if (reply_qid) { 2044 retval = -1; 2045 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n", 2046 reply_qid); 2047 2048 return retval; 2049 } 2050 2051 reply_qid = qidx + 1; 2052 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 2053 if ((mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) && 2054 !mrioc->pdev->revision) 2055 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K; 2056 op_reply_q->ci = 0; 2057 op_reply_q->ephase = 1; 2058 atomic_set(&op_reply_q->pend_ios, 0); 2059 atomic_set(&op_reply_q->in_use, 0); 2060 op_reply_q->enable_irq_poll = false; 2061 2062 if (!op_reply_q->q_segments) { 2063 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx); 2064 if (retval) { 2065 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 2066 goto out; 2067 } 2068 } 2069 2070 memset(&create_req, 0, sizeof(create_req)); 2071 mutex_lock(&mrioc->init_cmds.mutex); 2072 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2073 retval = -1; 2074 ioc_err(mrioc, "CreateRepQ: Init command is in use\n"); 2075 goto out_unlock; 2076 } 2077 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2078 mrioc->init_cmds.is_waiting = 1; 2079 mrioc->init_cmds.callback = NULL; 2080 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2081 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 2082 create_req.queue_id = cpu_to_le16(reply_qid); 2083 2084 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount)) 2085 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE; 2086 else 2087 op_reply_q->qtype = MPI3MR_POLL_QUEUE; 2088 2089 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) { 2090 create_req.flags = 2091 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 2092 create_req.msix_index = 2093 cpu_to_le16(mrioc->intr_info[midx].msix_index); 2094 } else { 2095 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1); 2096 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n", 2097 reply_qid, midx); 2098 if (!mrioc->active_poll_qcount) 2099 disable_irq_nosync(pci_irq_vector(mrioc->pdev, 2100 mrioc->intr_info_count - 1)); 2101 } 2102 2103 if (mrioc->enable_segqueue) { 2104 create_req.flags |= 2105 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2106 create_req.base_address = cpu_to_le64( 2107 op_reply_q->q_segment_list_dma); 2108 } else 2109 create_req.base_address = cpu_to_le64( 2110 op_reply_q->q_segments[0].segment_dma); 2111 2112 create_req.size = cpu_to_le16(op_reply_q->num_replies); 2113 2114 init_completion(&mrioc->init_cmds.done); 2115 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2116 sizeof(create_req), 1); 2117 if (retval) { 2118 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n"); 2119 goto out_unlock; 2120 } 2121 wait_for_completion_timeout(&mrioc->init_cmds.done, 2122 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2123 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2124 ioc_err(mrioc, "create reply queue timed out\n"); 2125 mpi3mr_check_rh_fault_ioc(mrioc, 2126 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 2127 retval = -1; 2128 goto out_unlock; 2129 } 2130 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2131 != MPI3_IOCSTATUS_SUCCESS) { 2132 ioc_err(mrioc, 2133 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2134 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2135 mrioc->init_cmds.ioc_loginfo); 2136 retval = -1; 2137 goto out_unlock; 2138 } 2139 op_reply_q->qid = reply_qid; 2140 if (midx < mrioc->intr_info_count) 2141 mrioc->intr_info[midx].op_reply_q = op_reply_q; 2142 2143 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ : 2144 mrioc->active_poll_qcount++; 2145 2146 out_unlock: 2147 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2148 mutex_unlock(&mrioc->init_cmds.mutex); 2149 out: 2150 2151 return retval; 2152 } 2153 2154 /** 2155 * mpi3mr_create_op_req_q - create operational request queue 2156 * @mrioc: Adapter instance reference 2157 * @idx: operational request queue index 2158 * @reply_qid: Reply queue ID 2159 * 2160 * Create operatinal request queue by issuing MPI request 2161 * through admin queue. 2162 * 2163 * Return: 0 on success, non-zero on failure. 2164 */ 2165 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, 2166 u16 reply_qid) 2167 { 2168 struct mpi3_create_request_queue_request create_req; 2169 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx; 2170 int retval = 0; 2171 u16 req_qid = 0; 2172 2173 req_qid = op_req_q->qid; 2174 2175 if (req_qid) { 2176 retval = -1; 2177 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n", 2178 req_qid); 2179 2180 return retval; 2181 } 2182 req_qid = idx + 1; 2183 2184 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD; 2185 op_req_q->ci = 0; 2186 op_req_q->pi = 0; 2187 op_req_q->reply_qid = reply_qid; 2188 spin_lock_init(&op_req_q->q_lock); 2189 2190 if (!op_req_q->q_segments) { 2191 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx); 2192 if (retval) { 2193 mpi3mr_free_op_req_q_segments(mrioc, idx); 2194 goto out; 2195 } 2196 } 2197 2198 memset(&create_req, 0, sizeof(create_req)); 2199 mutex_lock(&mrioc->init_cmds.mutex); 2200 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2201 retval = -1; 2202 ioc_err(mrioc, "CreateReqQ: Init command is in use\n"); 2203 goto out_unlock; 2204 } 2205 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2206 mrioc->init_cmds.is_waiting = 1; 2207 mrioc->init_cmds.callback = NULL; 2208 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2209 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 2210 create_req.queue_id = cpu_to_le16(req_qid); 2211 if (mrioc->enable_segqueue) { 2212 create_req.flags = 2213 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2214 create_req.base_address = cpu_to_le64( 2215 op_req_q->q_segment_list_dma); 2216 } else 2217 create_req.base_address = cpu_to_le64( 2218 op_req_q->q_segments[0].segment_dma); 2219 create_req.reply_queue_id = cpu_to_le16(reply_qid); 2220 create_req.size = cpu_to_le16(op_req_q->num_requests); 2221 2222 init_completion(&mrioc->init_cmds.done); 2223 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2224 sizeof(create_req), 1); 2225 if (retval) { 2226 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n"); 2227 goto out_unlock; 2228 } 2229 wait_for_completion_timeout(&mrioc->init_cmds.done, 2230 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2231 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2232 ioc_err(mrioc, "create request queue timed out\n"); 2233 mpi3mr_check_rh_fault_ioc(mrioc, 2234 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 2235 retval = -1; 2236 goto out_unlock; 2237 } 2238 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2239 != MPI3_IOCSTATUS_SUCCESS) { 2240 ioc_err(mrioc, 2241 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2242 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2243 mrioc->init_cmds.ioc_loginfo); 2244 retval = -1; 2245 goto out_unlock; 2246 } 2247 op_req_q->qid = req_qid; 2248 2249 out_unlock: 2250 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2251 mutex_unlock(&mrioc->init_cmds.mutex); 2252 out: 2253 2254 return retval; 2255 } 2256 2257 /** 2258 * mpi3mr_create_op_queues - create operational queue pairs 2259 * @mrioc: Adapter instance reference 2260 * 2261 * Allocate memory for operational queue meta data and call 2262 * create request and reply queue functions. 2263 * 2264 * Return: 0 on success, non-zero on failures. 2265 */ 2266 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) 2267 { 2268 int retval = 0; 2269 u16 num_queues = 0, i = 0, msix_count_op_q = 1; 2270 2271 num_queues = min_t(int, mrioc->facts.max_op_reply_q, 2272 mrioc->facts.max_op_req_q); 2273 2274 msix_count_op_q = 2275 mrioc->intr_info_count - mrioc->op_reply_q_offset; 2276 if (!mrioc->num_queues) 2277 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q); 2278 /* 2279 * During reset set the num_queues to the number of queues 2280 * that was set before the reset. 2281 */ 2282 num_queues = mrioc->num_op_reply_q ? 2283 mrioc->num_op_reply_q : mrioc->num_queues; 2284 ioc_info(mrioc, "trying to create %d operational queue pairs\n", 2285 num_queues); 2286 2287 if (!mrioc->req_qinfo) { 2288 mrioc->req_qinfo = kcalloc(num_queues, 2289 sizeof(struct op_req_qinfo), GFP_KERNEL); 2290 if (!mrioc->req_qinfo) { 2291 retval = -1; 2292 goto out_failed; 2293 } 2294 2295 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) * 2296 num_queues, GFP_KERNEL); 2297 if (!mrioc->op_reply_qinfo) { 2298 retval = -1; 2299 goto out_failed; 2300 } 2301 } 2302 2303 if (mrioc->enable_segqueue) 2304 ioc_info(mrioc, 2305 "allocating operational queues through segmented queues\n"); 2306 2307 for (i = 0; i < num_queues; i++) { 2308 if (mpi3mr_create_op_reply_q(mrioc, i)) { 2309 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i); 2310 break; 2311 } 2312 if (mpi3mr_create_op_req_q(mrioc, i, 2313 mrioc->op_reply_qinfo[i].qid)) { 2314 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i); 2315 mpi3mr_delete_op_reply_q(mrioc, i); 2316 break; 2317 } 2318 } 2319 2320 if (i == 0) { 2321 /* Not even one queue is created successfully*/ 2322 retval = -1; 2323 goto out_failed; 2324 } 2325 mrioc->num_op_reply_q = mrioc->num_op_req_q = i; 2326 ioc_info(mrioc, 2327 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n", 2328 mrioc->num_op_reply_q, mrioc->default_qcount, 2329 mrioc->active_poll_qcount); 2330 2331 return retval; 2332 out_failed: 2333 kfree(mrioc->req_qinfo); 2334 mrioc->req_qinfo = NULL; 2335 2336 kfree(mrioc->op_reply_qinfo); 2337 mrioc->op_reply_qinfo = NULL; 2338 2339 return retval; 2340 } 2341 2342 /** 2343 * mpi3mr_op_request_post - Post request to operational queue 2344 * @mrioc: Adapter reference 2345 * @op_req_q: Operational request queue info 2346 * @req: MPI3 request 2347 * 2348 * Post the MPI3 request into operational request queue and 2349 * inform the controller, if the queue is full return 2350 * appropriate error. 2351 * 2352 * Return: 0 on success, non-zero on failure. 2353 */ 2354 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 2355 struct op_req_qinfo *op_req_q, u8 *req) 2356 { 2357 u16 pi = 0, max_entries, reply_qidx = 0, midx; 2358 int retval = 0; 2359 unsigned long flags; 2360 u8 *req_entry; 2361 void *segment_base_addr; 2362 u16 req_sz = mrioc->facts.op_req_sz; 2363 struct segments *segments = op_req_q->q_segments; 2364 2365 reply_qidx = op_req_q->reply_qid - 1; 2366 2367 if (mrioc->unrecoverable) 2368 return -EFAULT; 2369 2370 spin_lock_irqsave(&op_req_q->q_lock, flags); 2371 pi = op_req_q->pi; 2372 max_entries = op_req_q->num_requests; 2373 2374 if (mpi3mr_check_req_qfull(op_req_q)) { 2375 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX( 2376 reply_qidx, mrioc->op_reply_q_offset); 2377 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q); 2378 2379 if (mpi3mr_check_req_qfull(op_req_q)) { 2380 retval = -EAGAIN; 2381 goto out; 2382 } 2383 } 2384 2385 if (mrioc->reset_in_progress) { 2386 ioc_err(mrioc, "OpReqQ submit reset in progress\n"); 2387 retval = -EAGAIN; 2388 goto out; 2389 } 2390 if (mrioc->pci_err_recovery) { 2391 ioc_err(mrioc, "operational request queue submission failed due to pci error recovery in progress\n"); 2392 retval = -EAGAIN; 2393 goto out; 2394 } 2395 2396 segment_base_addr = segments[pi / op_req_q->segment_qd].segment; 2397 req_entry = (u8 *)segment_base_addr + 2398 ((pi % op_req_q->segment_qd) * req_sz); 2399 2400 memset(req_entry, 0, req_sz); 2401 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ); 2402 2403 if (++pi == max_entries) 2404 pi = 0; 2405 op_req_q->pi = pi; 2406 2407 #ifndef CONFIG_PREEMPT_RT 2408 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) 2409 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) 2410 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; 2411 #else 2412 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios); 2413 #endif 2414 2415 writel(op_req_q->pi, 2416 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index); 2417 2418 out: 2419 spin_unlock_irqrestore(&op_req_q->q_lock, flags); 2420 return retval; 2421 } 2422 2423 /** 2424 * mpi3mr_check_rh_fault_ioc - check reset history and fault 2425 * controller 2426 * @mrioc: Adapter instance reference 2427 * @reason_code: reason code for the fault. 2428 * 2429 * This routine will save snapdump and fault the controller with 2430 * the given reason code if it is not already in the fault or 2431 * not asynchronosuly reset. This will be used to handle 2432 * initilaization time faults/resets/timeout as in those cases 2433 * immediate soft reset invocation is not required. 2434 * 2435 * Return: None. 2436 */ 2437 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code) 2438 { 2439 u32 ioc_status, host_diagnostic, timeout; 2440 union mpi3mr_trigger_data trigger_data; 2441 2442 if (mrioc->unrecoverable) { 2443 ioc_err(mrioc, "controller is unrecoverable\n"); 2444 return; 2445 } 2446 2447 if (!pci_device_is_present(mrioc->pdev)) { 2448 mrioc->unrecoverable = 1; 2449 ioc_err(mrioc, "controller is not present\n"); 2450 return; 2451 } 2452 memset(&trigger_data, 0, sizeof(trigger_data)); 2453 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2454 2455 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2456 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2457 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0); 2458 return; 2459 } else if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 2460 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) & 2461 MPI3_SYSIF_FAULT_CODE_MASK); 2462 2463 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2464 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0); 2465 mpi3mr_print_fault_info(mrioc); 2466 return; 2467 } 2468 2469 mpi3mr_set_diagsave(mrioc); 2470 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2471 reason_code); 2472 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) & 2473 MPI3_SYSIF_FAULT_CODE_MASK); 2474 mpi3mr_set_trigger_data_in_all_hdb(mrioc, MPI3MR_HDB_TRIGGER_TYPE_FAULT, 2475 &trigger_data, 0); 2476 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 2477 do { 2478 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2479 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 2480 break; 2481 msleep(100); 2482 } while (--timeout); 2483 } 2484 2485 /** 2486 * mpi3mr_sync_timestamp - Issue time stamp sync request 2487 * @mrioc: Adapter reference 2488 * 2489 * Issue IO unit control MPI request to synchornize firmware 2490 * timestamp with host time. 2491 * 2492 * Return: 0 on success, non-zero on failure. 2493 */ 2494 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc) 2495 { 2496 ktime_t current_time; 2497 struct mpi3_iounit_control_request iou_ctrl; 2498 int retval = 0; 2499 2500 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 2501 mutex_lock(&mrioc->init_cmds.mutex); 2502 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2503 retval = -1; 2504 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n"); 2505 mutex_unlock(&mrioc->init_cmds.mutex); 2506 goto out; 2507 } 2508 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2509 mrioc->init_cmds.is_waiting = 1; 2510 mrioc->init_cmds.callback = NULL; 2511 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2512 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL; 2513 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP; 2514 current_time = ktime_get_real(); 2515 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time)); 2516 2517 init_completion(&mrioc->init_cmds.done); 2518 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl, 2519 sizeof(iou_ctrl), 0); 2520 if (retval) { 2521 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n"); 2522 goto out_unlock; 2523 } 2524 2525 wait_for_completion_timeout(&mrioc->init_cmds.done, 2526 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2527 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2528 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n"); 2529 mrioc->init_cmds.is_waiting = 0; 2530 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 2531 mpi3mr_check_rh_fault_ioc(mrioc, 2532 MPI3MR_RESET_FROM_TSU_TIMEOUT); 2533 retval = -1; 2534 goto out_unlock; 2535 } 2536 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2537 != MPI3_IOCSTATUS_SUCCESS) { 2538 ioc_err(mrioc, 2539 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2540 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2541 mrioc->init_cmds.ioc_loginfo); 2542 retval = -1; 2543 goto out_unlock; 2544 } 2545 2546 out_unlock: 2547 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2548 mutex_unlock(&mrioc->init_cmds.mutex); 2549 2550 out: 2551 return retval; 2552 } 2553 2554 /** 2555 * mpi3mr_print_pkg_ver - display controller fw package version 2556 * @mrioc: Adapter reference 2557 * 2558 * Retrieve firmware package version from the component image 2559 * header of the controller flash and display it. 2560 * 2561 * Return: 0 on success and non-zero on failure. 2562 */ 2563 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc) 2564 { 2565 struct mpi3_ci_upload_request ci_upload; 2566 int retval = -1; 2567 void *data = NULL; 2568 dma_addr_t data_dma; 2569 struct mpi3_ci_manifest_mpi *manifest; 2570 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi); 2571 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2572 2573 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2574 GFP_KERNEL); 2575 if (!data) 2576 return -ENOMEM; 2577 2578 memset(&ci_upload, 0, sizeof(ci_upload)); 2579 mutex_lock(&mrioc->init_cmds.mutex); 2580 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2581 ioc_err(mrioc, "sending get package version failed due to command in use\n"); 2582 mutex_unlock(&mrioc->init_cmds.mutex); 2583 goto out; 2584 } 2585 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2586 mrioc->init_cmds.is_waiting = 1; 2587 mrioc->init_cmds.callback = NULL; 2588 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2589 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD; 2590 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 2591 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST); 2592 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE); 2593 ci_upload.segment_size = cpu_to_le32(data_len); 2594 2595 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len, 2596 data_dma); 2597 init_completion(&mrioc->init_cmds.done); 2598 retval = mpi3mr_admin_request_post(mrioc, &ci_upload, 2599 sizeof(ci_upload), 1); 2600 if (retval) { 2601 ioc_err(mrioc, "posting get package version failed\n"); 2602 goto out_unlock; 2603 } 2604 wait_for_completion_timeout(&mrioc->init_cmds.done, 2605 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2606 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2607 ioc_err(mrioc, "get package version timed out\n"); 2608 mpi3mr_check_rh_fault_ioc(mrioc, 2609 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2610 retval = -1; 2611 goto out_unlock; 2612 } 2613 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2614 == MPI3_IOCSTATUS_SUCCESS) { 2615 manifest = (struct mpi3_ci_manifest_mpi *) data; 2616 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) { 2617 ioc_info(mrioc, 2618 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n", 2619 manifest->package_version.gen_major, 2620 manifest->package_version.gen_minor, 2621 manifest->package_version.phase_major, 2622 manifest->package_version.phase_minor, 2623 manifest->package_version.customer_id, 2624 manifest->package_version.build_num); 2625 } 2626 } 2627 retval = 0; 2628 out_unlock: 2629 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2630 mutex_unlock(&mrioc->init_cmds.mutex); 2631 2632 out: 2633 if (data) 2634 dma_free_coherent(&mrioc->pdev->dev, data_len, data, 2635 data_dma); 2636 return retval; 2637 } 2638 2639 /** 2640 * mpi3mr_watchdog_work - watchdog thread to monitor faults 2641 * @work: work struct 2642 * 2643 * Watch dog work periodically executed (1 second interval) to 2644 * monitor firmware fault and to issue periodic timer sync to 2645 * the firmware. 2646 * 2647 * Return: Nothing. 2648 */ 2649 static void mpi3mr_watchdog_work(struct work_struct *work) 2650 { 2651 struct mpi3mr_ioc *mrioc = 2652 container_of(work, struct mpi3mr_ioc, watchdog_work.work); 2653 unsigned long flags; 2654 enum mpi3mr_iocstate ioc_state; 2655 u32 host_diagnostic, ioc_status; 2656 union mpi3mr_trigger_data trigger_data; 2657 u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH; 2658 2659 if (mrioc->reset_in_progress || mrioc->pci_err_recovery) 2660 return; 2661 2662 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) { 2663 ioc_err(mrioc, "watchdog could not detect the controller\n"); 2664 mrioc->unrecoverable = 1; 2665 } 2666 2667 if (mrioc->unrecoverable) { 2668 ioc_err(mrioc, 2669 "flush pending commands for unrecoverable controller\n"); 2670 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 2671 return; 2672 } 2673 2674 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) { 2675 mrioc->ts_update_counter = 0; 2676 mpi3mr_sync_timestamp(mrioc); 2677 } 2678 2679 if ((mrioc->prepare_for_reset) && 2680 ((mrioc->prepare_for_reset_timeout_counter++) >= 2681 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 2682 mpi3mr_soft_reset_handler(mrioc, 2683 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 2684 return; 2685 } 2686 2687 memset(&trigger_data, 0, sizeof(trigger_data)); 2688 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2689 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2690 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2691 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0); 2692 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0); 2693 return; 2694 } 2695 2696 /*Check for fault state every one second and issue Soft reset*/ 2697 ioc_state = mpi3mr_get_iocstate(mrioc); 2698 if (ioc_state != MRIOC_STATE_FAULT) 2699 goto schedule_work; 2700 2701 trigger_data.fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 2702 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2703 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0); 2704 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2705 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 2706 if (!mrioc->diagsave_timeout) { 2707 mpi3mr_print_fault_info(mrioc); 2708 ioc_warn(mrioc, "diag save in progress\n"); 2709 } 2710 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 2711 goto schedule_work; 2712 } 2713 2714 mpi3mr_print_fault_info(mrioc); 2715 mrioc->diagsave_timeout = 0; 2716 2717 switch (trigger_data.fault) { 2718 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED: 2719 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED: 2720 ioc_warn(mrioc, 2721 "controller requires system power cycle, marking controller as unrecoverable\n"); 2722 mrioc->unrecoverable = 1; 2723 goto schedule_work; 2724 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS: 2725 goto schedule_work; 2726 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET: 2727 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT; 2728 break; 2729 default: 2730 break; 2731 } 2732 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0); 2733 return; 2734 2735 schedule_work: 2736 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2737 if (mrioc->watchdog_work_q) 2738 queue_delayed_work(mrioc->watchdog_work_q, 2739 &mrioc->watchdog_work, 2740 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2741 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2742 return; 2743 } 2744 2745 /** 2746 * mpi3mr_start_watchdog - Start watchdog 2747 * @mrioc: Adapter instance reference 2748 * 2749 * Create and start the watchdog thread to monitor controller 2750 * faults. 2751 * 2752 * Return: Nothing. 2753 */ 2754 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc) 2755 { 2756 if (mrioc->watchdog_work_q) 2757 return; 2758 2759 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work); 2760 snprintf(mrioc->watchdog_work_q_name, 2761 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name, 2762 mrioc->id); 2763 mrioc->watchdog_work_q = alloc_ordered_workqueue( 2764 "%s", WQ_MEM_RECLAIM, mrioc->watchdog_work_q_name); 2765 if (!mrioc->watchdog_work_q) { 2766 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__); 2767 return; 2768 } 2769 2770 if (mrioc->watchdog_work_q) 2771 queue_delayed_work(mrioc->watchdog_work_q, 2772 &mrioc->watchdog_work, 2773 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2774 } 2775 2776 /** 2777 * mpi3mr_stop_watchdog - Stop watchdog 2778 * @mrioc: Adapter instance reference 2779 * 2780 * Stop the watchdog thread created to monitor controller 2781 * faults. 2782 * 2783 * Return: Nothing. 2784 */ 2785 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) 2786 { 2787 unsigned long flags; 2788 struct workqueue_struct *wq; 2789 2790 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2791 wq = mrioc->watchdog_work_q; 2792 mrioc->watchdog_work_q = NULL; 2793 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2794 if (wq) { 2795 if (!cancel_delayed_work_sync(&mrioc->watchdog_work)) 2796 flush_workqueue(wq); 2797 destroy_workqueue(wq); 2798 } 2799 } 2800 2801 /** 2802 * mpi3mr_setup_admin_qpair - Setup admin queue pair 2803 * @mrioc: Adapter instance reference 2804 * 2805 * Allocate memory for admin queue pair if required and register 2806 * the admin queue with the controller. 2807 * 2808 * Return: 0 on success, non-zero on failures. 2809 */ 2810 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc) 2811 { 2812 int retval = 0; 2813 u32 num_admin_entries = 0; 2814 2815 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE; 2816 mrioc->num_admin_req = mrioc->admin_req_q_sz / 2817 MPI3MR_ADMIN_REQ_FRAME_SZ; 2818 mrioc->admin_req_ci = mrioc->admin_req_pi = 0; 2819 2820 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE; 2821 mrioc->num_admin_replies = mrioc->admin_reply_q_sz / 2822 MPI3MR_ADMIN_REPLY_FRAME_SZ; 2823 mrioc->admin_reply_ci = 0; 2824 mrioc->admin_reply_ephase = 1; 2825 atomic_set(&mrioc->admin_reply_q_in_use, 0); 2826 2827 if (!mrioc->admin_req_base) { 2828 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev, 2829 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL); 2830 2831 if (!mrioc->admin_req_base) { 2832 retval = -1; 2833 goto out_failed; 2834 } 2835 2836 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev, 2837 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma, 2838 GFP_KERNEL); 2839 2840 if (!mrioc->admin_reply_base) { 2841 retval = -1; 2842 goto out_failed; 2843 } 2844 } 2845 2846 num_admin_entries = (mrioc->num_admin_replies << 16) | 2847 (mrioc->num_admin_req); 2848 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); 2849 mpi3mr_writeq(mrioc->admin_req_dma, 2850 &mrioc->sysif_regs->admin_request_queue_address); 2851 mpi3mr_writeq(mrioc->admin_reply_dma, 2852 &mrioc->sysif_regs->admin_reply_queue_address); 2853 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 2854 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 2855 return retval; 2856 2857 out_failed: 2858 2859 if (mrioc->admin_reply_base) { 2860 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 2861 mrioc->admin_reply_base, mrioc->admin_reply_dma); 2862 mrioc->admin_reply_base = NULL; 2863 } 2864 if (mrioc->admin_req_base) { 2865 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 2866 mrioc->admin_req_base, mrioc->admin_req_dma); 2867 mrioc->admin_req_base = NULL; 2868 } 2869 return retval; 2870 } 2871 2872 /** 2873 * mpi3mr_issue_iocfacts - Send IOC Facts 2874 * @mrioc: Adapter instance reference 2875 * @facts_data: Cached IOC facts data 2876 * 2877 * Issue IOC Facts MPI request through admin queue and wait for 2878 * the completion of it or time out. 2879 * 2880 * Return: 0 on success, non-zero on failures. 2881 */ 2882 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, 2883 struct mpi3_ioc_facts_data *facts_data) 2884 { 2885 struct mpi3_ioc_facts_request iocfacts_req; 2886 void *data = NULL; 2887 dma_addr_t data_dma; 2888 u32 data_len = sizeof(*facts_data); 2889 int retval = 0; 2890 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2891 2892 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2893 GFP_KERNEL); 2894 2895 if (!data) { 2896 retval = -1; 2897 goto out; 2898 } 2899 2900 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 2901 mutex_lock(&mrioc->init_cmds.mutex); 2902 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2903 retval = -1; 2904 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n"); 2905 mutex_unlock(&mrioc->init_cmds.mutex); 2906 goto out; 2907 } 2908 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2909 mrioc->init_cmds.is_waiting = 1; 2910 mrioc->init_cmds.callback = NULL; 2911 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2912 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS; 2913 2914 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len, 2915 data_dma); 2916 2917 init_completion(&mrioc->init_cmds.done); 2918 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req, 2919 sizeof(iocfacts_req), 1); 2920 if (retval) { 2921 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n"); 2922 goto out_unlock; 2923 } 2924 wait_for_completion_timeout(&mrioc->init_cmds.done, 2925 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2926 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2927 ioc_err(mrioc, "ioc_facts timed out\n"); 2928 mpi3mr_check_rh_fault_ioc(mrioc, 2929 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 2930 retval = -1; 2931 goto out_unlock; 2932 } 2933 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2934 != MPI3_IOCSTATUS_SUCCESS) { 2935 ioc_err(mrioc, 2936 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2937 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2938 mrioc->init_cmds.ioc_loginfo); 2939 retval = -1; 2940 goto out_unlock; 2941 } 2942 memcpy(facts_data, (u8 *)data, data_len); 2943 mpi3mr_process_factsdata(mrioc, facts_data); 2944 out_unlock: 2945 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2946 mutex_unlock(&mrioc->init_cmds.mutex); 2947 2948 out: 2949 if (data) 2950 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma); 2951 2952 return retval; 2953 } 2954 2955 /** 2956 * mpi3mr_check_reset_dma_mask - Process IOC facts data 2957 * @mrioc: Adapter instance reference 2958 * 2959 * Check whether the new DMA mask requested through IOCFacts by 2960 * firmware needs to be set, if so set it . 2961 * 2962 * Return: 0 on success, non-zero on failure. 2963 */ 2964 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc) 2965 { 2966 struct pci_dev *pdev = mrioc->pdev; 2967 int r; 2968 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask); 2969 2970 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask)) 2971 return 0; 2972 2973 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n", 2974 mrioc->dma_mask, facts_dma_mask); 2975 2976 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask); 2977 if (r) { 2978 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n", 2979 facts_dma_mask, r); 2980 return r; 2981 } 2982 mrioc->dma_mask = facts_dma_mask; 2983 return r; 2984 } 2985 2986 /** 2987 * mpi3mr_process_factsdata - Process IOC facts data 2988 * @mrioc: Adapter instance reference 2989 * @facts_data: Cached IOC facts data 2990 * 2991 * Convert IOC facts data into cpu endianness and cache it in 2992 * the driver . 2993 * 2994 * Return: Nothing. 2995 */ 2996 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 2997 struct mpi3_ioc_facts_data *facts_data) 2998 { 2999 u32 ioc_config, req_sz, facts_flags; 3000 3001 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) != 3002 (sizeof(*facts_data) / 4)) { 3003 ioc_warn(mrioc, 3004 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n", 3005 sizeof(*facts_data), 3006 le16_to_cpu(facts_data->ioc_facts_data_length) * 4); 3007 } 3008 3009 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 3010 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 3011 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 3012 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) { 3013 ioc_err(mrioc, 3014 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n", 3015 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size)); 3016 } 3017 3018 memset(&mrioc->facts, 0, sizeof(mrioc->facts)); 3019 3020 facts_flags = le32_to_cpu(facts_data->flags); 3021 mrioc->facts.op_req_sz = req_sz; 3022 mrioc->op_reply_desc_sz = 1 << ((ioc_config & 3023 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 3024 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 3025 3026 mrioc->facts.ioc_num = facts_data->ioc_number; 3027 mrioc->facts.who_init = facts_data->who_init; 3028 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors); 3029 mrioc->facts.personality = (facts_flags & 3030 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 3031 mrioc->facts.dma_mask = (facts_flags & 3032 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 3033 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 3034 mrioc->facts.protocol_flags = facts_data->protocol_flags; 3035 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word); 3036 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests); 3037 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id); 3038 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; 3039 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); 3040 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); 3041 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); 3042 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); 3043 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds); 3044 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds); 3045 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); 3046 mrioc->facts.max_pcie_switches = 3047 le16_to_cpu(facts_data->max_pcie_switches); 3048 mrioc->facts.max_sasexpanders = 3049 le16_to_cpu(facts_data->max_sas_expanders); 3050 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length); 3051 mrioc->facts.max_sasinitiators = 3052 le16_to_cpu(facts_data->max_sas_initiators); 3053 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures); 3054 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle); 3055 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle); 3056 mrioc->facts.max_op_req_q = 3057 le16_to_cpu(facts_data->max_operational_request_queues); 3058 mrioc->facts.max_op_reply_q = 3059 le16_to_cpu(facts_data->max_operational_reply_queues); 3060 mrioc->facts.ioc_capabilities = 3061 le32_to_cpu(facts_data->ioc_capabilities); 3062 mrioc->facts.fw_ver.build_num = 3063 le16_to_cpu(facts_data->fw_version.build_num); 3064 mrioc->facts.fw_ver.cust_id = 3065 le16_to_cpu(facts_data->fw_version.customer_id); 3066 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor; 3067 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major; 3068 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor; 3069 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major; 3070 mrioc->msix_count = min_t(int, mrioc->msix_count, 3071 mrioc->facts.max_msix_vectors); 3072 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask; 3073 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value; 3074 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift; 3075 mrioc->facts.shutdown_timeout = 3076 le16_to_cpu(facts_data->shutdown_timeout); 3077 mrioc->facts.diag_trace_sz = 3078 le32_to_cpu(facts_data->diag_trace_size); 3079 mrioc->facts.diag_fw_sz = 3080 le32_to_cpu(facts_data->diag_fw_size); 3081 mrioc->facts.diag_drvr_sz = le32_to_cpu(facts_data->diag_driver_size); 3082 mrioc->facts.max_dev_per_tg = 3083 facts_data->max_devices_per_throttle_group; 3084 mrioc->facts.io_throttle_data_length = 3085 le16_to_cpu(facts_data->io_throttle_data_length); 3086 mrioc->facts.max_io_throttle_group = 3087 le16_to_cpu(facts_data->max_io_throttle_group); 3088 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low); 3089 mrioc->facts.io_throttle_high = 3090 le16_to_cpu(facts_data->io_throttle_high); 3091 3092 if (mrioc->facts.max_data_length == 3093 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED) 3094 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE; 3095 else 3096 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K; 3097 /* Store in 512b block count */ 3098 if (mrioc->facts.io_throttle_data_length) 3099 mrioc->io_throttle_data_length = 3100 (mrioc->facts.io_throttle_data_length * 2 * 4); 3101 else 3102 /* set the length to 1MB + 1K to disable throttle */ 3103 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2; 3104 3105 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024); 3106 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024); 3107 3108 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),", 3109 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, 3110 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); 3111 ioc_info(mrioc, 3112 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n", 3113 mrioc->facts.max_reqs, mrioc->facts.min_devhandle, 3114 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids); 3115 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", 3116 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, 3117 mrioc->facts.sge_mod_shift); 3118 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n", 3119 mrioc->facts.dma_mask, (facts_flags & 3120 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length); 3121 ioc_info(mrioc, 3122 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n", 3123 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group); 3124 ioc_info(mrioc, 3125 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n", 3126 mrioc->facts.io_throttle_data_length * 4, 3127 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low); 3128 } 3129 3130 /** 3131 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init 3132 * @mrioc: Adapter instance reference 3133 * 3134 * Allocate and initialize the reply free buffers, sense 3135 * buffers, reply free queue and sense buffer queue. 3136 * 3137 * Return: 0 on success, non-zero on failures. 3138 */ 3139 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) 3140 { 3141 int retval = 0; 3142 u32 sz, i; 3143 3144 if (mrioc->init_cmds.reply) 3145 return retval; 3146 3147 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3148 if (!mrioc->init_cmds.reply) 3149 goto out_failed; 3150 3151 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3152 if (!mrioc->bsg_cmds.reply) 3153 goto out_failed; 3154 3155 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3156 if (!mrioc->transport_cmds.reply) 3157 goto out_failed; 3158 3159 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 3160 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz, 3161 GFP_KERNEL); 3162 if (!mrioc->dev_rmhs_cmds[i].reply) 3163 goto out_failed; 3164 } 3165 3166 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 3167 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz, 3168 GFP_KERNEL); 3169 if (!mrioc->evtack_cmds[i].reply) 3170 goto out_failed; 3171 } 3172 3173 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3174 if (!mrioc->host_tm_cmds.reply) 3175 goto out_failed; 3176 3177 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3178 if (!mrioc->pel_cmds.reply) 3179 goto out_failed; 3180 3181 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3182 if (!mrioc->pel_abort_cmd.reply) 3183 goto out_failed; 3184 3185 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 3186 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits, 3187 GFP_KERNEL); 3188 if (!mrioc->removepend_bitmap) 3189 goto out_failed; 3190 3191 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL); 3192 if (!mrioc->devrem_bitmap) 3193 goto out_failed; 3194 3195 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD, 3196 GFP_KERNEL); 3197 if (!mrioc->evtack_cmds_bitmap) 3198 goto out_failed; 3199 3200 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES; 3201 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1; 3202 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 3203 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1; 3204 3205 /* reply buffer pool, 16 byte align */ 3206 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3207 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool", 3208 &mrioc->pdev->dev, sz, 16, 0); 3209 if (!mrioc->reply_buf_pool) { 3210 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n"); 3211 goto out_failed; 3212 } 3213 3214 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL, 3215 &mrioc->reply_buf_dma); 3216 if (!mrioc->reply_buf) 3217 goto out_failed; 3218 3219 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz; 3220 3221 /* reply free queue, 8 byte align */ 3222 sz = mrioc->reply_free_qsz * 8; 3223 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool", 3224 &mrioc->pdev->dev, sz, 8, 0); 3225 if (!mrioc->reply_free_q_pool) { 3226 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n"); 3227 goto out_failed; 3228 } 3229 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool, 3230 GFP_KERNEL, &mrioc->reply_free_q_dma); 3231 if (!mrioc->reply_free_q) 3232 goto out_failed; 3233 3234 /* sense buffer pool, 4 byte align */ 3235 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3236 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", 3237 &mrioc->pdev->dev, sz, 4, 0); 3238 if (!mrioc->sense_buf_pool) { 3239 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n"); 3240 goto out_failed; 3241 } 3242 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL, 3243 &mrioc->sense_buf_dma); 3244 if (!mrioc->sense_buf) 3245 goto out_failed; 3246 3247 /* sense buffer queue, 8 byte align */ 3248 sz = mrioc->sense_buf_q_sz * 8; 3249 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool", 3250 &mrioc->pdev->dev, sz, 8, 0); 3251 if (!mrioc->sense_buf_q_pool) { 3252 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n"); 3253 goto out_failed; 3254 } 3255 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool, 3256 GFP_KERNEL, &mrioc->sense_buf_q_dma); 3257 if (!mrioc->sense_buf_q) 3258 goto out_failed; 3259 3260 return retval; 3261 3262 out_failed: 3263 retval = -1; 3264 return retval; 3265 } 3266 3267 /** 3268 * mpimr_initialize_reply_sbuf_queues - initialize reply sense 3269 * buffers 3270 * @mrioc: Adapter instance reference 3271 * 3272 * Helper function to initialize reply and sense buffers along 3273 * with some debug prints. 3274 * 3275 * Return: None. 3276 */ 3277 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc) 3278 { 3279 u32 sz, i; 3280 dma_addr_t phy_addr; 3281 3282 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3283 ioc_info(mrioc, 3284 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3285 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz, 3286 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma); 3287 sz = mrioc->reply_free_qsz * 8; 3288 ioc_info(mrioc, 3289 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3290 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), 3291 (unsigned long long)mrioc->reply_free_q_dma); 3292 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3293 ioc_info(mrioc, 3294 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3295 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ, 3296 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma); 3297 sz = mrioc->sense_buf_q_sz * 8; 3298 ioc_info(mrioc, 3299 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3300 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024), 3301 (unsigned long long)mrioc->sense_buf_q_dma); 3302 3303 /* initialize Reply buffer Queue */ 3304 for (i = 0, phy_addr = mrioc->reply_buf_dma; 3305 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz) 3306 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr); 3307 mrioc->reply_free_q[i] = cpu_to_le64(0); 3308 3309 /* initialize Sense Buffer Queue */ 3310 for (i = 0, phy_addr = mrioc->sense_buf_dma; 3311 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ) 3312 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); 3313 mrioc->sense_buf_q[i] = cpu_to_le64(0); 3314 } 3315 3316 /** 3317 * mpi3mr_issue_iocinit - Send IOC Init 3318 * @mrioc: Adapter instance reference 3319 * 3320 * Issue IOC Init MPI request through admin queue and wait for 3321 * the completion of it or time out. 3322 * 3323 * Return: 0 on success, non-zero on failures. 3324 */ 3325 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) 3326 { 3327 struct mpi3_ioc_init_request iocinit_req; 3328 struct mpi3_driver_info_layout *drv_info; 3329 dma_addr_t data_dma; 3330 u32 data_len = sizeof(*drv_info); 3331 int retval = 0; 3332 ktime_t current_time; 3333 3334 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 3335 GFP_KERNEL); 3336 if (!drv_info) { 3337 retval = -1; 3338 goto out; 3339 } 3340 mpimr_initialize_reply_sbuf_queues(mrioc); 3341 3342 drv_info->information_length = cpu_to_le32(data_len); 3343 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature)); 3344 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name)); 3345 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version)); 3346 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name)); 3347 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version)); 3348 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE, 3349 sizeof(drv_info->driver_release_date)); 3350 drv_info->driver_capabilities = 0; 3351 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info, 3352 sizeof(mrioc->driver_info)); 3353 3354 memset(&iocinit_req, 0, sizeof(iocinit_req)); 3355 mutex_lock(&mrioc->init_cmds.mutex); 3356 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3357 retval = -1; 3358 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n"); 3359 mutex_unlock(&mrioc->init_cmds.mutex); 3360 goto out; 3361 } 3362 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3363 mrioc->init_cmds.is_waiting = 1; 3364 mrioc->init_cmds.callback = NULL; 3365 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3366 iocinit_req.function = MPI3_FUNCTION_IOC_INIT; 3367 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV; 3368 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT; 3369 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR; 3370 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR; 3371 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER; 3372 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); 3373 iocinit_req.reply_free_queue_address = 3374 cpu_to_le64(mrioc->reply_free_q_dma); 3375 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ); 3376 iocinit_req.sense_buffer_free_queue_depth = 3377 cpu_to_le16(mrioc->sense_buf_q_sz); 3378 iocinit_req.sense_buffer_free_queue_address = 3379 cpu_to_le64(mrioc->sense_buf_q_dma); 3380 iocinit_req.driver_information_address = cpu_to_le64(data_dma); 3381 3382 current_time = ktime_get_real(); 3383 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time)); 3384 3385 iocinit_req.msg_flags |= 3386 MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED; 3387 iocinit_req.msg_flags |= 3388 MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED; 3389 3390 init_completion(&mrioc->init_cmds.done); 3391 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, 3392 sizeof(iocinit_req), 1); 3393 if (retval) { 3394 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n"); 3395 goto out_unlock; 3396 } 3397 wait_for_completion_timeout(&mrioc->init_cmds.done, 3398 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3399 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3400 mpi3mr_check_rh_fault_ioc(mrioc, 3401 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 3402 ioc_err(mrioc, "ioc_init timed out\n"); 3403 retval = -1; 3404 goto out_unlock; 3405 } 3406 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3407 != MPI3_IOCSTATUS_SUCCESS) { 3408 ioc_err(mrioc, 3409 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3410 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3411 mrioc->init_cmds.ioc_loginfo); 3412 retval = -1; 3413 goto out_unlock; 3414 } 3415 3416 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs; 3417 writel(mrioc->reply_free_queue_host_index, 3418 &mrioc->sysif_regs->reply_free_host_index); 3419 3420 mrioc->sbq_host_index = mrioc->num_sense_bufs; 3421 writel(mrioc->sbq_host_index, 3422 &mrioc->sysif_regs->sense_buffer_free_host_index); 3423 out_unlock: 3424 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3425 mutex_unlock(&mrioc->init_cmds.mutex); 3426 3427 out: 3428 if (drv_info) 3429 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info, 3430 data_dma); 3431 3432 return retval; 3433 } 3434 3435 /** 3436 * mpi3mr_unmask_events - Unmask events in event mask bitmap 3437 * @mrioc: Adapter instance reference 3438 * @event: MPI event ID 3439 * 3440 * Un mask the specific event by resetting the event_mask 3441 * bitmap. 3442 * 3443 * Return: 0 on success, non-zero on failures. 3444 */ 3445 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event) 3446 { 3447 u32 desired_event; 3448 u8 word; 3449 3450 if (event >= 128) 3451 return; 3452 3453 desired_event = (1 << (event % 32)); 3454 word = event / 32; 3455 3456 mrioc->event_masks[word] &= ~desired_event; 3457 } 3458 3459 /** 3460 * mpi3mr_issue_event_notification - Send event notification 3461 * @mrioc: Adapter instance reference 3462 * 3463 * Issue event notification MPI request through admin queue and 3464 * wait for the completion of it or time out. 3465 * 3466 * Return: 0 on success, non-zero on failures. 3467 */ 3468 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) 3469 { 3470 struct mpi3_event_notification_request evtnotify_req; 3471 int retval = 0; 3472 u8 i; 3473 3474 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 3475 mutex_lock(&mrioc->init_cmds.mutex); 3476 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3477 retval = -1; 3478 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n"); 3479 mutex_unlock(&mrioc->init_cmds.mutex); 3480 goto out; 3481 } 3482 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3483 mrioc->init_cmds.is_waiting = 1; 3484 mrioc->init_cmds.callback = NULL; 3485 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3486 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION; 3487 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3488 evtnotify_req.event_masks[i] = 3489 cpu_to_le32(mrioc->event_masks[i]); 3490 init_completion(&mrioc->init_cmds.done); 3491 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req, 3492 sizeof(evtnotify_req), 1); 3493 if (retval) { 3494 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n"); 3495 goto out_unlock; 3496 } 3497 wait_for_completion_timeout(&mrioc->init_cmds.done, 3498 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3499 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3500 ioc_err(mrioc, "event notification timed out\n"); 3501 mpi3mr_check_rh_fault_ioc(mrioc, 3502 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 3503 retval = -1; 3504 goto out_unlock; 3505 } 3506 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3507 != MPI3_IOCSTATUS_SUCCESS) { 3508 ioc_err(mrioc, 3509 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3510 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3511 mrioc->init_cmds.ioc_loginfo); 3512 retval = -1; 3513 goto out_unlock; 3514 } 3515 3516 out_unlock: 3517 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3518 mutex_unlock(&mrioc->init_cmds.mutex); 3519 out: 3520 return retval; 3521 } 3522 3523 /** 3524 * mpi3mr_process_event_ack - Process event acknowledgment 3525 * @mrioc: Adapter instance reference 3526 * @event: MPI3 event ID 3527 * @event_ctx: event context 3528 * 3529 * Send event acknowledgment through admin queue and wait for 3530 * it to complete. 3531 * 3532 * Return: 0 on success, non-zero on failures. 3533 */ 3534 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 3535 u32 event_ctx) 3536 { 3537 struct mpi3_event_ack_request evtack_req; 3538 int retval = 0; 3539 3540 memset(&evtack_req, 0, sizeof(evtack_req)); 3541 mutex_lock(&mrioc->init_cmds.mutex); 3542 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3543 retval = -1; 3544 ioc_err(mrioc, "Send EvtAck: Init command is in use\n"); 3545 mutex_unlock(&mrioc->init_cmds.mutex); 3546 goto out; 3547 } 3548 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3549 mrioc->init_cmds.is_waiting = 1; 3550 mrioc->init_cmds.callback = NULL; 3551 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3552 evtack_req.function = MPI3_FUNCTION_EVENT_ACK; 3553 evtack_req.event = event; 3554 evtack_req.event_context = cpu_to_le32(event_ctx); 3555 3556 init_completion(&mrioc->init_cmds.done); 3557 retval = mpi3mr_admin_request_post(mrioc, &evtack_req, 3558 sizeof(evtack_req), 1); 3559 if (retval) { 3560 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n"); 3561 goto out_unlock; 3562 } 3563 wait_for_completion_timeout(&mrioc->init_cmds.done, 3564 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3565 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3566 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 3567 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 3568 mpi3mr_check_rh_fault_ioc(mrioc, 3569 MPI3MR_RESET_FROM_EVTACK_TIMEOUT); 3570 retval = -1; 3571 goto out_unlock; 3572 } 3573 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3574 != MPI3_IOCSTATUS_SUCCESS) { 3575 ioc_err(mrioc, 3576 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3577 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3578 mrioc->init_cmds.ioc_loginfo); 3579 retval = -1; 3580 goto out_unlock; 3581 } 3582 3583 out_unlock: 3584 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3585 mutex_unlock(&mrioc->init_cmds.mutex); 3586 out: 3587 return retval; 3588 } 3589 3590 /** 3591 * mpi3mr_alloc_chain_bufs - Allocate chain buffers 3592 * @mrioc: Adapter instance reference 3593 * 3594 * Allocate chain buffers and set a bitmap to indicate free 3595 * chain buffers. Chain buffers are used to pass the SGE 3596 * information along with MPI3 SCSI IO requests for host I/O. 3597 * 3598 * Return: 0 on success, non-zero on failure 3599 */ 3600 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) 3601 { 3602 int retval = 0; 3603 u32 sz, i; 3604 u16 num_chains; 3605 3606 if (mrioc->chain_sgl_list) 3607 return retval; 3608 3609 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR; 3610 3611 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION 3612 | SHOST_DIX_TYPE1_PROTECTION 3613 | SHOST_DIX_TYPE2_PROTECTION 3614 | SHOST_DIX_TYPE3_PROTECTION)) 3615 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR); 3616 3617 mrioc->chain_buf_count = num_chains; 3618 sz = sizeof(struct chain_element) * num_chains; 3619 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL); 3620 if (!mrioc->chain_sgl_list) 3621 goto out_failed; 3622 3623 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length / 3624 MPI3MR_PAGE_SIZE_4K)) 3625 mrioc->max_sgl_entries = mrioc->facts.max_data_length / 3626 MPI3MR_PAGE_SIZE_4K; 3627 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common); 3628 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n", 3629 mrioc->max_sgl_entries, sz/1024); 3630 3631 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool", 3632 &mrioc->pdev->dev, sz, 16, 0); 3633 if (!mrioc->chain_buf_pool) { 3634 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n"); 3635 goto out_failed; 3636 } 3637 3638 for (i = 0; i < num_chains; i++) { 3639 mrioc->chain_sgl_list[i].addr = 3640 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL, 3641 &mrioc->chain_sgl_list[i].dma_addr); 3642 3643 if (!mrioc->chain_sgl_list[i].addr) 3644 goto out_failed; 3645 } 3646 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL); 3647 if (!mrioc->chain_bitmap) 3648 goto out_failed; 3649 return retval; 3650 out_failed: 3651 retval = -1; 3652 return retval; 3653 } 3654 3655 /** 3656 * mpi3mr_port_enable_complete - Mark port enable complete 3657 * @mrioc: Adapter instance reference 3658 * @drv_cmd: Internal command tracker 3659 * 3660 * Call back for asynchronous port enable request sets the 3661 * driver command to indicate port enable request is complete. 3662 * 3663 * Return: Nothing 3664 */ 3665 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc, 3666 struct mpi3mr_drv_cmd *drv_cmd) 3667 { 3668 drv_cmd->callback = NULL; 3669 mrioc->scan_started = 0; 3670 if (drv_cmd->state & MPI3MR_CMD_RESET) 3671 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR; 3672 else 3673 mrioc->scan_failed = drv_cmd->ioc_status; 3674 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3675 } 3676 3677 /** 3678 * mpi3mr_issue_port_enable - Issue Port Enable 3679 * @mrioc: Adapter instance reference 3680 * @async: Flag to wait for completion or not 3681 * 3682 * Issue Port Enable MPI request through admin queue and if the 3683 * async flag is not set wait for the completion of the port 3684 * enable or time out. 3685 * 3686 * Return: 0 on success, non-zero on failures. 3687 */ 3688 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) 3689 { 3690 struct mpi3_port_enable_request pe_req; 3691 int retval = 0; 3692 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT; 3693 3694 memset(&pe_req, 0, sizeof(pe_req)); 3695 mutex_lock(&mrioc->init_cmds.mutex); 3696 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3697 retval = -1; 3698 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n"); 3699 mutex_unlock(&mrioc->init_cmds.mutex); 3700 goto out; 3701 } 3702 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3703 if (async) { 3704 mrioc->init_cmds.is_waiting = 0; 3705 mrioc->init_cmds.callback = mpi3mr_port_enable_complete; 3706 } else { 3707 mrioc->init_cmds.is_waiting = 1; 3708 mrioc->init_cmds.callback = NULL; 3709 init_completion(&mrioc->init_cmds.done); 3710 } 3711 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3712 pe_req.function = MPI3_FUNCTION_PORT_ENABLE; 3713 3714 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1); 3715 if (retval) { 3716 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n"); 3717 goto out_unlock; 3718 } 3719 if (async) { 3720 mutex_unlock(&mrioc->init_cmds.mutex); 3721 goto out; 3722 } 3723 3724 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ)); 3725 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3726 ioc_err(mrioc, "port enable timed out\n"); 3727 retval = -1; 3728 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3729 goto out_unlock; 3730 } 3731 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds); 3732 3733 out_unlock: 3734 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3735 mutex_unlock(&mrioc->init_cmds.mutex); 3736 out: 3737 return retval; 3738 } 3739 3740 /* Protocol type to name mapper structure */ 3741 static const struct { 3742 u8 protocol; 3743 char *name; 3744 } mpi3mr_protocols[] = { 3745 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" }, 3746 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" }, 3747 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" }, 3748 }; 3749 3750 /* Capability to name mapper structure*/ 3751 static const struct { 3752 u32 capability; 3753 char *name; 3754 } mpi3mr_capabilities[] = { 3755 { MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" }, 3756 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" }, 3757 }; 3758 3759 /** 3760 * mpi3mr_repost_diag_bufs - repost host diag buffers 3761 * @mrioc: Adapter instance reference 3762 * 3763 * repost firmware and trace diag buffers based on global 3764 * trigger flag from driver page 2 3765 * 3766 * Return: 0 on success, non-zero on failures. 3767 */ 3768 static int mpi3mr_repost_diag_bufs(struct mpi3mr_ioc *mrioc) 3769 { 3770 u64 global_trigger; 3771 union mpi3mr_trigger_data prev_trigger_data; 3772 struct diag_buffer_desc *trace_hdb = NULL; 3773 struct diag_buffer_desc *fw_hdb = NULL; 3774 int retval = 0; 3775 bool trace_repost_needed = false; 3776 bool fw_repost_needed = false; 3777 u8 prev_trigger_type; 3778 3779 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT); 3780 if (retval) 3781 return -1; 3782 3783 trace_hdb = mpi3mr_diag_buffer_for_type(mrioc, 3784 MPI3_DIAG_BUFFER_TYPE_TRACE); 3785 3786 if (trace_hdb && 3787 trace_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED && 3788 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL && 3789 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT) 3790 trace_repost_needed = true; 3791 3792 fw_hdb = mpi3mr_diag_buffer_for_type(mrioc, MPI3_DIAG_BUFFER_TYPE_FW); 3793 3794 if (fw_hdb && fw_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED && 3795 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL && 3796 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT) 3797 fw_repost_needed = true; 3798 3799 if (trace_repost_needed || fw_repost_needed) { 3800 global_trigger = le64_to_cpu(mrioc->driver_pg2->global_trigger); 3801 if (global_trigger & 3802 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED) 3803 trace_repost_needed = false; 3804 if (global_trigger & 3805 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED) 3806 fw_repost_needed = false; 3807 } 3808 3809 if (trace_repost_needed) { 3810 prev_trigger_type = trace_hdb->trigger_type; 3811 memcpy(&prev_trigger_data, &trace_hdb->trigger_data, 3812 sizeof(trace_hdb->trigger_data)); 3813 retval = mpi3mr_issue_diag_buf_post(mrioc, trace_hdb); 3814 if (!retval) { 3815 dprint_init(mrioc, "trace diag buffer reposted"); 3816 mpi3mr_set_trigger_data_in_hdb(trace_hdb, 3817 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1); 3818 } else { 3819 trace_hdb->trigger_type = prev_trigger_type; 3820 memcpy(&trace_hdb->trigger_data, &prev_trigger_data, 3821 sizeof(prev_trigger_data)); 3822 ioc_err(mrioc, "trace diag buffer repost failed"); 3823 return -1; 3824 } 3825 } 3826 3827 if (fw_repost_needed) { 3828 prev_trigger_type = fw_hdb->trigger_type; 3829 memcpy(&prev_trigger_data, &fw_hdb->trigger_data, 3830 sizeof(fw_hdb->trigger_data)); 3831 retval = mpi3mr_issue_diag_buf_post(mrioc, fw_hdb); 3832 if (!retval) { 3833 dprint_init(mrioc, "firmware diag buffer reposted"); 3834 mpi3mr_set_trigger_data_in_hdb(fw_hdb, 3835 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1); 3836 } else { 3837 fw_hdb->trigger_type = prev_trigger_type; 3838 memcpy(&fw_hdb->trigger_data, &prev_trigger_data, 3839 sizeof(prev_trigger_data)); 3840 ioc_err(mrioc, "firmware diag buffer repost failed"); 3841 return -1; 3842 } 3843 } 3844 return retval; 3845 } 3846 3847 /** 3848 * mpi3mr_print_ioc_info - Display controller information 3849 * @mrioc: Adapter instance reference 3850 * 3851 * Display controller personality, capability, supported 3852 * protocols etc. 3853 * 3854 * Return: Nothing 3855 */ 3856 static void 3857 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc) 3858 { 3859 int i = 0, bytes_written = 0; 3860 const char *personality; 3861 char protocol[50] = {0}; 3862 char capabilities[100] = {0}; 3863 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver; 3864 3865 switch (mrioc->facts.personality) { 3866 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 3867 personality = "Enhanced HBA"; 3868 break; 3869 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 3870 personality = "RAID"; 3871 break; 3872 default: 3873 personality = "Unknown"; 3874 break; 3875 } 3876 3877 ioc_info(mrioc, "Running in %s Personality", personality); 3878 3879 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n", 3880 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 3881 fwver->ph_minor, fwver->cust_id, fwver->build_num); 3882 3883 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) { 3884 if (mrioc->facts.protocol_flags & 3885 mpi3mr_protocols[i].protocol) { 3886 bytes_written += scnprintf(protocol + bytes_written, 3887 sizeof(protocol) - bytes_written, "%s%s", 3888 bytes_written ? "," : "", 3889 mpi3mr_protocols[i].name); 3890 } 3891 } 3892 3893 bytes_written = 0; 3894 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) { 3895 if (mrioc->facts.protocol_flags & 3896 mpi3mr_capabilities[i].capability) { 3897 bytes_written += scnprintf(capabilities + bytes_written, 3898 sizeof(capabilities) - bytes_written, "%s%s", 3899 bytes_written ? "," : "", 3900 mpi3mr_capabilities[i].name); 3901 } 3902 } 3903 3904 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n", 3905 protocol, capabilities); 3906 } 3907 3908 /** 3909 * mpi3mr_cleanup_resources - Free PCI resources 3910 * @mrioc: Adapter instance reference 3911 * 3912 * Unmap PCI device memory and disable PCI device. 3913 * 3914 * Return: 0 on success and non-zero on failure. 3915 */ 3916 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc) 3917 { 3918 struct pci_dev *pdev = mrioc->pdev; 3919 3920 mpi3mr_cleanup_isr(mrioc); 3921 3922 if (mrioc->sysif_regs) { 3923 iounmap((void __iomem *)mrioc->sysif_regs); 3924 mrioc->sysif_regs = NULL; 3925 } 3926 3927 if (pci_is_enabled(pdev)) { 3928 if (mrioc->bars) 3929 pci_release_selected_regions(pdev, mrioc->bars); 3930 pci_disable_device(pdev); 3931 } 3932 } 3933 3934 /** 3935 * mpi3mr_setup_resources - Enable PCI resources 3936 * @mrioc: Adapter instance reference 3937 * 3938 * Enable PCI device memory, MSI-x registers and set DMA mask. 3939 * 3940 * Return: 0 on success and non-zero on failure. 3941 */ 3942 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) 3943 { 3944 struct pci_dev *pdev = mrioc->pdev; 3945 u32 memap_sz = 0; 3946 int i, retval = 0, capb = 0; 3947 u16 message_control; 3948 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask : 3949 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); 3950 3951 if (pci_enable_device_mem(pdev)) { 3952 ioc_err(mrioc, "pci_enable_device_mem: failed\n"); 3953 retval = -ENODEV; 3954 goto out_failed; 3955 } 3956 3957 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 3958 if (!capb) { 3959 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n"); 3960 retval = -ENODEV; 3961 goto out_failed; 3962 } 3963 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 3964 3965 if (pci_request_selected_regions(pdev, mrioc->bars, 3966 mrioc->driver_name)) { 3967 ioc_err(mrioc, "pci_request_selected_regions: failed\n"); 3968 retval = -ENODEV; 3969 goto out_failed; 3970 } 3971 3972 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) { 3973 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 3974 mrioc->sysif_regs_phys = pci_resource_start(pdev, i); 3975 memap_sz = pci_resource_len(pdev, i); 3976 mrioc->sysif_regs = 3977 ioremap(mrioc->sysif_regs_phys, memap_sz); 3978 break; 3979 } 3980 } 3981 3982 pci_set_master(pdev); 3983 3984 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 3985 if (retval) { 3986 if (dma_mask != DMA_BIT_MASK(32)) { 3987 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n"); 3988 dma_mask = DMA_BIT_MASK(32); 3989 retval = dma_set_mask_and_coherent(&pdev->dev, 3990 dma_mask); 3991 } 3992 if (retval) { 3993 mrioc->dma_mask = 0; 3994 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n"); 3995 goto out_failed; 3996 } 3997 } 3998 mrioc->dma_mask = dma_mask; 3999 4000 if (!mrioc->sysif_regs) { 4001 ioc_err(mrioc, 4002 "Unable to map adapter memory or resource not found\n"); 4003 retval = -EINVAL; 4004 goto out_failed; 4005 } 4006 4007 pci_read_config_word(pdev, capb + 2, &message_control); 4008 mrioc->msix_count = (message_control & 0x3FF) + 1; 4009 4010 pci_save_state(pdev); 4011 4012 pci_set_drvdata(pdev, mrioc->shost); 4013 4014 mpi3mr_ioc_disable_intr(mrioc); 4015 4016 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 4017 (unsigned long long)mrioc->sysif_regs_phys, 4018 mrioc->sysif_regs, memap_sz); 4019 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n", 4020 mrioc->msix_count); 4021 4022 if (!reset_devices && poll_queues > 0) 4023 mrioc->requested_poll_qcount = min_t(int, poll_queues, 4024 mrioc->msix_count - 2); 4025 return retval; 4026 4027 out_failed: 4028 mpi3mr_cleanup_resources(mrioc); 4029 return retval; 4030 } 4031 4032 /** 4033 * mpi3mr_enable_events - Enable required events 4034 * @mrioc: Adapter instance reference 4035 * 4036 * This routine unmasks the events required by the driver by 4037 * sennding appropriate event mask bitmapt through an event 4038 * notification request. 4039 * 4040 * Return: 0 on success and non-zero on failure. 4041 */ 4042 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc) 4043 { 4044 int retval = 0; 4045 u32 i; 4046 4047 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4048 mrioc->event_masks[i] = -1; 4049 4050 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED); 4051 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED); 4052 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 4053 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 4054 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED); 4055 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 4056 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY); 4057 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 4058 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 4059 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 4060 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION); 4061 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET); 4062 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT); 4063 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE); 4064 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE); 4065 4066 retval = mpi3mr_issue_event_notification(mrioc); 4067 if (retval) 4068 ioc_err(mrioc, "failed to issue event notification %d\n", 4069 retval); 4070 return retval; 4071 } 4072 4073 /** 4074 * mpi3mr_init_ioc - Initialize the controller 4075 * @mrioc: Adapter instance reference 4076 * 4077 * This the controller initialization routine, executed either 4078 * after soft reset or from pci probe callback. 4079 * Setup the required resources, memory map the controller 4080 * registers, create admin and operational reply queue pairs, 4081 * allocate required memory for reply pool, sense buffer pool, 4082 * issue IOC init request to the firmware, unmask the events and 4083 * issue port enable to discover SAS/SATA/NVMe devies and RAID 4084 * volumes. 4085 * 4086 * Return: 0 on success and non-zero on failure. 4087 */ 4088 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) 4089 { 4090 int retval = 0; 4091 u8 retry = 0; 4092 struct mpi3_ioc_facts_data facts_data; 4093 u32 sz; 4094 4095 retry_init: 4096 retval = mpi3mr_bring_ioc_ready(mrioc); 4097 if (retval) { 4098 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n", 4099 retval); 4100 goto out_failed_noretry; 4101 } 4102 4103 retval = mpi3mr_setup_isr(mrioc, 1); 4104 if (retval) { 4105 ioc_err(mrioc, "Failed to setup ISR error %d\n", 4106 retval); 4107 goto out_failed_noretry; 4108 } 4109 4110 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 4111 if (retval) { 4112 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n", 4113 retval); 4114 goto out_failed; 4115 } 4116 4117 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD; 4118 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512; 4119 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group; 4120 atomic_set(&mrioc->pend_large_data_sz, 0); 4121 4122 if (reset_devices) 4123 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios, 4124 MPI3MR_HOST_IOS_KDUMP); 4125 4126 if (!(mrioc->facts.ioc_capabilities & 4127 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) { 4128 mrioc->sas_transport_enabled = 1; 4129 mrioc->scsi_device_channel = 1; 4130 mrioc->shost->max_channel = 1; 4131 mrioc->shost->transportt = mpi3mr_transport_template; 4132 } 4133 4134 mrioc->reply_sz = mrioc->facts.reply_sz; 4135 4136 retval = mpi3mr_check_reset_dma_mask(mrioc); 4137 if (retval) { 4138 ioc_err(mrioc, "Resetting dma mask failed %d\n", 4139 retval); 4140 goto out_failed_noretry; 4141 } 4142 4143 mpi3mr_print_ioc_info(mrioc); 4144 4145 if (!mrioc->cfg_page) { 4146 dprint_init(mrioc, "allocating config page buffers\n"); 4147 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ; 4148 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev, 4149 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL); 4150 if (!mrioc->cfg_page) { 4151 retval = -1; 4152 goto out_failed_noretry; 4153 } 4154 } 4155 4156 dprint_init(mrioc, "allocating host diag buffers\n"); 4157 mpi3mr_alloc_diag_bufs(mrioc); 4158 4159 dprint_init(mrioc, "allocating ioctl dma buffers\n"); 4160 mpi3mr_alloc_ioctl_dma_memory(mrioc); 4161 4162 dprint_init(mrioc, "posting host diag buffers\n"); 4163 retval = mpi3mr_post_diag_bufs(mrioc); 4164 4165 if (retval) 4166 ioc_warn(mrioc, "failed to post host diag buffers\n"); 4167 4168 if (!mrioc->init_cmds.reply) { 4169 retval = mpi3mr_alloc_reply_sense_bufs(mrioc); 4170 if (retval) { 4171 ioc_err(mrioc, 4172 "%s :Failed to allocated reply sense buffers %d\n", 4173 __func__, retval); 4174 goto out_failed_noretry; 4175 } 4176 } 4177 4178 if (!mrioc->chain_sgl_list) { 4179 retval = mpi3mr_alloc_chain_bufs(mrioc); 4180 if (retval) { 4181 ioc_err(mrioc, "Failed to allocated chain buffers %d\n", 4182 retval); 4183 goto out_failed_noretry; 4184 } 4185 } 4186 4187 retval = mpi3mr_issue_iocinit(mrioc); 4188 if (retval) { 4189 ioc_err(mrioc, "Failed to Issue IOC Init %d\n", 4190 retval); 4191 goto out_failed; 4192 } 4193 4194 retval = mpi3mr_print_pkg_ver(mrioc); 4195 if (retval) { 4196 ioc_err(mrioc, "failed to get package version\n"); 4197 goto out_failed; 4198 } 4199 4200 retval = mpi3mr_setup_isr(mrioc, 0); 4201 if (retval) { 4202 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n", 4203 retval); 4204 goto out_failed_noretry; 4205 } 4206 4207 retval = mpi3mr_create_op_queues(mrioc); 4208 if (retval) { 4209 ioc_err(mrioc, "Failed to create OpQueues error %d\n", 4210 retval); 4211 goto out_failed; 4212 } 4213 4214 if (!mrioc->pel_seqnum_virt) { 4215 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n"); 4216 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4217 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4218 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4219 GFP_KERNEL); 4220 if (!mrioc->pel_seqnum_virt) { 4221 retval = -ENOMEM; 4222 goto out_failed_noretry; 4223 } 4224 } 4225 4226 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) { 4227 dprint_init(mrioc, "allocating memory for throttle groups\n"); 4228 sz = sizeof(struct mpi3mr_throttle_group_info); 4229 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL); 4230 if (!mrioc->throttle_groups) { 4231 retval = -1; 4232 goto out_failed_noretry; 4233 } 4234 } 4235 4236 retval = mpi3mr_enable_events(mrioc); 4237 if (retval) { 4238 ioc_err(mrioc, "failed to enable events %d\n", 4239 retval); 4240 goto out_failed; 4241 } 4242 4243 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT); 4244 if (retval) { 4245 ioc_err(mrioc, "failed to refresh triggers\n"); 4246 goto out_failed; 4247 } 4248 4249 ioc_info(mrioc, "controller initialization completed successfully\n"); 4250 return retval; 4251 out_failed: 4252 if (retry < 2) { 4253 retry++; 4254 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n", 4255 retry); 4256 mpi3mr_memset_buffers(mrioc); 4257 goto retry_init; 4258 } 4259 retval = -1; 4260 out_failed_noretry: 4261 ioc_err(mrioc, "controller initialization failed\n"); 4262 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4263 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4264 mrioc->unrecoverable = 1; 4265 return retval; 4266 } 4267 4268 /** 4269 * mpi3mr_reinit_ioc - Re-Initialize the controller 4270 * @mrioc: Adapter instance reference 4271 * @is_resume: Called from resume or reset path 4272 * 4273 * This the controller re-initialization routine, executed from 4274 * the soft reset handler or resume callback. Creates 4275 * operational reply queue pairs, allocate required memory for 4276 * reply pool, sense buffer pool, issue IOC init request to the 4277 * firmware, unmask the events and issue port enable to discover 4278 * SAS/SATA/NVMe devices and RAID volumes. 4279 * 4280 * Return: 0 on success and non-zero on failure. 4281 */ 4282 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume) 4283 { 4284 int retval = 0; 4285 u8 retry = 0; 4286 struct mpi3_ioc_facts_data facts_data; 4287 u32 pe_timeout, ioc_status; 4288 4289 retry_init: 4290 pe_timeout = 4291 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL); 4292 4293 dprint_reset(mrioc, "bringing up the controller to ready state\n"); 4294 retval = mpi3mr_bring_ioc_ready(mrioc); 4295 if (retval) { 4296 ioc_err(mrioc, "failed to bring to ready state\n"); 4297 goto out_failed_noretry; 4298 } 4299 4300 if (is_resume || mrioc->block_on_pci_err) { 4301 dprint_reset(mrioc, "setting up single ISR\n"); 4302 retval = mpi3mr_setup_isr(mrioc, 1); 4303 if (retval) { 4304 ioc_err(mrioc, "failed to setup ISR\n"); 4305 goto out_failed_noretry; 4306 } 4307 } else 4308 mpi3mr_ioc_enable_intr(mrioc); 4309 4310 dprint_reset(mrioc, "getting ioc_facts\n"); 4311 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 4312 if (retval) { 4313 ioc_err(mrioc, "failed to get ioc_facts\n"); 4314 goto out_failed; 4315 } 4316 4317 dprint_reset(mrioc, "validating ioc_facts\n"); 4318 retval = mpi3mr_revalidate_factsdata(mrioc); 4319 if (retval) { 4320 ioc_err(mrioc, "failed to revalidate ioc_facts data\n"); 4321 goto out_failed_noretry; 4322 } 4323 4324 mpi3mr_print_ioc_info(mrioc); 4325 4326 if (is_resume) { 4327 dprint_reset(mrioc, "posting host diag buffers\n"); 4328 retval = mpi3mr_post_diag_bufs(mrioc); 4329 if (retval) 4330 ioc_warn(mrioc, "failed to post host diag buffers\n"); 4331 } else { 4332 retval = mpi3mr_repost_diag_bufs(mrioc); 4333 if (retval) 4334 ioc_warn(mrioc, "failed to re post host diag buffers\n"); 4335 } 4336 4337 dprint_reset(mrioc, "sending ioc_init\n"); 4338 retval = mpi3mr_issue_iocinit(mrioc); 4339 if (retval) { 4340 ioc_err(mrioc, "failed to send ioc_init\n"); 4341 goto out_failed; 4342 } 4343 4344 dprint_reset(mrioc, "getting package version\n"); 4345 retval = mpi3mr_print_pkg_ver(mrioc); 4346 if (retval) { 4347 ioc_err(mrioc, "failed to get package version\n"); 4348 goto out_failed; 4349 } 4350 4351 if (is_resume || mrioc->block_on_pci_err) { 4352 dprint_reset(mrioc, "setting up multiple ISR\n"); 4353 retval = mpi3mr_setup_isr(mrioc, 0); 4354 if (retval) { 4355 ioc_err(mrioc, "failed to re-setup ISR\n"); 4356 goto out_failed_noretry; 4357 } 4358 } 4359 4360 dprint_reset(mrioc, "creating operational queue pairs\n"); 4361 retval = mpi3mr_create_op_queues(mrioc); 4362 if (retval) { 4363 ioc_err(mrioc, "failed to create operational queue pairs\n"); 4364 goto out_failed; 4365 } 4366 4367 if (!mrioc->pel_seqnum_virt) { 4368 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n"); 4369 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4370 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4371 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4372 GFP_KERNEL); 4373 if (!mrioc->pel_seqnum_virt) { 4374 retval = -ENOMEM; 4375 goto out_failed_noretry; 4376 } 4377 } 4378 4379 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) { 4380 ioc_err(mrioc, 4381 "cannot create minimum number of operational queues expected:%d created:%d\n", 4382 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q); 4383 retval = -1; 4384 goto out_failed_noretry; 4385 } 4386 4387 dprint_reset(mrioc, "enabling events\n"); 4388 retval = mpi3mr_enable_events(mrioc); 4389 if (retval) { 4390 ioc_err(mrioc, "failed to enable events\n"); 4391 goto out_failed; 4392 } 4393 4394 mrioc->device_refresh_on = 1; 4395 mpi3mr_add_event_wait_for_device_refresh(mrioc); 4396 4397 ioc_info(mrioc, "sending port enable\n"); 4398 retval = mpi3mr_issue_port_enable(mrioc, 1); 4399 if (retval) { 4400 ioc_err(mrioc, "failed to issue port enable\n"); 4401 goto out_failed; 4402 } 4403 do { 4404 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL); 4405 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED) 4406 break; 4407 if (!pci_device_is_present(mrioc->pdev)) 4408 mrioc->unrecoverable = 1; 4409 if (mrioc->unrecoverable) { 4410 retval = -1; 4411 goto out_failed_noretry; 4412 } 4413 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4414 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 4415 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 4416 mpi3mr_print_fault_info(mrioc); 4417 mrioc->init_cmds.is_waiting = 0; 4418 mrioc->init_cmds.callback = NULL; 4419 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4420 goto out_failed; 4421 } 4422 } while (--pe_timeout); 4423 4424 if (!pe_timeout) { 4425 ioc_err(mrioc, "port enable timed out\n"); 4426 mpi3mr_check_rh_fault_ioc(mrioc, 4427 MPI3MR_RESET_FROM_PE_TIMEOUT); 4428 mrioc->init_cmds.is_waiting = 0; 4429 mrioc->init_cmds.callback = NULL; 4430 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4431 goto out_failed; 4432 } else if (mrioc->scan_failed) { 4433 ioc_err(mrioc, 4434 "port enable failed with status=0x%04x\n", 4435 mrioc->scan_failed); 4436 } else 4437 ioc_info(mrioc, "port enable completed successfully\n"); 4438 4439 ioc_info(mrioc, "controller %s completed successfully\n", 4440 (is_resume)?"resume":"re-initialization"); 4441 return retval; 4442 out_failed: 4443 if (retry < 2) { 4444 retry++; 4445 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n", 4446 (is_resume)?"resume":"re-initialization", retry); 4447 mpi3mr_memset_buffers(mrioc); 4448 goto retry_init; 4449 } 4450 retval = -1; 4451 out_failed_noretry: 4452 ioc_err(mrioc, "controller %s is failed\n", 4453 (is_resume)?"resume":"re-initialization"); 4454 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4455 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4456 mrioc->unrecoverable = 1; 4457 return retval; 4458 } 4459 4460 /** 4461 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's 4462 * segments 4463 * @mrioc: Adapter instance reference 4464 * @qidx: Operational reply queue index 4465 * 4466 * Return: Nothing. 4467 */ 4468 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4469 { 4470 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 4471 struct segments *segments; 4472 int i, size; 4473 4474 if (!op_reply_q->q_segments) 4475 return; 4476 4477 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz; 4478 segments = op_reply_q->q_segments; 4479 for (i = 0; i < op_reply_q->num_segments; i++) 4480 memset(segments[i].segment, 0, size); 4481 } 4482 4483 /** 4484 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's 4485 * segments 4486 * @mrioc: Adapter instance reference 4487 * @qidx: Operational request queue index 4488 * 4489 * Return: Nothing. 4490 */ 4491 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4492 { 4493 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 4494 struct segments *segments; 4495 int i, size; 4496 4497 if (!op_req_q->q_segments) 4498 return; 4499 4500 size = op_req_q->segment_qd * mrioc->facts.op_req_sz; 4501 segments = op_req_q->q_segments; 4502 for (i = 0; i < op_req_q->num_segments; i++) 4503 memset(segments[i].segment, 0, size); 4504 } 4505 4506 /** 4507 * mpi3mr_memset_buffers - memset memory for a controller 4508 * @mrioc: Adapter instance reference 4509 * 4510 * clear all the memory allocated for a controller, typically 4511 * called post reset to reuse the memory allocated during the 4512 * controller init. 4513 * 4514 * Return: Nothing. 4515 */ 4516 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) 4517 { 4518 u16 i; 4519 struct mpi3mr_throttle_group_info *tg; 4520 4521 mrioc->change_count = 0; 4522 mrioc->active_poll_qcount = 0; 4523 mrioc->default_qcount = 0; 4524 if (mrioc->admin_req_base) 4525 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz); 4526 if (mrioc->admin_reply_base) 4527 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz); 4528 atomic_set(&mrioc->admin_reply_q_in_use, 0); 4529 4530 if (mrioc->init_cmds.reply) { 4531 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply)); 4532 memset(mrioc->bsg_cmds.reply, 0, 4533 sizeof(*mrioc->bsg_cmds.reply)); 4534 memset(mrioc->host_tm_cmds.reply, 0, 4535 sizeof(*mrioc->host_tm_cmds.reply)); 4536 memset(mrioc->pel_cmds.reply, 0, 4537 sizeof(*mrioc->pel_cmds.reply)); 4538 memset(mrioc->pel_abort_cmd.reply, 0, 4539 sizeof(*mrioc->pel_abort_cmd.reply)); 4540 memset(mrioc->transport_cmds.reply, 0, 4541 sizeof(*mrioc->transport_cmds.reply)); 4542 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 4543 memset(mrioc->dev_rmhs_cmds[i].reply, 0, 4544 sizeof(*mrioc->dev_rmhs_cmds[i].reply)); 4545 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 4546 memset(mrioc->evtack_cmds[i].reply, 0, 4547 sizeof(*mrioc->evtack_cmds[i].reply)); 4548 bitmap_clear(mrioc->removepend_bitmap, 0, 4549 mrioc->dev_handle_bitmap_bits); 4550 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 4551 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, 4552 MPI3MR_NUM_EVTACKCMD); 4553 } 4554 4555 for (i = 0; i < mrioc->num_queues; i++) { 4556 mrioc->op_reply_qinfo[i].qid = 0; 4557 mrioc->op_reply_qinfo[i].ci = 0; 4558 mrioc->op_reply_qinfo[i].num_replies = 0; 4559 mrioc->op_reply_qinfo[i].ephase = 0; 4560 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0); 4561 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0); 4562 mpi3mr_memset_op_reply_q_buffers(mrioc, i); 4563 4564 mrioc->req_qinfo[i].ci = 0; 4565 mrioc->req_qinfo[i].pi = 0; 4566 mrioc->req_qinfo[i].num_requests = 0; 4567 mrioc->req_qinfo[i].qid = 0; 4568 mrioc->req_qinfo[i].reply_qid = 0; 4569 spin_lock_init(&mrioc->req_qinfo[i].q_lock); 4570 mpi3mr_memset_op_req_q_buffers(mrioc, i); 4571 } 4572 4573 atomic_set(&mrioc->pend_large_data_sz, 0); 4574 if (mrioc->throttle_groups) { 4575 tg = mrioc->throttle_groups; 4576 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) { 4577 tg->id = 0; 4578 tg->fw_qd = 0; 4579 tg->modified_qd = 0; 4580 tg->io_divert = 0; 4581 tg->need_qd_reduction = 0; 4582 tg->high = 0; 4583 tg->low = 0; 4584 tg->qd_reduction = 0; 4585 atomic_set(&tg->pend_large_data_sz, 0); 4586 } 4587 } 4588 } 4589 4590 /** 4591 * mpi3mr_free_mem - Free memory allocated for a controller 4592 * @mrioc: Adapter instance reference 4593 * 4594 * Free all the memory allocated for a controller. 4595 * 4596 * Return: Nothing. 4597 */ 4598 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) 4599 { 4600 u16 i; 4601 struct mpi3mr_intr_info *intr_info; 4602 struct diag_buffer_desc *diag_buffer; 4603 4604 mpi3mr_free_enclosure_list(mrioc); 4605 mpi3mr_free_ioctl_dma_memory(mrioc); 4606 4607 if (mrioc->sense_buf_pool) { 4608 if (mrioc->sense_buf) 4609 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf, 4610 mrioc->sense_buf_dma); 4611 dma_pool_destroy(mrioc->sense_buf_pool); 4612 mrioc->sense_buf = NULL; 4613 mrioc->sense_buf_pool = NULL; 4614 } 4615 if (mrioc->sense_buf_q_pool) { 4616 if (mrioc->sense_buf_q) 4617 dma_pool_free(mrioc->sense_buf_q_pool, 4618 mrioc->sense_buf_q, mrioc->sense_buf_q_dma); 4619 dma_pool_destroy(mrioc->sense_buf_q_pool); 4620 mrioc->sense_buf_q = NULL; 4621 mrioc->sense_buf_q_pool = NULL; 4622 } 4623 4624 if (mrioc->reply_buf_pool) { 4625 if (mrioc->reply_buf) 4626 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf, 4627 mrioc->reply_buf_dma); 4628 dma_pool_destroy(mrioc->reply_buf_pool); 4629 mrioc->reply_buf = NULL; 4630 mrioc->reply_buf_pool = NULL; 4631 } 4632 if (mrioc->reply_free_q_pool) { 4633 if (mrioc->reply_free_q) 4634 dma_pool_free(mrioc->reply_free_q_pool, 4635 mrioc->reply_free_q, mrioc->reply_free_q_dma); 4636 dma_pool_destroy(mrioc->reply_free_q_pool); 4637 mrioc->reply_free_q = NULL; 4638 mrioc->reply_free_q_pool = NULL; 4639 } 4640 4641 for (i = 0; i < mrioc->num_op_req_q; i++) 4642 mpi3mr_free_op_req_q_segments(mrioc, i); 4643 4644 for (i = 0; i < mrioc->num_op_reply_q; i++) 4645 mpi3mr_free_op_reply_q_segments(mrioc, i); 4646 4647 for (i = 0; i < mrioc->intr_info_count; i++) { 4648 intr_info = mrioc->intr_info + i; 4649 intr_info->op_reply_q = NULL; 4650 } 4651 4652 kfree(mrioc->req_qinfo); 4653 mrioc->req_qinfo = NULL; 4654 mrioc->num_op_req_q = 0; 4655 4656 kfree(mrioc->op_reply_qinfo); 4657 mrioc->op_reply_qinfo = NULL; 4658 mrioc->num_op_reply_q = 0; 4659 4660 kfree(mrioc->init_cmds.reply); 4661 mrioc->init_cmds.reply = NULL; 4662 4663 kfree(mrioc->bsg_cmds.reply); 4664 mrioc->bsg_cmds.reply = NULL; 4665 4666 kfree(mrioc->host_tm_cmds.reply); 4667 mrioc->host_tm_cmds.reply = NULL; 4668 4669 kfree(mrioc->pel_cmds.reply); 4670 mrioc->pel_cmds.reply = NULL; 4671 4672 kfree(mrioc->pel_abort_cmd.reply); 4673 mrioc->pel_abort_cmd.reply = NULL; 4674 4675 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4676 kfree(mrioc->evtack_cmds[i].reply); 4677 mrioc->evtack_cmds[i].reply = NULL; 4678 } 4679 4680 bitmap_free(mrioc->removepend_bitmap); 4681 mrioc->removepend_bitmap = NULL; 4682 4683 bitmap_free(mrioc->devrem_bitmap); 4684 mrioc->devrem_bitmap = NULL; 4685 4686 bitmap_free(mrioc->evtack_cmds_bitmap); 4687 mrioc->evtack_cmds_bitmap = NULL; 4688 4689 bitmap_free(mrioc->chain_bitmap); 4690 mrioc->chain_bitmap = NULL; 4691 4692 kfree(mrioc->transport_cmds.reply); 4693 mrioc->transport_cmds.reply = NULL; 4694 4695 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4696 kfree(mrioc->dev_rmhs_cmds[i].reply); 4697 mrioc->dev_rmhs_cmds[i].reply = NULL; 4698 } 4699 4700 if (mrioc->chain_buf_pool) { 4701 for (i = 0; i < mrioc->chain_buf_count; i++) { 4702 if (mrioc->chain_sgl_list[i].addr) { 4703 dma_pool_free(mrioc->chain_buf_pool, 4704 mrioc->chain_sgl_list[i].addr, 4705 mrioc->chain_sgl_list[i].dma_addr); 4706 mrioc->chain_sgl_list[i].addr = NULL; 4707 } 4708 } 4709 dma_pool_destroy(mrioc->chain_buf_pool); 4710 mrioc->chain_buf_pool = NULL; 4711 } 4712 4713 kfree(mrioc->chain_sgl_list); 4714 mrioc->chain_sgl_list = NULL; 4715 4716 if (mrioc->admin_reply_base) { 4717 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 4718 mrioc->admin_reply_base, mrioc->admin_reply_dma); 4719 mrioc->admin_reply_base = NULL; 4720 } 4721 if (mrioc->admin_req_base) { 4722 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 4723 mrioc->admin_req_base, mrioc->admin_req_dma); 4724 mrioc->admin_req_base = NULL; 4725 } 4726 if (mrioc->cfg_page) { 4727 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz, 4728 mrioc->cfg_page, mrioc->cfg_page_dma); 4729 mrioc->cfg_page = NULL; 4730 } 4731 if (mrioc->pel_seqnum_virt) { 4732 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz, 4733 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma); 4734 mrioc->pel_seqnum_virt = NULL; 4735 } 4736 4737 for (i = 0; i < MPI3MR_MAX_NUM_HDB; i++) { 4738 diag_buffer = &mrioc->diag_buffers[i]; 4739 if (diag_buffer->addr) { 4740 dma_free_coherent(&mrioc->pdev->dev, 4741 diag_buffer->size, diag_buffer->addr, 4742 diag_buffer->dma_addr); 4743 diag_buffer->addr = NULL; 4744 diag_buffer->size = 0; 4745 diag_buffer->type = 0; 4746 diag_buffer->status = 0; 4747 } 4748 } 4749 4750 kfree(mrioc->throttle_groups); 4751 mrioc->throttle_groups = NULL; 4752 4753 kfree(mrioc->logdata_buf); 4754 mrioc->logdata_buf = NULL; 4755 4756 } 4757 4758 /** 4759 * mpi3mr_issue_ioc_shutdown - shutdown controller 4760 * @mrioc: Adapter instance reference 4761 * 4762 * Send shutodwn notification to the controller and wait for the 4763 * shutdown_timeout for it to be completed. 4764 * 4765 * Return: Nothing. 4766 */ 4767 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) 4768 { 4769 u32 ioc_config, ioc_status; 4770 u8 retval = 1; 4771 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 4772 4773 ioc_info(mrioc, "Issuing shutdown Notification\n"); 4774 if (mrioc->unrecoverable) { 4775 ioc_warn(mrioc, 4776 "IOC is unrecoverable shutdown is not issued\n"); 4777 return; 4778 } 4779 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4780 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4781 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 4782 ioc_info(mrioc, "shutdown already in progress\n"); 4783 return; 4784 } 4785 4786 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4787 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 4788 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 4789 4790 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 4791 4792 if (mrioc->facts.shutdown_timeout) 4793 timeout = mrioc->facts.shutdown_timeout * 10; 4794 4795 do { 4796 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4797 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4798 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 4799 retval = 0; 4800 break; 4801 } 4802 msleep(100); 4803 } while (--timeout); 4804 4805 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4806 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4807 4808 if (retval) { 4809 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4810 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 4811 ioc_warn(mrioc, 4812 "shutdown still in progress after timeout\n"); 4813 } 4814 4815 ioc_info(mrioc, 4816 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n", 4817 (!retval) ? "successful" : "failed", ioc_status, 4818 ioc_config); 4819 } 4820 4821 /** 4822 * mpi3mr_cleanup_ioc - Cleanup controller 4823 * @mrioc: Adapter instance reference 4824 * 4825 * controller cleanup handler, Message unit reset or soft reset 4826 * and shutdown notification is issued to the controller. 4827 * 4828 * Return: Nothing. 4829 */ 4830 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc) 4831 { 4832 enum mpi3mr_iocstate ioc_state; 4833 4834 dprint_exit(mrioc, "cleaning up the controller\n"); 4835 mpi3mr_ioc_disable_intr(mrioc); 4836 4837 ioc_state = mpi3mr_get_iocstate(mrioc); 4838 4839 if (!mrioc->unrecoverable && !mrioc->reset_in_progress && 4840 !mrioc->pci_err_recovery && 4841 (ioc_state == MRIOC_STATE_READY)) { 4842 if (mpi3mr_issue_and_process_mur(mrioc, 4843 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 4844 mpi3mr_issue_reset(mrioc, 4845 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 4846 MPI3MR_RESET_FROM_MUR_FAILURE); 4847 mpi3mr_issue_ioc_shutdown(mrioc); 4848 } 4849 dprint_exit(mrioc, "controller cleanup completed\n"); 4850 } 4851 4852 /** 4853 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 4854 * @mrioc: Adapter instance reference 4855 * @cmdptr: Internal command tracker 4856 * 4857 * Complete an internal driver commands with state indicating it 4858 * is completed due to reset. 4859 * 4860 * Return: Nothing. 4861 */ 4862 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc, 4863 struct mpi3mr_drv_cmd *cmdptr) 4864 { 4865 if (cmdptr->state & MPI3MR_CMD_PENDING) { 4866 cmdptr->state |= MPI3MR_CMD_RESET; 4867 cmdptr->state &= ~MPI3MR_CMD_PENDING; 4868 if (cmdptr->is_waiting) { 4869 complete(&cmdptr->done); 4870 cmdptr->is_waiting = 0; 4871 } else if (cmdptr->callback) 4872 cmdptr->callback(mrioc, cmdptr); 4873 } 4874 } 4875 4876 /** 4877 * mpi3mr_flush_drv_cmds - Flush internaldriver commands 4878 * @mrioc: Adapter instance reference 4879 * 4880 * Flush all internal driver commands post reset 4881 * 4882 * Return: Nothing. 4883 */ 4884 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc) 4885 { 4886 struct mpi3mr_drv_cmd *cmdptr; 4887 u8 i; 4888 4889 cmdptr = &mrioc->init_cmds; 4890 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4891 4892 cmdptr = &mrioc->cfg_cmds; 4893 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4894 4895 cmdptr = &mrioc->bsg_cmds; 4896 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4897 cmdptr = &mrioc->host_tm_cmds; 4898 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4899 4900 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4901 cmdptr = &mrioc->dev_rmhs_cmds[i]; 4902 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4903 } 4904 4905 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4906 cmdptr = &mrioc->evtack_cmds[i]; 4907 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4908 } 4909 4910 cmdptr = &mrioc->pel_cmds; 4911 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4912 4913 cmdptr = &mrioc->pel_abort_cmd; 4914 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4915 4916 cmdptr = &mrioc->transport_cmds; 4917 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4918 } 4919 4920 /** 4921 * mpi3mr_pel_wait_post - Issue PEL Wait 4922 * @mrioc: Adapter instance reference 4923 * @drv_cmd: Internal command tracker 4924 * 4925 * Issue PEL Wait MPI request through admin queue and return. 4926 * 4927 * Return: Nothing. 4928 */ 4929 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc, 4930 struct mpi3mr_drv_cmd *drv_cmd) 4931 { 4932 struct mpi3_pel_req_action_wait pel_wait; 4933 4934 mrioc->pel_abort_requested = false; 4935 4936 memset(&pel_wait, 0, sizeof(pel_wait)); 4937 drv_cmd->state = MPI3MR_CMD_PENDING; 4938 drv_cmd->is_waiting = 0; 4939 drv_cmd->callback = mpi3mr_pel_wait_complete; 4940 drv_cmd->ioc_status = 0; 4941 drv_cmd->ioc_loginfo = 0; 4942 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4943 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4944 pel_wait.action = MPI3_PEL_ACTION_WAIT; 4945 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum); 4946 pel_wait.locale = cpu_to_le16(mrioc->pel_locale); 4947 pel_wait.class = cpu_to_le16(mrioc->pel_class); 4948 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT; 4949 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n", 4950 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale); 4951 4952 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) { 4953 dprint_bsg_err(mrioc, 4954 "Issuing PELWait: Admin post failed\n"); 4955 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4956 drv_cmd->callback = NULL; 4957 drv_cmd->retry_count = 0; 4958 mrioc->pel_enabled = false; 4959 } 4960 } 4961 4962 /** 4963 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number 4964 * @mrioc: Adapter instance reference 4965 * @drv_cmd: Internal command tracker 4966 * 4967 * Issue PEL get sequence number MPI request through admin queue 4968 * and return. 4969 * 4970 * Return: 0 on success, non-zero on failure. 4971 */ 4972 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 4973 struct mpi3mr_drv_cmd *drv_cmd) 4974 { 4975 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req; 4976 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 4977 int retval = 0; 4978 4979 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req)); 4980 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING; 4981 mrioc->pel_cmds.is_waiting = 0; 4982 mrioc->pel_cmds.ioc_status = 0; 4983 mrioc->pel_cmds.ioc_loginfo = 0; 4984 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete; 4985 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4986 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4987 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM; 4988 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags, 4989 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma); 4990 4991 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req, 4992 sizeof(pel_getseq_req), 0); 4993 if (retval) { 4994 if (drv_cmd) { 4995 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4996 drv_cmd->callback = NULL; 4997 drv_cmd->retry_count = 0; 4998 } 4999 mrioc->pel_enabled = false; 5000 } 5001 5002 return retval; 5003 } 5004 5005 /** 5006 * mpi3mr_pel_wait_complete - PELWait Completion callback 5007 * @mrioc: Adapter instance reference 5008 * @drv_cmd: Internal command tracker 5009 * 5010 * This is a callback handler for the PELWait request and 5011 * firmware completes a PELWait request when it is aborted or a 5012 * new PEL entry is available. This sends AEN to the application 5013 * and if the PELwait completion is not due to PELAbort then 5014 * this will send a request for new PEL Sequence number 5015 * 5016 * Return: Nothing. 5017 */ 5018 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 5019 struct mpi3mr_drv_cmd *drv_cmd) 5020 { 5021 struct mpi3_pel_reply *pel_reply = NULL; 5022 u16 ioc_status, pe_log_status; 5023 bool do_retry = false; 5024 5025 if (drv_cmd->state & MPI3MR_CMD_RESET) 5026 goto cleanup_drv_cmd; 5027 5028 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5029 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5030 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 5031 __func__, ioc_status, drv_cmd->ioc_loginfo); 5032 dprint_bsg_err(mrioc, 5033 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 5034 ioc_status, drv_cmd->ioc_loginfo); 5035 do_retry = true; 5036 } 5037 5038 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 5039 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 5040 5041 if (!pel_reply) { 5042 dprint_bsg_err(mrioc, 5043 "pel_wait: failed due to no reply\n"); 5044 goto out_failed; 5045 } 5046 5047 pe_log_status = le16_to_cpu(pel_reply->pe_log_status); 5048 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) && 5049 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) { 5050 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n", 5051 __func__, pe_log_status); 5052 dprint_bsg_err(mrioc, 5053 "pel_wait: failed due to pel_log_status(0x%04x)\n", 5054 pe_log_status); 5055 do_retry = true; 5056 } 5057 5058 if (do_retry) { 5059 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 5060 drv_cmd->retry_count++; 5061 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n", 5062 drv_cmd->retry_count); 5063 mpi3mr_pel_wait_post(mrioc, drv_cmd); 5064 return; 5065 } 5066 dprint_bsg_err(mrioc, 5067 "pel_wait: failed after all retries(%d)\n", 5068 drv_cmd->retry_count); 5069 goto out_failed; 5070 } 5071 atomic64_inc(&event_counter); 5072 if (!mrioc->pel_abort_requested) { 5073 mrioc->pel_cmds.retry_count = 0; 5074 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds); 5075 } 5076 5077 return; 5078 out_failed: 5079 mrioc->pel_enabled = false; 5080 cleanup_drv_cmd: 5081 drv_cmd->state = MPI3MR_CMD_NOTUSED; 5082 drv_cmd->callback = NULL; 5083 drv_cmd->retry_count = 0; 5084 } 5085 5086 /** 5087 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback 5088 * @mrioc: Adapter instance reference 5089 * @drv_cmd: Internal command tracker 5090 * 5091 * This is a callback handler for the PEL get sequence number 5092 * request and a new PEL wait request will be issued to the 5093 * firmware from this 5094 * 5095 * Return: Nothing. 5096 */ 5097 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 5098 struct mpi3mr_drv_cmd *drv_cmd) 5099 { 5100 struct mpi3_pel_reply *pel_reply = NULL; 5101 struct mpi3_pel_seq *pel_seqnum_virt; 5102 u16 ioc_status; 5103 bool do_retry = false; 5104 5105 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt; 5106 5107 if (drv_cmd->state & MPI3MR_CMD_RESET) 5108 goto cleanup_drv_cmd; 5109 5110 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5111 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5112 dprint_bsg_err(mrioc, 5113 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 5114 ioc_status, drv_cmd->ioc_loginfo); 5115 do_retry = true; 5116 } 5117 5118 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 5119 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 5120 if (!pel_reply) { 5121 dprint_bsg_err(mrioc, 5122 "pel_get_seqnum: failed due to no reply\n"); 5123 goto out_failed; 5124 } 5125 5126 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) { 5127 dprint_bsg_err(mrioc, 5128 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n", 5129 le16_to_cpu(pel_reply->pe_log_status)); 5130 do_retry = true; 5131 } 5132 5133 if (do_retry) { 5134 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 5135 drv_cmd->retry_count++; 5136 dprint_bsg_err(mrioc, 5137 "pel_get_seqnum: retrying(%d)\n", 5138 drv_cmd->retry_count); 5139 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd); 5140 return; 5141 } 5142 5143 dprint_bsg_err(mrioc, 5144 "pel_get_seqnum: failed after all retries(%d)\n", 5145 drv_cmd->retry_count); 5146 goto out_failed; 5147 } 5148 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1; 5149 drv_cmd->retry_count = 0; 5150 mpi3mr_pel_wait_post(mrioc, drv_cmd); 5151 5152 return; 5153 out_failed: 5154 mrioc->pel_enabled = false; 5155 cleanup_drv_cmd: 5156 drv_cmd->state = MPI3MR_CMD_NOTUSED; 5157 drv_cmd->callback = NULL; 5158 drv_cmd->retry_count = 0; 5159 } 5160 5161 /** 5162 * mpi3mr_soft_reset_handler - Reset the controller 5163 * @mrioc: Adapter instance reference 5164 * @reset_reason: Reset reason code 5165 * @snapdump: Flag to generate snapdump in firmware or not 5166 * 5167 * This is an handler for recovering controller by issuing soft 5168 * reset are diag fault reset. This is a blocking function and 5169 * when one reset is executed if any other resets they will be 5170 * blocked. All BSG requests will be blocked during the reset. If 5171 * controller reset is successful then the controller will be 5172 * reinitalized, otherwise the controller will be marked as not 5173 * recoverable 5174 * 5175 * In snapdump bit is set, the controller is issued with diag 5176 * fault reset so that the firmware can create a snap dump and 5177 * post that the firmware will result in F000 fault and the 5178 * driver will issue soft reset to recover from that. 5179 * 5180 * Return: 0 on success, non-zero on failure. 5181 */ 5182 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 5183 u16 reset_reason, u8 snapdump) 5184 { 5185 int retval = 0, i; 5186 unsigned long flags; 5187 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 5188 union mpi3mr_trigger_data trigger_data; 5189 5190 /* Block the reset handler until diag save in progress*/ 5191 dprint_reset(mrioc, 5192 "soft_reset_handler: check and block on diagsave_timeout(%d)\n", 5193 mrioc->diagsave_timeout); 5194 while (mrioc->diagsave_timeout) 5195 ssleep(1); 5196 /* 5197 * Block new resets until the currently executing one is finished and 5198 * return the status of the existing reset for all blocked resets 5199 */ 5200 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n"); 5201 if (!mutex_trylock(&mrioc->reset_mutex)) { 5202 ioc_info(mrioc, 5203 "controller reset triggered by %s is blocked due to another reset in progress\n", 5204 mpi3mr_reset_rc_name(reset_reason)); 5205 do { 5206 ssleep(1); 5207 } while (mrioc->reset_in_progress == 1); 5208 ioc_info(mrioc, 5209 "returning previous reset result(%d) for the reset triggered by %s\n", 5210 mrioc->prev_reset_result, 5211 mpi3mr_reset_rc_name(reset_reason)); 5212 return mrioc->prev_reset_result; 5213 } 5214 ioc_info(mrioc, "controller reset is triggered by %s\n", 5215 mpi3mr_reset_rc_name(reset_reason)); 5216 5217 mrioc->device_refresh_on = 0; 5218 mrioc->reset_in_progress = 1; 5219 mrioc->stop_bsgs = 1; 5220 mrioc->prev_reset_result = -1; 5221 memset(&trigger_data, 0, sizeof(trigger_data)); 5222 5223 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 5224 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 5225 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 5226 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 5227 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0); 5228 dprint_reset(mrioc, 5229 "soft_reset_handler: releasing host diagnostic buffers\n"); 5230 mpi3mr_release_diag_bufs(mrioc, 0); 5231 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5232 mrioc->event_masks[i] = -1; 5233 5234 dprint_reset(mrioc, "soft_reset_handler: masking events\n"); 5235 mpi3mr_issue_event_notification(mrioc); 5236 } 5237 5238 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT); 5239 5240 mpi3mr_ioc_disable_intr(mrioc); 5241 5242 if (snapdump) { 5243 mpi3mr_set_diagsave(mrioc); 5244 retval = mpi3mr_issue_reset(mrioc, 5245 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5246 if (!retval) { 5247 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) & 5248 MPI3_SYSIF_FAULT_CODE_MASK); 5249 do { 5250 host_diagnostic = 5251 readl(&mrioc->sysif_regs->host_diagnostic); 5252 if (!(host_diagnostic & 5253 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 5254 break; 5255 msleep(100); 5256 } while (--timeout); 5257 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 5258 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0); 5259 } 5260 } 5261 5262 retval = mpi3mr_issue_reset(mrioc, 5263 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 5264 if (retval) { 5265 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n"); 5266 goto out; 5267 } 5268 if (mrioc->num_io_throttle_group != 5269 mrioc->facts.max_io_throttle_group) { 5270 ioc_err(mrioc, 5271 "max io throttle group doesn't match old(%d), new(%d)\n", 5272 mrioc->num_io_throttle_group, 5273 mrioc->facts.max_io_throttle_group); 5274 retval = -EPERM; 5275 goto out; 5276 } 5277 5278 mpi3mr_flush_delayed_cmd_lists(mrioc); 5279 mpi3mr_flush_drv_cmds(mrioc); 5280 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 5281 bitmap_clear(mrioc->removepend_bitmap, 0, 5282 mrioc->dev_handle_bitmap_bits); 5283 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD); 5284 mpi3mr_flush_host_io(mrioc); 5285 mpi3mr_cleanup_fwevt_list(mrioc); 5286 mpi3mr_invalidate_devhandles(mrioc); 5287 mpi3mr_free_enclosure_list(mrioc); 5288 5289 if (mrioc->prepare_for_reset) { 5290 mrioc->prepare_for_reset = 0; 5291 mrioc->prepare_for_reset_timeout_counter = 0; 5292 } 5293 mpi3mr_memset_buffers(mrioc); 5294 mpi3mr_release_diag_bufs(mrioc, 1); 5295 mrioc->fw_release_trigger_active = false; 5296 mrioc->trace_release_trigger_active = false; 5297 mrioc->snapdump_trigger_active = false; 5298 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 5299 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0); 5300 5301 dprint_reset(mrioc, 5302 "soft_reset_handler: reinitializing the controller\n"); 5303 retval = mpi3mr_reinit_ioc(mrioc, 0); 5304 if (retval) { 5305 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n", 5306 mrioc->name, reset_reason); 5307 goto out; 5308 } 5309 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME); 5310 5311 out: 5312 if (!retval) { 5313 mrioc->diagsave_timeout = 0; 5314 mrioc->reset_in_progress = 0; 5315 mrioc->pel_abort_requested = 0; 5316 if (mrioc->pel_enabled) { 5317 mrioc->pel_cmds.retry_count = 0; 5318 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds); 5319 } 5320 5321 mrioc->device_refresh_on = 0; 5322 5323 mrioc->ts_update_counter = 0; 5324 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 5325 if (mrioc->watchdog_work_q) 5326 queue_delayed_work(mrioc->watchdog_work_q, 5327 &mrioc->watchdog_work, 5328 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 5329 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 5330 mrioc->stop_bsgs = 0; 5331 if (mrioc->pel_enabled) 5332 atomic64_inc(&event_counter); 5333 } else { 5334 mpi3mr_issue_reset(mrioc, 5335 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5336 mrioc->device_refresh_on = 0; 5337 mrioc->unrecoverable = 1; 5338 mrioc->reset_in_progress = 0; 5339 mrioc->stop_bsgs = 0; 5340 retval = -1; 5341 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 5342 } 5343 mrioc->prev_reset_result = retval; 5344 mutex_unlock(&mrioc->reset_mutex); 5345 ioc_info(mrioc, "controller reset is %s\n", 5346 ((retval == 0) ? "successful" : "failed")); 5347 return retval; 5348 } 5349 5350 5351 /** 5352 * mpi3mr_free_config_dma_memory - free memory for config page 5353 * @mrioc: Adapter instance reference 5354 * @mem_desc: memory descriptor structure 5355 * 5356 * Check whether the size of the buffer specified by the memory 5357 * descriptor is greater than the default page size if so then 5358 * free the memory pointed by the descriptor. 5359 * 5360 * Return: Nothing. 5361 */ 5362 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc, 5363 struct dma_memory_desc *mem_desc) 5364 { 5365 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) { 5366 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 5367 mem_desc->addr, mem_desc->dma_addr); 5368 mem_desc->addr = NULL; 5369 } 5370 } 5371 5372 /** 5373 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page 5374 * @mrioc: Adapter instance reference 5375 * @mem_desc: Memory descriptor to hold dma memory info 5376 * 5377 * This function allocates new dmaable memory or provides the 5378 * default config page dmaable memory based on the memory size 5379 * described by the descriptor. 5380 * 5381 * Return: 0 on success, non-zero on failure. 5382 */ 5383 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc, 5384 struct dma_memory_desc *mem_desc) 5385 { 5386 if (mem_desc->size > mrioc->cfg_page_sz) { 5387 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 5388 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL); 5389 if (!mem_desc->addr) 5390 return -ENOMEM; 5391 } else { 5392 mem_desc->addr = mrioc->cfg_page; 5393 mem_desc->dma_addr = mrioc->cfg_page_dma; 5394 memset(mem_desc->addr, 0, mrioc->cfg_page_sz); 5395 } 5396 return 0; 5397 } 5398 5399 /** 5400 * mpi3mr_post_cfg_req - Issue config requests and wait 5401 * @mrioc: Adapter instance reference 5402 * @cfg_req: Configuration request 5403 * @timeout: Timeout in seconds 5404 * @ioc_status: Pointer to return ioc status 5405 * 5406 * A generic function for posting MPI3 configuration request to 5407 * the firmware. This blocks for the completion of request for 5408 * timeout seconds and if the request times out this function 5409 * faults the controller with proper reason code. 5410 * 5411 * On successful completion of the request this function returns 5412 * appropriate ioc status from the firmware back to the caller. 5413 * 5414 * Return: 0 on success, non-zero on failure. 5415 */ 5416 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc, 5417 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status) 5418 { 5419 int retval = 0; 5420 5421 mutex_lock(&mrioc->cfg_cmds.mutex); 5422 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) { 5423 retval = -1; 5424 ioc_err(mrioc, "sending config request failed due to command in use\n"); 5425 mutex_unlock(&mrioc->cfg_cmds.mutex); 5426 goto out; 5427 } 5428 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING; 5429 mrioc->cfg_cmds.is_waiting = 1; 5430 mrioc->cfg_cmds.callback = NULL; 5431 mrioc->cfg_cmds.ioc_status = 0; 5432 mrioc->cfg_cmds.ioc_loginfo = 0; 5433 5434 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS); 5435 cfg_req->function = MPI3_FUNCTION_CONFIG; 5436 5437 init_completion(&mrioc->cfg_cmds.done); 5438 dprint_cfg_info(mrioc, "posting config request\n"); 5439 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5440 dprint_dump(cfg_req, sizeof(struct mpi3_config_request), 5441 "mpi3_cfg_req"); 5442 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1); 5443 if (retval) { 5444 ioc_err(mrioc, "posting config request failed\n"); 5445 goto out_unlock; 5446 } 5447 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ)); 5448 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) { 5449 mpi3mr_check_rh_fault_ioc(mrioc, 5450 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT); 5451 ioc_err(mrioc, "config request timed out\n"); 5452 retval = -1; 5453 goto out_unlock; 5454 } 5455 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5456 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS) 5457 dprint_cfg_err(mrioc, 5458 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n", 5459 *ioc_status, mrioc->cfg_cmds.ioc_loginfo); 5460 5461 out_unlock: 5462 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED; 5463 mutex_unlock(&mrioc->cfg_cmds.mutex); 5464 5465 out: 5466 return retval; 5467 } 5468 5469 /** 5470 * mpi3mr_process_cfg_req - config page request processor 5471 * @mrioc: Adapter instance reference 5472 * @cfg_req: Configuration request 5473 * @cfg_hdr: Configuration page header 5474 * @timeout: Timeout in seconds 5475 * @ioc_status: Pointer to return ioc status 5476 * @cfg_buf: Memory pointer to copy config page or header 5477 * @cfg_buf_sz: Size of the memory to get config page or header 5478 * 5479 * This is handler for config page read, write and config page 5480 * header read operations. 5481 * 5482 * This function expects the cfg_req to be populated with page 5483 * type, page number, action for the header read and with page 5484 * address for all other operations. 5485 * 5486 * The cfg_hdr can be passed as null for reading required header 5487 * details for read/write pages the cfg_hdr should point valid 5488 * configuration page header. 5489 * 5490 * This allocates dmaable memory based on the size of the config 5491 * buffer and set the SGE of the cfg_req. 5492 * 5493 * For write actions, the config page data has to be passed in 5494 * the cfg_buf and size of the data has to be mentioned in the 5495 * cfg_buf_sz. 5496 * 5497 * For read/header actions, on successful completion of the 5498 * request with successful ioc_status the data will be copied 5499 * into the cfg_buf limited to a minimum of actual page size and 5500 * cfg_buf_sz 5501 * 5502 * 5503 * Return: 0 on success, non-zero on failure. 5504 */ 5505 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc, 5506 struct mpi3_config_request *cfg_req, 5507 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status, 5508 void *cfg_buf, u32 cfg_buf_sz) 5509 { 5510 struct dma_memory_desc mem_desc; 5511 int retval = -1; 5512 u8 invalid_action = 0; 5513 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 5514 5515 memset(&mem_desc, 0, sizeof(struct dma_memory_desc)); 5516 5517 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER) 5518 mem_desc.size = sizeof(struct mpi3_config_page_header); 5519 else { 5520 if (!cfg_hdr) { 5521 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n", 5522 cfg_req->action, cfg_req->page_type, 5523 cfg_req->page_number); 5524 goto out; 5525 } 5526 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) { 5527 case MPI3_CONFIG_PAGEATTR_READ_ONLY: 5528 if (cfg_req->action 5529 != MPI3_CONFIG_ACTION_READ_CURRENT) 5530 invalid_action = 1; 5531 break; 5532 case MPI3_CONFIG_PAGEATTR_CHANGEABLE: 5533 if ((cfg_req->action == 5534 MPI3_CONFIG_ACTION_READ_PERSISTENT) || 5535 (cfg_req->action == 5536 MPI3_CONFIG_ACTION_WRITE_PERSISTENT)) 5537 invalid_action = 1; 5538 break; 5539 case MPI3_CONFIG_PAGEATTR_PERSISTENT: 5540 default: 5541 break; 5542 } 5543 if (invalid_action) { 5544 ioc_err(mrioc, 5545 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n", 5546 cfg_req->action, cfg_req->page_type, 5547 cfg_req->page_number, cfg_hdr->page_attribute); 5548 goto out; 5549 } 5550 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4; 5551 cfg_req->page_length = cfg_hdr->page_length; 5552 cfg_req->page_version = cfg_hdr->page_version; 5553 } 5554 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc)) 5555 goto out; 5556 5557 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size, 5558 mem_desc.dma_addr); 5559 5560 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) || 5561 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5562 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size, 5563 cfg_buf_sz)); 5564 dprint_cfg_info(mrioc, "config buffer to be written\n"); 5565 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5566 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5567 } 5568 5569 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status)) 5570 goto out; 5571 5572 retval = 0; 5573 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) && 5574 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) && 5575 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5576 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size, 5577 cfg_buf_sz)); 5578 dprint_cfg_info(mrioc, "config buffer read\n"); 5579 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5580 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5581 } 5582 5583 out: 5584 mpi3mr_free_config_dma_memory(mrioc, &mem_desc); 5585 return retval; 5586 } 5587 5588 /** 5589 * mpi3mr_cfg_get_dev_pg0 - Read current device page0 5590 * @mrioc: Adapter instance reference 5591 * @ioc_status: Pointer to return ioc status 5592 * @dev_pg0: Pointer to return device page 0 5593 * @pg_sz: Size of the memory allocated to the page pointer 5594 * @form: The form to be used for addressing the page 5595 * @form_spec: Form specific information like device handle 5596 * 5597 * This is handler for config page read for a specific device 5598 * page0. The ioc_status has the controller returned ioc_status. 5599 * This routine doesn't check ioc_status to decide whether the 5600 * page read is success or not and it is the callers 5601 * responsibility. 5602 * 5603 * Return: 0 on success, non-zero on failure. 5604 */ 5605 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5606 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec) 5607 { 5608 struct mpi3_config_page_header cfg_hdr; 5609 struct mpi3_config_request cfg_req; 5610 u32 page_address; 5611 5612 memset(dev_pg0, 0, pg_sz); 5613 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5614 memset(&cfg_req, 0, sizeof(cfg_req)); 5615 5616 cfg_req.function = MPI3_FUNCTION_CONFIG; 5617 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5618 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE; 5619 cfg_req.page_number = 0; 5620 cfg_req.page_address = 0; 5621 5622 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5623 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5624 ioc_err(mrioc, "device page0 header read failed\n"); 5625 goto out_failed; 5626 } 5627 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5628 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n", 5629 *ioc_status); 5630 goto out_failed; 5631 } 5632 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5633 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) | 5634 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK)); 5635 cfg_req.page_address = cpu_to_le32(page_address); 5636 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5637 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) { 5638 ioc_err(mrioc, "device page0 read failed\n"); 5639 goto out_failed; 5640 } 5641 return 0; 5642 out_failed: 5643 return -1; 5644 } 5645 5646 5647 /** 5648 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0 5649 * @mrioc: Adapter instance reference 5650 * @ioc_status: Pointer to return ioc status 5651 * @phy_pg0: Pointer to return SAS Phy page 0 5652 * @pg_sz: Size of the memory allocated to the page pointer 5653 * @form: The form to be used for addressing the page 5654 * @form_spec: Form specific information like phy number 5655 * 5656 * This is handler for config page read for a specific SAS Phy 5657 * page0. The ioc_status has the controller returned ioc_status. 5658 * This routine doesn't check ioc_status to decide whether the 5659 * page read is success or not and it is the callers 5660 * responsibility. 5661 * 5662 * Return: 0 on success, non-zero on failure. 5663 */ 5664 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5665 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 5666 u32 form_spec) 5667 { 5668 struct mpi3_config_page_header cfg_hdr; 5669 struct mpi3_config_request cfg_req; 5670 u32 page_address; 5671 5672 memset(phy_pg0, 0, pg_sz); 5673 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5674 memset(&cfg_req, 0, sizeof(cfg_req)); 5675 5676 cfg_req.function = MPI3_FUNCTION_CONFIG; 5677 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5678 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5679 cfg_req.page_number = 0; 5680 cfg_req.page_address = 0; 5681 5682 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5683 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5684 ioc_err(mrioc, "sas phy page0 header read failed\n"); 5685 goto out_failed; 5686 } 5687 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5688 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n", 5689 *ioc_status); 5690 goto out_failed; 5691 } 5692 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5693 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5694 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5695 cfg_req.page_address = cpu_to_le32(page_address); 5696 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5697 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) { 5698 ioc_err(mrioc, "sas phy page0 read failed\n"); 5699 goto out_failed; 5700 } 5701 return 0; 5702 out_failed: 5703 return -1; 5704 } 5705 5706 /** 5707 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1 5708 * @mrioc: Adapter instance reference 5709 * @ioc_status: Pointer to return ioc status 5710 * @phy_pg1: Pointer to return SAS Phy page 1 5711 * @pg_sz: Size of the memory allocated to the page pointer 5712 * @form: The form to be used for addressing the page 5713 * @form_spec: Form specific information like phy number 5714 * 5715 * This is handler for config page read for a specific SAS Phy 5716 * page1. The ioc_status has the controller returned ioc_status. 5717 * This routine doesn't check ioc_status to decide whether the 5718 * page read is success or not and it is the callers 5719 * responsibility. 5720 * 5721 * Return: 0 on success, non-zero on failure. 5722 */ 5723 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5724 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 5725 u32 form_spec) 5726 { 5727 struct mpi3_config_page_header cfg_hdr; 5728 struct mpi3_config_request cfg_req; 5729 u32 page_address; 5730 5731 memset(phy_pg1, 0, pg_sz); 5732 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5733 memset(&cfg_req, 0, sizeof(cfg_req)); 5734 5735 cfg_req.function = MPI3_FUNCTION_CONFIG; 5736 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5737 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5738 cfg_req.page_number = 1; 5739 cfg_req.page_address = 0; 5740 5741 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5742 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5743 ioc_err(mrioc, "sas phy page1 header read failed\n"); 5744 goto out_failed; 5745 } 5746 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5747 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n", 5748 *ioc_status); 5749 goto out_failed; 5750 } 5751 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5752 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5753 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5754 cfg_req.page_address = cpu_to_le32(page_address); 5755 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5756 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) { 5757 ioc_err(mrioc, "sas phy page1 read failed\n"); 5758 goto out_failed; 5759 } 5760 return 0; 5761 out_failed: 5762 return -1; 5763 } 5764 5765 5766 /** 5767 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0 5768 * @mrioc: Adapter instance reference 5769 * @ioc_status: Pointer to return ioc status 5770 * @exp_pg0: Pointer to return SAS Expander page 0 5771 * @pg_sz: Size of the memory allocated to the page pointer 5772 * @form: The form to be used for addressing the page 5773 * @form_spec: Form specific information like device handle 5774 * 5775 * This is handler for config page read for a specific SAS 5776 * Expander page0. The ioc_status has the controller returned 5777 * ioc_status. This routine doesn't check ioc_status to decide 5778 * whether the page read is success or not and it is the callers 5779 * responsibility. 5780 * 5781 * Return: 0 on success, non-zero on failure. 5782 */ 5783 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5784 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 5785 u32 form_spec) 5786 { 5787 struct mpi3_config_page_header cfg_hdr; 5788 struct mpi3_config_request cfg_req; 5789 u32 page_address; 5790 5791 memset(exp_pg0, 0, pg_sz); 5792 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5793 memset(&cfg_req, 0, sizeof(cfg_req)); 5794 5795 cfg_req.function = MPI3_FUNCTION_CONFIG; 5796 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5797 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5798 cfg_req.page_number = 0; 5799 cfg_req.page_address = 0; 5800 5801 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5802 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5803 ioc_err(mrioc, "expander page0 header read failed\n"); 5804 goto out_failed; 5805 } 5806 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5807 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n", 5808 *ioc_status); 5809 goto out_failed; 5810 } 5811 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5812 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5813 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5814 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5815 cfg_req.page_address = cpu_to_le32(page_address); 5816 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5817 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) { 5818 ioc_err(mrioc, "expander page0 read failed\n"); 5819 goto out_failed; 5820 } 5821 return 0; 5822 out_failed: 5823 return -1; 5824 } 5825 5826 /** 5827 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1 5828 * @mrioc: Adapter instance reference 5829 * @ioc_status: Pointer to return ioc status 5830 * @exp_pg1: Pointer to return SAS Expander page 1 5831 * @pg_sz: Size of the memory allocated to the page pointer 5832 * @form: The form to be used for addressing the page 5833 * @form_spec: Form specific information like phy number 5834 * 5835 * This is handler for config page read for a specific SAS 5836 * Expander page1. The ioc_status has the controller returned 5837 * ioc_status. This routine doesn't check ioc_status to decide 5838 * whether the page read is success or not and it is the callers 5839 * responsibility. 5840 * 5841 * Return: 0 on success, non-zero on failure. 5842 */ 5843 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5844 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 5845 u32 form_spec) 5846 { 5847 struct mpi3_config_page_header cfg_hdr; 5848 struct mpi3_config_request cfg_req; 5849 u32 page_address; 5850 5851 memset(exp_pg1, 0, pg_sz); 5852 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5853 memset(&cfg_req, 0, sizeof(cfg_req)); 5854 5855 cfg_req.function = MPI3_FUNCTION_CONFIG; 5856 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5857 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5858 cfg_req.page_number = 1; 5859 cfg_req.page_address = 0; 5860 5861 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5862 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5863 ioc_err(mrioc, "expander page1 header read failed\n"); 5864 goto out_failed; 5865 } 5866 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5867 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n", 5868 *ioc_status); 5869 goto out_failed; 5870 } 5871 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5872 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5873 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5874 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5875 cfg_req.page_address = cpu_to_le32(page_address); 5876 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5877 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) { 5878 ioc_err(mrioc, "expander page1 read failed\n"); 5879 goto out_failed; 5880 } 5881 return 0; 5882 out_failed: 5883 return -1; 5884 } 5885 5886 /** 5887 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0 5888 * @mrioc: Adapter instance reference 5889 * @ioc_status: Pointer to return ioc status 5890 * @encl_pg0: Pointer to return Enclosure page 0 5891 * @pg_sz: Size of the memory allocated to the page pointer 5892 * @form: The form to be used for addressing the page 5893 * @form_spec: Form specific information like device handle 5894 * 5895 * This is handler for config page read for a specific Enclosure 5896 * page0. The ioc_status has the controller returned ioc_status. 5897 * This routine doesn't check ioc_status to decide whether the 5898 * page read is success or not and it is the callers 5899 * responsibility. 5900 * 5901 * Return: 0 on success, non-zero on failure. 5902 */ 5903 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5904 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 5905 u32 form_spec) 5906 { 5907 struct mpi3_config_page_header cfg_hdr; 5908 struct mpi3_config_request cfg_req; 5909 u32 page_address; 5910 5911 memset(encl_pg0, 0, pg_sz); 5912 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5913 memset(&cfg_req, 0, sizeof(cfg_req)); 5914 5915 cfg_req.function = MPI3_FUNCTION_CONFIG; 5916 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5917 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE; 5918 cfg_req.page_number = 0; 5919 cfg_req.page_address = 0; 5920 5921 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5922 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5923 ioc_err(mrioc, "enclosure page0 header read failed\n"); 5924 goto out_failed; 5925 } 5926 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5927 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n", 5928 *ioc_status); 5929 goto out_failed; 5930 } 5931 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5932 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) | 5933 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK)); 5934 cfg_req.page_address = cpu_to_le32(page_address); 5935 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5936 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) { 5937 ioc_err(mrioc, "enclosure page0 read failed\n"); 5938 goto out_failed; 5939 } 5940 return 0; 5941 out_failed: 5942 return -1; 5943 } 5944 5945 5946 /** 5947 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0 5948 * @mrioc: Adapter instance reference 5949 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0 5950 * @pg_sz: Size of the memory allocated to the page pointer 5951 * 5952 * This is handler for config page read for the SAS IO Unit 5953 * page0. This routine checks ioc_status to decide whether the 5954 * page read is success or not. 5955 * 5956 * Return: 0 on success, non-zero on failure. 5957 */ 5958 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 5959 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz) 5960 { 5961 struct mpi3_config_page_header cfg_hdr; 5962 struct mpi3_config_request cfg_req; 5963 u16 ioc_status = 0; 5964 5965 memset(sas_io_unit_pg0, 0, pg_sz); 5966 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5967 memset(&cfg_req, 0, sizeof(cfg_req)); 5968 5969 cfg_req.function = MPI3_FUNCTION_CONFIG; 5970 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5971 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5972 cfg_req.page_number = 0; 5973 cfg_req.page_address = 0; 5974 5975 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5976 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5977 ioc_err(mrioc, "sas io unit page0 header read failed\n"); 5978 goto out_failed; 5979 } 5980 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5981 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n", 5982 ioc_status); 5983 goto out_failed; 5984 } 5985 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5986 5987 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5988 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) { 5989 ioc_err(mrioc, "sas io unit page0 read failed\n"); 5990 goto out_failed; 5991 } 5992 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5993 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n", 5994 ioc_status); 5995 goto out_failed; 5996 } 5997 return 0; 5998 out_failed: 5999 return -1; 6000 } 6001 6002 /** 6003 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1 6004 * @mrioc: Adapter instance reference 6005 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1 6006 * @pg_sz: Size of the memory allocated to the page pointer 6007 * 6008 * This is handler for config page read for the SAS IO Unit 6009 * page1. This routine checks ioc_status to decide whether the 6010 * page read is success or not. 6011 * 6012 * Return: 0 on success, non-zero on failure. 6013 */ 6014 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 6015 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 6016 { 6017 struct mpi3_config_page_header cfg_hdr; 6018 struct mpi3_config_request cfg_req; 6019 u16 ioc_status = 0; 6020 6021 memset(sas_io_unit_pg1, 0, pg_sz); 6022 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6023 memset(&cfg_req, 0, sizeof(cfg_req)); 6024 6025 cfg_req.function = MPI3_FUNCTION_CONFIG; 6026 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6027 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 6028 cfg_req.page_number = 1; 6029 cfg_req.page_address = 0; 6030 6031 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6032 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6033 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 6034 goto out_failed; 6035 } 6036 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6037 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 6038 ioc_status); 6039 goto out_failed; 6040 } 6041 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6042 6043 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6044 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 6045 ioc_err(mrioc, "sas io unit page1 read failed\n"); 6046 goto out_failed; 6047 } 6048 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6049 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n", 6050 ioc_status); 6051 goto out_failed; 6052 } 6053 return 0; 6054 out_failed: 6055 return -1; 6056 } 6057 6058 /** 6059 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1 6060 * @mrioc: Adapter instance reference 6061 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write 6062 * @pg_sz: Size of the memory allocated to the page pointer 6063 * 6064 * This is handler for config page write for the SAS IO Unit 6065 * page1. This routine checks ioc_status to decide whether the 6066 * page read is success or not. This will modify both current 6067 * and persistent page. 6068 * 6069 * Return: 0 on success, non-zero on failure. 6070 */ 6071 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 6072 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 6073 { 6074 struct mpi3_config_page_header cfg_hdr; 6075 struct mpi3_config_request cfg_req; 6076 u16 ioc_status = 0; 6077 6078 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6079 memset(&cfg_req, 0, sizeof(cfg_req)); 6080 6081 cfg_req.function = MPI3_FUNCTION_CONFIG; 6082 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6083 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 6084 cfg_req.page_number = 1; 6085 cfg_req.page_address = 0; 6086 6087 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6088 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6089 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 6090 goto out_failed; 6091 } 6092 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6093 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 6094 ioc_status); 6095 goto out_failed; 6096 } 6097 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT; 6098 6099 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6100 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 6101 ioc_err(mrioc, "sas io unit page1 write current failed\n"); 6102 goto out_failed; 6103 } 6104 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6105 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n", 6106 ioc_status); 6107 goto out_failed; 6108 } 6109 6110 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT; 6111 6112 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6113 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 6114 ioc_err(mrioc, "sas io unit page1 write persistent failed\n"); 6115 goto out_failed; 6116 } 6117 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6118 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n", 6119 ioc_status); 6120 goto out_failed; 6121 } 6122 return 0; 6123 out_failed: 6124 return -1; 6125 } 6126 6127 /** 6128 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1 6129 * @mrioc: Adapter instance reference 6130 * @driver_pg1: Pointer to return Driver page 1 6131 * @pg_sz: Size of the memory allocated to the page pointer 6132 * 6133 * This is handler for config page read for the Driver page1. 6134 * This routine checks ioc_status to decide whether the page 6135 * read is success or not. 6136 * 6137 * Return: 0 on success, non-zero on failure. 6138 */ 6139 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 6140 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz) 6141 { 6142 struct mpi3_config_page_header cfg_hdr; 6143 struct mpi3_config_request cfg_req; 6144 u16 ioc_status = 0; 6145 6146 memset(driver_pg1, 0, pg_sz); 6147 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6148 memset(&cfg_req, 0, sizeof(cfg_req)); 6149 6150 cfg_req.function = MPI3_FUNCTION_CONFIG; 6151 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6152 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER; 6153 cfg_req.page_number = 1; 6154 cfg_req.page_address = 0; 6155 6156 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6157 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6158 ioc_err(mrioc, "driver page1 header read failed\n"); 6159 goto out_failed; 6160 } 6161 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6162 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n", 6163 ioc_status); 6164 goto out_failed; 6165 } 6166 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6167 6168 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6169 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) { 6170 ioc_err(mrioc, "driver page1 read failed\n"); 6171 goto out_failed; 6172 } 6173 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6174 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n", 6175 ioc_status); 6176 goto out_failed; 6177 } 6178 return 0; 6179 out_failed: 6180 return -1; 6181 } 6182 6183 /** 6184 * mpi3mr_cfg_get_driver_pg2 - Read current driver page2 6185 * @mrioc: Adapter instance reference 6186 * @driver_pg2: Pointer to return driver page 2 6187 * @pg_sz: Size of the memory allocated to the page pointer 6188 * @page_action: Page action 6189 * 6190 * This is handler for config page read for the driver page2. 6191 * This routine checks ioc_status to decide whether the page 6192 * read is success or not. 6193 * 6194 * Return: 0 on success, non-zero on failure. 6195 */ 6196 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc, 6197 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_action) 6198 { 6199 struct mpi3_config_page_header cfg_hdr; 6200 struct mpi3_config_request cfg_req; 6201 u16 ioc_status = 0; 6202 6203 memset(driver_pg2, 0, pg_sz); 6204 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6205 memset(&cfg_req, 0, sizeof(cfg_req)); 6206 6207 cfg_req.function = MPI3_FUNCTION_CONFIG; 6208 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6209 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER; 6210 cfg_req.page_number = 2; 6211 cfg_req.page_address = 0; 6212 cfg_req.page_version = MPI3_DRIVER2_PAGEVERSION; 6213 6214 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6215 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6216 ioc_err(mrioc, "driver page2 header read failed\n"); 6217 goto out_failed; 6218 } 6219 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6220 ioc_err(mrioc, "driver page2 header read failed with\n" 6221 "ioc_status(0x%04x)\n", 6222 ioc_status); 6223 goto out_failed; 6224 } 6225 cfg_req.action = page_action; 6226 6227 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6228 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg2, pg_sz)) { 6229 ioc_err(mrioc, "driver page2 read failed\n"); 6230 goto out_failed; 6231 } 6232 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6233 ioc_err(mrioc, "driver page2 read failed with\n" 6234 "ioc_status(0x%04x)\n", 6235 ioc_status); 6236 goto out_failed; 6237 } 6238 return 0; 6239 out_failed: 6240 return -1; 6241 } 6242 6243