1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10 #include "mpi3mr.h"
11 #include <linux/io-64-nonatomic-lo-hi.h>
12
13 static int
14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason);
15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
17 struct mpi3_ioc_facts_data *facts_data);
18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
19 struct mpi3mr_drv_cmd *drv_cmd);
20
21 static int poll_queues;
22 module_param(poll_queues, int, 0444);
23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
24
25 #if defined(writeq) && defined(CONFIG_64BIT)
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
27 {
28 writeq(b, addr);
29 }
30 #else
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
32 {
33 __u64 data_out = b;
34
35 writel((u32)(data_out), addr);
36 writel((u32)(data_out >> 32), (addr + 4));
37 }
38 #endif
39
40 static inline bool
mpi3mr_check_req_qfull(struct op_req_qinfo * op_req_q)41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
42 {
43 u16 pi, ci, max_entries;
44 bool is_qfull = false;
45
46 pi = op_req_q->pi;
47 ci = READ_ONCE(op_req_q->ci);
48 max_entries = op_req_q->num_requests;
49
50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
51 is_qfull = true;
52
53 return is_qfull;
54 }
55
mpi3mr_sync_irqs(struct mpi3mr_ioc * mrioc)56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
57 {
58 u16 i, max_vectors;
59
60 max_vectors = mrioc->intr_info_count;
61
62 for (i = 0; i < max_vectors; i++)
63 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
64 }
65
mpi3mr_ioc_disable_intr(struct mpi3mr_ioc * mrioc)66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
67 {
68 mrioc->intr_enabled = 0;
69 mpi3mr_sync_irqs(mrioc);
70 }
71
mpi3mr_ioc_enable_intr(struct mpi3mr_ioc * mrioc)72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
73 {
74 mrioc->intr_enabled = 1;
75 }
76
mpi3mr_cleanup_isr(struct mpi3mr_ioc * mrioc)77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
78 {
79 u16 i;
80
81 mpi3mr_ioc_disable_intr(mrioc);
82
83 if (!mrioc->intr_info)
84 return;
85
86 for (i = 0; i < mrioc->intr_info_count; i++)
87 free_irq(pci_irq_vector(mrioc->pdev, i),
88 (mrioc->intr_info + i));
89
90 kfree(mrioc->intr_info);
91 mrioc->intr_info = NULL;
92 mrioc->intr_info_count = 0;
93 mrioc->is_intr_info_set = false;
94 pci_free_irq_vectors(mrioc->pdev);
95 }
96
mpi3mr_add_sg_single(void * paddr,u8 flags,u32 length,dma_addr_t dma_addr)97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
98 dma_addr_t dma_addr)
99 {
100 struct mpi3_sge_common *sgel = paddr;
101
102 sgel->flags = flags;
103 sgel->length = cpu_to_le32(length);
104 sgel->address = cpu_to_le64(dma_addr);
105 }
106
mpi3mr_build_zero_len_sge(void * paddr)107 void mpi3mr_build_zero_len_sge(void *paddr)
108 {
109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
110
111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
112 }
113
mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
116 {
117 if (!phys_addr)
118 return NULL;
119
120 if ((phys_addr < mrioc->reply_buf_dma) ||
121 (phys_addr > mrioc->reply_buf_dma_max_address))
122 return NULL;
123
124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
125 }
126
mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
128 dma_addr_t phys_addr)
129 {
130 if (!phys_addr)
131 return NULL;
132
133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
134 }
135
mpi3mr_repost_reply_buf(struct mpi3mr_ioc * mrioc,u64 reply_dma)136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
137 u64 reply_dma)
138 {
139 u32 old_idx = 0;
140 unsigned long flags;
141
142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
143 old_idx = mrioc->reply_free_queue_host_index;
144 mrioc->reply_free_queue_host_index = (
145 (mrioc->reply_free_queue_host_index ==
146 (mrioc->reply_free_qsz - 1)) ? 0 :
147 (mrioc->reply_free_queue_host_index + 1));
148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
149 writel(mrioc->reply_free_queue_host_index,
150 &mrioc->sysif_regs->reply_free_host_index);
151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
152 }
153
mpi3mr_repost_sense_buf(struct mpi3mr_ioc * mrioc,u64 sense_buf_dma)154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
155 u64 sense_buf_dma)
156 {
157 u32 old_idx = 0;
158 unsigned long flags;
159
160 spin_lock_irqsave(&mrioc->sbq_lock, flags);
161 old_idx = mrioc->sbq_host_index;
162 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
163 (mrioc->sense_buf_q_sz - 1)) ? 0 :
164 (mrioc->sbq_host_index + 1));
165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
166 writel(mrioc->sbq_host_index,
167 &mrioc->sysif_regs->sense_buffer_free_host_index);
168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
169 }
170
mpi3mr_print_event_data(struct mpi3mr_ioc * mrioc,struct mpi3_event_notification_reply * event_reply)171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
172 struct mpi3_event_notification_reply *event_reply)
173 {
174 char *desc = NULL;
175 u16 event;
176
177 event = event_reply->event;
178
179 switch (event) {
180 case MPI3_EVENT_LOG_DATA:
181 desc = "Log Data";
182 break;
183 case MPI3_EVENT_CHANGE:
184 desc = "Event Change";
185 break;
186 case MPI3_EVENT_GPIO_INTERRUPT:
187 desc = "GPIO Interrupt";
188 break;
189 case MPI3_EVENT_CABLE_MGMT:
190 desc = "Cable Management";
191 break;
192 case MPI3_EVENT_ENERGY_PACK_CHANGE:
193 desc = "Energy Pack Change";
194 break;
195 case MPI3_EVENT_DEVICE_ADDED:
196 {
197 struct mpi3_device_page0 *event_data =
198 (struct mpi3_device_page0 *)event_reply->event_data;
199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
200 event_data->dev_handle, event_data->device_form);
201 return;
202 }
203 case MPI3_EVENT_DEVICE_INFO_CHANGED:
204 {
205 struct mpi3_device_page0 *event_data =
206 (struct mpi3_device_page0 *)event_reply->event_data;
207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
208 event_data->dev_handle, event_data->device_form);
209 return;
210 }
211 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
212 {
213 struct mpi3_event_data_device_status_change *event_data =
214 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
216 event_data->dev_handle, event_data->reason_code);
217 return;
218 }
219 case MPI3_EVENT_SAS_DISCOVERY:
220 {
221 struct mpi3_event_data_sas_discovery *event_data =
222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
225 "start" : "stop",
226 le32_to_cpu(event_data->discovery_status));
227 return;
228 }
229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
230 desc = "SAS Broadcast Primitive";
231 break;
232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
233 desc = "SAS Notify Primitive";
234 break;
235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
236 desc = "SAS Init Device Status Change";
237 break;
238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
239 desc = "SAS Init Table Overflow";
240 break;
241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
242 desc = "SAS Topology Change List";
243 break;
244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
245 desc = "Enclosure Device Status Change";
246 break;
247 case MPI3_EVENT_ENCL_DEVICE_ADDED:
248 desc = "Enclosure Added";
249 break;
250 case MPI3_EVENT_HARD_RESET_RECEIVED:
251 desc = "Hard Reset Received";
252 break;
253 case MPI3_EVENT_SAS_PHY_COUNTER:
254 desc = "SAS PHY Counter";
255 break;
256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
257 desc = "SAS Device Discovery Error";
258 break;
259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
260 desc = "PCIE Topology Change List";
261 break;
262 case MPI3_EVENT_PCIE_ENUMERATION:
263 {
264 struct mpi3_event_data_pcie_enumeration *event_data =
265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
266 ioc_info(mrioc, "PCIE Enumeration: (%s)",
267 (event_data->reason_code ==
268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
269 if (event_data->enumeration_status)
270 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
271 le32_to_cpu(event_data->enumeration_status));
272 return;
273 }
274 case MPI3_EVENT_PREPARE_FOR_RESET:
275 desc = "Prepare For Reset";
276 break;
277 case MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE:
278 desc = "Diagnostic Buffer Status Change";
279 break;
280 }
281
282 if (!desc)
283 return;
284
285 ioc_info(mrioc, "%s\n", desc);
286 }
287
mpi3mr_handle_events(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply * def_reply)288 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
289 struct mpi3_default_reply *def_reply)
290 {
291 struct mpi3_event_notification_reply *event_reply =
292 (struct mpi3_event_notification_reply *)def_reply;
293
294 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
295 mpi3mr_print_event_data(mrioc, event_reply);
296 mpi3mr_os_handle_events(mrioc, event_reply);
297 }
298
299 static struct mpi3mr_drv_cmd *
mpi3mr_get_drv_cmd(struct mpi3mr_ioc * mrioc,u16 host_tag,struct mpi3_default_reply * def_reply)300 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
301 struct mpi3_default_reply *def_reply)
302 {
303 u16 idx;
304
305 switch (host_tag) {
306 case MPI3MR_HOSTTAG_INITCMDS:
307 return &mrioc->init_cmds;
308 case MPI3MR_HOSTTAG_CFG_CMDS:
309 return &mrioc->cfg_cmds;
310 case MPI3MR_HOSTTAG_BSG_CMDS:
311 return &mrioc->bsg_cmds;
312 case MPI3MR_HOSTTAG_BLK_TMS:
313 return &mrioc->host_tm_cmds;
314 case MPI3MR_HOSTTAG_PEL_ABORT:
315 return &mrioc->pel_abort_cmd;
316 case MPI3MR_HOSTTAG_PEL_WAIT:
317 return &mrioc->pel_cmds;
318 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
319 return &mrioc->transport_cmds;
320 case MPI3MR_HOSTTAG_INVALID:
321 if (def_reply && def_reply->function ==
322 MPI3_FUNCTION_EVENT_NOTIFICATION)
323 mpi3mr_handle_events(mrioc, def_reply);
324 return NULL;
325 default:
326 break;
327 }
328 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
329 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
330 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
331 return &mrioc->dev_rmhs_cmds[idx];
332 }
333
334 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
335 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
336 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
337 return &mrioc->evtack_cmds[idx];
338 }
339
340 return NULL;
341 }
342
mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply_descriptor * reply_desc,u64 * reply_dma)343 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
344 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
345 {
346 u16 reply_desc_type, host_tag = 0;
347 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
348 u16 masked_ioc_status = MPI3_IOCSTATUS_SUCCESS;
349 u32 ioc_loginfo = 0, sense_count = 0;
350 struct mpi3_status_reply_descriptor *status_desc;
351 struct mpi3_address_reply_descriptor *addr_desc;
352 struct mpi3_success_reply_descriptor *success_desc;
353 struct mpi3_default_reply *def_reply = NULL;
354 struct mpi3mr_drv_cmd *cmdptr = NULL;
355 struct mpi3_scsi_io_reply *scsi_reply;
356 struct scsi_sense_hdr sshdr;
357 u8 *sense_buf = NULL;
358
359 *reply_dma = 0;
360 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
361 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
362 switch (reply_desc_type) {
363 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
364 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
365 host_tag = le16_to_cpu(status_desc->host_tag);
366 ioc_status = le16_to_cpu(status_desc->ioc_status);
367 if (ioc_status &
368 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
369 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
370 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
371 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
372 break;
373 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
374 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
375 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
376 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
377 if (!def_reply)
378 goto out;
379 host_tag = le16_to_cpu(def_reply->host_tag);
380 ioc_status = le16_to_cpu(def_reply->ioc_status);
381 if (ioc_status &
382 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
383 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
384 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
385 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
386 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
387 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
388 le64_to_cpu(scsi_reply->sense_data_buffer_address));
389 sense_count = le32_to_cpu(scsi_reply->sense_count);
390 if (sense_buf) {
391 scsi_normalize_sense(sense_buf, sense_count,
392 &sshdr);
393 mpi3mr_scsisense_trigger(mrioc, sshdr.sense_key,
394 sshdr.asc, sshdr.ascq);
395 }
396 }
397 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
398 break;
399 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
400 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
401 host_tag = le16_to_cpu(success_desc->host_tag);
402 break;
403 default:
404 break;
405 }
406
407 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
408 if (cmdptr) {
409 if (cmdptr->state & MPI3MR_CMD_PENDING) {
410 cmdptr->state |= MPI3MR_CMD_COMPLETE;
411 cmdptr->ioc_loginfo = ioc_loginfo;
412 if (host_tag == MPI3MR_HOSTTAG_BSG_CMDS)
413 cmdptr->ioc_status = ioc_status;
414 else
415 cmdptr->ioc_status = masked_ioc_status;
416 cmdptr->state &= ~MPI3MR_CMD_PENDING;
417 if (def_reply) {
418 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
419 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
420 mrioc->reply_sz);
421 }
422 if (sense_buf && cmdptr->sensebuf) {
423 cmdptr->is_sense = 1;
424 memcpy(cmdptr->sensebuf, sense_buf,
425 MPI3MR_SENSE_BUF_SZ);
426 }
427 if (cmdptr->is_waiting) {
428 complete(&cmdptr->done);
429 cmdptr->is_waiting = 0;
430 } else if (cmdptr->callback)
431 cmdptr->callback(mrioc, cmdptr);
432 }
433 }
434 out:
435 if (sense_buf)
436 mpi3mr_repost_sense_buf(mrioc,
437 le64_to_cpu(scsi_reply->sense_data_buffer_address));
438 }
439
mpi3mr_process_admin_reply_q(struct mpi3mr_ioc * mrioc)440 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
441 {
442 u32 exp_phase = mrioc->admin_reply_ephase;
443 u32 admin_reply_ci = mrioc->admin_reply_ci;
444 u32 num_admin_replies = 0;
445 u64 reply_dma = 0;
446 u16 threshold_comps = 0;
447 struct mpi3_default_reply_descriptor *reply_desc;
448
449 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
450 return 0;
451
452 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
453 admin_reply_ci;
454
455 if ((le16_to_cpu(reply_desc->reply_flags) &
456 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
457 atomic_dec(&mrioc->admin_reply_q_in_use);
458 return 0;
459 }
460
461 do {
462 if (mrioc->unrecoverable)
463 break;
464
465 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
466 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
467 if (reply_dma)
468 mpi3mr_repost_reply_buf(mrioc, reply_dma);
469 num_admin_replies++;
470 threshold_comps++;
471 if (++admin_reply_ci == mrioc->num_admin_replies) {
472 admin_reply_ci = 0;
473 exp_phase ^= 1;
474 }
475 reply_desc =
476 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
477 admin_reply_ci;
478 if ((le16_to_cpu(reply_desc->reply_flags) &
479 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
480 break;
481 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
482 writel(admin_reply_ci,
483 &mrioc->sysif_regs->admin_reply_queue_ci);
484 threshold_comps = 0;
485 }
486 } while (1);
487
488 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
489 mrioc->admin_reply_ci = admin_reply_ci;
490 mrioc->admin_reply_ephase = exp_phase;
491 atomic_dec(&mrioc->admin_reply_q_in_use);
492
493 return num_admin_replies;
494 }
495
496 /**
497 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
498 * queue's consumer index from operational reply descriptor queue.
499 * @op_reply_q: op_reply_qinfo object
500 * @reply_ci: operational reply descriptor's queue consumer index
501 *
502 * Returns: reply descriptor frame address
503 */
504 static inline struct mpi3_default_reply_descriptor *
mpi3mr_get_reply_desc(struct op_reply_qinfo * op_reply_q,u32 reply_ci)505 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
506 {
507 void *segment_base_addr;
508 struct segments *segments = op_reply_q->q_segments;
509 struct mpi3_default_reply_descriptor *reply_desc = NULL;
510
511 segment_base_addr =
512 segments[reply_ci / op_reply_q->segment_qd].segment;
513 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
514 (reply_ci % op_reply_q->segment_qd);
515 return reply_desc;
516 }
517
518 /**
519 * mpi3mr_process_op_reply_q - Operational reply queue handler
520 * @mrioc: Adapter instance reference
521 * @op_reply_q: Operational reply queue info
522 *
523 * Checks the specific operational reply queue and drains the
524 * reply queue entries until the queue is empty and process the
525 * individual reply descriptors.
526 *
527 * Return: 0 if queue is already processed,or number of reply
528 * descriptors processed.
529 */
mpi3mr_process_op_reply_q(struct mpi3mr_ioc * mrioc,struct op_reply_qinfo * op_reply_q)530 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
531 struct op_reply_qinfo *op_reply_q)
532 {
533 struct op_req_qinfo *op_req_q;
534 u32 exp_phase;
535 u32 reply_ci;
536 u32 num_op_reply = 0;
537 u64 reply_dma = 0;
538 struct mpi3_default_reply_descriptor *reply_desc;
539 u16 req_q_idx = 0, reply_qidx, threshold_comps = 0;
540
541 reply_qidx = op_reply_q->qid - 1;
542
543 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
544 return 0;
545
546 exp_phase = op_reply_q->ephase;
547 reply_ci = op_reply_q->ci;
548
549 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
550 if ((le16_to_cpu(reply_desc->reply_flags) &
551 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
552 atomic_dec(&op_reply_q->in_use);
553 return 0;
554 }
555
556 do {
557 if (mrioc->unrecoverable)
558 break;
559
560 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
561 op_req_q = &mrioc->req_qinfo[req_q_idx];
562
563 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
564 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
565 reply_qidx);
566 atomic_dec(&op_reply_q->pend_ios);
567 if (reply_dma)
568 mpi3mr_repost_reply_buf(mrioc, reply_dma);
569 num_op_reply++;
570 threshold_comps++;
571
572 if (++reply_ci == op_reply_q->num_replies) {
573 reply_ci = 0;
574 exp_phase ^= 1;
575 }
576
577 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
578
579 if ((le16_to_cpu(reply_desc->reply_flags) &
580 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
581 break;
582 #ifndef CONFIG_PREEMPT_RT
583 /*
584 * Exit completion loop to avoid CPU lockup
585 * Ensure remaining completion happens from threaded ISR.
586 */
587 if (num_op_reply > mrioc->max_host_ios) {
588 op_reply_q->enable_irq_poll = true;
589 break;
590 }
591 #endif
592 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
593 writel(reply_ci,
594 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
595 atomic_sub(threshold_comps, &op_reply_q->pend_ios);
596 threshold_comps = 0;
597 }
598 } while (1);
599
600 writel(reply_ci,
601 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
602 op_reply_q->ci = reply_ci;
603 op_reply_q->ephase = exp_phase;
604 atomic_sub(threshold_comps, &op_reply_q->pend_ios);
605 atomic_dec(&op_reply_q->in_use);
606 return num_op_reply;
607 }
608
609 /**
610 * mpi3mr_blk_mq_poll - Operational reply queue handler
611 * @shost: SCSI Host reference
612 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
613 *
614 * Checks the specific operational reply queue and drains the
615 * reply queue entries until the queue is empty and process the
616 * individual reply descriptors.
617 *
618 * Return: 0 if queue is already processed,or number of reply
619 * descriptors processed.
620 */
mpi3mr_blk_mq_poll(struct Scsi_Host * shost,unsigned int queue_num)621 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
622 {
623 int num_entries = 0;
624 struct mpi3mr_ioc *mrioc;
625
626 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
627
628 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
629 mrioc->unrecoverable || mrioc->pci_err_recovery))
630 return 0;
631
632 num_entries = mpi3mr_process_op_reply_q(mrioc,
633 &mrioc->op_reply_qinfo[queue_num]);
634
635 return num_entries;
636 }
637
mpi3mr_isr_primary(int irq,void * privdata)638 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
639 {
640 struct mpi3mr_intr_info *intr_info = privdata;
641 struct mpi3mr_ioc *mrioc;
642 u16 midx;
643 u32 num_admin_replies = 0, num_op_reply = 0;
644
645 if (!intr_info)
646 return IRQ_NONE;
647
648 mrioc = intr_info->mrioc;
649
650 if (!mrioc->intr_enabled)
651 return IRQ_NONE;
652
653 midx = intr_info->msix_index;
654
655 if (!midx)
656 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
657 if (intr_info->op_reply_q)
658 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
659 intr_info->op_reply_q);
660
661 if (num_admin_replies || num_op_reply)
662 return IRQ_HANDLED;
663 else
664 return IRQ_NONE;
665 }
666
667 #ifndef CONFIG_PREEMPT_RT
668
mpi3mr_isr(int irq,void * privdata)669 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
670 {
671 struct mpi3mr_intr_info *intr_info = privdata;
672 int ret;
673
674 if (!intr_info)
675 return IRQ_NONE;
676
677 /* Call primary ISR routine */
678 ret = mpi3mr_isr_primary(irq, privdata);
679
680 /*
681 * If more IOs are expected, schedule IRQ polling thread.
682 * Otherwise exit from ISR.
683 */
684 if (!intr_info->op_reply_q)
685 return ret;
686
687 if (!intr_info->op_reply_q->enable_irq_poll ||
688 !atomic_read(&intr_info->op_reply_q->pend_ios))
689 return ret;
690
691 disable_irq_nosync(intr_info->os_irq);
692
693 return IRQ_WAKE_THREAD;
694 }
695
696 /**
697 * mpi3mr_isr_poll - Reply queue polling routine
698 * @irq: IRQ
699 * @privdata: Interrupt info
700 *
701 * poll for pending I/O completions in a loop until pending I/Os
702 * present or controller queue depth I/Os are processed.
703 *
704 * Return: IRQ_NONE or IRQ_HANDLED
705 */
mpi3mr_isr_poll(int irq,void * privdata)706 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
707 {
708 struct mpi3mr_intr_info *intr_info = privdata;
709 struct mpi3mr_ioc *mrioc;
710 u16 midx;
711 u32 num_op_reply = 0;
712
713 if (!intr_info || !intr_info->op_reply_q)
714 return IRQ_NONE;
715
716 mrioc = intr_info->mrioc;
717 midx = intr_info->msix_index;
718
719 /* Poll for pending IOs completions */
720 do {
721 if (!mrioc->intr_enabled || mrioc->unrecoverable)
722 break;
723
724 if (!midx)
725 mpi3mr_process_admin_reply_q(mrioc);
726 if (intr_info->op_reply_q)
727 num_op_reply +=
728 mpi3mr_process_op_reply_q(mrioc,
729 intr_info->op_reply_q);
730
731 usleep_range(MPI3MR_IRQ_POLL_SLEEP, MPI3MR_IRQ_POLL_SLEEP + 1);
732
733 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
734 (num_op_reply < mrioc->max_host_ios));
735
736 intr_info->op_reply_q->enable_irq_poll = false;
737 enable_irq(intr_info->os_irq);
738
739 return IRQ_HANDLED;
740 }
741
742 #endif
743
744 /**
745 * mpi3mr_request_irq - Request IRQ and register ISR
746 * @mrioc: Adapter instance reference
747 * @index: IRQ vector index
748 *
749 * Request threaded ISR with primary ISR and secondary
750 *
751 * Return: 0 on success and non zero on failures.
752 */
mpi3mr_request_irq(struct mpi3mr_ioc * mrioc,u16 index)753 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
754 {
755 struct pci_dev *pdev = mrioc->pdev;
756 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
757 int retval = 0;
758
759 intr_info->mrioc = mrioc;
760 intr_info->msix_index = index;
761 intr_info->op_reply_q = NULL;
762
763 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
764 mrioc->driver_name, mrioc->id, index);
765
766 #ifndef CONFIG_PREEMPT_RT
767 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
768 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
769 #else
770 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
771 NULL, IRQF_SHARED, intr_info->name, intr_info);
772 #endif
773 if (retval) {
774 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
775 intr_info->name, pci_irq_vector(pdev, index));
776 return retval;
777 }
778
779 intr_info->os_irq = pci_irq_vector(pdev, index);
780 return retval;
781 }
782
mpi3mr_calc_poll_queues(struct mpi3mr_ioc * mrioc,u16 max_vectors)783 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
784 {
785 if (!mrioc->requested_poll_qcount)
786 return;
787
788 /* Reserved for Admin and Default Queue */
789 if (max_vectors > 2 &&
790 (mrioc->requested_poll_qcount < max_vectors - 2)) {
791 ioc_info(mrioc,
792 "enabled polled queues (%d) msix (%d)\n",
793 mrioc->requested_poll_qcount, max_vectors);
794 } else {
795 ioc_info(mrioc,
796 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
797 mrioc->requested_poll_qcount, max_vectors);
798 mrioc->requested_poll_qcount = 0;
799 }
800 }
801
802 /**
803 * mpi3mr_setup_isr - Setup ISR for the controller
804 * @mrioc: Adapter instance reference
805 * @setup_one: Request one IRQ or more
806 *
807 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
808 *
809 * Return: 0 on success and non zero on failures.
810 */
mpi3mr_setup_isr(struct mpi3mr_ioc * mrioc,u8 setup_one)811 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
812 {
813 unsigned int irq_flags = PCI_IRQ_MSIX;
814 int max_vectors, min_vec;
815 int retval;
816 int i;
817 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
818
819 if (mrioc->is_intr_info_set)
820 return 0;
821
822 mpi3mr_cleanup_isr(mrioc);
823
824 if (setup_one || reset_devices) {
825 max_vectors = 1;
826 retval = pci_alloc_irq_vectors(mrioc->pdev,
827 1, max_vectors, irq_flags);
828 if (retval < 0) {
829 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
830 retval);
831 goto out_failed;
832 }
833 } else {
834 max_vectors =
835 min_t(int, mrioc->cpu_count + 1 +
836 mrioc->requested_poll_qcount, mrioc->msix_count);
837
838 mpi3mr_calc_poll_queues(mrioc, max_vectors);
839
840 ioc_info(mrioc,
841 "MSI-X vectors supported: %d, no of cores: %d,",
842 mrioc->msix_count, mrioc->cpu_count);
843 ioc_info(mrioc,
844 "MSI-x vectors requested: %d poll_queues %d\n",
845 max_vectors, mrioc->requested_poll_qcount);
846
847 desc.post_vectors = mrioc->requested_poll_qcount;
848 min_vec = desc.pre_vectors + desc.post_vectors;
849 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
850
851 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
852 min_vec, max_vectors, irq_flags, &desc);
853
854 if (retval < 0) {
855 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
856 retval);
857 goto out_failed;
858 }
859
860
861 /*
862 * If only one MSI-x is allocated, then MSI-x 0 will be shared
863 * between Admin queue and operational queue
864 */
865 if (retval == min_vec)
866 mrioc->op_reply_q_offset = 0;
867 else if (retval != (max_vectors)) {
868 ioc_info(mrioc,
869 "allocated vectors (%d) are less than configured (%d)\n",
870 retval, max_vectors);
871 }
872
873 max_vectors = retval;
874 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
875
876 mpi3mr_calc_poll_queues(mrioc, max_vectors);
877
878 }
879
880 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
881 GFP_KERNEL);
882 if (!mrioc->intr_info) {
883 retval = -ENOMEM;
884 pci_free_irq_vectors(mrioc->pdev);
885 goto out_failed;
886 }
887 for (i = 0; i < max_vectors; i++) {
888 retval = mpi3mr_request_irq(mrioc, i);
889 if (retval) {
890 mrioc->intr_info_count = i;
891 goto out_failed;
892 }
893 }
894 if (reset_devices || !setup_one)
895 mrioc->is_intr_info_set = true;
896 mrioc->intr_info_count = max_vectors;
897 mpi3mr_ioc_enable_intr(mrioc);
898 return 0;
899
900 out_failed:
901 mpi3mr_cleanup_isr(mrioc);
902
903 return retval;
904 }
905
906 static const struct {
907 enum mpi3mr_iocstate value;
908 char *name;
909 } mrioc_states[] = {
910 { MRIOC_STATE_READY, "ready" },
911 { MRIOC_STATE_FAULT, "fault" },
912 { MRIOC_STATE_RESET, "reset" },
913 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
914 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
915 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
916 };
917
mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)918 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
919 {
920 int i;
921 char *name = NULL;
922
923 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
924 if (mrioc_states[i].value == mrioc_state) {
925 name = mrioc_states[i].name;
926 break;
927 }
928 }
929 return name;
930 }
931
932 /* Reset reason to name mapper structure*/
933 static const struct {
934 enum mpi3mr_reset_reason value;
935 char *name;
936 } mpi3mr_reset_reason_codes[] = {
937 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
938 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
939 { MPI3MR_RESET_FROM_APP, "application invocation" },
940 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
941 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
942 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
943 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
944 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
945 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
946 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
947 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
948 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
949 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
950 {
951 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
952 "create request queue timeout"
953 },
954 {
955 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
956 "create reply queue timeout"
957 },
958 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
959 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
960 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
961 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
962 {
963 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
964 "component image activation timeout"
965 },
966 {
967 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
968 "get package version timeout"
969 },
970 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
971 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
972 {
973 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT,
974 "diagnostic buffer post timeout"
975 },
976 {
977 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT,
978 "diagnostic buffer release timeout"
979 },
980 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
981 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
982 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
983 };
984
985 /**
986 * mpi3mr_reset_rc_name - get reset reason code name
987 * @reason_code: reset reason code value
988 *
989 * Map reset reason to an NULL terminated ASCII string
990 *
991 * Return: name corresponding to reset reason value or NULL.
992 */
mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)993 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
994 {
995 int i;
996 char *name = NULL;
997
998 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
999 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
1000 name = mpi3mr_reset_reason_codes[i].name;
1001 break;
1002 }
1003 }
1004 return name;
1005 }
1006
1007 /* Reset type to name mapper structure*/
1008 static const struct {
1009 u16 reset_type;
1010 char *name;
1011 } mpi3mr_reset_types[] = {
1012 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
1013 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
1014 };
1015
1016 /**
1017 * mpi3mr_reset_type_name - get reset type name
1018 * @reset_type: reset type value
1019 *
1020 * Map reset type to an NULL terminated ASCII string
1021 *
1022 * Return: name corresponding to reset type value or NULL.
1023 */
mpi3mr_reset_type_name(u16 reset_type)1024 static const char *mpi3mr_reset_type_name(u16 reset_type)
1025 {
1026 int i;
1027 char *name = NULL;
1028
1029 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
1030 if (mpi3mr_reset_types[i].reset_type == reset_type) {
1031 name = mpi3mr_reset_types[i].name;
1032 break;
1033 }
1034 }
1035 return name;
1036 }
1037
1038 /**
1039 * mpi3mr_print_fault_info - Display fault information
1040 * @mrioc: Adapter instance reference
1041 *
1042 * Display the controller fault information if there is a
1043 * controller fault.
1044 *
1045 * Return: Nothing.
1046 */
mpi3mr_print_fault_info(struct mpi3mr_ioc * mrioc)1047 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1048 {
1049 u32 ioc_status, code, code1, code2, code3;
1050
1051 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1052
1053 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1054 code = readl(&mrioc->sysif_regs->fault);
1055 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1056 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1057 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1058
1059 ioc_info(mrioc,
1060 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1061 code, code1, code2, code3);
1062 }
1063 }
1064
1065 /**
1066 * mpi3mr_get_iocstate - Get IOC State
1067 * @mrioc: Adapter instance reference
1068 *
1069 * Return a proper IOC state enum based on the IOC status and
1070 * IOC configuration and unrcoverable state of the controller.
1071 *
1072 * Return: Current IOC state.
1073 */
mpi3mr_get_iocstate(struct mpi3mr_ioc * mrioc)1074 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1075 {
1076 u32 ioc_status, ioc_config;
1077 u8 ready, enabled;
1078
1079 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1080 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1081
1082 if (mrioc->unrecoverable)
1083 return MRIOC_STATE_UNRECOVERABLE;
1084 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1085 return MRIOC_STATE_FAULT;
1086
1087 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1088 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1089
1090 if (ready && enabled)
1091 return MRIOC_STATE_READY;
1092 if ((!ready) && (!enabled))
1093 return MRIOC_STATE_RESET;
1094 if ((!ready) && (enabled))
1095 return MRIOC_STATE_BECOMING_READY;
1096
1097 return MRIOC_STATE_RESET_REQUESTED;
1098 }
1099
1100 /**
1101 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma
1102 * @mrioc: Adapter instance reference
1103 *
1104 * Free the DMA memory allocated for IOCTL handling purpose.
1105 *
1106 * Return: None
1107 */
mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc * mrioc)1108 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1109 {
1110 struct dma_memory_desc *mem_desc;
1111 u16 i;
1112
1113 if (!mrioc->ioctl_dma_pool)
1114 return;
1115
1116 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1117 mem_desc = &mrioc->ioctl_sge[i];
1118 if (mem_desc->addr) {
1119 dma_pool_free(mrioc->ioctl_dma_pool,
1120 mem_desc->addr,
1121 mem_desc->dma_addr);
1122 mem_desc->addr = NULL;
1123 }
1124 }
1125 dma_pool_destroy(mrioc->ioctl_dma_pool);
1126 mrioc->ioctl_dma_pool = NULL;
1127 mem_desc = &mrioc->ioctl_chain_sge;
1128
1129 if (mem_desc->addr) {
1130 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1131 mem_desc->addr, mem_desc->dma_addr);
1132 mem_desc->addr = NULL;
1133 }
1134 mem_desc = &mrioc->ioctl_resp_sge;
1135 if (mem_desc->addr) {
1136 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1137 mem_desc->addr, mem_desc->dma_addr);
1138 mem_desc->addr = NULL;
1139 }
1140
1141 mrioc->ioctl_sges_allocated = false;
1142 }
1143
1144 /**
1145 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma
1146 * @mrioc: Adapter instance reference
1147 *
1148 * This function allocates dmaable memory required to handle the
1149 * application issued MPI3 IOCTL requests.
1150 *
1151 * Return: None
1152 */
mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc * mrioc)1153 static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1154
1155 {
1156 struct dma_memory_desc *mem_desc;
1157 u16 i;
1158
1159 mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool",
1160 &mrioc->pdev->dev,
1161 MPI3MR_IOCTL_SGE_SIZE,
1162 MPI3MR_PAGE_SIZE_4K, 0);
1163
1164 if (!mrioc->ioctl_dma_pool) {
1165 ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n");
1166 goto out_failed;
1167 }
1168
1169 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1170 mem_desc = &mrioc->ioctl_sge[i];
1171 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE;
1172 mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool,
1173 GFP_KERNEL,
1174 &mem_desc->dma_addr);
1175 if (!mem_desc->addr)
1176 goto out_failed;
1177 }
1178
1179 mem_desc = &mrioc->ioctl_chain_sge;
1180 mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1181 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1182 mem_desc->size,
1183 &mem_desc->dma_addr,
1184 GFP_KERNEL);
1185 if (!mem_desc->addr)
1186 goto out_failed;
1187
1188 mem_desc = &mrioc->ioctl_resp_sge;
1189 mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1190 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1191 mem_desc->size,
1192 &mem_desc->dma_addr,
1193 GFP_KERNEL);
1194 if (!mem_desc->addr)
1195 goto out_failed;
1196
1197 mrioc->ioctl_sges_allocated = true;
1198
1199 return;
1200 out_failed:
1201 ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n"
1202 "from the applications, application interface for MPT command is disabled\n");
1203 mpi3mr_free_ioctl_dma_memory(mrioc);
1204 }
1205
1206 /**
1207 * mpi3mr_clear_reset_history - clear reset history
1208 * @mrioc: Adapter instance reference
1209 *
1210 * Write the reset history bit in IOC status to clear the bit,
1211 * if it is already set.
1212 *
1213 * Return: Nothing.
1214 */
mpi3mr_clear_reset_history(struct mpi3mr_ioc * mrioc)1215 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1216 {
1217 u32 ioc_status;
1218
1219 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1220 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1221 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1222 }
1223
1224 /**
1225 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1226 * @mrioc: Adapter instance reference
1227 * @reset_reason: Reset reason code
1228 *
1229 * Issue Message unit Reset to the controller and wait for it to
1230 * be complete.
1231 *
1232 * Return: 0 on success, -1 on failure.
1233 */
mpi3mr_issue_and_process_mur(struct mpi3mr_ioc * mrioc,u32 reset_reason)1234 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1235 u32 reset_reason)
1236 {
1237 u32 ioc_config, timeout, ioc_status, scratch_pad0;
1238 int retval = -1;
1239
1240 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1241 if (mrioc->unrecoverable) {
1242 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1243 return retval;
1244 }
1245 mpi3mr_clear_reset_history(mrioc);
1246 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1247 MPI3MR_RESET_REASON_OSTYPE_SHIFT) |
1248 (mrioc->facts.ioc_num <<
1249 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1250 writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
1251 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1252 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1253 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1254
1255 timeout = MPI3MR_MUR_TIMEOUT * 10;
1256 do {
1257 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1258 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1259 mpi3mr_clear_reset_history(mrioc);
1260 break;
1261 }
1262 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1263 mpi3mr_print_fault_info(mrioc);
1264 break;
1265 }
1266 msleep(100);
1267 } while (--timeout);
1268
1269 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1270 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1271 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1272 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1273 retval = 0;
1274
1275 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1276 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1277 return retval;
1278 }
1279
1280 /**
1281 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1282 * during reset/resume
1283 * @mrioc: Adapter instance reference
1284 *
1285 * Return: zero if the new IOCFacts parameters value is compatible with
1286 * older values else return -EPERM
1287 */
1288 static int
mpi3mr_revalidate_factsdata(struct mpi3mr_ioc * mrioc)1289 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1290 {
1291 unsigned long *removepend_bitmap;
1292
1293 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1294 ioc_err(mrioc,
1295 "cannot increase reply size from %d to %d\n",
1296 mrioc->reply_sz, mrioc->facts.reply_sz);
1297 return -EPERM;
1298 }
1299
1300 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1301 ioc_err(mrioc,
1302 "cannot reduce number of operational reply queues from %d to %d\n",
1303 mrioc->num_op_reply_q,
1304 mrioc->facts.max_op_reply_q);
1305 return -EPERM;
1306 }
1307
1308 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1309 ioc_err(mrioc,
1310 "cannot reduce number of operational request queues from %d to %d\n",
1311 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1312 return -EPERM;
1313 }
1314
1315 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512))
1316 ioc_err(mrioc, "Warning: The maximum data transfer length\n"
1317 "\tchanged after reset: previous(%d), new(%d),\n"
1318 "the driver cannot change this at run time\n",
1319 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
1320
1321 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1322 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED))
1323 ioc_err(mrioc,
1324 "critical error: multipath capability is enabled at the\n"
1325 "\tcontroller while sas transport support is enabled at the\n"
1326 "\tdriver, please reboot the system or reload the driver\n");
1327
1328 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1329 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1330 GFP_KERNEL);
1331 if (!removepend_bitmap) {
1332 ioc_err(mrioc,
1333 "failed to increase removepend_bitmap bits from %d to %d\n",
1334 mrioc->dev_handle_bitmap_bits,
1335 mrioc->facts.max_devhandle);
1336 return -EPERM;
1337 }
1338 bitmap_free(mrioc->removepend_bitmap);
1339 mrioc->removepend_bitmap = removepend_bitmap;
1340 ioc_info(mrioc,
1341 "increased bits of dev_handle_bitmap from %d to %d\n",
1342 mrioc->dev_handle_bitmap_bits,
1343 mrioc->facts.max_devhandle);
1344 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1345 }
1346
1347 return 0;
1348 }
1349
1350 /**
1351 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1352 * @mrioc: Adapter instance reference
1353 *
1354 * Set Enable IOC bit in IOC configuration register and wait for
1355 * the controller to become ready.
1356 *
1357 * Return: 0 on success, appropriate error on failure.
1358 */
mpi3mr_bring_ioc_ready(struct mpi3mr_ioc * mrioc)1359 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1360 {
1361 u32 ioc_config, ioc_status, timeout, host_diagnostic;
1362 int retval = 0;
1363 enum mpi3mr_iocstate ioc_state;
1364 u64 base_info;
1365 u8 retry = 0;
1366 u64 start_time, elapsed_time_sec;
1367
1368 retry_bring_ioc_ready:
1369
1370 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1371 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1372 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1373 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1374 ioc_status, ioc_config, base_info);
1375
1376 /*The timeout value is in 2sec unit, changing it to seconds*/
1377 mrioc->ready_timeout =
1378 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1379 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1380
1381 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1382
1383 ioc_state = mpi3mr_get_iocstate(mrioc);
1384 ioc_info(mrioc, "controller is in %s state during detection\n",
1385 mpi3mr_iocstate_name(ioc_state));
1386
1387 timeout = mrioc->ready_timeout * 10;
1388
1389 do {
1390 ioc_state = mpi3mr_get_iocstate(mrioc);
1391
1392 if (ioc_state != MRIOC_STATE_BECOMING_READY &&
1393 ioc_state != MRIOC_STATE_RESET_REQUESTED)
1394 break;
1395
1396 if (!pci_device_is_present(mrioc->pdev)) {
1397 mrioc->unrecoverable = 1;
1398 ioc_err(mrioc, "controller is not present while waiting to reset\n");
1399 goto out_device_not_present;
1400 }
1401
1402 msleep(100);
1403 } while (--timeout);
1404
1405 if (ioc_state == MRIOC_STATE_READY) {
1406 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1407 retval = mpi3mr_issue_and_process_mur(mrioc,
1408 MPI3MR_RESET_FROM_BRINGUP);
1409 ioc_state = mpi3mr_get_iocstate(mrioc);
1410 if (retval)
1411 ioc_err(mrioc,
1412 "message unit reset failed with error %d current state %s\n",
1413 retval, mpi3mr_iocstate_name(ioc_state));
1414 }
1415 if (ioc_state != MRIOC_STATE_RESET) {
1416 if (ioc_state == MRIOC_STATE_FAULT) {
1417 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1418 mpi3mr_print_fault_info(mrioc);
1419 do {
1420 host_diagnostic =
1421 readl(&mrioc->sysif_regs->host_diagnostic);
1422 if (!(host_diagnostic &
1423 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1424 break;
1425 if (!pci_device_is_present(mrioc->pdev)) {
1426 mrioc->unrecoverable = 1;
1427 ioc_err(mrioc, "controller is not present at the bringup\n");
1428 goto out_device_not_present;
1429 }
1430 msleep(100);
1431 } while (--timeout);
1432 }
1433 mpi3mr_print_fault_info(mrioc);
1434 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1435 retval = mpi3mr_issue_reset(mrioc,
1436 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1437 MPI3MR_RESET_FROM_BRINGUP);
1438 if (retval) {
1439 ioc_err(mrioc,
1440 "soft reset failed with error %d\n", retval);
1441 goto out_failed;
1442 }
1443 }
1444 ioc_state = mpi3mr_get_iocstate(mrioc);
1445 if (ioc_state != MRIOC_STATE_RESET) {
1446 ioc_err(mrioc,
1447 "cannot bring controller to reset state, current state: %s\n",
1448 mpi3mr_iocstate_name(ioc_state));
1449 goto out_failed;
1450 }
1451 mpi3mr_clear_reset_history(mrioc);
1452 retval = mpi3mr_setup_admin_qpair(mrioc);
1453 if (retval) {
1454 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1455 retval);
1456 goto out_failed;
1457 }
1458
1459 ioc_info(mrioc, "bringing controller to ready state\n");
1460 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1461 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1462 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1463
1464 if (retry == 0)
1465 start_time = jiffies;
1466
1467 timeout = mrioc->ready_timeout * 10;
1468 do {
1469 ioc_state = mpi3mr_get_iocstate(mrioc);
1470 if (ioc_state == MRIOC_STATE_READY) {
1471 ioc_info(mrioc,
1472 "successfully transitioned to %s state\n",
1473 mpi3mr_iocstate_name(ioc_state));
1474 return 0;
1475 }
1476 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1477 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
1478 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
1479 mpi3mr_print_fault_info(mrioc);
1480 goto out_failed;
1481 }
1482 if (!pci_device_is_present(mrioc->pdev)) {
1483 mrioc->unrecoverable = 1;
1484 ioc_err(mrioc,
1485 "controller is not present at the bringup\n");
1486 retval = -1;
1487 goto out_device_not_present;
1488 }
1489 msleep(100);
1490 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1491 } while (elapsed_time_sec < mrioc->ready_timeout);
1492
1493 out_failed:
1494 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1495 if ((retry < 2) && (elapsed_time_sec < (mrioc->ready_timeout - 60))) {
1496 retry++;
1497
1498 ioc_warn(mrioc, "retrying to bring IOC ready, retry_count:%d\n"
1499 " elapsed time =%llu\n", retry, elapsed_time_sec);
1500
1501 goto retry_bring_ioc_ready;
1502 }
1503 ioc_state = mpi3mr_get_iocstate(mrioc);
1504 ioc_err(mrioc,
1505 "failed to bring to ready state, current state: %s\n",
1506 mpi3mr_iocstate_name(ioc_state));
1507 out_device_not_present:
1508 return retval;
1509 }
1510
1511 /**
1512 * mpi3mr_soft_reset_success - Check softreset is success or not
1513 * @ioc_status: IOC status register value
1514 * @ioc_config: IOC config register value
1515 *
1516 * Check whether the soft reset is successful or not based on
1517 * IOC status and IOC config register values.
1518 *
1519 * Return: True when the soft reset is success, false otherwise.
1520 */
1521 static inline bool
mpi3mr_soft_reset_success(u32 ioc_status,u32 ioc_config)1522 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1523 {
1524 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1525 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1526 return true;
1527 return false;
1528 }
1529
1530 /**
1531 * mpi3mr_diagfault_success - Check diag fault is success or not
1532 * @mrioc: Adapter reference
1533 * @ioc_status: IOC status register value
1534 *
1535 * Check whether the controller hit diag reset fault code.
1536 *
1537 * Return: True when there is diag fault, false otherwise.
1538 */
mpi3mr_diagfault_success(struct mpi3mr_ioc * mrioc,u32 ioc_status)1539 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1540 u32 ioc_status)
1541 {
1542 u32 fault;
1543
1544 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1545 return false;
1546 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1547 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1548 mpi3mr_print_fault_info(mrioc);
1549 return true;
1550 }
1551 return false;
1552 }
1553
1554 /**
1555 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1556 * @mrioc: Adapter reference
1557 *
1558 * Set diag save bit in IOC configuration register to enable
1559 * snapdump.
1560 *
1561 * Return: Nothing.
1562 */
mpi3mr_set_diagsave(struct mpi3mr_ioc * mrioc)1563 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1564 {
1565 u32 ioc_config;
1566
1567 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1568 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1569 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1570 }
1571
1572 /**
1573 * mpi3mr_issue_reset - Issue reset to the controller
1574 * @mrioc: Adapter reference
1575 * @reset_type: Reset type
1576 * @reset_reason: Reset reason code
1577 *
1578 * Unlock the host diagnostic registers and write the specific
1579 * reset type to that, wait for reset acknowledgment from the
1580 * controller, if the reset is not successful retry for the
1581 * predefined number of times.
1582 *
1583 * Return: 0 on success, non-zero on failure.
1584 */
mpi3mr_issue_reset(struct mpi3mr_ioc * mrioc,u16 reset_type,u16 reset_reason)1585 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1586 u16 reset_reason)
1587 {
1588 int retval = -1;
1589 u8 unlock_retry_count = 0;
1590 u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0;
1591 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1592
1593 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1594 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1595 return retval;
1596 if (mrioc->unrecoverable)
1597 return retval;
1598 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1599 retval = 0;
1600 return retval;
1601 }
1602
1603 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1604 mpi3mr_reset_type_name(reset_type),
1605 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1606
1607 mpi3mr_clear_reset_history(mrioc);
1608 do {
1609 ioc_info(mrioc,
1610 "Write magic sequence to unlock host diag register (retry=%d)\n",
1611 ++unlock_retry_count);
1612 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1613 ioc_err(mrioc,
1614 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1615 mpi3mr_reset_type_name(reset_type),
1616 host_diagnostic);
1617 mrioc->unrecoverable = 1;
1618 return retval;
1619 }
1620
1621 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1622 &mrioc->sysif_regs->write_sequence);
1623 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1624 &mrioc->sysif_regs->write_sequence);
1625 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1626 &mrioc->sysif_regs->write_sequence);
1627 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1628 &mrioc->sysif_regs->write_sequence);
1629 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1630 &mrioc->sysif_regs->write_sequence);
1631 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1632 &mrioc->sysif_regs->write_sequence);
1633 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1634 &mrioc->sysif_regs->write_sequence);
1635 usleep_range(1000, 1100);
1636 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1637 ioc_info(mrioc,
1638 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1639 unlock_retry_count, host_diagnostic);
1640 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1641
1642 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1643 MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num <<
1644 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1645 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1646 writel(host_diagnostic | reset_type,
1647 &mrioc->sysif_regs->host_diagnostic);
1648 switch (reset_type) {
1649 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1650 do {
1651 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1652 ioc_config =
1653 readl(&mrioc->sysif_regs->ioc_configuration);
1654 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1655 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1656 ) {
1657 mpi3mr_clear_reset_history(mrioc);
1658 retval = 0;
1659 break;
1660 }
1661 msleep(100);
1662 } while (--timeout);
1663 mpi3mr_print_fault_info(mrioc);
1664 break;
1665 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1666 do {
1667 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1668 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1669 retval = 0;
1670 break;
1671 }
1672 msleep(100);
1673 } while (--timeout);
1674 break;
1675 default:
1676 break;
1677 }
1678
1679 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1680 &mrioc->sysif_regs->write_sequence);
1681
1682 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1683 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1684 ioc_info(mrioc,
1685 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1686 (!retval)?"successful":"failed", ioc_status,
1687 ioc_config);
1688 if (retval)
1689 mrioc->unrecoverable = 1;
1690 return retval;
1691 }
1692
1693 /**
1694 * mpi3mr_admin_request_post - Post request to admin queue
1695 * @mrioc: Adapter reference
1696 * @admin_req: MPI3 request
1697 * @admin_req_sz: Request size
1698 * @ignore_reset: Ignore reset in process
1699 *
1700 * Post the MPI3 request into admin request queue and
1701 * inform the controller, if the queue is full return
1702 * appropriate error.
1703 *
1704 * Return: 0 on success, non-zero on failure.
1705 */
mpi3mr_admin_request_post(struct mpi3mr_ioc * mrioc,void * admin_req,u16 admin_req_sz,u8 ignore_reset)1706 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1707 u16 admin_req_sz, u8 ignore_reset)
1708 {
1709 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1710 int retval = 0;
1711 unsigned long flags;
1712 u8 *areq_entry;
1713
1714 if (mrioc->unrecoverable) {
1715 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1716 return -EFAULT;
1717 }
1718
1719 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1720 areq_pi = mrioc->admin_req_pi;
1721 areq_ci = mrioc->admin_req_ci;
1722 max_entries = mrioc->num_admin_req;
1723 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1724 (areq_pi == (max_entries - 1)))) {
1725 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1726 retval = -EAGAIN;
1727 goto out;
1728 }
1729 if (!ignore_reset && mrioc->reset_in_progress) {
1730 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1731 retval = -EAGAIN;
1732 goto out;
1733 }
1734 if (mrioc->pci_err_recovery) {
1735 ioc_err(mrioc, "admin request queue submission failed due to pci error recovery in progress\n");
1736 retval = -EAGAIN;
1737 goto out;
1738 }
1739
1740 areq_entry = (u8 *)mrioc->admin_req_base +
1741 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1742 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1743 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1744
1745 if (++areq_pi == max_entries)
1746 areq_pi = 0;
1747 mrioc->admin_req_pi = areq_pi;
1748
1749 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1750
1751 out:
1752 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1753
1754 return retval;
1755 }
1756
1757 /**
1758 * mpi3mr_free_op_req_q_segments - free request memory segments
1759 * @mrioc: Adapter instance reference
1760 * @q_idx: operational request queue index
1761 *
1762 * Free memory segments allocated for operational request queue
1763 *
1764 * Return: Nothing.
1765 */
mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1766 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1767 {
1768 u16 j;
1769 int size;
1770 struct segments *segments;
1771
1772 segments = mrioc->req_qinfo[q_idx].q_segments;
1773 if (!segments)
1774 return;
1775
1776 if (mrioc->enable_segqueue) {
1777 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1778 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1779 dma_free_coherent(&mrioc->pdev->dev,
1780 MPI3MR_MAX_SEG_LIST_SIZE,
1781 mrioc->req_qinfo[q_idx].q_segment_list,
1782 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1783 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1784 }
1785 } else
1786 size = mrioc->req_qinfo[q_idx].segment_qd *
1787 mrioc->facts.op_req_sz;
1788
1789 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1790 if (!segments[j].segment)
1791 continue;
1792 dma_free_coherent(&mrioc->pdev->dev,
1793 size, segments[j].segment, segments[j].segment_dma);
1794 segments[j].segment = NULL;
1795 }
1796 kfree(mrioc->req_qinfo[q_idx].q_segments);
1797 mrioc->req_qinfo[q_idx].q_segments = NULL;
1798 mrioc->req_qinfo[q_idx].qid = 0;
1799 }
1800
1801 /**
1802 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1803 * @mrioc: Adapter instance reference
1804 * @q_idx: operational reply queue index
1805 *
1806 * Free memory segments allocated for operational reply queue
1807 *
1808 * Return: Nothing.
1809 */
mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1810 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1811 {
1812 u16 j;
1813 int size;
1814 struct segments *segments;
1815
1816 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1817 if (!segments)
1818 return;
1819
1820 if (mrioc->enable_segqueue) {
1821 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1822 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1823 dma_free_coherent(&mrioc->pdev->dev,
1824 MPI3MR_MAX_SEG_LIST_SIZE,
1825 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1826 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1827 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1828 }
1829 } else
1830 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1831 mrioc->op_reply_desc_sz;
1832
1833 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1834 if (!segments[j].segment)
1835 continue;
1836 dma_free_coherent(&mrioc->pdev->dev,
1837 size, segments[j].segment, segments[j].segment_dma);
1838 segments[j].segment = NULL;
1839 }
1840
1841 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1842 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1843 mrioc->op_reply_qinfo[q_idx].qid = 0;
1844 }
1845
1846 /**
1847 * mpi3mr_delete_op_reply_q - delete operational reply queue
1848 * @mrioc: Adapter instance reference
1849 * @qidx: operational reply queue index
1850 *
1851 * Delete operatinal reply queue by issuing MPI request
1852 * through admin queue.
1853 *
1854 * Return: 0 on success, non-zero on failure.
1855 */
mpi3mr_delete_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1856 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1857 {
1858 struct mpi3_delete_reply_queue_request delq_req;
1859 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1860 int retval = 0;
1861 u16 reply_qid = 0, midx;
1862
1863 reply_qid = op_reply_q->qid;
1864
1865 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1866
1867 if (!reply_qid) {
1868 retval = -1;
1869 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1870 goto out;
1871 }
1872
1873 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1874 mrioc->active_poll_qcount--;
1875
1876 memset(&delq_req, 0, sizeof(delq_req));
1877 mutex_lock(&mrioc->init_cmds.mutex);
1878 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1879 retval = -1;
1880 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1881 mutex_unlock(&mrioc->init_cmds.mutex);
1882 goto out;
1883 }
1884 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1885 mrioc->init_cmds.is_waiting = 1;
1886 mrioc->init_cmds.callback = NULL;
1887 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1888 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1889 delq_req.queue_id = cpu_to_le16(reply_qid);
1890
1891 init_completion(&mrioc->init_cmds.done);
1892 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1893 1);
1894 if (retval) {
1895 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1896 goto out_unlock;
1897 }
1898 wait_for_completion_timeout(&mrioc->init_cmds.done,
1899 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1900 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1901 ioc_err(mrioc, "delete reply queue timed out\n");
1902 mpi3mr_check_rh_fault_ioc(mrioc,
1903 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1904 retval = -1;
1905 goto out_unlock;
1906 }
1907 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1908 != MPI3_IOCSTATUS_SUCCESS) {
1909 ioc_err(mrioc,
1910 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1911 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1912 mrioc->init_cmds.ioc_loginfo);
1913 retval = -1;
1914 goto out_unlock;
1915 }
1916 mrioc->intr_info[midx].op_reply_q = NULL;
1917
1918 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1919 out_unlock:
1920 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1921 mutex_unlock(&mrioc->init_cmds.mutex);
1922 out:
1923
1924 return retval;
1925 }
1926
1927 /**
1928 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1929 * @mrioc: Adapter instance reference
1930 * @qidx: request queue index
1931 *
1932 * Allocate segmented memory pools for operational reply
1933 * queue.
1934 *
1935 * Return: 0 on success, non-zero on failure.
1936 */
mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1937 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1938 {
1939 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1940 int i, size;
1941 u64 *q_segment_list_entry = NULL;
1942 struct segments *segments;
1943
1944 if (mrioc->enable_segqueue) {
1945 op_reply_q->segment_qd =
1946 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1947
1948 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1949
1950 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1951 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1952 GFP_KERNEL);
1953 if (!op_reply_q->q_segment_list)
1954 return -ENOMEM;
1955 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1956 } else {
1957 op_reply_q->segment_qd = op_reply_q->num_replies;
1958 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1959 }
1960
1961 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1962 op_reply_q->segment_qd);
1963
1964 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1965 sizeof(struct segments), GFP_KERNEL);
1966 if (!op_reply_q->q_segments)
1967 return -ENOMEM;
1968
1969 segments = op_reply_q->q_segments;
1970 for (i = 0; i < op_reply_q->num_segments; i++) {
1971 segments[i].segment =
1972 dma_alloc_coherent(&mrioc->pdev->dev,
1973 size, &segments[i].segment_dma, GFP_KERNEL);
1974 if (!segments[i].segment)
1975 return -ENOMEM;
1976 if (mrioc->enable_segqueue)
1977 q_segment_list_entry[i] =
1978 (unsigned long)segments[i].segment_dma;
1979 }
1980
1981 return 0;
1982 }
1983
1984 /**
1985 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1986 * @mrioc: Adapter instance reference
1987 * @qidx: request queue index
1988 *
1989 * Allocate segmented memory pools for operational request
1990 * queue.
1991 *
1992 * Return: 0 on success, non-zero on failure.
1993 */
mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1994 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1995 {
1996 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1997 int i, size;
1998 u64 *q_segment_list_entry = NULL;
1999 struct segments *segments;
2000
2001 if (mrioc->enable_segqueue) {
2002 op_req_q->segment_qd =
2003 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
2004
2005 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
2006
2007 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
2008 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
2009 GFP_KERNEL);
2010 if (!op_req_q->q_segment_list)
2011 return -ENOMEM;
2012 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
2013
2014 } else {
2015 op_req_q->segment_qd = op_req_q->num_requests;
2016 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
2017 }
2018
2019 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
2020 op_req_q->segment_qd);
2021
2022 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
2023 sizeof(struct segments), GFP_KERNEL);
2024 if (!op_req_q->q_segments)
2025 return -ENOMEM;
2026
2027 segments = op_req_q->q_segments;
2028 for (i = 0; i < op_req_q->num_segments; i++) {
2029 segments[i].segment =
2030 dma_alloc_coherent(&mrioc->pdev->dev,
2031 size, &segments[i].segment_dma, GFP_KERNEL);
2032 if (!segments[i].segment)
2033 return -ENOMEM;
2034 if (mrioc->enable_segqueue)
2035 q_segment_list_entry[i] =
2036 (unsigned long)segments[i].segment_dma;
2037 }
2038
2039 return 0;
2040 }
2041
2042 /**
2043 * mpi3mr_create_op_reply_q - create operational reply queue
2044 * @mrioc: Adapter instance reference
2045 * @qidx: operational reply queue index
2046 *
2047 * Create operatinal reply queue by issuing MPI request
2048 * through admin queue.
2049 *
2050 * Return: 0 on success, non-zero on failure.
2051 */
mpi3mr_create_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)2052 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
2053 {
2054 struct mpi3_create_reply_queue_request create_req;
2055 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2056 int retval = 0;
2057 u16 reply_qid = 0, midx;
2058
2059 reply_qid = op_reply_q->qid;
2060
2061 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
2062
2063 if (reply_qid) {
2064 retval = -1;
2065 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
2066 reply_qid);
2067
2068 return retval;
2069 }
2070
2071 reply_qid = qidx + 1;
2072 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
2073 if ((mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) &&
2074 !mrioc->pdev->revision)
2075 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
2076 op_reply_q->ci = 0;
2077 op_reply_q->ephase = 1;
2078 atomic_set(&op_reply_q->pend_ios, 0);
2079 atomic_set(&op_reply_q->in_use, 0);
2080 op_reply_q->enable_irq_poll = false;
2081
2082 if (!op_reply_q->q_segments) {
2083 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
2084 if (retval) {
2085 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
2086 goto out;
2087 }
2088 }
2089
2090 memset(&create_req, 0, sizeof(create_req));
2091 mutex_lock(&mrioc->init_cmds.mutex);
2092 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2093 retval = -1;
2094 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
2095 goto out_unlock;
2096 }
2097 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2098 mrioc->init_cmds.is_waiting = 1;
2099 mrioc->init_cmds.callback = NULL;
2100 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2101 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
2102 create_req.queue_id = cpu_to_le16(reply_qid);
2103
2104 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
2105 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
2106 else
2107 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
2108
2109 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
2110 create_req.flags =
2111 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
2112 create_req.msix_index =
2113 cpu_to_le16(mrioc->intr_info[midx].msix_index);
2114 } else {
2115 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
2116 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
2117 reply_qid, midx);
2118 if (!mrioc->active_poll_qcount)
2119 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
2120 mrioc->intr_info_count - 1));
2121 }
2122
2123 if (mrioc->enable_segqueue) {
2124 create_req.flags |=
2125 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2126 create_req.base_address = cpu_to_le64(
2127 op_reply_q->q_segment_list_dma);
2128 } else
2129 create_req.base_address = cpu_to_le64(
2130 op_reply_q->q_segments[0].segment_dma);
2131
2132 create_req.size = cpu_to_le16(op_reply_q->num_replies);
2133
2134 init_completion(&mrioc->init_cmds.done);
2135 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2136 sizeof(create_req), 1);
2137 if (retval) {
2138 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
2139 goto out_unlock;
2140 }
2141 wait_for_completion_timeout(&mrioc->init_cmds.done,
2142 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2143 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2144 ioc_err(mrioc, "create reply queue timed out\n");
2145 mpi3mr_check_rh_fault_ioc(mrioc,
2146 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
2147 retval = -1;
2148 goto out_unlock;
2149 }
2150 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2151 != MPI3_IOCSTATUS_SUCCESS) {
2152 ioc_err(mrioc,
2153 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2154 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2155 mrioc->init_cmds.ioc_loginfo);
2156 retval = -1;
2157 goto out_unlock;
2158 }
2159 op_reply_q->qid = reply_qid;
2160 if (midx < mrioc->intr_info_count)
2161 mrioc->intr_info[midx].op_reply_q = op_reply_q;
2162
2163 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
2164 mrioc->active_poll_qcount++;
2165
2166 out_unlock:
2167 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2168 mutex_unlock(&mrioc->init_cmds.mutex);
2169 out:
2170
2171 return retval;
2172 }
2173
2174 /**
2175 * mpi3mr_create_op_req_q - create operational request queue
2176 * @mrioc: Adapter instance reference
2177 * @idx: operational request queue index
2178 * @reply_qid: Reply queue ID
2179 *
2180 * Create operatinal request queue by issuing MPI request
2181 * through admin queue.
2182 *
2183 * Return: 0 on success, non-zero on failure.
2184 */
mpi3mr_create_op_req_q(struct mpi3mr_ioc * mrioc,u16 idx,u16 reply_qid)2185 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2186 u16 reply_qid)
2187 {
2188 struct mpi3_create_request_queue_request create_req;
2189 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2190 int retval = 0;
2191 u16 req_qid = 0;
2192
2193 req_qid = op_req_q->qid;
2194
2195 if (req_qid) {
2196 retval = -1;
2197 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2198 req_qid);
2199
2200 return retval;
2201 }
2202 req_qid = idx + 1;
2203
2204 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2205 op_req_q->ci = 0;
2206 op_req_q->pi = 0;
2207 op_req_q->reply_qid = reply_qid;
2208 spin_lock_init(&op_req_q->q_lock);
2209
2210 if (!op_req_q->q_segments) {
2211 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2212 if (retval) {
2213 mpi3mr_free_op_req_q_segments(mrioc, idx);
2214 goto out;
2215 }
2216 }
2217
2218 memset(&create_req, 0, sizeof(create_req));
2219 mutex_lock(&mrioc->init_cmds.mutex);
2220 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2221 retval = -1;
2222 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2223 goto out_unlock;
2224 }
2225 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2226 mrioc->init_cmds.is_waiting = 1;
2227 mrioc->init_cmds.callback = NULL;
2228 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2229 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2230 create_req.queue_id = cpu_to_le16(req_qid);
2231 if (mrioc->enable_segqueue) {
2232 create_req.flags =
2233 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2234 create_req.base_address = cpu_to_le64(
2235 op_req_q->q_segment_list_dma);
2236 } else
2237 create_req.base_address = cpu_to_le64(
2238 op_req_q->q_segments[0].segment_dma);
2239 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2240 create_req.size = cpu_to_le16(op_req_q->num_requests);
2241
2242 init_completion(&mrioc->init_cmds.done);
2243 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2244 sizeof(create_req), 1);
2245 if (retval) {
2246 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2247 goto out_unlock;
2248 }
2249 wait_for_completion_timeout(&mrioc->init_cmds.done,
2250 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2251 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2252 ioc_err(mrioc, "create request queue timed out\n");
2253 mpi3mr_check_rh_fault_ioc(mrioc,
2254 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2255 retval = -1;
2256 goto out_unlock;
2257 }
2258 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2259 != MPI3_IOCSTATUS_SUCCESS) {
2260 ioc_err(mrioc,
2261 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2262 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2263 mrioc->init_cmds.ioc_loginfo);
2264 retval = -1;
2265 goto out_unlock;
2266 }
2267 op_req_q->qid = req_qid;
2268
2269 out_unlock:
2270 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2271 mutex_unlock(&mrioc->init_cmds.mutex);
2272 out:
2273
2274 return retval;
2275 }
2276
2277 /**
2278 * mpi3mr_create_op_queues - create operational queue pairs
2279 * @mrioc: Adapter instance reference
2280 *
2281 * Allocate memory for operational queue meta data and call
2282 * create request and reply queue functions.
2283 *
2284 * Return: 0 on success, non-zero on failures.
2285 */
mpi3mr_create_op_queues(struct mpi3mr_ioc * mrioc)2286 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2287 {
2288 int retval = 0;
2289 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2290
2291 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2292 mrioc->facts.max_op_req_q);
2293
2294 msix_count_op_q =
2295 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2296 if (!mrioc->num_queues)
2297 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2298 /*
2299 * During reset set the num_queues to the number of queues
2300 * that was set before the reset.
2301 */
2302 num_queues = mrioc->num_op_reply_q ?
2303 mrioc->num_op_reply_q : mrioc->num_queues;
2304 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2305 num_queues);
2306
2307 if (!mrioc->req_qinfo) {
2308 mrioc->req_qinfo = kcalloc(num_queues,
2309 sizeof(struct op_req_qinfo), GFP_KERNEL);
2310 if (!mrioc->req_qinfo) {
2311 retval = -1;
2312 goto out_failed;
2313 }
2314
2315 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2316 num_queues, GFP_KERNEL);
2317 if (!mrioc->op_reply_qinfo) {
2318 retval = -1;
2319 goto out_failed;
2320 }
2321 }
2322
2323 if (mrioc->enable_segqueue)
2324 ioc_info(mrioc,
2325 "allocating operational queues through segmented queues\n");
2326
2327 for (i = 0; i < num_queues; i++) {
2328 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2329 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2330 break;
2331 }
2332 if (mpi3mr_create_op_req_q(mrioc, i,
2333 mrioc->op_reply_qinfo[i].qid)) {
2334 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2335 mpi3mr_delete_op_reply_q(mrioc, i);
2336 break;
2337 }
2338 }
2339
2340 if (i == 0) {
2341 /* Not even one queue is created successfully*/
2342 retval = -1;
2343 goto out_failed;
2344 }
2345 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2346 ioc_info(mrioc,
2347 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2348 mrioc->num_op_reply_q, mrioc->default_qcount,
2349 mrioc->active_poll_qcount);
2350
2351 return retval;
2352 out_failed:
2353 kfree(mrioc->req_qinfo);
2354 mrioc->req_qinfo = NULL;
2355
2356 kfree(mrioc->op_reply_qinfo);
2357 mrioc->op_reply_qinfo = NULL;
2358
2359 return retval;
2360 }
2361
2362 /**
2363 * mpi3mr_op_request_post - Post request to operational queue
2364 * @mrioc: Adapter reference
2365 * @op_req_q: Operational request queue info
2366 * @req: MPI3 request
2367 *
2368 * Post the MPI3 request into operational request queue and
2369 * inform the controller, if the queue is full return
2370 * appropriate error.
2371 *
2372 * Return: 0 on success, non-zero on failure.
2373 */
mpi3mr_op_request_post(struct mpi3mr_ioc * mrioc,struct op_req_qinfo * op_req_q,u8 * req)2374 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2375 struct op_req_qinfo *op_req_q, u8 *req)
2376 {
2377 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2378 int retval = 0;
2379 unsigned long flags;
2380 u8 *req_entry;
2381 void *segment_base_addr;
2382 u16 req_sz = mrioc->facts.op_req_sz;
2383 struct segments *segments = op_req_q->q_segments;
2384
2385 reply_qidx = op_req_q->reply_qid - 1;
2386
2387 if (mrioc->unrecoverable)
2388 return -EFAULT;
2389
2390 spin_lock_irqsave(&op_req_q->q_lock, flags);
2391 pi = op_req_q->pi;
2392 max_entries = op_req_q->num_requests;
2393
2394 if (mpi3mr_check_req_qfull(op_req_q)) {
2395 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2396 reply_qidx, mrioc->op_reply_q_offset);
2397 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2398
2399 if (mpi3mr_check_req_qfull(op_req_q)) {
2400 retval = -EAGAIN;
2401 goto out;
2402 }
2403 }
2404
2405 if (mrioc->reset_in_progress) {
2406 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2407 retval = -EAGAIN;
2408 goto out;
2409 }
2410 if (mrioc->pci_err_recovery) {
2411 ioc_err(mrioc, "operational request queue submission failed due to pci error recovery in progress\n");
2412 retval = -EAGAIN;
2413 goto out;
2414 }
2415
2416 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2417 req_entry = (u8 *)segment_base_addr +
2418 ((pi % op_req_q->segment_qd) * req_sz);
2419
2420 memset(req_entry, 0, req_sz);
2421 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2422
2423 if (++pi == max_entries)
2424 pi = 0;
2425 op_req_q->pi = pi;
2426
2427 #ifndef CONFIG_PREEMPT_RT
2428 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2429 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2430 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2431 #else
2432 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2433 #endif
2434
2435 writel(op_req_q->pi,
2436 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2437
2438 out:
2439 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2440 return retval;
2441 }
2442
2443 /**
2444 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2445 * controller
2446 * @mrioc: Adapter instance reference
2447 * @reason_code: reason code for the fault.
2448 *
2449 * This routine will save snapdump and fault the controller with
2450 * the given reason code if it is not already in the fault or
2451 * not asynchronosuly reset. This will be used to handle
2452 * initilaization time faults/resets/timeout as in those cases
2453 * immediate soft reset invocation is not required.
2454 *
2455 * Return: None.
2456 */
mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc * mrioc,u32 reason_code)2457 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2458 {
2459 u32 ioc_status, host_diagnostic, timeout;
2460 union mpi3mr_trigger_data trigger_data;
2461
2462 if (mrioc->unrecoverable) {
2463 ioc_err(mrioc, "controller is unrecoverable\n");
2464 return;
2465 }
2466
2467 if (!pci_device_is_present(mrioc->pdev)) {
2468 mrioc->unrecoverable = 1;
2469 ioc_err(mrioc, "controller is not present\n");
2470 return;
2471 }
2472 memset(&trigger_data, 0, sizeof(trigger_data));
2473 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2474
2475 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2476 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2477 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2478 return;
2479 } else if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
2480 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2481 MPI3_SYSIF_FAULT_CODE_MASK);
2482
2483 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2484 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2485 mpi3mr_print_fault_info(mrioc);
2486 return;
2487 }
2488
2489 mpi3mr_set_diagsave(mrioc);
2490 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2491 reason_code);
2492 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2493 MPI3_SYSIF_FAULT_CODE_MASK);
2494 mpi3mr_set_trigger_data_in_all_hdb(mrioc, MPI3MR_HDB_TRIGGER_TYPE_FAULT,
2495 &trigger_data, 0);
2496 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2497 do {
2498 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2499 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2500 break;
2501 msleep(100);
2502 } while (--timeout);
2503 }
2504
2505 /**
2506 * mpi3mr_sync_timestamp - Issue time stamp sync request
2507 * @mrioc: Adapter reference
2508 *
2509 * Issue IO unit control MPI request to synchornize firmware
2510 * timestamp with host time.
2511 *
2512 * Return: 0 on success, non-zero on failure.
2513 */
mpi3mr_sync_timestamp(struct mpi3mr_ioc * mrioc)2514 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2515 {
2516 ktime_t current_time;
2517 struct mpi3_iounit_control_request iou_ctrl;
2518 int retval = 0;
2519
2520 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2521 mutex_lock(&mrioc->init_cmds.mutex);
2522 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2523 retval = -1;
2524 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2525 mutex_unlock(&mrioc->init_cmds.mutex);
2526 goto out;
2527 }
2528 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2529 mrioc->init_cmds.is_waiting = 1;
2530 mrioc->init_cmds.callback = NULL;
2531 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2532 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2533 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2534 current_time = ktime_get_real();
2535 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2536
2537 init_completion(&mrioc->init_cmds.done);
2538 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2539 sizeof(iou_ctrl), 0);
2540 if (retval) {
2541 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2542 goto out_unlock;
2543 }
2544
2545 wait_for_completion_timeout(&mrioc->init_cmds.done,
2546 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2547 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2548 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2549 mrioc->init_cmds.is_waiting = 0;
2550 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2551 mpi3mr_check_rh_fault_ioc(mrioc,
2552 MPI3MR_RESET_FROM_TSU_TIMEOUT);
2553 retval = -1;
2554 goto out_unlock;
2555 }
2556 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2557 != MPI3_IOCSTATUS_SUCCESS) {
2558 ioc_err(mrioc,
2559 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2560 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2561 mrioc->init_cmds.ioc_loginfo);
2562 retval = -1;
2563 goto out_unlock;
2564 }
2565
2566 out_unlock:
2567 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2568 mutex_unlock(&mrioc->init_cmds.mutex);
2569
2570 out:
2571 return retval;
2572 }
2573
2574 /**
2575 * mpi3mr_print_pkg_ver - display controller fw package version
2576 * @mrioc: Adapter reference
2577 *
2578 * Retrieve firmware package version from the component image
2579 * header of the controller flash and display it.
2580 *
2581 * Return: 0 on success and non-zero on failure.
2582 */
mpi3mr_print_pkg_ver(struct mpi3mr_ioc * mrioc)2583 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2584 {
2585 struct mpi3_ci_upload_request ci_upload;
2586 int retval = -1;
2587 void *data = NULL;
2588 dma_addr_t data_dma;
2589 struct mpi3_ci_manifest_mpi *manifest;
2590 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2591 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2592
2593 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2594 GFP_KERNEL);
2595 if (!data)
2596 return -ENOMEM;
2597
2598 memset(&ci_upload, 0, sizeof(ci_upload));
2599 mutex_lock(&mrioc->init_cmds.mutex);
2600 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2601 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2602 mutex_unlock(&mrioc->init_cmds.mutex);
2603 goto out;
2604 }
2605 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2606 mrioc->init_cmds.is_waiting = 1;
2607 mrioc->init_cmds.callback = NULL;
2608 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2609 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2610 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2611 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2612 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2613 ci_upload.segment_size = cpu_to_le32(data_len);
2614
2615 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2616 data_dma);
2617 init_completion(&mrioc->init_cmds.done);
2618 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2619 sizeof(ci_upload), 1);
2620 if (retval) {
2621 ioc_err(mrioc, "posting get package version failed\n");
2622 goto out_unlock;
2623 }
2624 wait_for_completion_timeout(&mrioc->init_cmds.done,
2625 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2626 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2627 ioc_err(mrioc, "get package version timed out\n");
2628 mpi3mr_check_rh_fault_ioc(mrioc,
2629 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2630 retval = -1;
2631 goto out_unlock;
2632 }
2633 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2634 == MPI3_IOCSTATUS_SUCCESS) {
2635 manifest = (struct mpi3_ci_manifest_mpi *) data;
2636 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2637 ioc_info(mrioc,
2638 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2639 manifest->package_version.gen_major,
2640 manifest->package_version.gen_minor,
2641 manifest->package_version.phase_major,
2642 manifest->package_version.phase_minor,
2643 manifest->package_version.customer_id,
2644 manifest->package_version.build_num);
2645 }
2646 }
2647 retval = 0;
2648 out_unlock:
2649 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2650 mutex_unlock(&mrioc->init_cmds.mutex);
2651
2652 out:
2653 if (data)
2654 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2655 data_dma);
2656 return retval;
2657 }
2658
2659 /**
2660 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2661 * @work: work struct
2662 *
2663 * Watch dog work periodically executed (1 second interval) to
2664 * monitor firmware fault and to issue periodic timer sync to
2665 * the firmware.
2666 *
2667 * Return: Nothing.
2668 */
mpi3mr_watchdog_work(struct work_struct * work)2669 static void mpi3mr_watchdog_work(struct work_struct *work)
2670 {
2671 struct mpi3mr_ioc *mrioc =
2672 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2673 unsigned long flags;
2674 enum mpi3mr_iocstate ioc_state;
2675 u32 host_diagnostic, ioc_status;
2676 union mpi3mr_trigger_data trigger_data;
2677 u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2678
2679 if (mrioc->reset_in_progress || mrioc->pci_err_recovery)
2680 return;
2681
2682 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2683 ioc_err(mrioc, "watchdog could not detect the controller\n");
2684 mrioc->unrecoverable = 1;
2685 }
2686
2687 if (mrioc->unrecoverable) {
2688 ioc_err(mrioc,
2689 "flush pending commands for unrecoverable controller\n");
2690 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2691 return;
2692 }
2693
2694 if (mrioc->ts_update_counter++ >= mrioc->ts_update_interval) {
2695 mrioc->ts_update_counter = 0;
2696 mpi3mr_sync_timestamp(mrioc);
2697 }
2698
2699 if ((mrioc->prepare_for_reset) &&
2700 ((mrioc->prepare_for_reset_timeout_counter++) >=
2701 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2702 mpi3mr_soft_reset_handler(mrioc,
2703 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2704 return;
2705 }
2706
2707 memset(&trigger_data, 0, sizeof(trigger_data));
2708 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2709 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2710 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2711 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2712 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2713 return;
2714 }
2715
2716 /*Check for fault state every one second and issue Soft reset*/
2717 ioc_state = mpi3mr_get_iocstate(mrioc);
2718 if (ioc_state != MRIOC_STATE_FAULT)
2719 goto schedule_work;
2720
2721 trigger_data.fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2722 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2723 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2724 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2725 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2726 if (!mrioc->diagsave_timeout) {
2727 mpi3mr_print_fault_info(mrioc);
2728 ioc_warn(mrioc, "diag save in progress\n");
2729 }
2730 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2731 goto schedule_work;
2732 }
2733
2734 mpi3mr_print_fault_info(mrioc);
2735 mrioc->diagsave_timeout = 0;
2736
2737 switch (trigger_data.fault) {
2738 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2739 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2740 ioc_warn(mrioc,
2741 "controller requires system power cycle, marking controller as unrecoverable\n");
2742 mrioc->unrecoverable = 1;
2743 goto schedule_work;
2744 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2745 goto schedule_work;
2746 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2747 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2748 break;
2749 default:
2750 break;
2751 }
2752 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2753 return;
2754
2755 schedule_work:
2756 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2757 if (mrioc->watchdog_work_q)
2758 queue_delayed_work(mrioc->watchdog_work_q,
2759 &mrioc->watchdog_work,
2760 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2761 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2762 return;
2763 }
2764
2765 /**
2766 * mpi3mr_start_watchdog - Start watchdog
2767 * @mrioc: Adapter instance reference
2768 *
2769 * Create and start the watchdog thread to monitor controller
2770 * faults.
2771 *
2772 * Return: Nothing.
2773 */
mpi3mr_start_watchdog(struct mpi3mr_ioc * mrioc)2774 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2775 {
2776 if (mrioc->watchdog_work_q)
2777 return;
2778
2779 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2780 snprintf(mrioc->watchdog_work_q_name,
2781 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2782 mrioc->id);
2783 mrioc->watchdog_work_q = alloc_ordered_workqueue(
2784 "%s", WQ_MEM_RECLAIM, mrioc->watchdog_work_q_name);
2785 if (!mrioc->watchdog_work_q) {
2786 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2787 return;
2788 }
2789
2790 if (mrioc->watchdog_work_q)
2791 queue_delayed_work(mrioc->watchdog_work_q,
2792 &mrioc->watchdog_work,
2793 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2794 }
2795
2796 /**
2797 * mpi3mr_stop_watchdog - Stop watchdog
2798 * @mrioc: Adapter instance reference
2799 *
2800 * Stop the watchdog thread created to monitor controller
2801 * faults.
2802 *
2803 * Return: Nothing.
2804 */
mpi3mr_stop_watchdog(struct mpi3mr_ioc * mrioc)2805 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2806 {
2807 unsigned long flags;
2808 struct workqueue_struct *wq;
2809
2810 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2811 wq = mrioc->watchdog_work_q;
2812 mrioc->watchdog_work_q = NULL;
2813 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2814 if (wq) {
2815 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2816 flush_workqueue(wq);
2817 destroy_workqueue(wq);
2818 }
2819 }
2820
2821 /**
2822 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2823 * @mrioc: Adapter instance reference
2824 *
2825 * Allocate memory for admin queue pair if required and register
2826 * the admin queue with the controller.
2827 *
2828 * Return: 0 on success, non-zero on failures.
2829 */
mpi3mr_setup_admin_qpair(struct mpi3mr_ioc * mrioc)2830 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2831 {
2832 int retval = 0;
2833 u32 num_admin_entries = 0;
2834
2835 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2836 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2837 MPI3MR_ADMIN_REQ_FRAME_SZ;
2838 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2839
2840 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2841 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2842 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2843 mrioc->admin_reply_ci = 0;
2844 mrioc->admin_reply_ephase = 1;
2845 atomic_set(&mrioc->admin_reply_q_in_use, 0);
2846
2847 if (!mrioc->admin_req_base) {
2848 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2849 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2850
2851 if (!mrioc->admin_req_base) {
2852 retval = -1;
2853 goto out_failed;
2854 }
2855
2856 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2857 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2858 GFP_KERNEL);
2859
2860 if (!mrioc->admin_reply_base) {
2861 retval = -1;
2862 goto out_failed;
2863 }
2864 }
2865
2866 num_admin_entries = (mrioc->num_admin_replies << 16) |
2867 (mrioc->num_admin_req);
2868 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2869 mpi3mr_writeq(mrioc->admin_req_dma,
2870 &mrioc->sysif_regs->admin_request_queue_address);
2871 mpi3mr_writeq(mrioc->admin_reply_dma,
2872 &mrioc->sysif_regs->admin_reply_queue_address);
2873 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2874 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2875 return retval;
2876
2877 out_failed:
2878
2879 if (mrioc->admin_reply_base) {
2880 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2881 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2882 mrioc->admin_reply_base = NULL;
2883 }
2884 if (mrioc->admin_req_base) {
2885 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2886 mrioc->admin_req_base, mrioc->admin_req_dma);
2887 mrioc->admin_req_base = NULL;
2888 }
2889 return retval;
2890 }
2891
2892 /**
2893 * mpi3mr_issue_iocfacts - Send IOC Facts
2894 * @mrioc: Adapter instance reference
2895 * @facts_data: Cached IOC facts data
2896 *
2897 * Issue IOC Facts MPI request through admin queue and wait for
2898 * the completion of it or time out.
2899 *
2900 * Return: 0 on success, non-zero on failures.
2901 */
mpi3mr_issue_iocfacts(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2902 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2903 struct mpi3_ioc_facts_data *facts_data)
2904 {
2905 struct mpi3_ioc_facts_request iocfacts_req;
2906 void *data = NULL;
2907 dma_addr_t data_dma;
2908 u32 data_len = sizeof(*facts_data);
2909 int retval = 0;
2910 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2911
2912 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2913 GFP_KERNEL);
2914
2915 if (!data) {
2916 retval = -1;
2917 goto out;
2918 }
2919
2920 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2921 mutex_lock(&mrioc->init_cmds.mutex);
2922 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2923 retval = -1;
2924 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2925 mutex_unlock(&mrioc->init_cmds.mutex);
2926 goto out;
2927 }
2928 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2929 mrioc->init_cmds.is_waiting = 1;
2930 mrioc->init_cmds.callback = NULL;
2931 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2932 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2933
2934 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2935 data_dma);
2936
2937 init_completion(&mrioc->init_cmds.done);
2938 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2939 sizeof(iocfacts_req), 1);
2940 if (retval) {
2941 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2942 goto out_unlock;
2943 }
2944 wait_for_completion_timeout(&mrioc->init_cmds.done,
2945 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2946 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2947 ioc_err(mrioc, "ioc_facts timed out\n");
2948 mpi3mr_check_rh_fault_ioc(mrioc,
2949 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2950 retval = -1;
2951 goto out_unlock;
2952 }
2953 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2954 != MPI3_IOCSTATUS_SUCCESS) {
2955 ioc_err(mrioc,
2956 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2957 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2958 mrioc->init_cmds.ioc_loginfo);
2959 retval = -1;
2960 goto out_unlock;
2961 }
2962 memcpy(facts_data, (u8 *)data, data_len);
2963 mpi3mr_process_factsdata(mrioc, facts_data);
2964 out_unlock:
2965 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2966 mutex_unlock(&mrioc->init_cmds.mutex);
2967
2968 out:
2969 if (data)
2970 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2971
2972 return retval;
2973 }
2974
2975 /**
2976 * mpi3mr_check_reset_dma_mask - Process IOC facts data
2977 * @mrioc: Adapter instance reference
2978 *
2979 * Check whether the new DMA mask requested through IOCFacts by
2980 * firmware needs to be set, if so set it .
2981 *
2982 * Return: 0 on success, non-zero on failure.
2983 */
mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc * mrioc)2984 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2985 {
2986 struct pci_dev *pdev = mrioc->pdev;
2987 int r;
2988 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2989
2990 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2991 return 0;
2992
2993 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2994 mrioc->dma_mask, facts_dma_mask);
2995
2996 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2997 if (r) {
2998 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2999 facts_dma_mask, r);
3000 return r;
3001 }
3002 mrioc->dma_mask = facts_dma_mask;
3003 return r;
3004 }
3005
3006 /**
3007 * mpi3mr_process_factsdata - Process IOC facts data
3008 * @mrioc: Adapter instance reference
3009 * @facts_data: Cached IOC facts data
3010 *
3011 * Convert IOC facts data into cpu endianness and cache it in
3012 * the driver .
3013 *
3014 * Return: Nothing.
3015 */
mpi3mr_process_factsdata(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)3016 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
3017 struct mpi3_ioc_facts_data *facts_data)
3018 {
3019 u32 ioc_config, req_sz, facts_flags;
3020
3021 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
3022 (sizeof(*facts_data) / 4)) {
3023 ioc_warn(mrioc,
3024 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
3025 sizeof(*facts_data),
3026 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
3027 }
3028
3029 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3030 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
3031 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
3032 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
3033 ioc_err(mrioc,
3034 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
3035 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
3036 }
3037
3038 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
3039
3040 facts_flags = le32_to_cpu(facts_data->flags);
3041 mrioc->facts.op_req_sz = req_sz;
3042 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
3043 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
3044 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
3045
3046 mrioc->facts.ioc_num = facts_data->ioc_number;
3047 mrioc->facts.who_init = facts_data->who_init;
3048 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
3049 mrioc->facts.personality = (facts_flags &
3050 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
3051 mrioc->facts.dma_mask = (facts_flags &
3052 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3053 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3054 mrioc->facts.protocol_flags = facts_data->protocol_flags;
3055 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
3056 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
3057 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
3058 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
3059 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
3060 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
3061 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
3062 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
3063 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
3064 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
3065 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
3066 mrioc->facts.max_pcie_switches =
3067 le16_to_cpu(facts_data->max_pcie_switches);
3068 mrioc->facts.max_sasexpanders =
3069 le16_to_cpu(facts_data->max_sas_expanders);
3070 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length);
3071 mrioc->facts.max_sasinitiators =
3072 le16_to_cpu(facts_data->max_sas_initiators);
3073 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
3074 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
3075 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
3076 mrioc->facts.max_op_req_q =
3077 le16_to_cpu(facts_data->max_operational_request_queues);
3078 mrioc->facts.max_op_reply_q =
3079 le16_to_cpu(facts_data->max_operational_reply_queues);
3080 mrioc->facts.ioc_capabilities =
3081 le32_to_cpu(facts_data->ioc_capabilities);
3082 mrioc->facts.fw_ver.build_num =
3083 le16_to_cpu(facts_data->fw_version.build_num);
3084 mrioc->facts.fw_ver.cust_id =
3085 le16_to_cpu(facts_data->fw_version.customer_id);
3086 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
3087 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
3088 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
3089 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
3090 mrioc->msix_count = min_t(int, mrioc->msix_count,
3091 mrioc->facts.max_msix_vectors);
3092 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
3093 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
3094 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
3095 mrioc->facts.shutdown_timeout =
3096 le16_to_cpu(facts_data->shutdown_timeout);
3097 mrioc->facts.diag_trace_sz =
3098 le32_to_cpu(facts_data->diag_trace_size);
3099 mrioc->facts.diag_fw_sz =
3100 le32_to_cpu(facts_data->diag_fw_size);
3101 mrioc->facts.diag_drvr_sz = le32_to_cpu(facts_data->diag_driver_size);
3102 mrioc->facts.max_dev_per_tg =
3103 facts_data->max_devices_per_throttle_group;
3104 mrioc->facts.io_throttle_data_length =
3105 le16_to_cpu(facts_data->io_throttle_data_length);
3106 mrioc->facts.max_io_throttle_group =
3107 le16_to_cpu(facts_data->max_io_throttle_group);
3108 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
3109 mrioc->facts.io_throttle_high =
3110 le16_to_cpu(facts_data->io_throttle_high);
3111
3112 if (mrioc->facts.max_data_length ==
3113 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED)
3114 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE;
3115 else
3116 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K;
3117 /* Store in 512b block count */
3118 if (mrioc->facts.io_throttle_data_length)
3119 mrioc->io_throttle_data_length =
3120 (mrioc->facts.io_throttle_data_length * 2 * 4);
3121 else
3122 /* set the length to 1MB + 1K to disable throttle */
3123 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2;
3124
3125 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
3126 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
3127
3128 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
3129 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
3130 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
3131 ioc_info(mrioc,
3132 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
3133 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
3134 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
3135 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
3136 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
3137 mrioc->facts.sge_mod_shift);
3138 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n",
3139 mrioc->facts.dma_mask, (facts_flags &
3140 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length);
3141 ioc_info(mrioc,
3142 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
3143 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
3144 ioc_info(mrioc,
3145 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
3146 mrioc->facts.io_throttle_data_length * 4,
3147 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
3148 }
3149
3150 /**
3151 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
3152 * @mrioc: Adapter instance reference
3153 *
3154 * Allocate and initialize the reply free buffers, sense
3155 * buffers, reply free queue and sense buffer queue.
3156 *
3157 * Return: 0 on success, non-zero on failures.
3158 */
mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc * mrioc)3159 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
3160 {
3161 int retval = 0;
3162 u32 sz, i;
3163
3164 if (mrioc->init_cmds.reply)
3165 return retval;
3166
3167 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3168 if (!mrioc->init_cmds.reply)
3169 goto out_failed;
3170
3171 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3172 if (!mrioc->bsg_cmds.reply)
3173 goto out_failed;
3174
3175 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3176 if (!mrioc->transport_cmds.reply)
3177 goto out_failed;
3178
3179 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
3180 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
3181 GFP_KERNEL);
3182 if (!mrioc->dev_rmhs_cmds[i].reply)
3183 goto out_failed;
3184 }
3185
3186 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
3187 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
3188 GFP_KERNEL);
3189 if (!mrioc->evtack_cmds[i].reply)
3190 goto out_failed;
3191 }
3192
3193 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3194 if (!mrioc->host_tm_cmds.reply)
3195 goto out_failed;
3196
3197 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3198 if (!mrioc->pel_cmds.reply)
3199 goto out_failed;
3200
3201 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3202 if (!mrioc->pel_abort_cmd.reply)
3203 goto out_failed;
3204
3205 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
3206 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
3207 GFP_KERNEL);
3208 if (!mrioc->removepend_bitmap)
3209 goto out_failed;
3210
3211 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
3212 if (!mrioc->devrem_bitmap)
3213 goto out_failed;
3214
3215 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
3216 GFP_KERNEL);
3217 if (!mrioc->evtack_cmds_bitmap)
3218 goto out_failed;
3219
3220 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3221 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3222 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3223 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3224
3225 /* reply buffer pool, 16 byte align */
3226 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3227 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3228 &mrioc->pdev->dev, sz, 16, 0);
3229 if (!mrioc->reply_buf_pool) {
3230 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3231 goto out_failed;
3232 }
3233
3234 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3235 &mrioc->reply_buf_dma);
3236 if (!mrioc->reply_buf)
3237 goto out_failed;
3238
3239 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3240
3241 /* reply free queue, 8 byte align */
3242 sz = mrioc->reply_free_qsz * 8;
3243 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3244 &mrioc->pdev->dev, sz, 8, 0);
3245 if (!mrioc->reply_free_q_pool) {
3246 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3247 goto out_failed;
3248 }
3249 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3250 GFP_KERNEL, &mrioc->reply_free_q_dma);
3251 if (!mrioc->reply_free_q)
3252 goto out_failed;
3253
3254 /* sense buffer pool, 4 byte align */
3255 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3256 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3257 &mrioc->pdev->dev, sz, 4, 0);
3258 if (!mrioc->sense_buf_pool) {
3259 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3260 goto out_failed;
3261 }
3262 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3263 &mrioc->sense_buf_dma);
3264 if (!mrioc->sense_buf)
3265 goto out_failed;
3266
3267 /* sense buffer queue, 8 byte align */
3268 sz = mrioc->sense_buf_q_sz * 8;
3269 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3270 &mrioc->pdev->dev, sz, 8, 0);
3271 if (!mrioc->sense_buf_q_pool) {
3272 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3273 goto out_failed;
3274 }
3275 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3276 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3277 if (!mrioc->sense_buf_q)
3278 goto out_failed;
3279
3280 return retval;
3281
3282 out_failed:
3283 retval = -1;
3284 return retval;
3285 }
3286
3287 /**
3288 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3289 * buffers
3290 * @mrioc: Adapter instance reference
3291 *
3292 * Helper function to initialize reply and sense buffers along
3293 * with some debug prints.
3294 *
3295 * Return: None.
3296 */
mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc * mrioc)3297 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3298 {
3299 u32 sz, i;
3300 dma_addr_t phy_addr;
3301
3302 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3303 ioc_info(mrioc,
3304 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3305 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3306 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3307 sz = mrioc->reply_free_qsz * 8;
3308 ioc_info(mrioc,
3309 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3310 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3311 (unsigned long long)mrioc->reply_free_q_dma);
3312 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3313 ioc_info(mrioc,
3314 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3315 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3316 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3317 sz = mrioc->sense_buf_q_sz * 8;
3318 ioc_info(mrioc,
3319 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3320 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3321 (unsigned long long)mrioc->sense_buf_q_dma);
3322
3323 /* initialize Reply buffer Queue */
3324 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3325 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3326 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3327 mrioc->reply_free_q[i] = cpu_to_le64(0);
3328
3329 /* initialize Sense Buffer Queue */
3330 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3331 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3332 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3333 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3334 }
3335
3336 /**
3337 * mpi3mr_issue_iocinit - Send IOC Init
3338 * @mrioc: Adapter instance reference
3339 *
3340 * Issue IOC Init MPI request through admin queue and wait for
3341 * the completion of it or time out.
3342 *
3343 * Return: 0 on success, non-zero on failures.
3344 */
mpi3mr_issue_iocinit(struct mpi3mr_ioc * mrioc)3345 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3346 {
3347 struct mpi3_ioc_init_request iocinit_req;
3348 struct mpi3_driver_info_layout *drv_info;
3349 dma_addr_t data_dma;
3350 u32 data_len = sizeof(*drv_info);
3351 int retval = 0;
3352 ktime_t current_time;
3353
3354 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3355 GFP_KERNEL);
3356 if (!drv_info) {
3357 retval = -1;
3358 goto out;
3359 }
3360 mpimr_initialize_reply_sbuf_queues(mrioc);
3361
3362 drv_info->information_length = cpu_to_le32(data_len);
3363 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3364 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3365 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3366 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3367 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3368 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3369 sizeof(drv_info->driver_release_date));
3370 drv_info->driver_capabilities = 0;
3371 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3372 sizeof(mrioc->driver_info));
3373
3374 memset(&iocinit_req, 0, sizeof(iocinit_req));
3375 mutex_lock(&mrioc->init_cmds.mutex);
3376 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3377 retval = -1;
3378 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3379 mutex_unlock(&mrioc->init_cmds.mutex);
3380 goto out;
3381 }
3382 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3383 mrioc->init_cmds.is_waiting = 1;
3384 mrioc->init_cmds.callback = NULL;
3385 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3386 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3387 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3388 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3389 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3390 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3391 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3392 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3393 iocinit_req.reply_free_queue_address =
3394 cpu_to_le64(mrioc->reply_free_q_dma);
3395 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3396 iocinit_req.sense_buffer_free_queue_depth =
3397 cpu_to_le16(mrioc->sense_buf_q_sz);
3398 iocinit_req.sense_buffer_free_queue_address =
3399 cpu_to_le64(mrioc->sense_buf_q_dma);
3400 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3401
3402 current_time = ktime_get_real();
3403 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3404
3405 iocinit_req.msg_flags |=
3406 MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED;
3407 iocinit_req.msg_flags |=
3408 MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED;
3409
3410 init_completion(&mrioc->init_cmds.done);
3411 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3412 sizeof(iocinit_req), 1);
3413 if (retval) {
3414 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3415 goto out_unlock;
3416 }
3417 wait_for_completion_timeout(&mrioc->init_cmds.done,
3418 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3419 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3420 mpi3mr_check_rh_fault_ioc(mrioc,
3421 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3422 ioc_err(mrioc, "ioc_init timed out\n");
3423 retval = -1;
3424 goto out_unlock;
3425 }
3426 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3427 != MPI3_IOCSTATUS_SUCCESS) {
3428 ioc_err(mrioc,
3429 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3430 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3431 mrioc->init_cmds.ioc_loginfo);
3432 retval = -1;
3433 goto out_unlock;
3434 }
3435
3436 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3437 writel(mrioc->reply_free_queue_host_index,
3438 &mrioc->sysif_regs->reply_free_host_index);
3439
3440 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3441 writel(mrioc->sbq_host_index,
3442 &mrioc->sysif_regs->sense_buffer_free_host_index);
3443 out_unlock:
3444 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3445 mutex_unlock(&mrioc->init_cmds.mutex);
3446
3447 out:
3448 if (drv_info)
3449 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3450 data_dma);
3451
3452 return retval;
3453 }
3454
3455 /**
3456 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3457 * @mrioc: Adapter instance reference
3458 * @event: MPI event ID
3459 *
3460 * Un mask the specific event by resetting the event_mask
3461 * bitmap.
3462 *
3463 * Return: 0 on success, non-zero on failures.
3464 */
mpi3mr_unmask_events(struct mpi3mr_ioc * mrioc,u16 event)3465 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3466 {
3467 u32 desired_event;
3468 u8 word;
3469
3470 if (event >= 128)
3471 return;
3472
3473 desired_event = (1 << (event % 32));
3474 word = event / 32;
3475
3476 mrioc->event_masks[word] &= ~desired_event;
3477 }
3478
3479 /**
3480 * mpi3mr_issue_event_notification - Send event notification
3481 * @mrioc: Adapter instance reference
3482 *
3483 * Issue event notification MPI request through admin queue and
3484 * wait for the completion of it or time out.
3485 *
3486 * Return: 0 on success, non-zero on failures.
3487 */
mpi3mr_issue_event_notification(struct mpi3mr_ioc * mrioc)3488 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3489 {
3490 struct mpi3_event_notification_request evtnotify_req;
3491 int retval = 0;
3492 u8 i;
3493
3494 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3495 mutex_lock(&mrioc->init_cmds.mutex);
3496 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3497 retval = -1;
3498 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3499 mutex_unlock(&mrioc->init_cmds.mutex);
3500 goto out;
3501 }
3502 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3503 mrioc->init_cmds.is_waiting = 1;
3504 mrioc->init_cmds.callback = NULL;
3505 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3506 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3507 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3508 evtnotify_req.event_masks[i] =
3509 cpu_to_le32(mrioc->event_masks[i]);
3510 init_completion(&mrioc->init_cmds.done);
3511 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3512 sizeof(evtnotify_req), 1);
3513 if (retval) {
3514 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3515 goto out_unlock;
3516 }
3517 wait_for_completion_timeout(&mrioc->init_cmds.done,
3518 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3519 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3520 ioc_err(mrioc, "event notification timed out\n");
3521 mpi3mr_check_rh_fault_ioc(mrioc,
3522 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3523 retval = -1;
3524 goto out_unlock;
3525 }
3526 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3527 != MPI3_IOCSTATUS_SUCCESS) {
3528 ioc_err(mrioc,
3529 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3530 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3531 mrioc->init_cmds.ioc_loginfo);
3532 retval = -1;
3533 goto out_unlock;
3534 }
3535
3536 out_unlock:
3537 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3538 mutex_unlock(&mrioc->init_cmds.mutex);
3539 out:
3540 return retval;
3541 }
3542
3543 /**
3544 * mpi3mr_process_event_ack - Process event acknowledgment
3545 * @mrioc: Adapter instance reference
3546 * @event: MPI3 event ID
3547 * @event_ctx: event context
3548 *
3549 * Send event acknowledgment through admin queue and wait for
3550 * it to complete.
3551 *
3552 * Return: 0 on success, non-zero on failures.
3553 */
mpi3mr_process_event_ack(struct mpi3mr_ioc * mrioc,u8 event,u32 event_ctx)3554 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3555 u32 event_ctx)
3556 {
3557 struct mpi3_event_ack_request evtack_req;
3558 int retval = 0;
3559
3560 memset(&evtack_req, 0, sizeof(evtack_req));
3561 mutex_lock(&mrioc->init_cmds.mutex);
3562 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3563 retval = -1;
3564 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3565 mutex_unlock(&mrioc->init_cmds.mutex);
3566 goto out;
3567 }
3568 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3569 mrioc->init_cmds.is_waiting = 1;
3570 mrioc->init_cmds.callback = NULL;
3571 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3572 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3573 evtack_req.event = event;
3574 evtack_req.event_context = cpu_to_le32(event_ctx);
3575
3576 init_completion(&mrioc->init_cmds.done);
3577 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3578 sizeof(evtack_req), 1);
3579 if (retval) {
3580 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3581 goto out_unlock;
3582 }
3583 wait_for_completion_timeout(&mrioc->init_cmds.done,
3584 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3585 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3586 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3587 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3588 mpi3mr_check_rh_fault_ioc(mrioc,
3589 MPI3MR_RESET_FROM_EVTACK_TIMEOUT);
3590 retval = -1;
3591 goto out_unlock;
3592 }
3593 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3594 != MPI3_IOCSTATUS_SUCCESS) {
3595 ioc_err(mrioc,
3596 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3597 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3598 mrioc->init_cmds.ioc_loginfo);
3599 retval = -1;
3600 goto out_unlock;
3601 }
3602
3603 out_unlock:
3604 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3605 mutex_unlock(&mrioc->init_cmds.mutex);
3606 out:
3607 return retval;
3608 }
3609
3610 /**
3611 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3612 * @mrioc: Adapter instance reference
3613 *
3614 * Allocate chain buffers and set a bitmap to indicate free
3615 * chain buffers. Chain buffers are used to pass the SGE
3616 * information along with MPI3 SCSI IO requests for host I/O.
3617 *
3618 * Return: 0 on success, non-zero on failure
3619 */
mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc * mrioc)3620 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3621 {
3622 int retval = 0;
3623 u32 sz, i;
3624 u16 num_chains;
3625
3626 if (mrioc->chain_sgl_list)
3627 return retval;
3628
3629 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3630
3631 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3632 | SHOST_DIX_TYPE1_PROTECTION
3633 | SHOST_DIX_TYPE2_PROTECTION
3634 | SHOST_DIX_TYPE3_PROTECTION))
3635 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3636
3637 mrioc->chain_buf_count = num_chains;
3638 sz = sizeof(struct chain_element) * num_chains;
3639 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3640 if (!mrioc->chain_sgl_list)
3641 goto out_failed;
3642
3643 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length /
3644 MPI3MR_PAGE_SIZE_4K))
3645 mrioc->max_sgl_entries = mrioc->facts.max_data_length /
3646 MPI3MR_PAGE_SIZE_4K;
3647 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common);
3648 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n",
3649 mrioc->max_sgl_entries, sz/1024);
3650
3651 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3652 &mrioc->pdev->dev, sz, 16, 0);
3653 if (!mrioc->chain_buf_pool) {
3654 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3655 goto out_failed;
3656 }
3657
3658 for (i = 0; i < num_chains; i++) {
3659 mrioc->chain_sgl_list[i].addr =
3660 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3661 &mrioc->chain_sgl_list[i].dma_addr);
3662
3663 if (!mrioc->chain_sgl_list[i].addr)
3664 goto out_failed;
3665 }
3666 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3667 if (!mrioc->chain_bitmap)
3668 goto out_failed;
3669 return retval;
3670 out_failed:
3671 retval = -1;
3672 return retval;
3673 }
3674
3675 /**
3676 * mpi3mr_port_enable_complete - Mark port enable complete
3677 * @mrioc: Adapter instance reference
3678 * @drv_cmd: Internal command tracker
3679 *
3680 * Call back for asynchronous port enable request sets the
3681 * driver command to indicate port enable request is complete.
3682 *
3683 * Return: Nothing
3684 */
mpi3mr_port_enable_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)3685 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3686 struct mpi3mr_drv_cmd *drv_cmd)
3687 {
3688 drv_cmd->callback = NULL;
3689 mrioc->scan_started = 0;
3690 if (drv_cmd->state & MPI3MR_CMD_RESET)
3691 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3692 else
3693 mrioc->scan_failed = drv_cmd->ioc_status;
3694 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3695 }
3696
3697 /**
3698 * mpi3mr_issue_port_enable - Issue Port Enable
3699 * @mrioc: Adapter instance reference
3700 * @async: Flag to wait for completion or not
3701 *
3702 * Issue Port Enable MPI request through admin queue and if the
3703 * async flag is not set wait for the completion of the port
3704 * enable or time out.
3705 *
3706 * Return: 0 on success, non-zero on failures.
3707 */
mpi3mr_issue_port_enable(struct mpi3mr_ioc * mrioc,u8 async)3708 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3709 {
3710 struct mpi3_port_enable_request pe_req;
3711 int retval = 0;
3712 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3713
3714 memset(&pe_req, 0, sizeof(pe_req));
3715 mutex_lock(&mrioc->init_cmds.mutex);
3716 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3717 retval = -1;
3718 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3719 mutex_unlock(&mrioc->init_cmds.mutex);
3720 goto out;
3721 }
3722 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3723 if (async) {
3724 mrioc->init_cmds.is_waiting = 0;
3725 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3726 } else {
3727 mrioc->init_cmds.is_waiting = 1;
3728 mrioc->init_cmds.callback = NULL;
3729 init_completion(&mrioc->init_cmds.done);
3730 }
3731 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3732 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3733
3734 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3735 if (retval) {
3736 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3737 goto out_unlock;
3738 }
3739 if (async) {
3740 mutex_unlock(&mrioc->init_cmds.mutex);
3741 goto out;
3742 }
3743
3744 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3745 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3746 ioc_err(mrioc, "port enable timed out\n");
3747 retval = -1;
3748 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3749 goto out_unlock;
3750 }
3751 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3752
3753 out_unlock:
3754 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3755 mutex_unlock(&mrioc->init_cmds.mutex);
3756 out:
3757 return retval;
3758 }
3759
3760 /* Protocol type to name mapper structure */
3761 static const struct {
3762 u8 protocol;
3763 char *name;
3764 } mpi3mr_protocols[] = {
3765 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3766 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3767 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3768 };
3769
3770 /* Capability to name mapper structure*/
3771 static const struct {
3772 u32 capability;
3773 char *name;
3774 } mpi3mr_capabilities[] = {
3775 { MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" },
3776 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" },
3777 };
3778
3779 /**
3780 * mpi3mr_repost_diag_bufs - repost host diag buffers
3781 * @mrioc: Adapter instance reference
3782 *
3783 * repost firmware and trace diag buffers based on global
3784 * trigger flag from driver page 2
3785 *
3786 * Return: 0 on success, non-zero on failures.
3787 */
mpi3mr_repost_diag_bufs(struct mpi3mr_ioc * mrioc)3788 static int mpi3mr_repost_diag_bufs(struct mpi3mr_ioc *mrioc)
3789 {
3790 u64 global_trigger;
3791 union mpi3mr_trigger_data prev_trigger_data;
3792 struct diag_buffer_desc *trace_hdb = NULL;
3793 struct diag_buffer_desc *fw_hdb = NULL;
3794 int retval = 0;
3795 bool trace_repost_needed = false;
3796 bool fw_repost_needed = false;
3797 u8 prev_trigger_type;
3798
3799 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
3800 if (retval)
3801 return -1;
3802
3803 trace_hdb = mpi3mr_diag_buffer_for_type(mrioc,
3804 MPI3_DIAG_BUFFER_TYPE_TRACE);
3805
3806 if (trace_hdb &&
3807 trace_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3808 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3809 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3810 trace_repost_needed = true;
3811
3812 fw_hdb = mpi3mr_diag_buffer_for_type(mrioc, MPI3_DIAG_BUFFER_TYPE_FW);
3813
3814 if (fw_hdb && fw_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3815 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3816 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3817 fw_repost_needed = true;
3818
3819 if (trace_repost_needed || fw_repost_needed) {
3820 global_trigger = le64_to_cpu(mrioc->driver_pg2->global_trigger);
3821 if (global_trigger &
3822 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED)
3823 trace_repost_needed = false;
3824 if (global_trigger &
3825 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED)
3826 fw_repost_needed = false;
3827 }
3828
3829 if (trace_repost_needed) {
3830 prev_trigger_type = trace_hdb->trigger_type;
3831 memcpy(&prev_trigger_data, &trace_hdb->trigger_data,
3832 sizeof(trace_hdb->trigger_data));
3833 retval = mpi3mr_issue_diag_buf_post(mrioc, trace_hdb);
3834 if (!retval) {
3835 dprint_init(mrioc, "trace diag buffer reposted");
3836 mpi3mr_set_trigger_data_in_hdb(trace_hdb,
3837 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3838 } else {
3839 trace_hdb->trigger_type = prev_trigger_type;
3840 memcpy(&trace_hdb->trigger_data, &prev_trigger_data,
3841 sizeof(prev_trigger_data));
3842 ioc_err(mrioc, "trace diag buffer repost failed");
3843 return -1;
3844 }
3845 }
3846
3847 if (fw_repost_needed) {
3848 prev_trigger_type = fw_hdb->trigger_type;
3849 memcpy(&prev_trigger_data, &fw_hdb->trigger_data,
3850 sizeof(fw_hdb->trigger_data));
3851 retval = mpi3mr_issue_diag_buf_post(mrioc, fw_hdb);
3852 if (!retval) {
3853 dprint_init(mrioc, "firmware diag buffer reposted");
3854 mpi3mr_set_trigger_data_in_hdb(fw_hdb,
3855 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3856 } else {
3857 fw_hdb->trigger_type = prev_trigger_type;
3858 memcpy(&fw_hdb->trigger_data, &prev_trigger_data,
3859 sizeof(prev_trigger_data));
3860 ioc_err(mrioc, "firmware diag buffer repost failed");
3861 return -1;
3862 }
3863 }
3864 return retval;
3865 }
3866
3867 /**
3868 * mpi3mr_read_tsu_interval - Update time stamp interval
3869 * @mrioc: Adapter instance reference
3870 *
3871 * Update time stamp interval if its defined in driver page 1,
3872 * otherwise use default value.
3873 *
3874 * Return: Nothing
3875 */
3876 static void
mpi3mr_read_tsu_interval(struct mpi3mr_ioc * mrioc)3877 mpi3mr_read_tsu_interval(struct mpi3mr_ioc *mrioc)
3878 {
3879 struct mpi3_driver_page1 driver_pg1;
3880 u16 pg_sz = sizeof(driver_pg1);
3881 int retval = 0;
3882
3883 mrioc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL;
3884
3885 retval = mpi3mr_cfg_get_driver_pg1(mrioc, &driver_pg1, pg_sz);
3886 if (!retval && driver_pg1.time_stamp_update)
3887 mrioc->ts_update_interval = (driver_pg1.time_stamp_update * 60);
3888 }
3889
3890 /**
3891 * mpi3mr_print_ioc_info - Display controller information
3892 * @mrioc: Adapter instance reference
3893 *
3894 * Display controller personality, capability, supported
3895 * protocols etc.
3896 *
3897 * Return: Nothing
3898 */
3899 static void
mpi3mr_print_ioc_info(struct mpi3mr_ioc * mrioc)3900 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3901 {
3902 int i = 0, bytes_written = 0;
3903 const char *personality;
3904 char protocol[50] = {0};
3905 char capabilities[100] = {0};
3906 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3907
3908 switch (mrioc->facts.personality) {
3909 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3910 personality = "Enhanced HBA";
3911 break;
3912 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3913 personality = "RAID";
3914 break;
3915 default:
3916 personality = "Unknown";
3917 break;
3918 }
3919
3920 ioc_info(mrioc, "Running in %s Personality", personality);
3921
3922 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3923 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3924 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3925
3926 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3927 if (mrioc->facts.protocol_flags &
3928 mpi3mr_protocols[i].protocol) {
3929 bytes_written += scnprintf(protocol + bytes_written,
3930 sizeof(protocol) - bytes_written, "%s%s",
3931 bytes_written ? "," : "",
3932 mpi3mr_protocols[i].name);
3933 }
3934 }
3935
3936 bytes_written = 0;
3937 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3938 if (mrioc->facts.protocol_flags &
3939 mpi3mr_capabilities[i].capability) {
3940 bytes_written += scnprintf(capabilities + bytes_written,
3941 sizeof(capabilities) - bytes_written, "%s%s",
3942 bytes_written ? "," : "",
3943 mpi3mr_capabilities[i].name);
3944 }
3945 }
3946
3947 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3948 protocol, capabilities);
3949 }
3950
3951 /**
3952 * mpi3mr_cleanup_resources - Free PCI resources
3953 * @mrioc: Adapter instance reference
3954 *
3955 * Unmap PCI device memory and disable PCI device.
3956 *
3957 * Return: 0 on success and non-zero on failure.
3958 */
mpi3mr_cleanup_resources(struct mpi3mr_ioc * mrioc)3959 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3960 {
3961 struct pci_dev *pdev = mrioc->pdev;
3962
3963 mpi3mr_cleanup_isr(mrioc);
3964
3965 if (mrioc->sysif_regs) {
3966 iounmap((void __iomem *)mrioc->sysif_regs);
3967 mrioc->sysif_regs = NULL;
3968 }
3969
3970 if (pci_is_enabled(pdev)) {
3971 if (mrioc->bars)
3972 pci_release_selected_regions(pdev, mrioc->bars);
3973 pci_disable_device(pdev);
3974 }
3975 }
3976
3977 /**
3978 * mpi3mr_setup_resources - Enable PCI resources
3979 * @mrioc: Adapter instance reference
3980 *
3981 * Enable PCI device memory, MSI-x registers and set DMA mask.
3982 *
3983 * Return: 0 on success and non-zero on failure.
3984 */
mpi3mr_setup_resources(struct mpi3mr_ioc * mrioc)3985 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3986 {
3987 struct pci_dev *pdev = mrioc->pdev;
3988 u32 memap_sz = 0;
3989 int i, retval = 0, capb = 0;
3990 u16 message_control;
3991 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3992 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3993
3994 if (pci_enable_device_mem(pdev)) {
3995 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3996 retval = -ENODEV;
3997 goto out_failed;
3998 }
3999
4000 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
4001 if (!capb) {
4002 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
4003 retval = -ENODEV;
4004 goto out_failed;
4005 }
4006 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
4007
4008 if (pci_request_selected_regions(pdev, mrioc->bars,
4009 mrioc->driver_name)) {
4010 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
4011 retval = -ENODEV;
4012 goto out_failed;
4013 }
4014
4015 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
4016 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4017 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
4018 memap_sz = pci_resource_len(pdev, i);
4019 mrioc->sysif_regs =
4020 ioremap(mrioc->sysif_regs_phys, memap_sz);
4021 break;
4022 }
4023 }
4024
4025 pci_set_master(pdev);
4026
4027 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
4028 if (retval) {
4029 if (dma_mask != DMA_BIT_MASK(32)) {
4030 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
4031 dma_mask = DMA_BIT_MASK(32);
4032 retval = dma_set_mask_and_coherent(&pdev->dev,
4033 dma_mask);
4034 }
4035 if (retval) {
4036 mrioc->dma_mask = 0;
4037 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
4038 goto out_failed;
4039 }
4040 }
4041 mrioc->dma_mask = dma_mask;
4042
4043 if (!mrioc->sysif_regs) {
4044 ioc_err(mrioc,
4045 "Unable to map adapter memory or resource not found\n");
4046 retval = -EINVAL;
4047 goto out_failed;
4048 }
4049
4050 pci_read_config_word(pdev, capb + 2, &message_control);
4051 mrioc->msix_count = (message_control & 0x3FF) + 1;
4052
4053 pci_save_state(pdev);
4054
4055 pci_set_drvdata(pdev, mrioc->shost);
4056
4057 mpi3mr_ioc_disable_intr(mrioc);
4058
4059 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
4060 (unsigned long long)mrioc->sysif_regs_phys,
4061 mrioc->sysif_regs, memap_sz);
4062 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
4063 mrioc->msix_count);
4064
4065 if (!reset_devices && poll_queues > 0)
4066 mrioc->requested_poll_qcount = min_t(int, poll_queues,
4067 mrioc->msix_count - 2);
4068 return retval;
4069
4070 out_failed:
4071 mpi3mr_cleanup_resources(mrioc);
4072 return retval;
4073 }
4074
4075 /**
4076 * mpi3mr_enable_events - Enable required events
4077 * @mrioc: Adapter instance reference
4078 *
4079 * This routine unmasks the events required by the driver by
4080 * sennding appropriate event mask bitmapt through an event
4081 * notification request.
4082 *
4083 * Return: 0 on success and non-zero on failure.
4084 */
mpi3mr_enable_events(struct mpi3mr_ioc * mrioc)4085 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
4086 {
4087 int retval = 0;
4088 u32 i;
4089
4090 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4091 mrioc->event_masks[i] = -1;
4092
4093 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
4094 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
4095 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
4096 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
4097 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
4098 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4099 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
4100 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
4101 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
4102 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
4103 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
4104 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
4105 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
4106 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
4107 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE);
4108
4109 retval = mpi3mr_issue_event_notification(mrioc);
4110 if (retval)
4111 ioc_err(mrioc, "failed to issue event notification %d\n",
4112 retval);
4113 return retval;
4114 }
4115
4116 /**
4117 * mpi3mr_init_ioc - Initialize the controller
4118 * @mrioc: Adapter instance reference
4119 *
4120 * This the controller initialization routine, executed either
4121 * after soft reset or from pci probe callback.
4122 * Setup the required resources, memory map the controller
4123 * registers, create admin and operational reply queue pairs,
4124 * allocate required memory for reply pool, sense buffer pool,
4125 * issue IOC init request to the firmware, unmask the events and
4126 * issue port enable to discover SAS/SATA/NVMe devies and RAID
4127 * volumes.
4128 *
4129 * Return: 0 on success and non-zero on failure.
4130 */
mpi3mr_init_ioc(struct mpi3mr_ioc * mrioc)4131 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
4132 {
4133 int retval = 0;
4134 u8 retry = 0;
4135 struct mpi3_ioc_facts_data facts_data;
4136 u32 sz;
4137
4138 retry_init:
4139 retval = mpi3mr_bring_ioc_ready(mrioc);
4140 if (retval) {
4141 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
4142 retval);
4143 goto out_failed_noretry;
4144 }
4145
4146 retval = mpi3mr_setup_isr(mrioc, 1);
4147 if (retval) {
4148 ioc_err(mrioc, "Failed to setup ISR error %d\n",
4149 retval);
4150 goto out_failed_noretry;
4151 }
4152
4153 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4154 if (retval) {
4155 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
4156 retval);
4157 goto out_failed;
4158 }
4159
4160 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
4161 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512;
4162 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
4163 atomic_set(&mrioc->pend_large_data_sz, 0);
4164
4165 if (reset_devices)
4166 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
4167 MPI3MR_HOST_IOS_KDUMP);
4168
4169 if (!(mrioc->facts.ioc_capabilities &
4170 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) {
4171 mrioc->sas_transport_enabled = 1;
4172 mrioc->scsi_device_channel = 1;
4173 mrioc->shost->max_channel = 1;
4174 mrioc->shost->transportt = mpi3mr_transport_template;
4175 }
4176
4177 mrioc->reply_sz = mrioc->facts.reply_sz;
4178
4179 retval = mpi3mr_check_reset_dma_mask(mrioc);
4180 if (retval) {
4181 ioc_err(mrioc, "Resetting dma mask failed %d\n",
4182 retval);
4183 goto out_failed_noretry;
4184 }
4185
4186 mpi3mr_read_tsu_interval(mrioc);
4187 mpi3mr_print_ioc_info(mrioc);
4188
4189 if (!mrioc->cfg_page) {
4190 dprint_init(mrioc, "allocating config page buffers\n");
4191 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
4192 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
4193 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL);
4194 if (!mrioc->cfg_page) {
4195 retval = -1;
4196 goto out_failed_noretry;
4197 }
4198 }
4199
4200 dprint_init(mrioc, "allocating host diag buffers\n");
4201 mpi3mr_alloc_diag_bufs(mrioc);
4202
4203 dprint_init(mrioc, "allocating ioctl dma buffers\n");
4204 mpi3mr_alloc_ioctl_dma_memory(mrioc);
4205
4206 dprint_init(mrioc, "posting host diag buffers\n");
4207 retval = mpi3mr_post_diag_bufs(mrioc);
4208
4209 if (retval)
4210 ioc_warn(mrioc, "failed to post host diag buffers\n");
4211
4212 if (!mrioc->init_cmds.reply) {
4213 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
4214 if (retval) {
4215 ioc_err(mrioc,
4216 "%s :Failed to allocated reply sense buffers %d\n",
4217 __func__, retval);
4218 goto out_failed_noretry;
4219 }
4220 }
4221
4222 if (!mrioc->chain_sgl_list) {
4223 retval = mpi3mr_alloc_chain_bufs(mrioc);
4224 if (retval) {
4225 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
4226 retval);
4227 goto out_failed_noretry;
4228 }
4229 }
4230
4231 retval = mpi3mr_issue_iocinit(mrioc);
4232 if (retval) {
4233 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
4234 retval);
4235 goto out_failed;
4236 }
4237
4238 retval = mpi3mr_print_pkg_ver(mrioc);
4239 if (retval) {
4240 ioc_err(mrioc, "failed to get package version\n");
4241 goto out_failed;
4242 }
4243
4244 retval = mpi3mr_setup_isr(mrioc, 0);
4245 if (retval) {
4246 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
4247 retval);
4248 goto out_failed_noretry;
4249 }
4250
4251 retval = mpi3mr_create_op_queues(mrioc);
4252 if (retval) {
4253 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
4254 retval);
4255 goto out_failed;
4256 }
4257
4258 if (!mrioc->pel_seqnum_virt) {
4259 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
4260 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4261 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4262 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4263 GFP_KERNEL);
4264 if (!mrioc->pel_seqnum_virt) {
4265 retval = -ENOMEM;
4266 goto out_failed_noretry;
4267 }
4268 }
4269
4270 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
4271 dprint_init(mrioc, "allocating memory for throttle groups\n");
4272 sz = sizeof(struct mpi3mr_throttle_group_info);
4273 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
4274 if (!mrioc->throttle_groups) {
4275 retval = -1;
4276 goto out_failed_noretry;
4277 }
4278 }
4279
4280 retval = mpi3mr_enable_events(mrioc);
4281 if (retval) {
4282 ioc_err(mrioc, "failed to enable events %d\n",
4283 retval);
4284 goto out_failed;
4285 }
4286
4287 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
4288 if (retval) {
4289 ioc_err(mrioc, "failed to refresh triggers\n");
4290 goto out_failed;
4291 }
4292
4293 ioc_info(mrioc, "controller initialization completed successfully\n");
4294 return retval;
4295 out_failed:
4296 if (retry < 2) {
4297 retry++;
4298 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
4299 retry);
4300 mpi3mr_memset_buffers(mrioc);
4301 goto retry_init;
4302 }
4303 retval = -1;
4304 out_failed_noretry:
4305 ioc_err(mrioc, "controller initialization failed\n");
4306 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4307 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4308 mrioc->unrecoverable = 1;
4309 return retval;
4310 }
4311
4312 /**
4313 * mpi3mr_reinit_ioc - Re-Initialize the controller
4314 * @mrioc: Adapter instance reference
4315 * @is_resume: Called from resume or reset path
4316 *
4317 * This the controller re-initialization routine, executed from
4318 * the soft reset handler or resume callback. Creates
4319 * operational reply queue pairs, allocate required memory for
4320 * reply pool, sense buffer pool, issue IOC init request to the
4321 * firmware, unmask the events and issue port enable to discover
4322 * SAS/SATA/NVMe devices and RAID volumes.
4323 *
4324 * Return: 0 on success and non-zero on failure.
4325 */
mpi3mr_reinit_ioc(struct mpi3mr_ioc * mrioc,u8 is_resume)4326 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
4327 {
4328 int retval = 0;
4329 u8 retry = 0;
4330 struct mpi3_ioc_facts_data facts_data;
4331 u32 pe_timeout, ioc_status;
4332
4333 retry_init:
4334 pe_timeout =
4335 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
4336
4337 dprint_reset(mrioc, "bringing up the controller to ready state\n");
4338 retval = mpi3mr_bring_ioc_ready(mrioc);
4339 if (retval) {
4340 ioc_err(mrioc, "failed to bring to ready state\n");
4341 goto out_failed_noretry;
4342 }
4343
4344 if (is_resume || mrioc->block_on_pci_err) {
4345 dprint_reset(mrioc, "setting up single ISR\n");
4346 retval = mpi3mr_setup_isr(mrioc, 1);
4347 if (retval) {
4348 ioc_err(mrioc, "failed to setup ISR\n");
4349 goto out_failed_noretry;
4350 }
4351 } else
4352 mpi3mr_ioc_enable_intr(mrioc);
4353
4354 dprint_reset(mrioc, "getting ioc_facts\n");
4355 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4356 if (retval) {
4357 ioc_err(mrioc, "failed to get ioc_facts\n");
4358 goto out_failed;
4359 }
4360
4361 dprint_reset(mrioc, "validating ioc_facts\n");
4362 retval = mpi3mr_revalidate_factsdata(mrioc);
4363 if (retval) {
4364 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4365 goto out_failed_noretry;
4366 }
4367
4368 mpi3mr_read_tsu_interval(mrioc);
4369 mpi3mr_print_ioc_info(mrioc);
4370
4371 if (is_resume) {
4372 dprint_reset(mrioc, "posting host diag buffers\n");
4373 retval = mpi3mr_post_diag_bufs(mrioc);
4374 if (retval)
4375 ioc_warn(mrioc, "failed to post host diag buffers\n");
4376 } else {
4377 retval = mpi3mr_repost_diag_bufs(mrioc);
4378 if (retval)
4379 ioc_warn(mrioc, "failed to re post host diag buffers\n");
4380 }
4381
4382 dprint_reset(mrioc, "sending ioc_init\n");
4383 retval = mpi3mr_issue_iocinit(mrioc);
4384 if (retval) {
4385 ioc_err(mrioc, "failed to send ioc_init\n");
4386 goto out_failed;
4387 }
4388
4389 dprint_reset(mrioc, "getting package version\n");
4390 retval = mpi3mr_print_pkg_ver(mrioc);
4391 if (retval) {
4392 ioc_err(mrioc, "failed to get package version\n");
4393 goto out_failed;
4394 }
4395
4396 if (is_resume || mrioc->block_on_pci_err) {
4397 dprint_reset(mrioc, "setting up multiple ISR\n");
4398 retval = mpi3mr_setup_isr(mrioc, 0);
4399 if (retval) {
4400 ioc_err(mrioc, "failed to re-setup ISR\n");
4401 goto out_failed_noretry;
4402 }
4403 }
4404
4405 dprint_reset(mrioc, "creating operational queue pairs\n");
4406 retval = mpi3mr_create_op_queues(mrioc);
4407 if (retval) {
4408 ioc_err(mrioc, "failed to create operational queue pairs\n");
4409 goto out_failed;
4410 }
4411
4412 if (!mrioc->pel_seqnum_virt) {
4413 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4414 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4415 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4416 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4417 GFP_KERNEL);
4418 if (!mrioc->pel_seqnum_virt) {
4419 retval = -ENOMEM;
4420 goto out_failed_noretry;
4421 }
4422 }
4423
4424 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4425 ioc_err(mrioc,
4426 "cannot create minimum number of operational queues expected:%d created:%d\n",
4427 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4428 retval = -1;
4429 goto out_failed_noretry;
4430 }
4431
4432 dprint_reset(mrioc, "enabling events\n");
4433 retval = mpi3mr_enable_events(mrioc);
4434 if (retval) {
4435 ioc_err(mrioc, "failed to enable events\n");
4436 goto out_failed;
4437 }
4438
4439 mrioc->device_refresh_on = 1;
4440 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4441
4442 ioc_info(mrioc, "sending port enable\n");
4443 retval = mpi3mr_issue_port_enable(mrioc, 1);
4444 if (retval) {
4445 ioc_err(mrioc, "failed to issue port enable\n");
4446 goto out_failed;
4447 }
4448 do {
4449 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4450 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4451 break;
4452 if (!pci_device_is_present(mrioc->pdev))
4453 mrioc->unrecoverable = 1;
4454 if (mrioc->unrecoverable) {
4455 retval = -1;
4456 goto out_failed_noretry;
4457 }
4458 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4459 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4460 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4461 mpi3mr_print_fault_info(mrioc);
4462 mrioc->init_cmds.is_waiting = 0;
4463 mrioc->init_cmds.callback = NULL;
4464 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4465 goto out_failed;
4466 }
4467 } while (--pe_timeout);
4468
4469 if (!pe_timeout) {
4470 ioc_err(mrioc, "port enable timed out\n");
4471 mpi3mr_check_rh_fault_ioc(mrioc,
4472 MPI3MR_RESET_FROM_PE_TIMEOUT);
4473 mrioc->init_cmds.is_waiting = 0;
4474 mrioc->init_cmds.callback = NULL;
4475 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4476 goto out_failed;
4477 } else if (mrioc->scan_failed) {
4478 ioc_err(mrioc,
4479 "port enable failed with status=0x%04x\n",
4480 mrioc->scan_failed);
4481 } else
4482 ioc_info(mrioc, "port enable completed successfully\n");
4483
4484 ioc_info(mrioc, "controller %s completed successfully\n",
4485 (is_resume)?"resume":"re-initialization");
4486 return retval;
4487 out_failed:
4488 if (retry < 2) {
4489 retry++;
4490 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4491 (is_resume)?"resume":"re-initialization", retry);
4492 mpi3mr_memset_buffers(mrioc);
4493 goto retry_init;
4494 }
4495 retval = -1;
4496 out_failed_noretry:
4497 ioc_err(mrioc, "controller %s is failed\n",
4498 (is_resume)?"resume":"re-initialization");
4499 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4500 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4501 mrioc->unrecoverable = 1;
4502 return retval;
4503 }
4504
4505 /**
4506 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4507 * segments
4508 * @mrioc: Adapter instance reference
4509 * @qidx: Operational reply queue index
4510 *
4511 * Return: Nothing.
4512 */
mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4513 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4514 {
4515 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4516 struct segments *segments;
4517 int i, size;
4518
4519 if (!op_reply_q->q_segments)
4520 return;
4521
4522 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4523 segments = op_reply_q->q_segments;
4524 for (i = 0; i < op_reply_q->num_segments; i++)
4525 memset(segments[i].segment, 0, size);
4526 }
4527
4528 /**
4529 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4530 * segments
4531 * @mrioc: Adapter instance reference
4532 * @qidx: Operational request queue index
4533 *
4534 * Return: Nothing.
4535 */
mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4536 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4537 {
4538 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4539 struct segments *segments;
4540 int i, size;
4541
4542 if (!op_req_q->q_segments)
4543 return;
4544
4545 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4546 segments = op_req_q->q_segments;
4547 for (i = 0; i < op_req_q->num_segments; i++)
4548 memset(segments[i].segment, 0, size);
4549 }
4550
4551 /**
4552 * mpi3mr_memset_buffers - memset memory for a controller
4553 * @mrioc: Adapter instance reference
4554 *
4555 * clear all the memory allocated for a controller, typically
4556 * called post reset to reuse the memory allocated during the
4557 * controller init.
4558 *
4559 * Return: Nothing.
4560 */
mpi3mr_memset_buffers(struct mpi3mr_ioc * mrioc)4561 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4562 {
4563 u16 i;
4564 struct mpi3mr_throttle_group_info *tg;
4565
4566 mrioc->change_count = 0;
4567 mrioc->active_poll_qcount = 0;
4568 mrioc->default_qcount = 0;
4569 if (mrioc->admin_req_base)
4570 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4571 if (mrioc->admin_reply_base)
4572 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4573 atomic_set(&mrioc->admin_reply_q_in_use, 0);
4574
4575 if (mrioc->init_cmds.reply) {
4576 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4577 memset(mrioc->bsg_cmds.reply, 0,
4578 sizeof(*mrioc->bsg_cmds.reply));
4579 memset(mrioc->host_tm_cmds.reply, 0,
4580 sizeof(*mrioc->host_tm_cmds.reply));
4581 memset(mrioc->pel_cmds.reply, 0,
4582 sizeof(*mrioc->pel_cmds.reply));
4583 memset(mrioc->pel_abort_cmd.reply, 0,
4584 sizeof(*mrioc->pel_abort_cmd.reply));
4585 memset(mrioc->transport_cmds.reply, 0,
4586 sizeof(*mrioc->transport_cmds.reply));
4587 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4588 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4589 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4590 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4591 memset(mrioc->evtack_cmds[i].reply, 0,
4592 sizeof(*mrioc->evtack_cmds[i].reply));
4593 bitmap_clear(mrioc->removepend_bitmap, 0,
4594 mrioc->dev_handle_bitmap_bits);
4595 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4596 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4597 MPI3MR_NUM_EVTACKCMD);
4598 }
4599
4600 for (i = 0; i < mrioc->num_queues; i++) {
4601 mrioc->op_reply_qinfo[i].qid = 0;
4602 mrioc->op_reply_qinfo[i].ci = 0;
4603 mrioc->op_reply_qinfo[i].num_replies = 0;
4604 mrioc->op_reply_qinfo[i].ephase = 0;
4605 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4606 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4607 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4608
4609 mrioc->req_qinfo[i].ci = 0;
4610 mrioc->req_qinfo[i].pi = 0;
4611 mrioc->req_qinfo[i].num_requests = 0;
4612 mrioc->req_qinfo[i].qid = 0;
4613 mrioc->req_qinfo[i].reply_qid = 0;
4614 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4615 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4616 }
4617
4618 atomic_set(&mrioc->pend_large_data_sz, 0);
4619 if (mrioc->throttle_groups) {
4620 tg = mrioc->throttle_groups;
4621 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4622 tg->id = 0;
4623 tg->fw_qd = 0;
4624 tg->modified_qd = 0;
4625 tg->io_divert = 0;
4626 tg->need_qd_reduction = 0;
4627 tg->high = 0;
4628 tg->low = 0;
4629 tg->qd_reduction = 0;
4630 atomic_set(&tg->pend_large_data_sz, 0);
4631 }
4632 }
4633 }
4634
4635 /**
4636 * mpi3mr_free_mem - Free memory allocated for a controller
4637 * @mrioc: Adapter instance reference
4638 *
4639 * Free all the memory allocated for a controller.
4640 *
4641 * Return: Nothing.
4642 */
mpi3mr_free_mem(struct mpi3mr_ioc * mrioc)4643 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4644 {
4645 u16 i;
4646 struct mpi3mr_intr_info *intr_info;
4647 struct diag_buffer_desc *diag_buffer;
4648
4649 mpi3mr_free_enclosure_list(mrioc);
4650 mpi3mr_free_ioctl_dma_memory(mrioc);
4651
4652 if (mrioc->sense_buf_pool) {
4653 if (mrioc->sense_buf)
4654 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4655 mrioc->sense_buf_dma);
4656 dma_pool_destroy(mrioc->sense_buf_pool);
4657 mrioc->sense_buf = NULL;
4658 mrioc->sense_buf_pool = NULL;
4659 }
4660 if (mrioc->sense_buf_q_pool) {
4661 if (mrioc->sense_buf_q)
4662 dma_pool_free(mrioc->sense_buf_q_pool,
4663 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4664 dma_pool_destroy(mrioc->sense_buf_q_pool);
4665 mrioc->sense_buf_q = NULL;
4666 mrioc->sense_buf_q_pool = NULL;
4667 }
4668
4669 if (mrioc->reply_buf_pool) {
4670 if (mrioc->reply_buf)
4671 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4672 mrioc->reply_buf_dma);
4673 dma_pool_destroy(mrioc->reply_buf_pool);
4674 mrioc->reply_buf = NULL;
4675 mrioc->reply_buf_pool = NULL;
4676 }
4677 if (mrioc->reply_free_q_pool) {
4678 if (mrioc->reply_free_q)
4679 dma_pool_free(mrioc->reply_free_q_pool,
4680 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4681 dma_pool_destroy(mrioc->reply_free_q_pool);
4682 mrioc->reply_free_q = NULL;
4683 mrioc->reply_free_q_pool = NULL;
4684 }
4685
4686 for (i = 0; i < mrioc->num_op_req_q; i++)
4687 mpi3mr_free_op_req_q_segments(mrioc, i);
4688
4689 for (i = 0; i < mrioc->num_op_reply_q; i++)
4690 mpi3mr_free_op_reply_q_segments(mrioc, i);
4691
4692 for (i = 0; i < mrioc->intr_info_count; i++) {
4693 intr_info = mrioc->intr_info + i;
4694 intr_info->op_reply_q = NULL;
4695 }
4696
4697 kfree(mrioc->req_qinfo);
4698 mrioc->req_qinfo = NULL;
4699 mrioc->num_op_req_q = 0;
4700
4701 kfree(mrioc->op_reply_qinfo);
4702 mrioc->op_reply_qinfo = NULL;
4703 mrioc->num_op_reply_q = 0;
4704
4705 kfree(mrioc->init_cmds.reply);
4706 mrioc->init_cmds.reply = NULL;
4707
4708 kfree(mrioc->bsg_cmds.reply);
4709 mrioc->bsg_cmds.reply = NULL;
4710
4711 kfree(mrioc->host_tm_cmds.reply);
4712 mrioc->host_tm_cmds.reply = NULL;
4713
4714 kfree(mrioc->pel_cmds.reply);
4715 mrioc->pel_cmds.reply = NULL;
4716
4717 kfree(mrioc->pel_abort_cmd.reply);
4718 mrioc->pel_abort_cmd.reply = NULL;
4719
4720 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4721 kfree(mrioc->evtack_cmds[i].reply);
4722 mrioc->evtack_cmds[i].reply = NULL;
4723 }
4724
4725 bitmap_free(mrioc->removepend_bitmap);
4726 mrioc->removepend_bitmap = NULL;
4727
4728 bitmap_free(mrioc->devrem_bitmap);
4729 mrioc->devrem_bitmap = NULL;
4730
4731 bitmap_free(mrioc->evtack_cmds_bitmap);
4732 mrioc->evtack_cmds_bitmap = NULL;
4733
4734 bitmap_free(mrioc->chain_bitmap);
4735 mrioc->chain_bitmap = NULL;
4736
4737 kfree(mrioc->transport_cmds.reply);
4738 mrioc->transport_cmds.reply = NULL;
4739
4740 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4741 kfree(mrioc->dev_rmhs_cmds[i].reply);
4742 mrioc->dev_rmhs_cmds[i].reply = NULL;
4743 }
4744
4745 if (mrioc->chain_buf_pool) {
4746 for (i = 0; i < mrioc->chain_buf_count; i++) {
4747 if (mrioc->chain_sgl_list[i].addr) {
4748 dma_pool_free(mrioc->chain_buf_pool,
4749 mrioc->chain_sgl_list[i].addr,
4750 mrioc->chain_sgl_list[i].dma_addr);
4751 mrioc->chain_sgl_list[i].addr = NULL;
4752 }
4753 }
4754 dma_pool_destroy(mrioc->chain_buf_pool);
4755 mrioc->chain_buf_pool = NULL;
4756 }
4757
4758 kfree(mrioc->chain_sgl_list);
4759 mrioc->chain_sgl_list = NULL;
4760
4761 if (mrioc->admin_reply_base) {
4762 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4763 mrioc->admin_reply_base, mrioc->admin_reply_dma);
4764 mrioc->admin_reply_base = NULL;
4765 }
4766 if (mrioc->admin_req_base) {
4767 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4768 mrioc->admin_req_base, mrioc->admin_req_dma);
4769 mrioc->admin_req_base = NULL;
4770 }
4771 if (mrioc->cfg_page) {
4772 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz,
4773 mrioc->cfg_page, mrioc->cfg_page_dma);
4774 mrioc->cfg_page = NULL;
4775 }
4776 if (mrioc->pel_seqnum_virt) {
4777 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4778 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4779 mrioc->pel_seqnum_virt = NULL;
4780 }
4781
4782 for (i = 0; i < MPI3MR_MAX_NUM_HDB; i++) {
4783 diag_buffer = &mrioc->diag_buffers[i];
4784 if (diag_buffer->addr) {
4785 dma_free_coherent(&mrioc->pdev->dev,
4786 diag_buffer->size, diag_buffer->addr,
4787 diag_buffer->dma_addr);
4788 diag_buffer->addr = NULL;
4789 diag_buffer->size = 0;
4790 diag_buffer->type = 0;
4791 diag_buffer->status = 0;
4792 }
4793 }
4794
4795 kfree(mrioc->throttle_groups);
4796 mrioc->throttle_groups = NULL;
4797
4798 kfree(mrioc->logdata_buf);
4799 mrioc->logdata_buf = NULL;
4800
4801 }
4802
4803 /**
4804 * mpi3mr_issue_ioc_shutdown - shutdown controller
4805 * @mrioc: Adapter instance reference
4806 *
4807 * Send shutodwn notification to the controller and wait for the
4808 * shutdown_timeout for it to be completed.
4809 *
4810 * Return: Nothing.
4811 */
mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc * mrioc)4812 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4813 {
4814 u32 ioc_config, ioc_status;
4815 u8 retval = 1;
4816 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4817
4818 ioc_info(mrioc, "Issuing shutdown Notification\n");
4819 if (mrioc->unrecoverable) {
4820 ioc_warn(mrioc,
4821 "IOC is unrecoverable shutdown is not issued\n");
4822 return;
4823 }
4824 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4825 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4826 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4827 ioc_info(mrioc, "shutdown already in progress\n");
4828 return;
4829 }
4830
4831 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4832 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4833 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4834
4835 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4836
4837 if (mrioc->facts.shutdown_timeout)
4838 timeout = mrioc->facts.shutdown_timeout * 10;
4839
4840 do {
4841 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4842 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4843 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4844 retval = 0;
4845 break;
4846 }
4847 msleep(100);
4848 } while (--timeout);
4849
4850 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4851 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4852
4853 if (retval) {
4854 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4855 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4856 ioc_warn(mrioc,
4857 "shutdown still in progress after timeout\n");
4858 }
4859
4860 ioc_info(mrioc,
4861 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4862 (!retval) ? "successful" : "failed", ioc_status,
4863 ioc_config);
4864 }
4865
4866 /**
4867 * mpi3mr_cleanup_ioc - Cleanup controller
4868 * @mrioc: Adapter instance reference
4869 *
4870 * controller cleanup handler, Message unit reset or soft reset
4871 * and shutdown notification is issued to the controller.
4872 *
4873 * Return: Nothing.
4874 */
mpi3mr_cleanup_ioc(struct mpi3mr_ioc * mrioc)4875 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4876 {
4877 enum mpi3mr_iocstate ioc_state;
4878
4879 dprint_exit(mrioc, "cleaning up the controller\n");
4880 mpi3mr_ioc_disable_intr(mrioc);
4881
4882 ioc_state = mpi3mr_get_iocstate(mrioc);
4883
4884 if (!mrioc->unrecoverable && !mrioc->reset_in_progress &&
4885 !mrioc->pci_err_recovery &&
4886 (ioc_state == MRIOC_STATE_READY)) {
4887 if (mpi3mr_issue_and_process_mur(mrioc,
4888 MPI3MR_RESET_FROM_CTLR_CLEANUP))
4889 mpi3mr_issue_reset(mrioc,
4890 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4891 MPI3MR_RESET_FROM_MUR_FAILURE);
4892 mpi3mr_issue_ioc_shutdown(mrioc);
4893 }
4894 dprint_exit(mrioc, "controller cleanup completed\n");
4895 }
4896
4897 /**
4898 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4899 * @mrioc: Adapter instance reference
4900 * @cmdptr: Internal command tracker
4901 *
4902 * Complete an internal driver commands with state indicating it
4903 * is completed due to reset.
4904 *
4905 * Return: Nothing.
4906 */
mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * cmdptr)4907 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4908 struct mpi3mr_drv_cmd *cmdptr)
4909 {
4910 if (cmdptr->state & MPI3MR_CMD_PENDING) {
4911 cmdptr->state |= MPI3MR_CMD_RESET;
4912 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4913 if (cmdptr->is_waiting) {
4914 complete(&cmdptr->done);
4915 cmdptr->is_waiting = 0;
4916 } else if (cmdptr->callback)
4917 cmdptr->callback(mrioc, cmdptr);
4918 }
4919 }
4920
4921 /**
4922 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4923 * @mrioc: Adapter instance reference
4924 *
4925 * Flush all internal driver commands post reset
4926 *
4927 * Return: Nothing.
4928 */
mpi3mr_flush_drv_cmds(struct mpi3mr_ioc * mrioc)4929 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4930 {
4931 struct mpi3mr_drv_cmd *cmdptr;
4932 u8 i;
4933
4934 cmdptr = &mrioc->init_cmds;
4935 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4936
4937 cmdptr = &mrioc->cfg_cmds;
4938 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4939
4940 cmdptr = &mrioc->bsg_cmds;
4941 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4942 cmdptr = &mrioc->host_tm_cmds;
4943 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4944
4945 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4946 cmdptr = &mrioc->dev_rmhs_cmds[i];
4947 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4948 }
4949
4950 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4951 cmdptr = &mrioc->evtack_cmds[i];
4952 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4953 }
4954
4955 cmdptr = &mrioc->pel_cmds;
4956 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4957
4958 cmdptr = &mrioc->pel_abort_cmd;
4959 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4960
4961 cmdptr = &mrioc->transport_cmds;
4962 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4963 }
4964
4965 /**
4966 * mpi3mr_pel_wait_post - Issue PEL Wait
4967 * @mrioc: Adapter instance reference
4968 * @drv_cmd: Internal command tracker
4969 *
4970 * Issue PEL Wait MPI request through admin queue and return.
4971 *
4972 * Return: Nothing.
4973 */
mpi3mr_pel_wait_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4974 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4975 struct mpi3mr_drv_cmd *drv_cmd)
4976 {
4977 struct mpi3_pel_req_action_wait pel_wait;
4978
4979 mrioc->pel_abort_requested = false;
4980
4981 memset(&pel_wait, 0, sizeof(pel_wait));
4982 drv_cmd->state = MPI3MR_CMD_PENDING;
4983 drv_cmd->is_waiting = 0;
4984 drv_cmd->callback = mpi3mr_pel_wait_complete;
4985 drv_cmd->ioc_status = 0;
4986 drv_cmd->ioc_loginfo = 0;
4987 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4988 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4989 pel_wait.action = MPI3_PEL_ACTION_WAIT;
4990 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4991 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4992 pel_wait.class = cpu_to_le16(mrioc->pel_class);
4993 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4994 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4995 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4996
4997 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4998 dprint_bsg_err(mrioc,
4999 "Issuing PELWait: Admin post failed\n");
5000 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5001 drv_cmd->callback = NULL;
5002 drv_cmd->retry_count = 0;
5003 mrioc->pel_enabled = false;
5004 }
5005 }
5006
5007 /**
5008 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
5009 * @mrioc: Adapter instance reference
5010 * @drv_cmd: Internal command tracker
5011 *
5012 * Issue PEL get sequence number MPI request through admin queue
5013 * and return.
5014 *
5015 * Return: 0 on success, non-zero on failure.
5016 */
mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5017 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
5018 struct mpi3mr_drv_cmd *drv_cmd)
5019 {
5020 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
5021 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5022 int retval = 0;
5023
5024 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
5025 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
5026 mrioc->pel_cmds.is_waiting = 0;
5027 mrioc->pel_cmds.ioc_status = 0;
5028 mrioc->pel_cmds.ioc_loginfo = 0;
5029 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
5030 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5031 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5032 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
5033 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
5034 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
5035
5036 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
5037 sizeof(pel_getseq_req), 0);
5038 if (retval) {
5039 if (drv_cmd) {
5040 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5041 drv_cmd->callback = NULL;
5042 drv_cmd->retry_count = 0;
5043 }
5044 mrioc->pel_enabled = false;
5045 }
5046
5047 return retval;
5048 }
5049
5050 /**
5051 * mpi3mr_pel_wait_complete - PELWait Completion callback
5052 * @mrioc: Adapter instance reference
5053 * @drv_cmd: Internal command tracker
5054 *
5055 * This is a callback handler for the PELWait request and
5056 * firmware completes a PELWait request when it is aborted or a
5057 * new PEL entry is available. This sends AEN to the application
5058 * and if the PELwait completion is not due to PELAbort then
5059 * this will send a request for new PEL Sequence number
5060 *
5061 * Return: Nothing.
5062 */
mpi3mr_pel_wait_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5063 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
5064 struct mpi3mr_drv_cmd *drv_cmd)
5065 {
5066 struct mpi3_pel_reply *pel_reply = NULL;
5067 u16 ioc_status, pe_log_status;
5068 bool do_retry = false;
5069
5070 if (drv_cmd->state & MPI3MR_CMD_RESET)
5071 goto cleanup_drv_cmd;
5072
5073 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5074 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5075 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
5076 __func__, ioc_status, drv_cmd->ioc_loginfo);
5077 dprint_bsg_err(mrioc,
5078 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5079 ioc_status, drv_cmd->ioc_loginfo);
5080 do_retry = true;
5081 }
5082
5083 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5084 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5085
5086 if (!pel_reply) {
5087 dprint_bsg_err(mrioc,
5088 "pel_wait: failed due to no reply\n");
5089 goto out_failed;
5090 }
5091
5092 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
5093 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
5094 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
5095 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
5096 __func__, pe_log_status);
5097 dprint_bsg_err(mrioc,
5098 "pel_wait: failed due to pel_log_status(0x%04x)\n",
5099 pe_log_status);
5100 do_retry = true;
5101 }
5102
5103 if (do_retry) {
5104 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5105 drv_cmd->retry_count++;
5106 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
5107 drv_cmd->retry_count);
5108 mpi3mr_pel_wait_post(mrioc, drv_cmd);
5109 return;
5110 }
5111 dprint_bsg_err(mrioc,
5112 "pel_wait: failed after all retries(%d)\n",
5113 drv_cmd->retry_count);
5114 goto out_failed;
5115 }
5116 atomic64_inc(&event_counter);
5117 if (!mrioc->pel_abort_requested) {
5118 mrioc->pel_cmds.retry_count = 0;
5119 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
5120 }
5121
5122 return;
5123 out_failed:
5124 mrioc->pel_enabled = false;
5125 cleanup_drv_cmd:
5126 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5127 drv_cmd->callback = NULL;
5128 drv_cmd->retry_count = 0;
5129 }
5130
5131 /**
5132 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
5133 * @mrioc: Adapter instance reference
5134 * @drv_cmd: Internal command tracker
5135 *
5136 * This is a callback handler for the PEL get sequence number
5137 * request and a new PEL wait request will be issued to the
5138 * firmware from this
5139 *
5140 * Return: Nothing.
5141 */
mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5142 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
5143 struct mpi3mr_drv_cmd *drv_cmd)
5144 {
5145 struct mpi3_pel_reply *pel_reply = NULL;
5146 struct mpi3_pel_seq *pel_seqnum_virt;
5147 u16 ioc_status;
5148 bool do_retry = false;
5149
5150 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
5151
5152 if (drv_cmd->state & MPI3MR_CMD_RESET)
5153 goto cleanup_drv_cmd;
5154
5155 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5156 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5157 dprint_bsg_err(mrioc,
5158 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5159 ioc_status, drv_cmd->ioc_loginfo);
5160 do_retry = true;
5161 }
5162
5163 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5164 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5165 if (!pel_reply) {
5166 dprint_bsg_err(mrioc,
5167 "pel_get_seqnum: failed due to no reply\n");
5168 goto out_failed;
5169 }
5170
5171 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
5172 dprint_bsg_err(mrioc,
5173 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
5174 le16_to_cpu(pel_reply->pe_log_status));
5175 do_retry = true;
5176 }
5177
5178 if (do_retry) {
5179 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5180 drv_cmd->retry_count++;
5181 dprint_bsg_err(mrioc,
5182 "pel_get_seqnum: retrying(%d)\n",
5183 drv_cmd->retry_count);
5184 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
5185 return;
5186 }
5187
5188 dprint_bsg_err(mrioc,
5189 "pel_get_seqnum: failed after all retries(%d)\n",
5190 drv_cmd->retry_count);
5191 goto out_failed;
5192 }
5193 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
5194 drv_cmd->retry_count = 0;
5195 mpi3mr_pel_wait_post(mrioc, drv_cmd);
5196
5197 return;
5198 out_failed:
5199 mrioc->pel_enabled = false;
5200 cleanup_drv_cmd:
5201 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5202 drv_cmd->callback = NULL;
5203 drv_cmd->retry_count = 0;
5204 }
5205
5206 /**
5207 * mpi3mr_soft_reset_handler - Reset the controller
5208 * @mrioc: Adapter instance reference
5209 * @reset_reason: Reset reason code
5210 * @snapdump: Flag to generate snapdump in firmware or not
5211 *
5212 * This is an handler for recovering controller by issuing soft
5213 * reset are diag fault reset. This is a blocking function and
5214 * when one reset is executed if any other resets they will be
5215 * blocked. All BSG requests will be blocked during the reset. If
5216 * controller reset is successful then the controller will be
5217 * reinitalized, otherwise the controller will be marked as not
5218 * recoverable
5219 *
5220 * In snapdump bit is set, the controller is issued with diag
5221 * fault reset so that the firmware can create a snap dump and
5222 * post that the firmware will result in F000 fault and the
5223 * driver will issue soft reset to recover from that.
5224 *
5225 * Return: 0 on success, non-zero on failure.
5226 */
mpi3mr_soft_reset_handler(struct mpi3mr_ioc * mrioc,u16 reset_reason,u8 snapdump)5227 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
5228 u16 reset_reason, u8 snapdump)
5229 {
5230 int retval = 0, i;
5231 unsigned long flags;
5232 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
5233 union mpi3mr_trigger_data trigger_data;
5234
5235 /* Block the reset handler until diag save in progress*/
5236 dprint_reset(mrioc,
5237 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
5238 mrioc->diagsave_timeout);
5239 while (mrioc->diagsave_timeout)
5240 ssleep(1);
5241 /*
5242 * Block new resets until the currently executing one is finished and
5243 * return the status of the existing reset for all blocked resets
5244 */
5245 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
5246 if (!mutex_trylock(&mrioc->reset_mutex)) {
5247 ioc_info(mrioc,
5248 "controller reset triggered by %s is blocked due to another reset in progress\n",
5249 mpi3mr_reset_rc_name(reset_reason));
5250 do {
5251 ssleep(1);
5252 } while (mrioc->reset_in_progress == 1);
5253 ioc_info(mrioc,
5254 "returning previous reset result(%d) for the reset triggered by %s\n",
5255 mrioc->prev_reset_result,
5256 mpi3mr_reset_rc_name(reset_reason));
5257 return mrioc->prev_reset_result;
5258 }
5259 ioc_info(mrioc, "controller reset is triggered by %s\n",
5260 mpi3mr_reset_rc_name(reset_reason));
5261
5262 mrioc->device_refresh_on = 0;
5263 mrioc->reset_in_progress = 1;
5264 mrioc->stop_bsgs = 1;
5265 mrioc->prev_reset_result = -1;
5266 memset(&trigger_data, 0, sizeof(trigger_data));
5267
5268 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
5269 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
5270 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
5271 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5272 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5273 dprint_reset(mrioc,
5274 "soft_reset_handler: releasing host diagnostic buffers\n");
5275 mpi3mr_release_diag_bufs(mrioc, 0);
5276 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5277 mrioc->event_masks[i] = -1;
5278
5279 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
5280 mpi3mr_issue_event_notification(mrioc);
5281 }
5282
5283 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
5284
5285 mpi3mr_ioc_disable_intr(mrioc);
5286
5287 if (snapdump) {
5288 mpi3mr_set_diagsave(mrioc);
5289 retval = mpi3mr_issue_reset(mrioc,
5290 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5291 if (!retval) {
5292 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
5293 MPI3_SYSIF_FAULT_CODE_MASK);
5294 do {
5295 host_diagnostic =
5296 readl(&mrioc->sysif_regs->host_diagnostic);
5297 if (!(host_diagnostic &
5298 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
5299 break;
5300 msleep(100);
5301 } while (--timeout);
5302 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5303 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
5304 }
5305 }
5306
5307 retval = mpi3mr_issue_reset(mrioc,
5308 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
5309 if (retval) {
5310 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
5311 goto out;
5312 }
5313 if (mrioc->num_io_throttle_group !=
5314 mrioc->facts.max_io_throttle_group) {
5315 ioc_err(mrioc,
5316 "max io throttle group doesn't match old(%d), new(%d)\n",
5317 mrioc->num_io_throttle_group,
5318 mrioc->facts.max_io_throttle_group);
5319 retval = -EPERM;
5320 goto out;
5321 }
5322
5323 mpi3mr_flush_delayed_cmd_lists(mrioc);
5324 mpi3mr_flush_drv_cmds(mrioc);
5325 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
5326 bitmap_clear(mrioc->removepend_bitmap, 0,
5327 mrioc->dev_handle_bitmap_bits);
5328 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
5329 mpi3mr_flush_host_io(mrioc);
5330 mpi3mr_cleanup_fwevt_list(mrioc);
5331 mpi3mr_invalidate_devhandles(mrioc);
5332 mpi3mr_free_enclosure_list(mrioc);
5333
5334 if (mrioc->prepare_for_reset) {
5335 mrioc->prepare_for_reset = 0;
5336 mrioc->prepare_for_reset_timeout_counter = 0;
5337 }
5338 mpi3mr_memset_buffers(mrioc);
5339 mpi3mr_release_diag_bufs(mrioc, 1);
5340 mrioc->fw_release_trigger_active = false;
5341 mrioc->trace_release_trigger_active = false;
5342 mrioc->snapdump_trigger_active = false;
5343 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5344 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5345
5346 dprint_reset(mrioc,
5347 "soft_reset_handler: reinitializing the controller\n");
5348 retval = mpi3mr_reinit_ioc(mrioc, 0);
5349 if (retval) {
5350 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
5351 mrioc->name, reset_reason);
5352 goto out;
5353 }
5354 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
5355
5356 out:
5357 if (!retval) {
5358 mrioc->diagsave_timeout = 0;
5359 mrioc->reset_in_progress = 0;
5360 mrioc->pel_abort_requested = 0;
5361 if (mrioc->pel_enabled) {
5362 mrioc->pel_cmds.retry_count = 0;
5363 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
5364 }
5365
5366 mrioc->device_refresh_on = 0;
5367
5368 mrioc->ts_update_counter = 0;
5369 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
5370 if (mrioc->watchdog_work_q)
5371 queue_delayed_work(mrioc->watchdog_work_q,
5372 &mrioc->watchdog_work,
5373 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
5374 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
5375 mrioc->stop_bsgs = 0;
5376 if (mrioc->pel_enabled)
5377 atomic64_inc(&event_counter);
5378 } else {
5379 mpi3mr_issue_reset(mrioc,
5380 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5381 mrioc->device_refresh_on = 0;
5382 mrioc->unrecoverable = 1;
5383 mrioc->reset_in_progress = 0;
5384 mrioc->stop_bsgs = 0;
5385 retval = -1;
5386 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
5387 }
5388 mrioc->prev_reset_result = retval;
5389 mutex_unlock(&mrioc->reset_mutex);
5390 ioc_info(mrioc, "controller reset is %s\n",
5391 ((retval == 0) ? "successful" : "failed"));
5392 return retval;
5393 }
5394
5395
5396 /**
5397 * mpi3mr_free_config_dma_memory - free memory for config page
5398 * @mrioc: Adapter instance reference
5399 * @mem_desc: memory descriptor structure
5400 *
5401 * Check whether the size of the buffer specified by the memory
5402 * descriptor is greater than the default page size if so then
5403 * free the memory pointed by the descriptor.
5404 *
5405 * Return: Nothing.
5406 */
mpi3mr_free_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)5407 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
5408 struct dma_memory_desc *mem_desc)
5409 {
5410 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
5411 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
5412 mem_desc->addr, mem_desc->dma_addr);
5413 mem_desc->addr = NULL;
5414 }
5415 }
5416
5417 /**
5418 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
5419 * @mrioc: Adapter instance reference
5420 * @mem_desc: Memory descriptor to hold dma memory info
5421 *
5422 * This function allocates new dmaable memory or provides the
5423 * default config page dmaable memory based on the memory size
5424 * described by the descriptor.
5425 *
5426 * Return: 0 on success, non-zero on failure.
5427 */
mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)5428 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
5429 struct dma_memory_desc *mem_desc)
5430 {
5431 if (mem_desc->size > mrioc->cfg_page_sz) {
5432 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
5433 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
5434 if (!mem_desc->addr)
5435 return -ENOMEM;
5436 } else {
5437 mem_desc->addr = mrioc->cfg_page;
5438 mem_desc->dma_addr = mrioc->cfg_page_dma;
5439 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5440 }
5441 return 0;
5442 }
5443
5444 /**
5445 * mpi3mr_post_cfg_req - Issue config requests and wait
5446 * @mrioc: Adapter instance reference
5447 * @cfg_req: Configuration request
5448 * @timeout: Timeout in seconds
5449 * @ioc_status: Pointer to return ioc status
5450 *
5451 * A generic function for posting MPI3 configuration request to
5452 * the firmware. This blocks for the completion of request for
5453 * timeout seconds and if the request times out this function
5454 * faults the controller with proper reason code.
5455 *
5456 * On successful completion of the request this function returns
5457 * appropriate ioc status from the firmware back to the caller.
5458 *
5459 * Return: 0 on success, non-zero on failure.
5460 */
mpi3mr_post_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,int timeout,u16 * ioc_status)5461 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5462 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5463 {
5464 int retval = 0;
5465
5466 mutex_lock(&mrioc->cfg_cmds.mutex);
5467 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5468 retval = -1;
5469 ioc_err(mrioc, "sending config request failed due to command in use\n");
5470 mutex_unlock(&mrioc->cfg_cmds.mutex);
5471 goto out;
5472 }
5473 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5474 mrioc->cfg_cmds.is_waiting = 1;
5475 mrioc->cfg_cmds.callback = NULL;
5476 mrioc->cfg_cmds.ioc_status = 0;
5477 mrioc->cfg_cmds.ioc_loginfo = 0;
5478
5479 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5480 cfg_req->function = MPI3_FUNCTION_CONFIG;
5481
5482 init_completion(&mrioc->cfg_cmds.done);
5483 dprint_cfg_info(mrioc, "posting config request\n");
5484 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5485 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5486 "mpi3_cfg_req");
5487 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5488 if (retval) {
5489 ioc_err(mrioc, "posting config request failed\n");
5490 goto out_unlock;
5491 }
5492 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5493 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5494 mpi3mr_check_rh_fault_ioc(mrioc,
5495 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5496 ioc_err(mrioc, "config request timed out\n");
5497 retval = -1;
5498 goto out_unlock;
5499 }
5500 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5501 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5502 dprint_cfg_err(mrioc,
5503 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5504 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5505
5506 out_unlock:
5507 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5508 mutex_unlock(&mrioc->cfg_cmds.mutex);
5509
5510 out:
5511 return retval;
5512 }
5513
5514 /**
5515 * mpi3mr_process_cfg_req - config page request processor
5516 * @mrioc: Adapter instance reference
5517 * @cfg_req: Configuration request
5518 * @cfg_hdr: Configuration page header
5519 * @timeout: Timeout in seconds
5520 * @ioc_status: Pointer to return ioc status
5521 * @cfg_buf: Memory pointer to copy config page or header
5522 * @cfg_buf_sz: Size of the memory to get config page or header
5523 *
5524 * This is handler for config page read, write and config page
5525 * header read operations.
5526 *
5527 * This function expects the cfg_req to be populated with page
5528 * type, page number, action for the header read and with page
5529 * address for all other operations.
5530 *
5531 * The cfg_hdr can be passed as null for reading required header
5532 * details for read/write pages the cfg_hdr should point valid
5533 * configuration page header.
5534 *
5535 * This allocates dmaable memory based on the size of the config
5536 * buffer and set the SGE of the cfg_req.
5537 *
5538 * For write actions, the config page data has to be passed in
5539 * the cfg_buf and size of the data has to be mentioned in the
5540 * cfg_buf_sz.
5541 *
5542 * For read/header actions, on successful completion of the
5543 * request with successful ioc_status the data will be copied
5544 * into the cfg_buf limited to a minimum of actual page size and
5545 * cfg_buf_sz
5546 *
5547 *
5548 * Return: 0 on success, non-zero on failure.
5549 */
mpi3mr_process_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,struct mpi3_config_page_header * cfg_hdr,int timeout,u16 * ioc_status,void * cfg_buf,u32 cfg_buf_sz)5550 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5551 struct mpi3_config_request *cfg_req,
5552 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5553 void *cfg_buf, u32 cfg_buf_sz)
5554 {
5555 struct dma_memory_desc mem_desc;
5556 int retval = -1;
5557 u8 invalid_action = 0;
5558 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5559
5560 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5561
5562 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5563 mem_desc.size = sizeof(struct mpi3_config_page_header);
5564 else {
5565 if (!cfg_hdr) {
5566 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5567 cfg_req->action, cfg_req->page_type,
5568 cfg_req->page_number);
5569 goto out;
5570 }
5571 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5572 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5573 if (cfg_req->action
5574 != MPI3_CONFIG_ACTION_READ_CURRENT)
5575 invalid_action = 1;
5576 break;
5577 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5578 if ((cfg_req->action ==
5579 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5580 (cfg_req->action ==
5581 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5582 invalid_action = 1;
5583 break;
5584 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5585 default:
5586 break;
5587 }
5588 if (invalid_action) {
5589 ioc_err(mrioc,
5590 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5591 cfg_req->action, cfg_req->page_type,
5592 cfg_req->page_number, cfg_hdr->page_attribute);
5593 goto out;
5594 }
5595 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5596 cfg_req->page_length = cfg_hdr->page_length;
5597 cfg_req->page_version = cfg_hdr->page_version;
5598 }
5599 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5600 goto out;
5601
5602 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5603 mem_desc.dma_addr);
5604
5605 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5606 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5607 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5608 cfg_buf_sz));
5609 dprint_cfg_info(mrioc, "config buffer to be written\n");
5610 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5611 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5612 }
5613
5614 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5615 goto out;
5616
5617 retval = 0;
5618 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5619 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5620 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5621 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5622 cfg_buf_sz));
5623 dprint_cfg_info(mrioc, "config buffer read\n");
5624 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5625 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5626 }
5627
5628 out:
5629 mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5630 return retval;
5631 }
5632
5633 /**
5634 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5635 * @mrioc: Adapter instance reference
5636 * @ioc_status: Pointer to return ioc status
5637 * @dev_pg0: Pointer to return device page 0
5638 * @pg_sz: Size of the memory allocated to the page pointer
5639 * @form: The form to be used for addressing the page
5640 * @form_spec: Form specific information like device handle
5641 *
5642 * This is handler for config page read for a specific device
5643 * page0. The ioc_status has the controller returned ioc_status.
5644 * This routine doesn't check ioc_status to decide whether the
5645 * page read is success or not and it is the callers
5646 * responsibility.
5647 *
5648 * Return: 0 on success, non-zero on failure.
5649 */
mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_device_page0 * dev_pg0,u16 pg_sz,u32 form,u32 form_spec)5650 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5651 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5652 {
5653 struct mpi3_config_page_header cfg_hdr;
5654 struct mpi3_config_request cfg_req;
5655 u32 page_address;
5656
5657 memset(dev_pg0, 0, pg_sz);
5658 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5659 memset(&cfg_req, 0, sizeof(cfg_req));
5660
5661 cfg_req.function = MPI3_FUNCTION_CONFIG;
5662 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5663 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5664 cfg_req.page_number = 0;
5665 cfg_req.page_address = 0;
5666
5667 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5668 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5669 ioc_err(mrioc, "device page0 header read failed\n");
5670 goto out_failed;
5671 }
5672 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5673 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5674 *ioc_status);
5675 goto out_failed;
5676 }
5677 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5678 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5679 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5680 cfg_req.page_address = cpu_to_le32(page_address);
5681 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5682 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5683 ioc_err(mrioc, "device page0 read failed\n");
5684 goto out_failed;
5685 }
5686 return 0;
5687 out_failed:
5688 return -1;
5689 }
5690
5691
5692 /**
5693 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5694 * @mrioc: Adapter instance reference
5695 * @ioc_status: Pointer to return ioc status
5696 * @phy_pg0: Pointer to return SAS Phy page 0
5697 * @pg_sz: Size of the memory allocated to the page pointer
5698 * @form: The form to be used for addressing the page
5699 * @form_spec: Form specific information like phy number
5700 *
5701 * This is handler for config page read for a specific SAS Phy
5702 * page0. The ioc_status has the controller returned ioc_status.
5703 * This routine doesn't check ioc_status to decide whether the
5704 * page read is success or not and it is the callers
5705 * responsibility.
5706 *
5707 * Return: 0 on success, non-zero on failure.
5708 */
mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page0 * phy_pg0,u16 pg_sz,u32 form,u32 form_spec)5709 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5710 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5711 u32 form_spec)
5712 {
5713 struct mpi3_config_page_header cfg_hdr;
5714 struct mpi3_config_request cfg_req;
5715 u32 page_address;
5716
5717 memset(phy_pg0, 0, pg_sz);
5718 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5719 memset(&cfg_req, 0, sizeof(cfg_req));
5720
5721 cfg_req.function = MPI3_FUNCTION_CONFIG;
5722 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5723 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5724 cfg_req.page_number = 0;
5725 cfg_req.page_address = 0;
5726
5727 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5728 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5729 ioc_err(mrioc, "sas phy page0 header read failed\n");
5730 goto out_failed;
5731 }
5732 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5733 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5734 *ioc_status);
5735 goto out_failed;
5736 }
5737 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5738 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5739 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5740 cfg_req.page_address = cpu_to_le32(page_address);
5741 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5742 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5743 ioc_err(mrioc, "sas phy page0 read failed\n");
5744 goto out_failed;
5745 }
5746 return 0;
5747 out_failed:
5748 return -1;
5749 }
5750
5751 /**
5752 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5753 * @mrioc: Adapter instance reference
5754 * @ioc_status: Pointer to return ioc status
5755 * @phy_pg1: Pointer to return SAS Phy page 1
5756 * @pg_sz: Size of the memory allocated to the page pointer
5757 * @form: The form to be used for addressing the page
5758 * @form_spec: Form specific information like phy number
5759 *
5760 * This is handler for config page read for a specific SAS Phy
5761 * page1. The ioc_status has the controller returned ioc_status.
5762 * This routine doesn't check ioc_status to decide whether the
5763 * page read is success or not and it is the callers
5764 * responsibility.
5765 *
5766 * Return: 0 on success, non-zero on failure.
5767 */
mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page1 * phy_pg1,u16 pg_sz,u32 form,u32 form_spec)5768 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5769 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5770 u32 form_spec)
5771 {
5772 struct mpi3_config_page_header cfg_hdr;
5773 struct mpi3_config_request cfg_req;
5774 u32 page_address;
5775
5776 memset(phy_pg1, 0, pg_sz);
5777 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5778 memset(&cfg_req, 0, sizeof(cfg_req));
5779
5780 cfg_req.function = MPI3_FUNCTION_CONFIG;
5781 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5782 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5783 cfg_req.page_number = 1;
5784 cfg_req.page_address = 0;
5785
5786 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5787 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5788 ioc_err(mrioc, "sas phy page1 header read failed\n");
5789 goto out_failed;
5790 }
5791 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5792 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5793 *ioc_status);
5794 goto out_failed;
5795 }
5796 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5797 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5798 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5799 cfg_req.page_address = cpu_to_le32(page_address);
5800 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5801 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5802 ioc_err(mrioc, "sas phy page1 read failed\n");
5803 goto out_failed;
5804 }
5805 return 0;
5806 out_failed:
5807 return -1;
5808 }
5809
5810
5811 /**
5812 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5813 * @mrioc: Adapter instance reference
5814 * @ioc_status: Pointer to return ioc status
5815 * @exp_pg0: Pointer to return SAS Expander page 0
5816 * @pg_sz: Size of the memory allocated to the page pointer
5817 * @form: The form to be used for addressing the page
5818 * @form_spec: Form specific information like device handle
5819 *
5820 * This is handler for config page read for a specific SAS
5821 * Expander page0. The ioc_status has the controller returned
5822 * ioc_status. This routine doesn't check ioc_status to decide
5823 * whether the page read is success or not and it is the callers
5824 * responsibility.
5825 *
5826 * Return: 0 on success, non-zero on failure.
5827 */
mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page0 * exp_pg0,u16 pg_sz,u32 form,u32 form_spec)5828 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5829 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5830 u32 form_spec)
5831 {
5832 struct mpi3_config_page_header cfg_hdr;
5833 struct mpi3_config_request cfg_req;
5834 u32 page_address;
5835
5836 memset(exp_pg0, 0, pg_sz);
5837 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5838 memset(&cfg_req, 0, sizeof(cfg_req));
5839
5840 cfg_req.function = MPI3_FUNCTION_CONFIG;
5841 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5842 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5843 cfg_req.page_number = 0;
5844 cfg_req.page_address = 0;
5845
5846 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5847 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5848 ioc_err(mrioc, "expander page0 header read failed\n");
5849 goto out_failed;
5850 }
5851 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5852 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5853 *ioc_status);
5854 goto out_failed;
5855 }
5856 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5857 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5858 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5859 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5860 cfg_req.page_address = cpu_to_le32(page_address);
5861 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5862 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5863 ioc_err(mrioc, "expander page0 read failed\n");
5864 goto out_failed;
5865 }
5866 return 0;
5867 out_failed:
5868 return -1;
5869 }
5870
5871 /**
5872 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5873 * @mrioc: Adapter instance reference
5874 * @ioc_status: Pointer to return ioc status
5875 * @exp_pg1: Pointer to return SAS Expander page 1
5876 * @pg_sz: Size of the memory allocated to the page pointer
5877 * @form: The form to be used for addressing the page
5878 * @form_spec: Form specific information like phy number
5879 *
5880 * This is handler for config page read for a specific SAS
5881 * Expander page1. The ioc_status has the controller returned
5882 * ioc_status. This routine doesn't check ioc_status to decide
5883 * whether the page read is success or not and it is the callers
5884 * responsibility.
5885 *
5886 * Return: 0 on success, non-zero on failure.
5887 */
mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page1 * exp_pg1,u16 pg_sz,u32 form,u32 form_spec)5888 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5889 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5890 u32 form_spec)
5891 {
5892 struct mpi3_config_page_header cfg_hdr;
5893 struct mpi3_config_request cfg_req;
5894 u32 page_address;
5895
5896 memset(exp_pg1, 0, pg_sz);
5897 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5898 memset(&cfg_req, 0, sizeof(cfg_req));
5899
5900 cfg_req.function = MPI3_FUNCTION_CONFIG;
5901 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5902 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5903 cfg_req.page_number = 1;
5904 cfg_req.page_address = 0;
5905
5906 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5907 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5908 ioc_err(mrioc, "expander page1 header read failed\n");
5909 goto out_failed;
5910 }
5911 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5912 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5913 *ioc_status);
5914 goto out_failed;
5915 }
5916 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5917 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5918 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5919 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5920 cfg_req.page_address = cpu_to_le32(page_address);
5921 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5922 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5923 ioc_err(mrioc, "expander page1 read failed\n");
5924 goto out_failed;
5925 }
5926 return 0;
5927 out_failed:
5928 return -1;
5929 }
5930
5931 /**
5932 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5933 * @mrioc: Adapter instance reference
5934 * @ioc_status: Pointer to return ioc status
5935 * @encl_pg0: Pointer to return Enclosure page 0
5936 * @pg_sz: Size of the memory allocated to the page pointer
5937 * @form: The form to be used for addressing the page
5938 * @form_spec: Form specific information like device handle
5939 *
5940 * This is handler for config page read for a specific Enclosure
5941 * page0. The ioc_status has the controller returned ioc_status.
5942 * This routine doesn't check ioc_status to decide whether the
5943 * page read is success or not and it is the callers
5944 * responsibility.
5945 *
5946 * Return: 0 on success, non-zero on failure.
5947 */
mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_enclosure_page0 * encl_pg0,u16 pg_sz,u32 form,u32 form_spec)5948 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5949 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5950 u32 form_spec)
5951 {
5952 struct mpi3_config_page_header cfg_hdr;
5953 struct mpi3_config_request cfg_req;
5954 u32 page_address;
5955
5956 memset(encl_pg0, 0, pg_sz);
5957 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5958 memset(&cfg_req, 0, sizeof(cfg_req));
5959
5960 cfg_req.function = MPI3_FUNCTION_CONFIG;
5961 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5962 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5963 cfg_req.page_number = 0;
5964 cfg_req.page_address = 0;
5965
5966 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5967 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5968 ioc_err(mrioc, "enclosure page0 header read failed\n");
5969 goto out_failed;
5970 }
5971 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5972 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5973 *ioc_status);
5974 goto out_failed;
5975 }
5976 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5977 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5978 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5979 cfg_req.page_address = cpu_to_le32(page_address);
5980 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5981 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5982 ioc_err(mrioc, "enclosure page0 read failed\n");
5983 goto out_failed;
5984 }
5985 return 0;
5986 out_failed:
5987 return -1;
5988 }
5989
5990
5991 /**
5992 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5993 * @mrioc: Adapter instance reference
5994 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5995 * @pg_sz: Size of the memory allocated to the page pointer
5996 *
5997 * This is handler for config page read for the SAS IO Unit
5998 * page0. This routine checks ioc_status to decide whether the
5999 * page read is success or not.
6000 *
6001 * Return: 0 on success, non-zero on failure.
6002 */
mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page0 * sas_io_unit_pg0,u16 pg_sz)6003 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
6004 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
6005 {
6006 struct mpi3_config_page_header cfg_hdr;
6007 struct mpi3_config_request cfg_req;
6008 u16 ioc_status = 0;
6009
6010 memset(sas_io_unit_pg0, 0, pg_sz);
6011 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6012 memset(&cfg_req, 0, sizeof(cfg_req));
6013
6014 cfg_req.function = MPI3_FUNCTION_CONFIG;
6015 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6016 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6017 cfg_req.page_number = 0;
6018 cfg_req.page_address = 0;
6019
6020 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6021 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6022 ioc_err(mrioc, "sas io unit page0 header read failed\n");
6023 goto out_failed;
6024 }
6025 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6026 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
6027 ioc_status);
6028 goto out_failed;
6029 }
6030 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6031
6032 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6033 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
6034 ioc_err(mrioc, "sas io unit page0 read failed\n");
6035 goto out_failed;
6036 }
6037 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6038 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
6039 ioc_status);
6040 goto out_failed;
6041 }
6042 return 0;
6043 out_failed:
6044 return -1;
6045 }
6046
6047 /**
6048 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
6049 * @mrioc: Adapter instance reference
6050 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
6051 * @pg_sz: Size of the memory allocated to the page pointer
6052 *
6053 * This is handler for config page read for the SAS IO Unit
6054 * page1. This routine checks ioc_status to decide whether the
6055 * page read is success or not.
6056 *
6057 * Return: 0 on success, non-zero on failure.
6058 */
mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)6059 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6060 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6061 {
6062 struct mpi3_config_page_header cfg_hdr;
6063 struct mpi3_config_request cfg_req;
6064 u16 ioc_status = 0;
6065
6066 memset(sas_io_unit_pg1, 0, pg_sz);
6067 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6068 memset(&cfg_req, 0, sizeof(cfg_req));
6069
6070 cfg_req.function = MPI3_FUNCTION_CONFIG;
6071 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6072 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6073 cfg_req.page_number = 1;
6074 cfg_req.page_address = 0;
6075
6076 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6077 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6078 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6079 goto out_failed;
6080 }
6081 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6082 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6083 ioc_status);
6084 goto out_failed;
6085 }
6086 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6087
6088 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6089 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6090 ioc_err(mrioc, "sas io unit page1 read failed\n");
6091 goto out_failed;
6092 }
6093 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6094 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
6095 ioc_status);
6096 goto out_failed;
6097 }
6098 return 0;
6099 out_failed:
6100 return -1;
6101 }
6102
6103 /**
6104 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
6105 * @mrioc: Adapter instance reference
6106 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
6107 * @pg_sz: Size of the memory allocated to the page pointer
6108 *
6109 * This is handler for config page write for the SAS IO Unit
6110 * page1. This routine checks ioc_status to decide whether the
6111 * page read is success or not. This will modify both current
6112 * and persistent page.
6113 *
6114 * Return: 0 on success, non-zero on failure.
6115 */
mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)6116 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6117 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6118 {
6119 struct mpi3_config_page_header cfg_hdr;
6120 struct mpi3_config_request cfg_req;
6121 u16 ioc_status = 0;
6122
6123 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6124 memset(&cfg_req, 0, sizeof(cfg_req));
6125
6126 cfg_req.function = MPI3_FUNCTION_CONFIG;
6127 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6128 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6129 cfg_req.page_number = 1;
6130 cfg_req.page_address = 0;
6131
6132 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6133 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6134 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6135 goto out_failed;
6136 }
6137 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6138 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6139 ioc_status);
6140 goto out_failed;
6141 }
6142 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
6143
6144 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6145 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6146 ioc_err(mrioc, "sas io unit page1 write current failed\n");
6147 goto out_failed;
6148 }
6149 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6150 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
6151 ioc_status);
6152 goto out_failed;
6153 }
6154
6155 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
6156
6157 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6158 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6159 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
6160 goto out_failed;
6161 }
6162 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6163 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
6164 ioc_status);
6165 goto out_failed;
6166 }
6167 return 0;
6168 out_failed:
6169 return -1;
6170 }
6171
6172 /**
6173 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
6174 * @mrioc: Adapter instance reference
6175 * @driver_pg1: Pointer to return Driver page 1
6176 * @pg_sz: Size of the memory allocated to the page pointer
6177 *
6178 * This is handler for config page read for the Driver page1.
6179 * This routine checks ioc_status to decide whether the page
6180 * read is success or not.
6181 *
6182 * Return: 0 on success, non-zero on failure.
6183 */
mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page1 * driver_pg1,u16 pg_sz)6184 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
6185 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
6186 {
6187 struct mpi3_config_page_header cfg_hdr;
6188 struct mpi3_config_request cfg_req;
6189 u16 ioc_status = 0;
6190
6191 memset(driver_pg1, 0, pg_sz);
6192 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6193 memset(&cfg_req, 0, sizeof(cfg_req));
6194
6195 cfg_req.function = MPI3_FUNCTION_CONFIG;
6196 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6197 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6198 cfg_req.page_number = 1;
6199 cfg_req.page_address = 0;
6200
6201 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6202 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6203 ioc_err(mrioc, "driver page1 header read failed\n");
6204 goto out_failed;
6205 }
6206 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6207 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
6208 ioc_status);
6209 goto out_failed;
6210 }
6211 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6212
6213 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6214 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
6215 ioc_err(mrioc, "driver page1 read failed\n");
6216 goto out_failed;
6217 }
6218 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6219 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
6220 ioc_status);
6221 goto out_failed;
6222 }
6223 return 0;
6224 out_failed:
6225 return -1;
6226 }
6227
6228 /**
6229 * mpi3mr_cfg_get_driver_pg2 - Read current driver page2
6230 * @mrioc: Adapter instance reference
6231 * @driver_pg2: Pointer to return driver page 2
6232 * @pg_sz: Size of the memory allocated to the page pointer
6233 * @page_action: Page action
6234 *
6235 * This is handler for config page read for the driver page2.
6236 * This routine checks ioc_status to decide whether the page
6237 * read is success or not.
6238 *
6239 * Return: 0 on success, non-zero on failure.
6240 */
mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page2 * driver_pg2,u16 pg_sz,u8 page_action)6241 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
6242 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_action)
6243 {
6244 struct mpi3_config_page_header cfg_hdr;
6245 struct mpi3_config_request cfg_req;
6246 u16 ioc_status = 0;
6247
6248 memset(driver_pg2, 0, pg_sz);
6249 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6250 memset(&cfg_req, 0, sizeof(cfg_req));
6251
6252 cfg_req.function = MPI3_FUNCTION_CONFIG;
6253 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6254 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6255 cfg_req.page_number = 2;
6256 cfg_req.page_address = 0;
6257 cfg_req.page_version = MPI3_DRIVER2_PAGEVERSION;
6258
6259 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6260 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6261 ioc_err(mrioc, "driver page2 header read failed\n");
6262 goto out_failed;
6263 }
6264 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6265 ioc_err(mrioc, "driver page2 header read failed with\n"
6266 "ioc_status(0x%04x)\n",
6267 ioc_status);
6268 goto out_failed;
6269 }
6270 cfg_req.action = page_action;
6271
6272 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6273 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg2, pg_sz)) {
6274 ioc_err(mrioc, "driver page2 read failed\n");
6275 goto out_failed;
6276 }
6277 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6278 ioc_err(mrioc, "driver page2 read failed with\n"
6279 "ioc_status(0x%04x)\n",
6280 ioc_status);
6281 goto out_failed;
6282 }
6283 return 0;
6284 out_failed:
6285 return -1;
6286 }
6287
6288