1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #include "mpi3mr.h" 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 13 static int 14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason); 15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc); 16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 17 struct mpi3_ioc_facts_data *facts_data); 18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 19 struct mpi3mr_drv_cmd *drv_cmd); 20 static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc); 21 static int poll_queues; 22 module_param(poll_queues, int, 0444); 23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); 24 25 #if defined(writeq) && defined(CONFIG_64BIT) 26 static inline void mpi3mr_writeq(__u64 b, void __iomem *addr, 27 spinlock_t *write_queue_lock) 28 { 29 writeq(b, addr); 30 } 31 #else 32 static inline void mpi3mr_writeq(__u64 b, void __iomem *addr, 33 spinlock_t *write_queue_lock) 34 { 35 __u64 data_out = b; 36 unsigned long flags; 37 38 spin_lock_irqsave(write_queue_lock, flags); 39 writel((u32)(data_out), addr); 40 writel((u32)(data_out >> 32), (addr + 4)); 41 spin_unlock_irqrestore(write_queue_lock, flags); 42 } 43 #endif 44 45 static inline bool 46 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q) 47 { 48 u16 pi, ci, max_entries; 49 bool is_qfull = false; 50 51 pi = op_req_q->pi; 52 ci = READ_ONCE(op_req_q->ci); 53 max_entries = op_req_q->num_requests; 54 55 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 56 is_qfull = true; 57 58 return is_qfull; 59 } 60 61 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc) 62 { 63 u16 i, max_vectors; 64 65 max_vectors = mrioc->intr_info_count; 66 67 for (i = 0; i < max_vectors; i++) 68 synchronize_irq(pci_irq_vector(mrioc->pdev, i)); 69 } 70 71 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc) 72 { 73 mrioc->intr_enabled = 0; 74 mpi3mr_sync_irqs(mrioc); 75 } 76 77 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc) 78 { 79 mrioc->intr_enabled = 1; 80 } 81 82 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) 83 { 84 u16 i; 85 86 mpi3mr_ioc_disable_intr(mrioc); 87 88 if (!mrioc->intr_info) 89 return; 90 91 for (i = 0; i < mrioc->intr_info_count; i++) 92 free_irq(pci_irq_vector(mrioc->pdev, i), 93 (mrioc->intr_info + i)); 94 95 kfree(mrioc->intr_info); 96 mrioc->intr_info = NULL; 97 mrioc->intr_info_count = 0; 98 mrioc->is_intr_info_set = false; 99 pci_free_irq_vectors(mrioc->pdev); 100 } 101 102 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 103 dma_addr_t dma_addr) 104 { 105 struct mpi3_sge_common *sgel = paddr; 106 107 sgel->flags = flags; 108 sgel->length = cpu_to_le32(length); 109 sgel->address = cpu_to_le64(dma_addr); 110 } 111 112 void mpi3mr_build_zero_len_sge(void *paddr) 113 { 114 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 115 116 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 117 } 118 119 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 120 dma_addr_t phys_addr) 121 { 122 if (!phys_addr) 123 return NULL; 124 125 if ((phys_addr < mrioc->reply_buf_dma) || 126 (phys_addr > mrioc->reply_buf_dma_max_address)) 127 return NULL; 128 129 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma); 130 } 131 132 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 133 dma_addr_t phys_addr) 134 { 135 if (!phys_addr) 136 return NULL; 137 138 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma); 139 } 140 141 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, 142 u64 reply_dma) 143 { 144 u32 old_idx = 0; 145 unsigned long flags; 146 147 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags); 148 old_idx = mrioc->reply_free_queue_host_index; 149 mrioc->reply_free_queue_host_index = ( 150 (mrioc->reply_free_queue_host_index == 151 (mrioc->reply_free_qsz - 1)) ? 0 : 152 (mrioc->reply_free_queue_host_index + 1)); 153 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma); 154 writel(mrioc->reply_free_queue_host_index, 155 &mrioc->sysif_regs->reply_free_host_index); 156 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags); 157 } 158 159 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 160 u64 sense_buf_dma) 161 { 162 u32 old_idx = 0; 163 unsigned long flags; 164 165 spin_lock_irqsave(&mrioc->sbq_lock, flags); 166 old_idx = mrioc->sbq_host_index; 167 mrioc->sbq_host_index = ((mrioc->sbq_host_index == 168 (mrioc->sense_buf_q_sz - 1)) ? 0 : 169 (mrioc->sbq_host_index + 1)); 170 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma); 171 writel(mrioc->sbq_host_index, 172 &mrioc->sysif_regs->sense_buffer_free_host_index); 173 spin_unlock_irqrestore(&mrioc->sbq_lock, flags); 174 } 175 176 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc, 177 struct mpi3_event_notification_reply *event_reply) 178 { 179 char *desc = NULL; 180 u16 event; 181 182 if (!(mrioc->logging_level & MPI3_DEBUG_EVENT)) 183 return; 184 185 event = event_reply->event; 186 187 switch (event) { 188 case MPI3_EVENT_LOG_DATA: 189 desc = "Log Data"; 190 break; 191 case MPI3_EVENT_CHANGE: 192 desc = "Event Change"; 193 break; 194 case MPI3_EVENT_GPIO_INTERRUPT: 195 desc = "GPIO Interrupt"; 196 break; 197 case MPI3_EVENT_CABLE_MGMT: 198 desc = "Cable Management"; 199 break; 200 case MPI3_EVENT_ENERGY_PACK_CHANGE: 201 desc = "Energy Pack Change"; 202 break; 203 case MPI3_EVENT_DEVICE_ADDED: 204 { 205 struct mpi3_device_page0 *event_data = 206 (struct mpi3_device_page0 *)event_reply->event_data; 207 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n", 208 event_data->dev_handle, event_data->device_form); 209 return; 210 } 211 case MPI3_EVENT_DEVICE_INFO_CHANGED: 212 { 213 struct mpi3_device_page0 *event_data = 214 (struct mpi3_device_page0 *)event_reply->event_data; 215 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n", 216 event_data->dev_handle, event_data->device_form); 217 return; 218 } 219 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 220 { 221 struct mpi3_event_data_device_status_change *event_data = 222 (struct mpi3_event_data_device_status_change *)event_reply->event_data; 223 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n", 224 event_data->dev_handle, event_data->reason_code); 225 return; 226 } 227 case MPI3_EVENT_SAS_DISCOVERY: 228 { 229 struct mpi3_event_data_sas_discovery *event_data = 230 (struct mpi3_event_data_sas_discovery *)event_reply->event_data; 231 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n", 232 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 233 "start" : "stop", 234 le32_to_cpu(event_data->discovery_status)); 235 return; 236 } 237 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 238 desc = "SAS Broadcast Primitive"; 239 break; 240 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 241 desc = "SAS Notify Primitive"; 242 break; 243 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 244 desc = "SAS Init Device Status Change"; 245 break; 246 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 247 desc = "SAS Init Table Overflow"; 248 break; 249 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 250 desc = "SAS Topology Change List"; 251 break; 252 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 253 desc = "Enclosure Device Status Change"; 254 break; 255 case MPI3_EVENT_ENCL_DEVICE_ADDED: 256 desc = "Enclosure Added"; 257 break; 258 case MPI3_EVENT_HARD_RESET_RECEIVED: 259 desc = "Hard Reset Received"; 260 break; 261 case MPI3_EVENT_SAS_PHY_COUNTER: 262 desc = "SAS PHY Counter"; 263 break; 264 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 265 desc = "SAS Device Discovery Error"; 266 break; 267 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 268 desc = "PCIE Topology Change List"; 269 break; 270 case MPI3_EVENT_PCIE_ENUMERATION: 271 { 272 struct mpi3_event_data_pcie_enumeration *event_data = 273 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data; 274 ioc_info(mrioc, "PCIE Enumeration: (%s)", 275 (event_data->reason_code == 276 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop"); 277 if (event_data->enumeration_status) 278 ioc_info(mrioc, "enumeration_status(0x%08x)\n", 279 le32_to_cpu(event_data->enumeration_status)); 280 return; 281 } 282 case MPI3_EVENT_PREPARE_FOR_RESET: 283 desc = "Prepare For Reset"; 284 break; 285 case MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE: 286 desc = "Diagnostic Buffer Status Change"; 287 break; 288 } 289 290 if (!desc) 291 return; 292 293 ioc_info(mrioc, "%s\n", desc); 294 } 295 296 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc, 297 struct mpi3_default_reply *def_reply) 298 { 299 struct mpi3_event_notification_reply *event_reply = 300 (struct mpi3_event_notification_reply *)def_reply; 301 302 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count); 303 mpi3mr_print_event_data(mrioc, event_reply); 304 mpi3mr_os_handle_events(mrioc, event_reply); 305 } 306 307 static struct mpi3mr_drv_cmd * 308 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, 309 struct mpi3_default_reply *def_reply) 310 { 311 u16 idx; 312 313 switch (host_tag) { 314 case MPI3MR_HOSTTAG_INITCMDS: 315 return &mrioc->init_cmds; 316 case MPI3MR_HOSTTAG_CFG_CMDS: 317 return &mrioc->cfg_cmds; 318 case MPI3MR_HOSTTAG_BSG_CMDS: 319 return &mrioc->bsg_cmds; 320 case MPI3MR_HOSTTAG_BLK_TMS: 321 return &mrioc->host_tm_cmds; 322 case MPI3MR_HOSTTAG_PEL_ABORT: 323 return &mrioc->pel_abort_cmd; 324 case MPI3MR_HOSTTAG_PEL_WAIT: 325 return &mrioc->pel_cmds; 326 case MPI3MR_HOSTTAG_TRANSPORT_CMDS: 327 return &mrioc->transport_cmds; 328 case MPI3MR_HOSTTAG_INVALID: 329 if (def_reply && def_reply->function == 330 MPI3_FUNCTION_EVENT_NOTIFICATION) 331 mpi3mr_handle_events(mrioc, def_reply); 332 return NULL; 333 default: 334 break; 335 } 336 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 337 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) { 338 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 339 return &mrioc->dev_rmhs_cmds[idx]; 340 } 341 342 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 343 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 344 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 345 return &mrioc->evtack_cmds[idx]; 346 } 347 348 return NULL; 349 } 350 351 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, 352 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma) 353 { 354 u16 reply_desc_type, host_tag = 0; 355 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 356 u16 masked_ioc_status = MPI3_IOCSTATUS_SUCCESS; 357 u32 ioc_loginfo = 0, sense_count = 0; 358 struct mpi3_status_reply_descriptor *status_desc; 359 struct mpi3_address_reply_descriptor *addr_desc; 360 struct mpi3_success_reply_descriptor *success_desc; 361 struct mpi3_default_reply *def_reply = NULL; 362 struct mpi3mr_drv_cmd *cmdptr = NULL; 363 struct mpi3_scsi_io_reply *scsi_reply; 364 struct scsi_sense_hdr sshdr; 365 u8 *sense_buf = NULL; 366 367 *reply_dma = 0; 368 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) & 369 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 370 switch (reply_desc_type) { 371 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 372 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc; 373 host_tag = le16_to_cpu(status_desc->host_tag); 374 ioc_status = le16_to_cpu(status_desc->ioc_status); 375 if (ioc_status & 376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 377 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info); 378 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 379 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo); 380 break; 381 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 382 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc; 383 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address); 384 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma); 385 if (!def_reply) 386 goto out; 387 host_tag = le16_to_cpu(def_reply->host_tag); 388 ioc_status = le16_to_cpu(def_reply->ioc_status); 389 if (ioc_status & 390 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 391 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info); 392 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 393 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) { 394 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply; 395 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc, 396 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 397 sense_count = le32_to_cpu(scsi_reply->sense_count); 398 if (sense_buf) { 399 scsi_normalize_sense(sense_buf, sense_count, 400 &sshdr); 401 mpi3mr_scsisense_trigger(mrioc, sshdr.sense_key, 402 sshdr.asc, sshdr.ascq); 403 } 404 } 405 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo); 406 break; 407 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 408 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc; 409 host_tag = le16_to_cpu(success_desc->host_tag); 410 break; 411 default: 412 break; 413 } 414 415 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply); 416 if (cmdptr) { 417 if (cmdptr->state & MPI3MR_CMD_PENDING) { 418 cmdptr->state |= MPI3MR_CMD_COMPLETE; 419 cmdptr->ioc_loginfo = ioc_loginfo; 420 if (host_tag == MPI3MR_HOSTTAG_BSG_CMDS) 421 cmdptr->ioc_status = ioc_status; 422 else 423 cmdptr->ioc_status = masked_ioc_status; 424 cmdptr->state &= ~MPI3MR_CMD_PENDING; 425 if (def_reply) { 426 cmdptr->state |= MPI3MR_CMD_REPLY_VALID; 427 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply, 428 mrioc->reply_sz); 429 } 430 if (sense_buf && cmdptr->sensebuf) { 431 cmdptr->is_sense = 1; 432 memcpy(cmdptr->sensebuf, sense_buf, 433 MPI3MR_SENSE_BUF_SZ); 434 } 435 if (cmdptr->is_waiting) { 436 cmdptr->is_waiting = 0; 437 complete(&cmdptr->done); 438 } else if (cmdptr->callback) 439 cmdptr->callback(mrioc, cmdptr); 440 } 441 } 442 out: 443 if (sense_buf) 444 mpi3mr_repost_sense_buf(mrioc, 445 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 446 } 447 448 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc) 449 { 450 u32 exp_phase = mrioc->admin_reply_ephase; 451 u32 admin_reply_ci = mrioc->admin_reply_ci; 452 u32 num_admin_replies = 0; 453 u64 reply_dma = 0; 454 u16 threshold_comps = 0; 455 struct mpi3_default_reply_descriptor *reply_desc; 456 457 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1)) { 458 atomic_inc(&mrioc->admin_pend_isr); 459 return 0; 460 } 461 462 atomic_set(&mrioc->admin_pend_isr, 0); 463 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 464 admin_reply_ci; 465 466 if ((le16_to_cpu(reply_desc->reply_flags) & 467 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 468 atomic_dec(&mrioc->admin_reply_q_in_use); 469 return 0; 470 } 471 472 do { 473 if (mrioc->unrecoverable || mrioc->io_admin_reset_sync) 474 break; 475 476 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci); 477 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma); 478 if (reply_dma) 479 mpi3mr_repost_reply_buf(mrioc, reply_dma); 480 num_admin_replies++; 481 threshold_comps++; 482 if (++admin_reply_ci == mrioc->num_admin_replies) { 483 admin_reply_ci = 0; 484 exp_phase ^= 1; 485 } 486 reply_desc = 487 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 488 admin_reply_ci; 489 if ((le16_to_cpu(reply_desc->reply_flags) & 490 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 491 break; 492 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) { 493 writel(admin_reply_ci, 494 &mrioc->sysif_regs->admin_reply_queue_ci); 495 threshold_comps = 0; 496 } 497 } while (1); 498 499 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 500 mrioc->admin_reply_ci = admin_reply_ci; 501 mrioc->admin_reply_ephase = exp_phase; 502 atomic_dec(&mrioc->admin_reply_q_in_use); 503 504 return num_admin_replies; 505 } 506 507 /** 508 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to 509 * queue's consumer index from operational reply descriptor queue. 510 * @op_reply_q: op_reply_qinfo object 511 * @reply_ci: operational reply descriptor's queue consumer index 512 * 513 * Returns: reply descriptor frame address 514 */ 515 static inline struct mpi3_default_reply_descriptor * 516 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) 517 { 518 void *segment_base_addr; 519 struct segments *segments = op_reply_q->q_segments; 520 struct mpi3_default_reply_descriptor *reply_desc = NULL; 521 522 segment_base_addr = 523 segments[reply_ci / op_reply_q->segment_qd].segment; 524 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr + 525 (reply_ci % op_reply_q->segment_qd); 526 return reply_desc; 527 } 528 529 /** 530 * mpi3mr_process_op_reply_q - Operational reply queue handler 531 * @mrioc: Adapter instance reference 532 * @op_reply_q: Operational reply queue info 533 * 534 * Checks the specific operational reply queue and drains the 535 * reply queue entries until the queue is empty and process the 536 * individual reply descriptors. 537 * 538 * Return: 0 if queue is already processed,or number of reply 539 * descriptors processed. 540 */ 541 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 542 struct op_reply_qinfo *op_reply_q) 543 { 544 struct op_req_qinfo *op_req_q; 545 u32 exp_phase; 546 u32 reply_ci; 547 u32 num_op_reply = 0; 548 u64 reply_dma = 0; 549 struct mpi3_default_reply_descriptor *reply_desc; 550 u16 req_q_idx = 0, reply_qidx, threshold_comps = 0; 551 552 reply_qidx = op_reply_q->qid - 1; 553 554 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1)) 555 return 0; 556 557 exp_phase = op_reply_q->ephase; 558 reply_ci = op_reply_q->ci; 559 560 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 561 if ((le16_to_cpu(reply_desc->reply_flags) & 562 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 563 atomic_dec(&op_reply_q->in_use); 564 return 0; 565 } 566 567 do { 568 if (mrioc->unrecoverable || mrioc->io_admin_reset_sync) 569 break; 570 571 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1; 572 op_req_q = &mrioc->req_qinfo[req_q_idx]; 573 574 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci)); 575 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma, 576 reply_qidx); 577 578 if (reply_dma) 579 mpi3mr_repost_reply_buf(mrioc, reply_dma); 580 num_op_reply++; 581 threshold_comps++; 582 583 if (++reply_ci == op_reply_q->num_replies) { 584 reply_ci = 0; 585 exp_phase ^= 1; 586 } 587 588 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 589 590 if ((le16_to_cpu(reply_desc->reply_flags) & 591 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 592 break; 593 #ifndef CONFIG_PREEMPT_RT 594 /* 595 * Exit completion loop to avoid CPU lockup 596 * Ensure remaining completion happens from threaded ISR. 597 */ 598 if (num_op_reply > mrioc->max_host_ios) { 599 op_reply_q->enable_irq_poll = true; 600 break; 601 } 602 #endif 603 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) { 604 writel(reply_ci, 605 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 606 atomic_sub(threshold_comps, &op_reply_q->pend_ios); 607 threshold_comps = 0; 608 } 609 } while (1); 610 611 writel(reply_ci, 612 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 613 op_reply_q->ci = reply_ci; 614 op_reply_q->ephase = exp_phase; 615 atomic_sub(threshold_comps, &op_reply_q->pend_ios); 616 atomic_dec(&op_reply_q->in_use); 617 return num_op_reply; 618 } 619 620 /** 621 * mpi3mr_blk_mq_poll - Operational reply queue handler 622 * @shost: SCSI Host reference 623 * @queue_num: Request queue number (w.r.t OS it is hardware context number) 624 * 625 * Checks the specific operational reply queue and drains the 626 * reply queue entries until the queue is empty and process the 627 * individual reply descriptors. 628 * 629 * Return: 0 if queue is already processed,or number of reply 630 * descriptors processed. 631 */ 632 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 633 { 634 int num_entries = 0; 635 struct mpi3mr_ioc *mrioc; 636 637 mrioc = (struct mpi3mr_ioc *)shost->hostdata; 638 639 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset || 640 mrioc->unrecoverable || mrioc->pci_err_recovery)) 641 return 0; 642 643 num_entries = mpi3mr_process_op_reply_q(mrioc, 644 &mrioc->op_reply_qinfo[queue_num]); 645 646 return num_entries; 647 } 648 649 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) 650 { 651 struct mpi3mr_intr_info *intr_info = privdata; 652 struct mpi3mr_ioc *mrioc; 653 u16 midx; 654 u32 num_admin_replies = 0, num_op_reply = 0; 655 656 if (!intr_info) 657 return IRQ_NONE; 658 659 mrioc = intr_info->mrioc; 660 661 if (!mrioc->intr_enabled) 662 return IRQ_NONE; 663 664 midx = intr_info->msix_index; 665 666 if (!midx) 667 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc); 668 if (intr_info->op_reply_q) 669 num_op_reply = mpi3mr_process_op_reply_q(mrioc, 670 intr_info->op_reply_q); 671 672 if (num_admin_replies || num_op_reply) 673 return IRQ_HANDLED; 674 else 675 return IRQ_NONE; 676 } 677 678 #ifndef CONFIG_PREEMPT_RT 679 680 static irqreturn_t mpi3mr_isr(int irq, void *privdata) 681 { 682 struct mpi3mr_intr_info *intr_info = privdata; 683 int ret; 684 685 if (!intr_info) 686 return IRQ_NONE; 687 688 /* Call primary ISR routine */ 689 ret = mpi3mr_isr_primary(irq, privdata); 690 691 /* 692 * If more IOs are expected, schedule IRQ polling thread. 693 * Otherwise exit from ISR. 694 */ 695 if (!intr_info->op_reply_q) 696 return ret; 697 698 if (!intr_info->op_reply_q->enable_irq_poll || 699 !atomic_read(&intr_info->op_reply_q->pend_ios)) 700 return ret; 701 702 disable_irq_nosync(intr_info->os_irq); 703 704 return IRQ_WAKE_THREAD; 705 } 706 707 /** 708 * mpi3mr_isr_poll - Reply queue polling routine 709 * @irq: IRQ 710 * @privdata: Interrupt info 711 * 712 * poll for pending I/O completions in a loop until pending I/Os 713 * present or controller queue depth I/Os are processed. 714 * 715 * Return: IRQ_NONE or IRQ_HANDLED 716 */ 717 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) 718 { 719 struct mpi3mr_intr_info *intr_info = privdata; 720 struct mpi3mr_ioc *mrioc; 721 u16 midx; 722 u32 num_op_reply = 0; 723 724 if (!intr_info || !intr_info->op_reply_q) 725 return IRQ_NONE; 726 727 mrioc = intr_info->mrioc; 728 midx = intr_info->msix_index; 729 730 /* Poll for pending IOs completions */ 731 do { 732 if (!mrioc->intr_enabled || mrioc->unrecoverable) 733 break; 734 735 if (!midx) 736 mpi3mr_process_admin_reply_q(mrioc); 737 if (intr_info->op_reply_q) 738 num_op_reply += 739 mpi3mr_process_op_reply_q(mrioc, 740 intr_info->op_reply_q); 741 742 usleep_range(MPI3MR_IRQ_POLL_SLEEP, MPI3MR_IRQ_POLL_SLEEP + 1); 743 744 } while (atomic_read(&intr_info->op_reply_q->pend_ios) && 745 (num_op_reply < mrioc->max_host_ios)); 746 747 intr_info->op_reply_q->enable_irq_poll = false; 748 enable_irq(intr_info->os_irq); 749 750 return IRQ_HANDLED; 751 } 752 753 #endif 754 755 /** 756 * mpi3mr_request_irq - Request IRQ and register ISR 757 * @mrioc: Adapter instance reference 758 * @index: IRQ vector index 759 * 760 * Request threaded ISR with primary ISR and secondary 761 * 762 * Return: 0 on success and non zero on failures. 763 */ 764 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) 765 { 766 struct pci_dev *pdev = mrioc->pdev; 767 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index; 768 int retval = 0; 769 770 intr_info->mrioc = mrioc; 771 intr_info->msix_index = index; 772 intr_info->op_reply_q = NULL; 773 774 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", 775 mrioc->driver_name, mrioc->id, index); 776 777 #ifndef CONFIG_PREEMPT_RT 778 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, 779 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); 780 #else 781 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary, 782 NULL, IRQF_SHARED, intr_info->name, intr_info); 783 #endif 784 if (retval) { 785 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", 786 intr_info->name, pci_irq_vector(pdev, index)); 787 return retval; 788 } 789 790 intr_info->os_irq = pci_irq_vector(pdev, index); 791 return retval; 792 } 793 794 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors) 795 { 796 if (!mrioc->requested_poll_qcount) 797 return; 798 799 /* Reserved for Admin and Default Queue */ 800 if (max_vectors > 2 && 801 (mrioc->requested_poll_qcount < max_vectors - 2)) { 802 ioc_info(mrioc, 803 "enabled polled queues (%d) msix (%d)\n", 804 mrioc->requested_poll_qcount, max_vectors); 805 } else { 806 ioc_info(mrioc, 807 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n", 808 mrioc->requested_poll_qcount, max_vectors); 809 mrioc->requested_poll_qcount = 0; 810 } 811 } 812 813 /** 814 * mpi3mr_setup_isr - Setup ISR for the controller 815 * @mrioc: Adapter instance reference 816 * @setup_one: Request one IRQ or more 817 * 818 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR 819 * 820 * Return: 0 on success and non zero on failures. 821 */ 822 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) 823 { 824 unsigned int irq_flags = PCI_IRQ_MSIX; 825 int max_vectors, min_vec; 826 int retval; 827 int i; 828 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 }; 829 830 if (mrioc->is_intr_info_set) 831 return 0; 832 833 mpi3mr_cleanup_isr(mrioc); 834 835 if (setup_one || reset_devices) { 836 max_vectors = 1; 837 retval = pci_alloc_irq_vectors(mrioc->pdev, 838 1, max_vectors, irq_flags); 839 if (retval < 0) { 840 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 841 retval); 842 goto out_failed; 843 } 844 } else { 845 max_vectors = 846 min_t(int, mrioc->cpu_count + 1 + 847 mrioc->requested_poll_qcount, mrioc->msix_count); 848 849 mpi3mr_calc_poll_queues(mrioc, max_vectors); 850 851 ioc_info(mrioc, 852 "MSI-X vectors supported: %d, no of cores: %d,", 853 mrioc->msix_count, mrioc->cpu_count); 854 ioc_info(mrioc, 855 "MSI-x vectors requested: %d poll_queues %d\n", 856 max_vectors, mrioc->requested_poll_qcount); 857 858 desc.post_vectors = mrioc->requested_poll_qcount; 859 min_vec = desc.pre_vectors + desc.post_vectors; 860 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 861 862 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev, 863 min_vec, max_vectors, irq_flags, &desc); 864 865 if (retval < 0) { 866 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 867 retval); 868 goto out_failed; 869 } 870 871 872 /* 873 * If only one MSI-x is allocated, then MSI-x 0 will be shared 874 * between Admin queue and operational queue 875 */ 876 if (retval == min_vec) 877 mrioc->op_reply_q_offset = 0; 878 else if (retval != (max_vectors)) { 879 ioc_info(mrioc, 880 "allocated vectors (%d) are less than configured (%d)\n", 881 retval, max_vectors); 882 } 883 884 max_vectors = retval; 885 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0; 886 887 mpi3mr_calc_poll_queues(mrioc, max_vectors); 888 889 } 890 891 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors, 892 GFP_KERNEL); 893 if (!mrioc->intr_info) { 894 retval = -ENOMEM; 895 pci_free_irq_vectors(mrioc->pdev); 896 goto out_failed; 897 } 898 for (i = 0; i < max_vectors; i++) { 899 retval = mpi3mr_request_irq(mrioc, i); 900 if (retval) { 901 mrioc->intr_info_count = i; 902 goto out_failed; 903 } 904 } 905 if (reset_devices || !setup_one) 906 mrioc->is_intr_info_set = true; 907 mrioc->intr_info_count = max_vectors; 908 mpi3mr_ioc_enable_intr(mrioc); 909 return 0; 910 911 out_failed: 912 mpi3mr_cleanup_isr(mrioc); 913 914 return retval; 915 } 916 917 static const struct { 918 enum mpi3mr_iocstate value; 919 char *name; 920 } mrioc_states[] = { 921 { MRIOC_STATE_READY, "ready" }, 922 { MRIOC_STATE_FAULT, "fault" }, 923 { MRIOC_STATE_RESET, "reset" }, 924 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 925 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 926 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" }, 927 }; 928 929 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 930 { 931 int i; 932 char *name = NULL; 933 934 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) { 935 if (mrioc_states[i].value == mrioc_state) { 936 name = mrioc_states[i].name; 937 break; 938 } 939 } 940 return name; 941 } 942 943 /* Reset reason to name mapper structure*/ 944 static const struct { 945 enum mpi3mr_reset_reason value; 946 char *name; 947 } mpi3mr_reset_reason_codes[] = { 948 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 949 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 950 { MPI3MR_RESET_FROM_APP, "application invocation" }, 951 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 952 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 953 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" }, 954 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 955 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 956 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 957 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 958 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 959 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 960 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 961 { 962 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 963 "create request queue timeout" 964 }, 965 { 966 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 967 "create reply queue timeout" 968 }, 969 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 970 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 971 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 972 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 973 { 974 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 975 "component image activation timeout" 976 }, 977 { 978 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 979 "get package version timeout" 980 }, 981 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 982 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 983 { 984 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT, 985 "diagnostic buffer post timeout" 986 }, 987 { 988 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT, 989 "diagnostic buffer release timeout" 990 }, 991 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" }, 992 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"}, 993 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" }, 994 }; 995 996 /** 997 * mpi3mr_reset_rc_name - get reset reason code name 998 * @reason_code: reset reason code value 999 * 1000 * Map reset reason to an NULL terminated ASCII string 1001 * 1002 * Return: name corresponding to reset reason value or NULL. 1003 */ 1004 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 1005 { 1006 int i; 1007 char *name = NULL; 1008 1009 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) { 1010 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 1011 name = mpi3mr_reset_reason_codes[i].name; 1012 break; 1013 } 1014 } 1015 return name; 1016 } 1017 1018 /* Reset type to name mapper structure*/ 1019 static const struct { 1020 u16 reset_type; 1021 char *name; 1022 } mpi3mr_reset_types[] = { 1023 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 1024 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 1025 }; 1026 1027 /** 1028 * mpi3mr_reset_type_name - get reset type name 1029 * @reset_type: reset type value 1030 * 1031 * Map reset type to an NULL terminated ASCII string 1032 * 1033 * Return: name corresponding to reset type value or NULL. 1034 */ 1035 static const char *mpi3mr_reset_type_name(u16 reset_type) 1036 { 1037 int i; 1038 char *name = NULL; 1039 1040 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) { 1041 if (mpi3mr_reset_types[i].reset_type == reset_type) { 1042 name = mpi3mr_reset_types[i].name; 1043 break; 1044 } 1045 } 1046 return name; 1047 } 1048 1049 /** 1050 * mpi3mr_is_fault_recoverable - Read fault code and decide 1051 * whether the controller can be recoverable 1052 * @mrioc: Adapter instance reference 1053 * Return: true if fault is recoverable, false otherwise. 1054 */ 1055 static inline bool mpi3mr_is_fault_recoverable(struct mpi3mr_ioc *mrioc) 1056 { 1057 u32 fault; 1058 1059 fault = (readl(&mrioc->sysif_regs->fault) & 1060 MPI3_SYSIF_FAULT_CODE_MASK); 1061 1062 switch (fault) { 1063 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED: 1064 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED: 1065 ioc_warn(mrioc, 1066 "controller requires system power cycle, marking controller as unrecoverable\n"); 1067 return false; 1068 case MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER: 1069 ioc_warn(mrioc, 1070 "controller faulted due to insufficient power,\n" 1071 " try by connecting it to a different slot\n"); 1072 return false; 1073 default: 1074 break; 1075 } 1076 return true; 1077 } 1078 1079 /** 1080 * mpi3mr_print_fault_info - Display fault information 1081 * @mrioc: Adapter instance reference 1082 * 1083 * Display the controller fault information if there is a 1084 * controller fault. 1085 * 1086 * Return: Nothing. 1087 */ 1088 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc) 1089 { 1090 u32 ioc_status, code, code1, code2, code3; 1091 1092 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1093 1094 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1095 code = readl(&mrioc->sysif_regs->fault); 1096 code1 = readl(&mrioc->sysif_regs->fault_info[0]); 1097 code2 = readl(&mrioc->sysif_regs->fault_info[1]); 1098 code3 = readl(&mrioc->sysif_regs->fault_info[2]); 1099 1100 ioc_info(mrioc, 1101 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n", 1102 code, code1, code2, code3); 1103 } 1104 } 1105 1106 /** 1107 * mpi3mr_get_iocstate - Get IOC State 1108 * @mrioc: Adapter instance reference 1109 * 1110 * Return a proper IOC state enum based on the IOC status and 1111 * IOC configuration and unrcoverable state of the controller. 1112 * 1113 * Return: Current IOC state. 1114 */ 1115 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc) 1116 { 1117 u32 ioc_status, ioc_config; 1118 u8 ready, enabled; 1119 1120 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1121 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1122 1123 if (mrioc->unrecoverable) 1124 return MRIOC_STATE_UNRECOVERABLE; 1125 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1126 return MRIOC_STATE_FAULT; 1127 1128 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1129 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1130 1131 if (ready && enabled) 1132 return MRIOC_STATE_READY; 1133 if ((!ready) && (!enabled)) 1134 return MRIOC_STATE_RESET; 1135 if ((!ready) && (enabled)) 1136 return MRIOC_STATE_BECOMING_READY; 1137 1138 return MRIOC_STATE_RESET_REQUESTED; 1139 } 1140 1141 /** 1142 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma 1143 * @mrioc: Adapter instance reference 1144 * 1145 * Free the DMA memory allocated for IOCTL handling purpose. 1146 * 1147 * Return: None 1148 */ 1149 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc) 1150 { 1151 struct dma_memory_desc *mem_desc; 1152 u16 i; 1153 1154 if (!mrioc->ioctl_dma_pool) 1155 return; 1156 1157 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) { 1158 mem_desc = &mrioc->ioctl_sge[i]; 1159 if (mem_desc->addr) { 1160 dma_pool_free(mrioc->ioctl_dma_pool, 1161 mem_desc->addr, 1162 mem_desc->dma_addr); 1163 mem_desc->addr = NULL; 1164 } 1165 } 1166 dma_pool_destroy(mrioc->ioctl_dma_pool); 1167 mrioc->ioctl_dma_pool = NULL; 1168 mem_desc = &mrioc->ioctl_chain_sge; 1169 1170 if (mem_desc->addr) { 1171 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 1172 mem_desc->addr, mem_desc->dma_addr); 1173 mem_desc->addr = NULL; 1174 } 1175 mem_desc = &mrioc->ioctl_resp_sge; 1176 if (mem_desc->addr) { 1177 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 1178 mem_desc->addr, mem_desc->dma_addr); 1179 mem_desc->addr = NULL; 1180 } 1181 1182 mrioc->ioctl_sges_allocated = false; 1183 } 1184 1185 /** 1186 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma 1187 * @mrioc: Adapter instance reference 1188 * 1189 * This function allocates dmaable memory required to handle the 1190 * application issued MPI3 IOCTL requests. 1191 * 1192 * Return: None 1193 */ 1194 static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc) 1195 1196 { 1197 struct dma_memory_desc *mem_desc; 1198 u16 i; 1199 1200 mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool", 1201 &mrioc->pdev->dev, 1202 MPI3MR_IOCTL_SGE_SIZE, 1203 MPI3MR_PAGE_SIZE_4K, 0); 1204 1205 if (!mrioc->ioctl_dma_pool) { 1206 ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n"); 1207 goto out_failed; 1208 } 1209 1210 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) { 1211 mem_desc = &mrioc->ioctl_sge[i]; 1212 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE; 1213 mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool, 1214 GFP_KERNEL, 1215 &mem_desc->dma_addr); 1216 if (!mem_desc->addr) 1217 goto out_failed; 1218 } 1219 1220 mem_desc = &mrioc->ioctl_chain_sge; 1221 mem_desc->size = MPI3MR_PAGE_SIZE_4K; 1222 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 1223 mem_desc->size, 1224 &mem_desc->dma_addr, 1225 GFP_KERNEL); 1226 if (!mem_desc->addr) 1227 goto out_failed; 1228 1229 mem_desc = &mrioc->ioctl_resp_sge; 1230 mem_desc->size = MPI3MR_PAGE_SIZE_4K; 1231 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 1232 mem_desc->size, 1233 &mem_desc->dma_addr, 1234 GFP_KERNEL); 1235 if (!mem_desc->addr) 1236 goto out_failed; 1237 1238 mrioc->ioctl_sges_allocated = true; 1239 1240 return; 1241 out_failed: 1242 ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n" 1243 "from the applications, application interface for MPT command is disabled\n"); 1244 mpi3mr_free_ioctl_dma_memory(mrioc); 1245 } 1246 1247 /** 1248 * mpi3mr_clear_reset_history - clear reset history 1249 * @mrioc: Adapter instance reference 1250 * 1251 * Write the reset history bit in IOC status to clear the bit, 1252 * if it is already set. 1253 * 1254 * Return: Nothing. 1255 */ 1256 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) 1257 { 1258 u32 ioc_status; 1259 1260 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1261 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1262 writel(ioc_status, &mrioc->sysif_regs->ioc_status); 1263 } 1264 1265 /** 1266 * mpi3mr_issue_and_process_mur - Message unit Reset handler 1267 * @mrioc: Adapter instance reference 1268 * @reset_reason: Reset reason code 1269 * 1270 * Issue Message unit Reset to the controller and wait for it to 1271 * be complete. 1272 * 1273 * Return: 0 on success, -1 on failure. 1274 */ 1275 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, 1276 u32 reset_reason) 1277 { 1278 u32 ioc_config, timeout, ioc_status, scratch_pad0; 1279 int retval = -1; 1280 1281 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); 1282 if (mrioc->unrecoverable) { 1283 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n"); 1284 return retval; 1285 } 1286 mpi3mr_clear_reset_history(mrioc); 1287 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX << 1288 MPI3MR_RESET_REASON_OSTYPE_SHIFT) | 1289 (mrioc->facts.ioc_num << 1290 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason); 1291 writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]); 1292 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1293 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1294 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1295 1296 timeout = MPI3MR_MUR_TIMEOUT * 10; 1297 do { 1298 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1299 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1300 mpi3mr_clear_reset_history(mrioc); 1301 break; 1302 } 1303 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1304 mpi3mr_print_fault_info(mrioc); 1305 break; 1306 } 1307 msleep(100); 1308 } while (--timeout); 1309 1310 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1311 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1312 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1313 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1314 retval = 0; 1315 1316 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%08x)/(0x%08x)\n", 1317 (!retval) ? "successful" : "failed", ioc_status, ioc_config); 1318 return retval; 1319 } 1320 1321 /** 1322 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters 1323 * during reset/resume 1324 * @mrioc: Adapter instance reference 1325 * 1326 * Return: zero if the new IOCFacts parameters value is compatible with 1327 * older values else return -EPERM 1328 */ 1329 static int 1330 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc) 1331 { 1332 unsigned long *removepend_bitmap; 1333 1334 if (mrioc->facts.reply_sz > mrioc->reply_sz) { 1335 ioc_err(mrioc, 1336 "cannot increase reply size from %d to %d\n", 1337 mrioc->reply_sz, mrioc->facts.reply_sz); 1338 return -EPERM; 1339 } 1340 1341 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) { 1342 ioc_err(mrioc, 1343 "cannot reduce number of operational reply queues from %d to %d\n", 1344 mrioc->num_op_reply_q, 1345 mrioc->facts.max_op_reply_q); 1346 return -EPERM; 1347 } 1348 1349 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) { 1350 ioc_err(mrioc, 1351 "cannot reduce number of operational request queues from %d to %d\n", 1352 mrioc->num_op_req_q, mrioc->facts.max_op_req_q); 1353 return -EPERM; 1354 } 1355 1356 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512)) 1357 ioc_err(mrioc, "Warning: The maximum data transfer length\n" 1358 "\tchanged after reset: previous(%d), new(%d),\n" 1359 "the driver cannot change this at run time\n", 1360 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length); 1361 1362 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities & 1363 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) 1364 ioc_err(mrioc, 1365 "critical error: multipath capability is enabled at the\n" 1366 "\tcontroller while sas transport support is enabled at the\n" 1367 "\tdriver, please reboot the system or reload the driver\n"); 1368 1369 if (mrioc->seg_tb_support) { 1370 if (!(mrioc->facts.ioc_capabilities & 1371 MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED)) { 1372 ioc_err(mrioc, 1373 "critical error: previously enabled segmented trace\n" 1374 " buffer capability is disabled after reset. Please\n" 1375 " update the firmware or reboot the system or\n" 1376 " reload the driver to enable trace diag buffer\n"); 1377 mrioc->diag_buffers[0].disabled_after_reset = true; 1378 } else 1379 mrioc->diag_buffers[0].disabled_after_reset = false; 1380 } 1381 1382 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) { 1383 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle, 1384 GFP_KERNEL); 1385 if (!removepend_bitmap) { 1386 ioc_err(mrioc, 1387 "failed to increase removepend_bitmap bits from %d to %d\n", 1388 mrioc->dev_handle_bitmap_bits, 1389 mrioc->facts.max_devhandle); 1390 return -EPERM; 1391 } 1392 bitmap_free(mrioc->removepend_bitmap); 1393 mrioc->removepend_bitmap = removepend_bitmap; 1394 ioc_info(mrioc, 1395 "increased bits of dev_handle_bitmap from %d to %d\n", 1396 mrioc->dev_handle_bitmap_bits, 1397 mrioc->facts.max_devhandle); 1398 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 1399 } 1400 1401 return 0; 1402 } 1403 1404 /** 1405 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1406 * @mrioc: Adapter instance reference 1407 * 1408 * Set Enable IOC bit in IOC configuration register and wait for 1409 * the controller to become ready. 1410 * 1411 * Return: 0 on success, appropriate error on failure. 1412 */ 1413 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc) 1414 { 1415 u32 ioc_config, ioc_status, timeout, host_diagnostic; 1416 int retval = 0; 1417 enum mpi3mr_iocstate ioc_state; 1418 u64 base_info; 1419 u8 retry = 0; 1420 u64 start_time, elapsed_time_sec; 1421 1422 retry_bring_ioc_ready: 1423 1424 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1425 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1426 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information); 1427 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n", 1428 ioc_status, ioc_config, base_info); 1429 1430 if (!mpi3mr_is_fault_recoverable(mrioc)) { 1431 mrioc->unrecoverable = 1; 1432 goto out_device_not_present; 1433 } 1434 1435 /*The timeout value is in 2sec unit, changing it to seconds*/ 1436 mrioc->ready_timeout = 1437 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 1438 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 1439 1440 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout); 1441 1442 ioc_state = mpi3mr_get_iocstate(mrioc); 1443 ioc_info(mrioc, "controller is in %s state during detection\n", 1444 mpi3mr_iocstate_name(ioc_state)); 1445 1446 timeout = mrioc->ready_timeout * 10; 1447 1448 do { 1449 ioc_state = mpi3mr_get_iocstate(mrioc); 1450 1451 if (ioc_state != MRIOC_STATE_BECOMING_READY && 1452 ioc_state != MRIOC_STATE_RESET_REQUESTED) 1453 break; 1454 1455 if (!pci_device_is_present(mrioc->pdev)) { 1456 mrioc->unrecoverable = 1; 1457 ioc_err(mrioc, "controller is not present while waiting to reset\n"); 1458 goto out_device_not_present; 1459 } 1460 1461 msleep(100); 1462 } while (--timeout); 1463 1464 if (ioc_state == MRIOC_STATE_READY) { 1465 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n"); 1466 retval = mpi3mr_issue_and_process_mur(mrioc, 1467 MPI3MR_RESET_FROM_BRINGUP); 1468 ioc_state = mpi3mr_get_iocstate(mrioc); 1469 if (retval) 1470 ioc_err(mrioc, 1471 "message unit reset failed with error %d current state %s\n", 1472 retval, mpi3mr_iocstate_name(ioc_state)); 1473 } 1474 if (ioc_state != MRIOC_STATE_RESET) { 1475 if (ioc_state == MRIOC_STATE_FAULT) { 1476 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 1477 mpi3mr_print_fault_info(mrioc); 1478 do { 1479 host_diagnostic = 1480 readl(&mrioc->sysif_regs->host_diagnostic); 1481 if (!(host_diagnostic & 1482 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 1483 break; 1484 if (!pci_device_is_present(mrioc->pdev)) { 1485 mrioc->unrecoverable = 1; 1486 ioc_err(mrioc, "controller is not present at the bringup\n"); 1487 goto out_device_not_present; 1488 } 1489 msleep(100); 1490 } while (--timeout); 1491 } 1492 mpi3mr_print_fault_info(mrioc); 1493 ioc_info(mrioc, "issuing soft reset to bring to reset state\n"); 1494 retval = mpi3mr_issue_reset(mrioc, 1495 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 1496 MPI3MR_RESET_FROM_BRINGUP); 1497 if (retval) { 1498 ioc_err(mrioc, 1499 "soft reset failed with error %d\n", retval); 1500 goto out_failed; 1501 } 1502 } 1503 ioc_state = mpi3mr_get_iocstate(mrioc); 1504 if (ioc_state != MRIOC_STATE_RESET) { 1505 ioc_err(mrioc, 1506 "cannot bring controller to reset state, current state: %s\n", 1507 mpi3mr_iocstate_name(ioc_state)); 1508 goto out_failed; 1509 } 1510 mpi3mr_clear_reset_history(mrioc); 1511 retval = mpi3mr_setup_admin_qpair(mrioc); 1512 if (retval) { 1513 ioc_err(mrioc, "failed to setup admin queues: error %d\n", 1514 retval); 1515 goto out_failed; 1516 } 1517 1518 ioc_info(mrioc, "bringing controller to ready state\n"); 1519 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1520 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1521 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1522 1523 if (retry == 0) 1524 start_time = jiffies; 1525 1526 timeout = mrioc->ready_timeout * 10; 1527 do { 1528 ioc_state = mpi3mr_get_iocstate(mrioc); 1529 if (ioc_state == MRIOC_STATE_READY) { 1530 ioc_info(mrioc, 1531 "successfully transitioned to %s state\n", 1532 mpi3mr_iocstate_name(ioc_state)); 1533 return 0; 1534 } 1535 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1536 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 1537 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 1538 mpi3mr_print_fault_info(mrioc); 1539 goto out_failed; 1540 } 1541 if (!pci_device_is_present(mrioc->pdev)) { 1542 mrioc->unrecoverable = 1; 1543 ioc_err(mrioc, 1544 "controller is not present at the bringup\n"); 1545 retval = -1; 1546 goto out_device_not_present; 1547 } 1548 msleep(100); 1549 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000; 1550 } while (elapsed_time_sec < mrioc->ready_timeout); 1551 1552 out_failed: 1553 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000; 1554 if ((retry < 2) && (elapsed_time_sec < (mrioc->ready_timeout - 60))) { 1555 retry++; 1556 1557 ioc_warn(mrioc, "retrying to bring IOC ready, retry_count:%d\n" 1558 " elapsed time =%llu\n", retry, elapsed_time_sec); 1559 1560 goto retry_bring_ioc_ready; 1561 } 1562 ioc_state = mpi3mr_get_iocstate(mrioc); 1563 ioc_err(mrioc, 1564 "failed to bring to ready state, current state: %s\n", 1565 mpi3mr_iocstate_name(ioc_state)); 1566 out_device_not_present: 1567 return retval; 1568 } 1569 1570 /** 1571 * mpi3mr_soft_reset_success - Check softreset is success or not 1572 * @ioc_status: IOC status register value 1573 * @ioc_config: IOC config register value 1574 * 1575 * Check whether the soft reset is successful or not based on 1576 * IOC status and IOC config register values. 1577 * 1578 * Return: True when the soft reset is success, false otherwise. 1579 */ 1580 static inline bool 1581 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config) 1582 { 1583 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1584 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1585 return true; 1586 return false; 1587 } 1588 1589 /** 1590 * mpi3mr_diagfault_success - Check diag fault is success or not 1591 * @mrioc: Adapter reference 1592 * @ioc_status: IOC status register value 1593 * 1594 * Check whether the controller hit diag reset fault code. 1595 * 1596 * Return: True when there is diag fault, false otherwise. 1597 */ 1598 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc, 1599 u32 ioc_status) 1600 { 1601 u32 fault; 1602 1603 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1604 return false; 1605 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 1606 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) { 1607 mpi3mr_print_fault_info(mrioc); 1608 return true; 1609 } 1610 return false; 1611 } 1612 1613 /** 1614 * mpi3mr_set_diagsave - Set diag save bit for snapdump 1615 * @mrioc: Adapter reference 1616 * 1617 * Set diag save bit in IOC configuration register to enable 1618 * snapdump. 1619 * 1620 * Return: Nothing. 1621 */ 1622 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) 1623 { 1624 u32 ioc_config; 1625 1626 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1627 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 1628 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1629 } 1630 1631 /** 1632 * mpi3mr_issue_reset - Issue reset to the controller 1633 * @mrioc: Adapter reference 1634 * @reset_type: Reset type 1635 * @reset_reason: Reset reason code 1636 * 1637 * Unlock the host diagnostic registers and write the specific 1638 * reset type to that, wait for reset acknowledgment from the 1639 * controller, if the reset is not successful retry for the 1640 * predefined number of times. 1641 * 1642 * Return: 0 on success, non-zero on failure. 1643 */ 1644 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, 1645 u16 reset_reason) 1646 { 1647 int retval = -1; 1648 u8 unlock_retry_count = 0; 1649 u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0; 1650 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1651 1652 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 1653 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 1654 return retval; 1655 if (mrioc->unrecoverable) 1656 return retval; 1657 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 1658 retval = 0; 1659 return retval; 1660 } 1661 1662 ioc_info(mrioc, "%s reset due to %s(0x%x)\n", 1663 mpi3mr_reset_type_name(reset_type), 1664 mpi3mr_reset_rc_name(reset_reason), reset_reason); 1665 1666 mpi3mr_clear_reset_history(mrioc); 1667 do { 1668 ioc_info(mrioc, 1669 "Write magic sequence to unlock host diag register (retry=%d)\n", 1670 ++unlock_retry_count); 1671 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 1672 ioc_err(mrioc, 1673 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n", 1674 mpi3mr_reset_type_name(reset_type), 1675 host_diagnostic); 1676 mrioc->unrecoverable = 1; 1677 return retval; 1678 } 1679 1680 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH, 1681 &mrioc->sysif_regs->write_sequence); 1682 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST, 1683 &mrioc->sysif_regs->write_sequence); 1684 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1685 &mrioc->sysif_regs->write_sequence); 1686 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD, 1687 &mrioc->sysif_regs->write_sequence); 1688 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH, 1689 &mrioc->sysif_regs->write_sequence); 1690 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH, 1691 &mrioc->sysif_regs->write_sequence); 1692 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH, 1693 &mrioc->sysif_regs->write_sequence); 1694 usleep_range(1000, 1100); 1695 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 1696 ioc_info(mrioc, 1697 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 1698 unlock_retry_count, host_diagnostic); 1699 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 1700 1701 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX << 1702 MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num << 1703 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason); 1704 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1705 writel(host_diagnostic | reset_type, 1706 &mrioc->sysif_regs->host_diagnostic); 1707 switch (reset_type) { 1708 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET: 1709 do { 1710 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1711 ioc_config = 1712 readl(&mrioc->sysif_regs->ioc_configuration); 1713 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1714 && mpi3mr_soft_reset_success(ioc_status, ioc_config) 1715 ) { 1716 mpi3mr_clear_reset_history(mrioc); 1717 retval = 0; 1718 break; 1719 } 1720 msleep(100); 1721 } while (--timeout); 1722 mpi3mr_print_fault_info(mrioc); 1723 break; 1724 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT: 1725 do { 1726 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1727 if (mpi3mr_diagfault_success(mrioc, ioc_status)) { 1728 retval = 0; 1729 break; 1730 } 1731 msleep(100); 1732 } while (--timeout); 1733 break; 1734 default: 1735 break; 1736 } 1737 1738 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1739 &mrioc->sysif_regs->write_sequence); 1740 1741 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1742 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1743 ioc_info(mrioc, 1744 "ioc_status/ioc_config after %s reset is (0x%08x)/(0x%08x)\n", 1745 (!retval)?"successful":"failed", ioc_status, 1746 ioc_config); 1747 if (retval) 1748 mrioc->unrecoverable = 1; 1749 return retval; 1750 } 1751 1752 /** 1753 * mpi3mr_admin_request_post - Post request to admin queue 1754 * @mrioc: Adapter reference 1755 * @admin_req: MPI3 request 1756 * @admin_req_sz: Request size 1757 * @ignore_reset: Ignore reset in process 1758 * 1759 * Post the MPI3 request into admin request queue and 1760 * inform the controller, if the queue is full return 1761 * appropriate error. 1762 * 1763 * Return: 0 on success, non-zero on failure. 1764 */ 1765 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1766 u16 admin_req_sz, u8 ignore_reset) 1767 { 1768 u16 areq_pi = 0, areq_ci = 0, max_entries = 0; 1769 int retval = 0; 1770 unsigned long flags; 1771 u8 *areq_entry; 1772 1773 if (mrioc->unrecoverable) { 1774 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__); 1775 return -EFAULT; 1776 } 1777 1778 spin_lock_irqsave(&mrioc->admin_req_lock, flags); 1779 areq_pi = mrioc->admin_req_pi; 1780 areq_ci = mrioc->admin_req_ci; 1781 max_entries = mrioc->num_admin_req; 1782 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 1783 (areq_pi == (max_entries - 1)))) { 1784 ioc_err(mrioc, "AdminReqQ full condition detected\n"); 1785 retval = -EAGAIN; 1786 goto out; 1787 } 1788 if (!ignore_reset && mrioc->reset_in_progress) { 1789 ioc_err(mrioc, "AdminReqQ submit reset in progress\n"); 1790 retval = -EAGAIN; 1791 goto out; 1792 } 1793 if (mrioc->pci_err_recovery) { 1794 ioc_err(mrioc, "admin request queue submission failed due to pci error recovery in progress\n"); 1795 retval = -EAGAIN; 1796 goto out; 1797 } 1798 1799 areq_entry = (u8 *)mrioc->admin_req_base + 1800 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ); 1801 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ); 1802 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz); 1803 1804 if (++areq_pi == max_entries) 1805 areq_pi = 0; 1806 mrioc->admin_req_pi = areq_pi; 1807 1808 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 1809 1810 out: 1811 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags); 1812 1813 return retval; 1814 } 1815 1816 /** 1817 * mpi3mr_free_op_req_q_segments - free request memory segments 1818 * @mrioc: Adapter instance reference 1819 * @q_idx: operational request queue index 1820 * 1821 * Free memory segments allocated for operational request queue 1822 * 1823 * Return: Nothing. 1824 */ 1825 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1826 { 1827 u16 j; 1828 int size; 1829 struct segments *segments; 1830 1831 segments = mrioc->req_qinfo[q_idx].q_segments; 1832 if (!segments) 1833 return; 1834 1835 if (mrioc->enable_segqueue) { 1836 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1837 if (mrioc->req_qinfo[q_idx].q_segment_list) { 1838 dma_free_coherent(&mrioc->pdev->dev, 1839 MPI3MR_MAX_SEG_LIST_SIZE, 1840 mrioc->req_qinfo[q_idx].q_segment_list, 1841 mrioc->req_qinfo[q_idx].q_segment_list_dma); 1842 mrioc->req_qinfo[q_idx].q_segment_list = NULL; 1843 } 1844 } else 1845 size = mrioc->req_qinfo[q_idx].segment_qd * 1846 mrioc->facts.op_req_sz; 1847 1848 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) { 1849 if (!segments[j].segment) 1850 continue; 1851 dma_free_coherent(&mrioc->pdev->dev, 1852 size, segments[j].segment, segments[j].segment_dma); 1853 segments[j].segment = NULL; 1854 } 1855 kfree(mrioc->req_qinfo[q_idx].q_segments); 1856 mrioc->req_qinfo[q_idx].q_segments = NULL; 1857 mrioc->req_qinfo[q_idx].qid = 0; 1858 } 1859 1860 /** 1861 * mpi3mr_free_op_reply_q_segments - free reply memory segments 1862 * @mrioc: Adapter instance reference 1863 * @q_idx: operational reply queue index 1864 * 1865 * Free memory segments allocated for operational reply queue 1866 * 1867 * Return: Nothing. 1868 */ 1869 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1870 { 1871 u16 j; 1872 int size; 1873 struct segments *segments; 1874 1875 segments = mrioc->op_reply_qinfo[q_idx].q_segments; 1876 if (!segments) 1877 return; 1878 1879 if (mrioc->enable_segqueue) { 1880 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1881 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) { 1882 dma_free_coherent(&mrioc->pdev->dev, 1883 MPI3MR_MAX_SEG_LIST_SIZE, 1884 mrioc->op_reply_qinfo[q_idx].q_segment_list, 1885 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma); 1886 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 1887 } 1888 } else 1889 size = mrioc->op_reply_qinfo[q_idx].segment_qd * 1890 mrioc->op_reply_desc_sz; 1891 1892 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) { 1893 if (!segments[j].segment) 1894 continue; 1895 dma_free_coherent(&mrioc->pdev->dev, 1896 size, segments[j].segment, segments[j].segment_dma); 1897 segments[j].segment = NULL; 1898 } 1899 1900 kfree(mrioc->op_reply_qinfo[q_idx].q_segments); 1901 mrioc->op_reply_qinfo[q_idx].q_segments = NULL; 1902 mrioc->op_reply_qinfo[q_idx].qid = 0; 1903 } 1904 1905 /** 1906 * mpi3mr_delete_op_reply_q - delete operational reply queue 1907 * @mrioc: Adapter instance reference 1908 * @qidx: operational reply queue index 1909 * 1910 * Delete operatinal reply queue by issuing MPI request 1911 * through admin queue. 1912 * 1913 * Return: 0 on success, non-zero on failure. 1914 */ 1915 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1916 { 1917 struct mpi3_delete_reply_queue_request delq_req; 1918 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1919 int retval = 0; 1920 u16 reply_qid = 0, midx; 1921 1922 reply_qid = op_reply_q->qid; 1923 1924 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1925 1926 if (!reply_qid) { 1927 retval = -1; 1928 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n"); 1929 goto out; 1930 } 1931 1932 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- : 1933 mrioc->active_poll_qcount--; 1934 1935 memset(&delq_req, 0, sizeof(delq_req)); 1936 mutex_lock(&mrioc->init_cmds.mutex); 1937 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1938 retval = -1; 1939 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n"); 1940 mutex_unlock(&mrioc->init_cmds.mutex); 1941 goto out; 1942 } 1943 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1944 mrioc->init_cmds.is_waiting = 1; 1945 mrioc->init_cmds.callback = NULL; 1946 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1947 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 1948 delq_req.queue_id = cpu_to_le16(reply_qid); 1949 1950 init_completion(&mrioc->init_cmds.done); 1951 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req), 1952 1); 1953 if (retval) { 1954 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n"); 1955 goto out_unlock; 1956 } 1957 wait_for_completion_timeout(&mrioc->init_cmds.done, 1958 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1959 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1960 ioc_err(mrioc, "delete reply queue timed out\n"); 1961 mpi3mr_check_rh_fault_ioc(mrioc, 1962 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 1963 retval = -1; 1964 goto out_unlock; 1965 } 1966 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1967 != MPI3_IOCSTATUS_SUCCESS) { 1968 ioc_err(mrioc, 1969 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1970 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1971 mrioc->init_cmds.ioc_loginfo); 1972 retval = -1; 1973 goto out_unlock; 1974 } 1975 mrioc->intr_info[midx].op_reply_q = NULL; 1976 1977 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1978 out_unlock: 1979 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1980 mutex_unlock(&mrioc->init_cmds.mutex); 1981 out: 1982 1983 return retval; 1984 } 1985 1986 /** 1987 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool 1988 * @mrioc: Adapter instance reference 1989 * @qidx: request queue index 1990 * 1991 * Allocate segmented memory pools for operational reply 1992 * queue. 1993 * 1994 * Return: 0 on success, non-zero on failure. 1995 */ 1996 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1997 { 1998 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1999 int i, size; 2000 u64 *q_segment_list_entry = NULL; 2001 struct segments *segments; 2002 2003 if (mrioc->enable_segqueue) { 2004 op_reply_q->segment_qd = 2005 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz; 2006 2007 size = MPI3MR_OP_REP_Q_SEG_SIZE; 2008 2009 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 2010 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma, 2011 GFP_KERNEL); 2012 if (!op_reply_q->q_segment_list) 2013 return -ENOMEM; 2014 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list; 2015 } else { 2016 op_reply_q->segment_qd = op_reply_q->num_replies; 2017 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz; 2018 } 2019 2020 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies, 2021 op_reply_q->segment_qd); 2022 2023 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments, 2024 sizeof(struct segments), GFP_KERNEL); 2025 if (!op_reply_q->q_segments) 2026 return -ENOMEM; 2027 2028 segments = op_reply_q->q_segments; 2029 for (i = 0; i < op_reply_q->num_segments; i++) { 2030 segments[i].segment = 2031 dma_alloc_coherent(&mrioc->pdev->dev, 2032 size, &segments[i].segment_dma, GFP_KERNEL); 2033 if (!segments[i].segment) 2034 return -ENOMEM; 2035 if (mrioc->enable_segqueue) 2036 q_segment_list_entry[i] = 2037 (unsigned long)segments[i].segment_dma; 2038 } 2039 2040 return 0; 2041 } 2042 2043 /** 2044 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool. 2045 * @mrioc: Adapter instance reference 2046 * @qidx: request queue index 2047 * 2048 * Allocate segmented memory pools for operational request 2049 * queue. 2050 * 2051 * Return: 0 on success, non-zero on failure. 2052 */ 2053 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 2054 { 2055 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 2056 int i, size; 2057 u64 *q_segment_list_entry = NULL; 2058 struct segments *segments; 2059 2060 if (mrioc->enable_segqueue) { 2061 op_req_q->segment_qd = 2062 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz; 2063 2064 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 2065 2066 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 2067 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma, 2068 GFP_KERNEL); 2069 if (!op_req_q->q_segment_list) 2070 return -ENOMEM; 2071 q_segment_list_entry = (u64 *)op_req_q->q_segment_list; 2072 2073 } else { 2074 op_req_q->segment_qd = op_req_q->num_requests; 2075 size = op_req_q->num_requests * mrioc->facts.op_req_sz; 2076 } 2077 2078 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests, 2079 op_req_q->segment_qd); 2080 2081 op_req_q->q_segments = kcalloc(op_req_q->num_segments, 2082 sizeof(struct segments), GFP_KERNEL); 2083 if (!op_req_q->q_segments) 2084 return -ENOMEM; 2085 2086 segments = op_req_q->q_segments; 2087 for (i = 0; i < op_req_q->num_segments; i++) { 2088 segments[i].segment = 2089 dma_alloc_coherent(&mrioc->pdev->dev, 2090 size, &segments[i].segment_dma, GFP_KERNEL); 2091 if (!segments[i].segment) 2092 return -ENOMEM; 2093 if (mrioc->enable_segqueue) 2094 q_segment_list_entry[i] = 2095 (unsigned long)segments[i].segment_dma; 2096 } 2097 2098 return 0; 2099 } 2100 2101 /** 2102 * mpi3mr_create_op_reply_q - create operational reply queue 2103 * @mrioc: Adapter instance reference 2104 * @qidx: operational reply queue index 2105 * 2106 * Create operatinal reply queue by issuing MPI request 2107 * through admin queue. 2108 * 2109 * Return: 0 on success, non-zero on failure. 2110 */ 2111 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 2112 { 2113 struct mpi3_create_reply_queue_request create_req; 2114 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 2115 int retval = 0; 2116 u16 reply_qid = 0, midx; 2117 2118 reply_qid = op_reply_q->qid; 2119 2120 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 2121 2122 if (reply_qid) { 2123 retval = -1; 2124 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n", 2125 reply_qid); 2126 2127 return retval; 2128 } 2129 2130 reply_qid = qidx + 1; 2131 2132 if (mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) { 2133 if (mrioc->pdev->revision) 2134 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 2135 else 2136 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K; 2137 } else 2138 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD2K; 2139 2140 op_reply_q->ci = 0; 2141 op_reply_q->ephase = 1; 2142 atomic_set(&op_reply_q->pend_ios, 0); 2143 atomic_set(&op_reply_q->in_use, 0); 2144 op_reply_q->enable_irq_poll = false; 2145 op_reply_q->qfull_watermark = 2146 op_reply_q->num_replies - (MPI3MR_THRESHOLD_REPLY_COUNT * 2); 2147 2148 if (!op_reply_q->q_segments) { 2149 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx); 2150 if (retval) { 2151 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 2152 goto out; 2153 } 2154 } 2155 2156 memset(&create_req, 0, sizeof(create_req)); 2157 mutex_lock(&mrioc->init_cmds.mutex); 2158 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2159 retval = -1; 2160 ioc_err(mrioc, "CreateRepQ: Init command is in use\n"); 2161 goto out_unlock; 2162 } 2163 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2164 mrioc->init_cmds.is_waiting = 1; 2165 mrioc->init_cmds.callback = NULL; 2166 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2167 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 2168 create_req.queue_id = cpu_to_le16(reply_qid); 2169 2170 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount)) 2171 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE; 2172 else 2173 op_reply_q->qtype = MPI3MR_POLL_QUEUE; 2174 2175 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) { 2176 create_req.flags = 2177 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 2178 create_req.msix_index = 2179 cpu_to_le16(mrioc->intr_info[midx].msix_index); 2180 } else { 2181 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1); 2182 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n", 2183 reply_qid, midx); 2184 if (!mrioc->active_poll_qcount) 2185 disable_irq_nosync(pci_irq_vector(mrioc->pdev, 2186 mrioc->intr_info_count - 1)); 2187 } 2188 2189 if (mrioc->enable_segqueue) { 2190 create_req.flags |= 2191 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2192 create_req.base_address = cpu_to_le64( 2193 op_reply_q->q_segment_list_dma); 2194 } else 2195 create_req.base_address = cpu_to_le64( 2196 op_reply_q->q_segments[0].segment_dma); 2197 2198 create_req.size = cpu_to_le16(op_reply_q->num_replies); 2199 2200 init_completion(&mrioc->init_cmds.done); 2201 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2202 sizeof(create_req), 1); 2203 if (retval) { 2204 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n"); 2205 goto out_unlock; 2206 } 2207 wait_for_completion_timeout(&mrioc->init_cmds.done, 2208 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2209 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2210 ioc_err(mrioc, "create reply queue timed out\n"); 2211 mpi3mr_check_rh_fault_ioc(mrioc, 2212 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 2213 retval = -1; 2214 goto out_unlock; 2215 } 2216 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2217 != MPI3_IOCSTATUS_SUCCESS) { 2218 ioc_err(mrioc, 2219 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2220 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2221 mrioc->init_cmds.ioc_loginfo); 2222 retval = -1; 2223 goto out_unlock; 2224 } 2225 op_reply_q->qid = reply_qid; 2226 if (midx < mrioc->intr_info_count) 2227 mrioc->intr_info[midx].op_reply_q = op_reply_q; 2228 2229 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ : 2230 mrioc->active_poll_qcount++; 2231 2232 out_unlock: 2233 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2234 mutex_unlock(&mrioc->init_cmds.mutex); 2235 out: 2236 2237 return retval; 2238 } 2239 2240 /** 2241 * mpi3mr_create_op_req_q - create operational request queue 2242 * @mrioc: Adapter instance reference 2243 * @idx: operational request queue index 2244 * @reply_qid: Reply queue ID 2245 * 2246 * Create operatinal request queue by issuing MPI request 2247 * through admin queue. 2248 * 2249 * Return: 0 on success, non-zero on failure. 2250 */ 2251 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, 2252 u16 reply_qid) 2253 { 2254 struct mpi3_create_request_queue_request create_req; 2255 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx; 2256 int retval = 0; 2257 u16 req_qid = 0; 2258 2259 req_qid = op_req_q->qid; 2260 2261 if (req_qid) { 2262 retval = -1; 2263 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n", 2264 req_qid); 2265 2266 return retval; 2267 } 2268 req_qid = idx + 1; 2269 2270 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD; 2271 op_req_q->ci = 0; 2272 op_req_q->pi = 0; 2273 op_req_q->reply_qid = reply_qid; 2274 spin_lock_init(&op_req_q->q_lock); 2275 2276 if (!op_req_q->q_segments) { 2277 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx); 2278 if (retval) { 2279 mpi3mr_free_op_req_q_segments(mrioc, idx); 2280 goto out; 2281 } 2282 } 2283 2284 memset(&create_req, 0, sizeof(create_req)); 2285 mutex_lock(&mrioc->init_cmds.mutex); 2286 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2287 retval = -1; 2288 ioc_err(mrioc, "CreateReqQ: Init command is in use\n"); 2289 goto out_unlock; 2290 } 2291 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2292 mrioc->init_cmds.is_waiting = 1; 2293 mrioc->init_cmds.callback = NULL; 2294 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2295 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 2296 create_req.queue_id = cpu_to_le16(req_qid); 2297 if (mrioc->enable_segqueue) { 2298 create_req.flags = 2299 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2300 create_req.base_address = cpu_to_le64( 2301 op_req_q->q_segment_list_dma); 2302 } else 2303 create_req.base_address = cpu_to_le64( 2304 op_req_q->q_segments[0].segment_dma); 2305 create_req.reply_queue_id = cpu_to_le16(reply_qid); 2306 create_req.size = cpu_to_le16(op_req_q->num_requests); 2307 2308 init_completion(&mrioc->init_cmds.done); 2309 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2310 sizeof(create_req), 1); 2311 if (retval) { 2312 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n"); 2313 goto out_unlock; 2314 } 2315 wait_for_completion_timeout(&mrioc->init_cmds.done, 2316 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2317 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2318 ioc_err(mrioc, "create request queue timed out\n"); 2319 mpi3mr_check_rh_fault_ioc(mrioc, 2320 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 2321 retval = -1; 2322 goto out_unlock; 2323 } 2324 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2325 != MPI3_IOCSTATUS_SUCCESS) { 2326 ioc_err(mrioc, 2327 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2328 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2329 mrioc->init_cmds.ioc_loginfo); 2330 retval = -1; 2331 goto out_unlock; 2332 } 2333 op_req_q->qid = req_qid; 2334 2335 out_unlock: 2336 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2337 mutex_unlock(&mrioc->init_cmds.mutex); 2338 out: 2339 2340 return retval; 2341 } 2342 2343 /** 2344 * mpi3mr_create_op_queues - create operational queue pairs 2345 * @mrioc: Adapter instance reference 2346 * 2347 * Allocate memory for operational queue meta data and call 2348 * create request and reply queue functions. 2349 * 2350 * Return: 0 on success, non-zero on failures. 2351 */ 2352 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) 2353 { 2354 int retval = 0; 2355 u16 num_queues = 0, i = 0, msix_count_op_q = 1; 2356 u32 ioc_status; 2357 enum mpi3mr_iocstate ioc_state; 2358 2359 num_queues = min_t(int, mrioc->facts.max_op_reply_q, 2360 mrioc->facts.max_op_req_q); 2361 2362 msix_count_op_q = 2363 mrioc->intr_info_count - mrioc->op_reply_q_offset; 2364 if (!mrioc->num_queues) 2365 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q); 2366 /* 2367 * During reset set the num_queues to the number of queues 2368 * that was set before the reset. 2369 */ 2370 num_queues = mrioc->num_op_reply_q ? 2371 mrioc->num_op_reply_q : mrioc->num_queues; 2372 ioc_info(mrioc, "trying to create %d operational queue pairs\n", 2373 num_queues); 2374 2375 if (!mrioc->req_qinfo) { 2376 mrioc->req_qinfo = kcalloc(num_queues, 2377 sizeof(struct op_req_qinfo), GFP_KERNEL); 2378 if (!mrioc->req_qinfo) { 2379 retval = -1; 2380 goto out_failed; 2381 } 2382 2383 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) * 2384 num_queues, GFP_KERNEL); 2385 if (!mrioc->op_reply_qinfo) { 2386 retval = -1; 2387 goto out_failed; 2388 } 2389 } 2390 2391 if (mrioc->enable_segqueue) 2392 ioc_info(mrioc, 2393 "allocating operational queues through segmented queues\n"); 2394 2395 for (i = 0; i < num_queues; i++) { 2396 if (mpi3mr_create_op_reply_q(mrioc, i)) { 2397 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i); 2398 break; 2399 } 2400 if (mpi3mr_create_op_req_q(mrioc, i, 2401 mrioc->op_reply_qinfo[i].qid)) { 2402 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i); 2403 mpi3mr_delete_op_reply_q(mrioc, i); 2404 break; 2405 } 2406 } 2407 2408 if (i == 0) { 2409 /* Not even one queue is created successfully*/ 2410 retval = -1; 2411 goto out_failed; 2412 } 2413 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2414 ioc_state = mpi3mr_get_iocstate(mrioc); 2415 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 2416 ioc_state != MRIOC_STATE_READY) { 2417 mpi3mr_print_fault_info(mrioc); 2418 retval = -1; 2419 goto out_failed; 2420 } 2421 mrioc->num_op_reply_q = mrioc->num_op_req_q = i; 2422 ioc_info(mrioc, 2423 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n", 2424 mrioc->num_op_reply_q, mrioc->default_qcount, 2425 mrioc->active_poll_qcount); 2426 2427 return retval; 2428 out_failed: 2429 kfree(mrioc->req_qinfo); 2430 mrioc->req_qinfo = NULL; 2431 2432 kfree(mrioc->op_reply_qinfo); 2433 mrioc->op_reply_qinfo = NULL; 2434 2435 return retval; 2436 } 2437 2438 /** 2439 * mpi3mr_op_request_post - Post request to operational queue 2440 * @mrioc: Adapter reference 2441 * @op_req_q: Operational request queue info 2442 * @req: MPI3 request 2443 * 2444 * Post the MPI3 request into operational request queue and 2445 * inform the controller, if the queue is full return 2446 * appropriate error. 2447 * 2448 * Return: 0 on success, non-zero on failure. 2449 */ 2450 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 2451 struct op_req_qinfo *op_req_q, u8 *req) 2452 { 2453 u16 pi = 0, max_entries, reply_qidx = 0, midx; 2454 int retval = 0; 2455 unsigned long flags; 2456 u8 *req_entry; 2457 void *segment_base_addr; 2458 u16 req_sz = mrioc->facts.op_req_sz; 2459 struct segments *segments = op_req_q->q_segments; 2460 struct op_reply_qinfo *op_reply_q = NULL; 2461 2462 reply_qidx = op_req_q->reply_qid - 1; 2463 op_reply_q = mrioc->op_reply_qinfo + reply_qidx; 2464 2465 if (mrioc->unrecoverable) 2466 return -EFAULT; 2467 2468 spin_lock_irqsave(&op_req_q->q_lock, flags); 2469 pi = op_req_q->pi; 2470 max_entries = op_req_q->num_requests; 2471 2472 if (mpi3mr_check_req_qfull(op_req_q)) { 2473 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX( 2474 reply_qidx, mrioc->op_reply_q_offset); 2475 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q); 2476 2477 if (mpi3mr_check_req_qfull(op_req_q)) { 2478 retval = -EAGAIN; 2479 goto out; 2480 } 2481 } 2482 2483 if (mrioc->reset_in_progress) { 2484 ioc_err(mrioc, "OpReqQ submit reset in progress\n"); 2485 retval = -EAGAIN; 2486 goto out; 2487 } 2488 if (mrioc->pci_err_recovery) { 2489 ioc_err(mrioc, "operational request queue submission failed due to pci error recovery in progress\n"); 2490 retval = -EAGAIN; 2491 goto out; 2492 } 2493 2494 /* Reply queue is nearing to get full, push back IOs to SML */ 2495 if ((mrioc->prevent_reply_qfull == true) && 2496 (atomic_read(&op_reply_q->pend_ios) > 2497 (op_reply_q->qfull_watermark))) { 2498 atomic_inc(&mrioc->reply_qfull_count); 2499 retval = -EAGAIN; 2500 goto out; 2501 } 2502 2503 segment_base_addr = segments[pi / op_req_q->segment_qd].segment; 2504 req_entry = (u8 *)segment_base_addr + 2505 ((pi % op_req_q->segment_qd) * req_sz); 2506 2507 memset(req_entry, 0, req_sz); 2508 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ); 2509 2510 if (++pi == max_entries) 2511 pi = 0; 2512 op_req_q->pi = pi; 2513 2514 #ifndef CONFIG_PREEMPT_RT 2515 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) 2516 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) 2517 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; 2518 #else 2519 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios); 2520 #endif 2521 2522 writel(op_req_q->pi, 2523 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index); 2524 2525 out: 2526 spin_unlock_irqrestore(&op_req_q->q_lock, flags); 2527 return retval; 2528 } 2529 2530 /** 2531 * mpi3mr_check_rh_fault_ioc - check reset history and fault 2532 * controller 2533 * @mrioc: Adapter instance reference 2534 * @reason_code: reason code for the fault. 2535 * 2536 * This routine will save snapdump and fault the controller with 2537 * the given reason code if it is not already in the fault or 2538 * not asynchronosuly reset. This will be used to handle 2539 * initilaization time faults/resets/timeout as in those cases 2540 * immediate soft reset invocation is not required. 2541 * 2542 * Return: None. 2543 */ 2544 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code) 2545 { 2546 u32 ioc_status, host_diagnostic, timeout; 2547 union mpi3mr_trigger_data trigger_data; 2548 2549 if (mrioc->unrecoverable) { 2550 ioc_err(mrioc, "controller is unrecoverable\n"); 2551 return; 2552 } 2553 2554 if (!pci_device_is_present(mrioc->pdev)) { 2555 mrioc->unrecoverable = 1; 2556 ioc_err(mrioc, "controller is not present\n"); 2557 return; 2558 } 2559 memset(&trigger_data, 0, sizeof(trigger_data)); 2560 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2561 2562 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2563 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2564 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0); 2565 return; 2566 } else if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 2567 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) & 2568 MPI3_SYSIF_FAULT_CODE_MASK); 2569 2570 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2571 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0); 2572 mpi3mr_print_fault_info(mrioc); 2573 return; 2574 } 2575 2576 mpi3mr_set_diagsave(mrioc); 2577 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2578 reason_code); 2579 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) & 2580 MPI3_SYSIF_FAULT_CODE_MASK); 2581 mpi3mr_set_trigger_data_in_all_hdb(mrioc, MPI3MR_HDB_TRIGGER_TYPE_FAULT, 2582 &trigger_data, 0); 2583 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 2584 do { 2585 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2586 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 2587 break; 2588 msleep(100); 2589 } while (--timeout); 2590 } 2591 2592 /** 2593 * mpi3mr_sync_timestamp - Issue time stamp sync request 2594 * @mrioc: Adapter reference 2595 * 2596 * Issue IO unit control MPI request to synchornize firmware 2597 * timestamp with host time. 2598 * 2599 * Return: 0 on success, non-zero on failure. 2600 */ 2601 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc) 2602 { 2603 ktime_t current_time; 2604 struct mpi3_iounit_control_request iou_ctrl; 2605 int retval = 0; 2606 2607 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 2608 mutex_lock(&mrioc->init_cmds.mutex); 2609 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2610 retval = -1; 2611 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n"); 2612 mutex_unlock(&mrioc->init_cmds.mutex); 2613 goto out; 2614 } 2615 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2616 mrioc->init_cmds.is_waiting = 1; 2617 mrioc->init_cmds.callback = NULL; 2618 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2619 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL; 2620 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP; 2621 current_time = ktime_get_real(); 2622 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time)); 2623 2624 init_completion(&mrioc->init_cmds.done); 2625 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl, 2626 sizeof(iou_ctrl), 0); 2627 if (retval) { 2628 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n"); 2629 goto out_unlock; 2630 } 2631 2632 wait_for_completion_timeout(&mrioc->init_cmds.done, 2633 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2634 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2635 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n"); 2636 mrioc->init_cmds.is_waiting = 0; 2637 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 2638 mpi3mr_check_rh_fault_ioc(mrioc, 2639 MPI3MR_RESET_FROM_TSU_TIMEOUT); 2640 retval = -1; 2641 goto out_unlock; 2642 } 2643 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2644 != MPI3_IOCSTATUS_SUCCESS) { 2645 ioc_err(mrioc, 2646 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2647 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2648 mrioc->init_cmds.ioc_loginfo); 2649 retval = -1; 2650 goto out_unlock; 2651 } 2652 2653 out_unlock: 2654 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2655 mutex_unlock(&mrioc->init_cmds.mutex); 2656 2657 out: 2658 return retval; 2659 } 2660 2661 /** 2662 * mpi3mr_print_pkg_ver - display controller fw package version 2663 * @mrioc: Adapter reference 2664 * 2665 * Retrieve firmware package version from the component image 2666 * header of the controller flash and display it. 2667 * 2668 * Return: 0 on success and non-zero on failure. 2669 */ 2670 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc) 2671 { 2672 struct mpi3_ci_upload_request ci_upload; 2673 int retval = -1; 2674 void *data = NULL; 2675 dma_addr_t data_dma; 2676 struct mpi3_ci_manifest_mpi *manifest; 2677 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi); 2678 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2679 2680 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2681 GFP_KERNEL); 2682 if (!data) 2683 return -ENOMEM; 2684 2685 memset(&ci_upload, 0, sizeof(ci_upload)); 2686 mutex_lock(&mrioc->init_cmds.mutex); 2687 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2688 ioc_err(mrioc, "sending get package version failed due to command in use\n"); 2689 mutex_unlock(&mrioc->init_cmds.mutex); 2690 goto out; 2691 } 2692 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2693 mrioc->init_cmds.is_waiting = 1; 2694 mrioc->init_cmds.callback = NULL; 2695 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2696 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD; 2697 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 2698 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST); 2699 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE); 2700 ci_upload.segment_size = cpu_to_le32(data_len); 2701 2702 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len, 2703 data_dma); 2704 init_completion(&mrioc->init_cmds.done); 2705 retval = mpi3mr_admin_request_post(mrioc, &ci_upload, 2706 sizeof(ci_upload), 1); 2707 if (retval) { 2708 ioc_err(mrioc, "posting get package version failed\n"); 2709 goto out_unlock; 2710 } 2711 wait_for_completion_timeout(&mrioc->init_cmds.done, 2712 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2713 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2714 ioc_err(mrioc, "get package version timed out\n"); 2715 mpi3mr_check_rh_fault_ioc(mrioc, 2716 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2717 retval = -1; 2718 goto out_unlock; 2719 } 2720 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2721 == MPI3_IOCSTATUS_SUCCESS) { 2722 manifest = (struct mpi3_ci_manifest_mpi *) data; 2723 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) { 2724 ioc_info(mrioc, 2725 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n", 2726 manifest->package_version.gen_major, 2727 manifest->package_version.gen_minor, 2728 manifest->package_version.phase_major, 2729 manifest->package_version.phase_minor, 2730 manifest->package_version.customer_id, 2731 manifest->package_version.build_num); 2732 } 2733 } 2734 retval = 0; 2735 out_unlock: 2736 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2737 mutex_unlock(&mrioc->init_cmds.mutex); 2738 2739 out: 2740 if (data) 2741 dma_free_coherent(&mrioc->pdev->dev, data_len, data, 2742 data_dma); 2743 return retval; 2744 } 2745 2746 /** 2747 * mpi3mr_watchdog_work - watchdog thread to monitor faults 2748 * @work: work struct 2749 * 2750 * Watch dog work periodically executed (1 second interval) to 2751 * monitor firmware fault and to issue periodic timer sync to 2752 * the firmware. 2753 * 2754 * Return: Nothing. 2755 */ 2756 static void mpi3mr_watchdog_work(struct work_struct *work) 2757 { 2758 struct mpi3mr_ioc *mrioc = 2759 container_of(work, struct mpi3mr_ioc, watchdog_work.work); 2760 unsigned long flags; 2761 enum mpi3mr_iocstate ioc_state; 2762 u32 host_diagnostic, ioc_status; 2763 union mpi3mr_trigger_data trigger_data; 2764 u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH; 2765 2766 if (mrioc->reset_in_progress || mrioc->pci_err_recovery) 2767 return; 2768 2769 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) { 2770 ioc_err(mrioc, "watchdog could not detect the controller\n"); 2771 mrioc->unrecoverable = 1; 2772 } 2773 2774 if (mrioc->unrecoverable) { 2775 ioc_err(mrioc, 2776 "flush pending commands for unrecoverable controller\n"); 2777 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 2778 return; 2779 } 2780 2781 if (atomic_read(&mrioc->admin_pend_isr)) { 2782 ioc_err(mrioc, "Unprocessed admin ISR instance found\n" 2783 "flush admin replies\n"); 2784 mpi3mr_process_admin_reply_q(mrioc); 2785 } 2786 2787 if (!(mrioc->facts.ioc_capabilities & 2788 MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC) && 2789 (mrioc->ts_update_counter++ >= mrioc->ts_update_interval)) { 2790 2791 mrioc->ts_update_counter = 0; 2792 mpi3mr_sync_timestamp(mrioc); 2793 } 2794 2795 if ((mrioc->prepare_for_reset) && 2796 ((mrioc->prepare_for_reset_timeout_counter++) >= 2797 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 2798 mpi3mr_soft_reset_handler(mrioc, 2799 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 2800 return; 2801 } 2802 2803 memset(&trigger_data, 0, sizeof(trigger_data)); 2804 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2805 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2806 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2807 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0); 2808 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0); 2809 return; 2810 } 2811 2812 /*Check for fault state every one second and issue Soft reset*/ 2813 ioc_state = mpi3mr_get_iocstate(mrioc); 2814 if (ioc_state != MRIOC_STATE_FAULT) 2815 goto schedule_work; 2816 2817 trigger_data.fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 2818 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 2819 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0); 2820 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2821 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 2822 if (!mrioc->diagsave_timeout) { 2823 mpi3mr_print_fault_info(mrioc); 2824 ioc_warn(mrioc, "diag save in progress\n"); 2825 } 2826 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 2827 goto schedule_work; 2828 } 2829 2830 mpi3mr_print_fault_info(mrioc); 2831 mrioc->diagsave_timeout = 0; 2832 2833 if (!mpi3mr_is_fault_recoverable(mrioc)) { 2834 mrioc->unrecoverable = 1; 2835 goto schedule_work; 2836 } 2837 2838 switch (trigger_data.fault) { 2839 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED: 2840 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED: 2841 ioc_warn(mrioc, 2842 "controller requires system power cycle, marking controller as unrecoverable\n"); 2843 mrioc->unrecoverable = 1; 2844 goto schedule_work; 2845 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS: 2846 goto schedule_work; 2847 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET: 2848 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT; 2849 break; 2850 default: 2851 break; 2852 } 2853 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0); 2854 return; 2855 2856 schedule_work: 2857 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2858 if (mrioc->watchdog_work_q) 2859 queue_delayed_work(mrioc->watchdog_work_q, 2860 &mrioc->watchdog_work, 2861 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2862 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2863 return; 2864 } 2865 2866 /** 2867 * mpi3mr_start_watchdog - Start watchdog 2868 * @mrioc: Adapter instance reference 2869 * 2870 * Create and start the watchdog thread to monitor controller 2871 * faults. 2872 * 2873 * Return: Nothing. 2874 */ 2875 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc) 2876 { 2877 if (mrioc->watchdog_work_q) 2878 return; 2879 2880 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work); 2881 snprintf(mrioc->watchdog_work_q_name, 2882 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name, 2883 mrioc->id); 2884 mrioc->watchdog_work_q = alloc_ordered_workqueue( 2885 "%s", WQ_MEM_RECLAIM, mrioc->watchdog_work_q_name); 2886 if (!mrioc->watchdog_work_q) { 2887 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__); 2888 return; 2889 } 2890 2891 if (mrioc->watchdog_work_q) 2892 queue_delayed_work(mrioc->watchdog_work_q, 2893 &mrioc->watchdog_work, 2894 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2895 } 2896 2897 /** 2898 * mpi3mr_stop_watchdog - Stop watchdog 2899 * @mrioc: Adapter instance reference 2900 * 2901 * Stop the watchdog thread created to monitor controller 2902 * faults. 2903 * 2904 * Return: Nothing. 2905 */ 2906 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) 2907 { 2908 unsigned long flags; 2909 struct workqueue_struct *wq; 2910 2911 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2912 wq = mrioc->watchdog_work_q; 2913 mrioc->watchdog_work_q = NULL; 2914 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2915 if (wq) { 2916 if (!cancel_delayed_work_sync(&mrioc->watchdog_work)) 2917 flush_workqueue(wq); 2918 destroy_workqueue(wq); 2919 } 2920 } 2921 2922 /** 2923 * mpi3mr_setup_admin_qpair - Setup admin queue pair 2924 * @mrioc: Adapter instance reference 2925 * 2926 * Allocate memory for admin queue pair if required and register 2927 * the admin queue with the controller. 2928 * 2929 * Return: 0 on success, non-zero on failures. 2930 */ 2931 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc) 2932 { 2933 int retval = 0; 2934 u32 num_admin_entries = 0; 2935 2936 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE; 2937 mrioc->num_admin_req = mrioc->admin_req_q_sz / 2938 MPI3MR_ADMIN_REQ_FRAME_SZ; 2939 mrioc->admin_req_ci = mrioc->admin_req_pi = 0; 2940 2941 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE; 2942 mrioc->num_admin_replies = mrioc->admin_reply_q_sz / 2943 MPI3MR_ADMIN_REPLY_FRAME_SZ; 2944 mrioc->admin_reply_ci = 0; 2945 mrioc->admin_reply_ephase = 1; 2946 atomic_set(&mrioc->admin_reply_q_in_use, 0); 2947 atomic_set(&mrioc->admin_pend_isr, 0); 2948 2949 if (!mrioc->admin_req_base) { 2950 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev, 2951 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL); 2952 2953 if (!mrioc->admin_req_base) { 2954 retval = -1; 2955 goto out_failed; 2956 } 2957 2958 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev, 2959 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma, 2960 GFP_KERNEL); 2961 2962 if (!mrioc->admin_reply_base) { 2963 retval = -1; 2964 goto out_failed; 2965 } 2966 } 2967 2968 num_admin_entries = (mrioc->num_admin_replies << 16) | 2969 (mrioc->num_admin_req); 2970 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); 2971 mpi3mr_writeq(mrioc->admin_req_dma, 2972 &mrioc->sysif_regs->admin_request_queue_address, 2973 &mrioc->adm_req_q_bar_writeq_lock); 2974 mpi3mr_writeq(mrioc->admin_reply_dma, 2975 &mrioc->sysif_regs->admin_reply_queue_address, 2976 &mrioc->adm_reply_q_bar_writeq_lock); 2977 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 2978 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 2979 return retval; 2980 2981 out_failed: 2982 2983 if (mrioc->admin_reply_base) { 2984 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 2985 mrioc->admin_reply_base, mrioc->admin_reply_dma); 2986 mrioc->admin_reply_base = NULL; 2987 } 2988 if (mrioc->admin_req_base) { 2989 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 2990 mrioc->admin_req_base, mrioc->admin_req_dma); 2991 mrioc->admin_req_base = NULL; 2992 } 2993 return retval; 2994 } 2995 2996 /** 2997 * mpi3mr_issue_iocfacts - Send IOC Facts 2998 * @mrioc: Adapter instance reference 2999 * @facts_data: Cached IOC facts data 3000 * 3001 * Issue IOC Facts MPI request through admin queue and wait for 3002 * the completion of it or time out. 3003 * 3004 * Return: 0 on success, non-zero on failures. 3005 */ 3006 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, 3007 struct mpi3_ioc_facts_data *facts_data) 3008 { 3009 struct mpi3_ioc_facts_request iocfacts_req; 3010 void *data = NULL; 3011 dma_addr_t data_dma; 3012 u32 data_len = sizeof(*facts_data); 3013 int retval = 0; 3014 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 3015 3016 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 3017 GFP_KERNEL); 3018 3019 if (!data) { 3020 retval = -1; 3021 goto out; 3022 } 3023 3024 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 3025 mutex_lock(&mrioc->init_cmds.mutex); 3026 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3027 retval = -1; 3028 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n"); 3029 mutex_unlock(&mrioc->init_cmds.mutex); 3030 goto out; 3031 } 3032 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3033 mrioc->init_cmds.is_waiting = 1; 3034 mrioc->init_cmds.callback = NULL; 3035 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3036 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS; 3037 3038 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len, 3039 data_dma); 3040 3041 init_completion(&mrioc->init_cmds.done); 3042 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req, 3043 sizeof(iocfacts_req), 1); 3044 if (retval) { 3045 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n"); 3046 goto out_unlock; 3047 } 3048 wait_for_completion_timeout(&mrioc->init_cmds.done, 3049 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3050 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3051 ioc_err(mrioc, "ioc_facts timed out\n"); 3052 mpi3mr_check_rh_fault_ioc(mrioc, 3053 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 3054 retval = -1; 3055 goto out_unlock; 3056 } 3057 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3058 != MPI3_IOCSTATUS_SUCCESS) { 3059 ioc_err(mrioc, 3060 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3061 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3062 mrioc->init_cmds.ioc_loginfo); 3063 retval = -1; 3064 goto out_unlock; 3065 } 3066 memcpy(facts_data, (u8 *)data, data_len); 3067 mpi3mr_process_factsdata(mrioc, facts_data); 3068 out_unlock: 3069 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3070 mutex_unlock(&mrioc->init_cmds.mutex); 3071 3072 out: 3073 if (data) 3074 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma); 3075 3076 return retval; 3077 } 3078 3079 /** 3080 * mpi3mr_check_reset_dma_mask - Process IOC facts data 3081 * @mrioc: Adapter instance reference 3082 * 3083 * Check whether the new DMA mask requested through IOCFacts by 3084 * firmware needs to be set, if so set it . 3085 * 3086 * Return: 0 on success, non-zero on failure. 3087 */ 3088 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc) 3089 { 3090 struct pci_dev *pdev = mrioc->pdev; 3091 int r; 3092 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask); 3093 3094 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask)) 3095 return 0; 3096 3097 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n", 3098 mrioc->dma_mask, facts_dma_mask); 3099 3100 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask); 3101 if (r) { 3102 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n", 3103 facts_dma_mask, r); 3104 return r; 3105 } 3106 mrioc->dma_mask = facts_dma_mask; 3107 return r; 3108 } 3109 3110 /** 3111 * mpi3mr_process_factsdata - Process IOC facts data 3112 * @mrioc: Adapter instance reference 3113 * @facts_data: Cached IOC facts data 3114 * 3115 * Convert IOC facts data into cpu endianness and cache it in 3116 * the driver . 3117 * 3118 * Return: Nothing. 3119 */ 3120 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 3121 struct mpi3_ioc_facts_data *facts_data) 3122 { 3123 u32 ioc_config, req_sz, facts_flags; 3124 3125 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) != 3126 (sizeof(*facts_data) / 4)) { 3127 ioc_warn(mrioc, 3128 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n", 3129 sizeof(*facts_data), 3130 le16_to_cpu(facts_data->ioc_facts_data_length) * 4); 3131 } 3132 3133 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 3134 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 3135 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 3136 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) { 3137 ioc_err(mrioc, 3138 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n", 3139 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size)); 3140 } 3141 3142 memset(&mrioc->facts, 0, sizeof(mrioc->facts)); 3143 3144 facts_flags = le32_to_cpu(facts_data->flags); 3145 mrioc->facts.op_req_sz = req_sz; 3146 mrioc->op_reply_desc_sz = 1 << ((ioc_config & 3147 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 3148 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 3149 3150 mrioc->facts.ioc_num = facts_data->ioc_number; 3151 mrioc->facts.who_init = facts_data->who_init; 3152 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors); 3153 mrioc->facts.personality = (facts_flags & 3154 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 3155 mrioc->facts.dma_mask = (facts_flags & 3156 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 3157 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 3158 mrioc->facts.dma_mask = (facts_flags & 3159 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 3160 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 3161 mrioc->facts.protocol_flags = facts_data->protocol_flags; 3162 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word); 3163 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests); 3164 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id); 3165 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; 3166 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); 3167 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); 3168 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); 3169 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); 3170 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds); 3171 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds); 3172 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); 3173 mrioc->facts.max_pcie_switches = 3174 le16_to_cpu(facts_data->max_pcie_switches); 3175 mrioc->facts.max_sasexpanders = 3176 le16_to_cpu(facts_data->max_sas_expanders); 3177 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length); 3178 mrioc->facts.max_sasinitiators = 3179 le16_to_cpu(facts_data->max_sas_initiators); 3180 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures); 3181 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle); 3182 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle); 3183 mrioc->facts.max_op_req_q = 3184 le16_to_cpu(facts_data->max_operational_request_queues); 3185 mrioc->facts.max_op_reply_q = 3186 le16_to_cpu(facts_data->max_operational_reply_queues); 3187 mrioc->facts.ioc_capabilities = 3188 le32_to_cpu(facts_data->ioc_capabilities); 3189 mrioc->facts.fw_ver.build_num = 3190 le16_to_cpu(facts_data->fw_version.build_num); 3191 mrioc->facts.fw_ver.cust_id = 3192 le16_to_cpu(facts_data->fw_version.customer_id); 3193 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor; 3194 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major; 3195 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor; 3196 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major; 3197 mrioc->msix_count = min_t(int, mrioc->msix_count, 3198 mrioc->facts.max_msix_vectors); 3199 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask; 3200 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value; 3201 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift; 3202 mrioc->facts.shutdown_timeout = 3203 le16_to_cpu(facts_data->shutdown_timeout); 3204 mrioc->facts.diag_trace_sz = 3205 le32_to_cpu(facts_data->diag_trace_size); 3206 mrioc->facts.diag_fw_sz = 3207 le32_to_cpu(facts_data->diag_fw_size); 3208 mrioc->facts.diag_drvr_sz = le32_to_cpu(facts_data->diag_driver_size); 3209 mrioc->facts.max_dev_per_tg = 3210 facts_data->max_devices_per_throttle_group; 3211 mrioc->facts.io_throttle_data_length = 3212 le16_to_cpu(facts_data->io_throttle_data_length); 3213 mrioc->facts.max_io_throttle_group = 3214 le16_to_cpu(facts_data->max_io_throttle_group); 3215 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low); 3216 mrioc->facts.io_throttle_high = 3217 le16_to_cpu(facts_data->io_throttle_high); 3218 3219 if (mrioc->facts.max_data_length == 3220 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED) 3221 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE; 3222 else 3223 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K; 3224 /* Store in 512b block count */ 3225 if (mrioc->facts.io_throttle_data_length) 3226 mrioc->io_throttle_data_length = 3227 (mrioc->facts.io_throttle_data_length * 2 * 4); 3228 else 3229 /* set the length to 1MB + 1K to disable throttle */ 3230 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2; 3231 3232 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024); 3233 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024); 3234 3235 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),", 3236 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, 3237 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); 3238 ioc_info(mrioc, 3239 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n", 3240 mrioc->facts.max_reqs, mrioc->facts.min_devhandle, 3241 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids); 3242 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", 3243 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, 3244 mrioc->facts.sge_mod_shift); 3245 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n", 3246 mrioc->facts.dma_mask, (facts_flags & 3247 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length); 3248 ioc_info(mrioc, 3249 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n", 3250 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group); 3251 ioc_info(mrioc, 3252 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n", 3253 mrioc->facts.io_throttle_data_length * 4, 3254 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low); 3255 } 3256 3257 /** 3258 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init 3259 * @mrioc: Adapter instance reference 3260 * 3261 * Allocate and initialize the reply free buffers, sense 3262 * buffers, reply free queue and sense buffer queue. 3263 * 3264 * Return: 0 on success, non-zero on failures. 3265 */ 3266 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) 3267 { 3268 int retval = 0; 3269 u32 sz, i; 3270 3271 if (mrioc->init_cmds.reply) 3272 return retval; 3273 3274 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3275 if (!mrioc->init_cmds.reply) 3276 goto out_failed; 3277 3278 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3279 if (!mrioc->bsg_cmds.reply) 3280 goto out_failed; 3281 3282 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3283 if (!mrioc->transport_cmds.reply) 3284 goto out_failed; 3285 3286 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 3287 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz, 3288 GFP_KERNEL); 3289 if (!mrioc->dev_rmhs_cmds[i].reply) 3290 goto out_failed; 3291 } 3292 3293 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 3294 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz, 3295 GFP_KERNEL); 3296 if (!mrioc->evtack_cmds[i].reply) 3297 goto out_failed; 3298 } 3299 3300 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3301 if (!mrioc->host_tm_cmds.reply) 3302 goto out_failed; 3303 3304 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3305 if (!mrioc->pel_cmds.reply) 3306 goto out_failed; 3307 3308 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3309 if (!mrioc->pel_abort_cmd.reply) 3310 goto out_failed; 3311 3312 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 3313 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits, 3314 GFP_KERNEL); 3315 if (!mrioc->removepend_bitmap) 3316 goto out_failed; 3317 3318 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL); 3319 if (!mrioc->devrem_bitmap) 3320 goto out_failed; 3321 3322 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD, 3323 GFP_KERNEL); 3324 if (!mrioc->evtack_cmds_bitmap) 3325 goto out_failed; 3326 3327 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES; 3328 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1; 3329 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 3330 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1; 3331 3332 /* reply buffer pool, 16 byte align */ 3333 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3334 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool", 3335 &mrioc->pdev->dev, sz, 16, 0); 3336 if (!mrioc->reply_buf_pool) { 3337 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n"); 3338 goto out_failed; 3339 } 3340 3341 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL, 3342 &mrioc->reply_buf_dma); 3343 if (!mrioc->reply_buf) 3344 goto out_failed; 3345 3346 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz; 3347 3348 /* reply free queue, 8 byte align */ 3349 sz = mrioc->reply_free_qsz * 8; 3350 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool", 3351 &mrioc->pdev->dev, sz, 8, 0); 3352 if (!mrioc->reply_free_q_pool) { 3353 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n"); 3354 goto out_failed; 3355 } 3356 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool, 3357 GFP_KERNEL, &mrioc->reply_free_q_dma); 3358 if (!mrioc->reply_free_q) 3359 goto out_failed; 3360 3361 /* sense buffer pool, 4 byte align */ 3362 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3363 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", 3364 &mrioc->pdev->dev, sz, 4, 0); 3365 if (!mrioc->sense_buf_pool) { 3366 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n"); 3367 goto out_failed; 3368 } 3369 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL, 3370 &mrioc->sense_buf_dma); 3371 if (!mrioc->sense_buf) 3372 goto out_failed; 3373 3374 /* sense buffer queue, 8 byte align */ 3375 sz = mrioc->sense_buf_q_sz * 8; 3376 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool", 3377 &mrioc->pdev->dev, sz, 8, 0); 3378 if (!mrioc->sense_buf_q_pool) { 3379 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n"); 3380 goto out_failed; 3381 } 3382 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool, 3383 GFP_KERNEL, &mrioc->sense_buf_q_dma); 3384 if (!mrioc->sense_buf_q) 3385 goto out_failed; 3386 3387 return retval; 3388 3389 out_failed: 3390 retval = -1; 3391 return retval; 3392 } 3393 3394 /** 3395 * mpimr_initialize_reply_sbuf_queues - initialize reply sense 3396 * buffers 3397 * @mrioc: Adapter instance reference 3398 * 3399 * Helper function to initialize reply and sense buffers along 3400 * with some debug prints. 3401 * 3402 * Return: None. 3403 */ 3404 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc) 3405 { 3406 u32 sz, i; 3407 dma_addr_t phy_addr; 3408 3409 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3410 ioc_info(mrioc, 3411 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3412 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz, 3413 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma); 3414 sz = mrioc->reply_free_qsz * 8; 3415 ioc_info(mrioc, 3416 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3417 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), 3418 (unsigned long long)mrioc->reply_free_q_dma); 3419 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3420 ioc_info(mrioc, 3421 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3422 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ, 3423 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma); 3424 sz = mrioc->sense_buf_q_sz * 8; 3425 ioc_info(mrioc, 3426 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3427 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024), 3428 (unsigned long long)mrioc->sense_buf_q_dma); 3429 3430 /* initialize Reply buffer Queue */ 3431 for (i = 0, phy_addr = mrioc->reply_buf_dma; 3432 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz) 3433 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr); 3434 mrioc->reply_free_q[i] = cpu_to_le64(0); 3435 3436 /* initialize Sense Buffer Queue */ 3437 for (i = 0, phy_addr = mrioc->sense_buf_dma; 3438 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ) 3439 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); 3440 mrioc->sense_buf_q[i] = cpu_to_le64(0); 3441 } 3442 3443 /** 3444 * mpi3mr_issue_iocinit - Send IOC Init 3445 * @mrioc: Adapter instance reference 3446 * 3447 * Issue IOC Init MPI request through admin queue and wait for 3448 * the completion of it or time out. 3449 * 3450 * Return: 0 on success, non-zero on failures. 3451 */ 3452 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) 3453 { 3454 struct mpi3_ioc_init_request iocinit_req; 3455 struct mpi3_driver_info_layout *drv_info; 3456 dma_addr_t data_dma; 3457 u32 data_len = sizeof(*drv_info); 3458 int retval = 0; 3459 ktime_t current_time; 3460 3461 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 3462 GFP_KERNEL); 3463 if (!drv_info) { 3464 retval = -1; 3465 goto out; 3466 } 3467 mpimr_initialize_reply_sbuf_queues(mrioc); 3468 3469 drv_info->information_length = cpu_to_le32(data_len); 3470 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature)); 3471 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name)); 3472 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version)); 3473 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name)); 3474 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version)); 3475 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE, 3476 sizeof(drv_info->driver_release_date)); 3477 drv_info->driver_capabilities = 0; 3478 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info, 3479 sizeof(mrioc->driver_info)); 3480 3481 memset(&iocinit_req, 0, sizeof(iocinit_req)); 3482 mutex_lock(&mrioc->init_cmds.mutex); 3483 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3484 retval = -1; 3485 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n"); 3486 mutex_unlock(&mrioc->init_cmds.mutex); 3487 goto out; 3488 } 3489 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3490 mrioc->init_cmds.is_waiting = 1; 3491 mrioc->init_cmds.callback = NULL; 3492 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3493 iocinit_req.function = MPI3_FUNCTION_IOC_INIT; 3494 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV; 3495 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT; 3496 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR; 3497 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR; 3498 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER; 3499 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); 3500 iocinit_req.reply_free_queue_address = 3501 cpu_to_le64(mrioc->reply_free_q_dma); 3502 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ); 3503 iocinit_req.sense_buffer_free_queue_depth = 3504 cpu_to_le16(mrioc->sense_buf_q_sz); 3505 iocinit_req.sense_buffer_free_queue_address = 3506 cpu_to_le64(mrioc->sense_buf_q_dma); 3507 iocinit_req.driver_information_address = cpu_to_le64(data_dma); 3508 3509 current_time = ktime_get_real(); 3510 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time)); 3511 3512 iocinit_req.msg_flags |= 3513 MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED; 3514 iocinit_req.msg_flags |= 3515 MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED; 3516 3517 init_completion(&mrioc->init_cmds.done); 3518 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, 3519 sizeof(iocinit_req), 1); 3520 if (retval) { 3521 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n"); 3522 goto out_unlock; 3523 } 3524 wait_for_completion_timeout(&mrioc->init_cmds.done, 3525 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3526 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3527 mpi3mr_check_rh_fault_ioc(mrioc, 3528 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 3529 ioc_err(mrioc, "ioc_init timed out\n"); 3530 retval = -1; 3531 goto out_unlock; 3532 } 3533 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3534 != MPI3_IOCSTATUS_SUCCESS) { 3535 ioc_err(mrioc, 3536 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3537 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3538 mrioc->init_cmds.ioc_loginfo); 3539 retval = -1; 3540 goto out_unlock; 3541 } 3542 3543 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs; 3544 writel(mrioc->reply_free_queue_host_index, 3545 &mrioc->sysif_regs->reply_free_host_index); 3546 3547 mrioc->sbq_host_index = mrioc->num_sense_bufs; 3548 writel(mrioc->sbq_host_index, 3549 &mrioc->sysif_regs->sense_buffer_free_host_index); 3550 out_unlock: 3551 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3552 mutex_unlock(&mrioc->init_cmds.mutex); 3553 3554 out: 3555 if (drv_info) 3556 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info, 3557 data_dma); 3558 3559 return retval; 3560 } 3561 3562 /** 3563 * mpi3mr_unmask_events - Unmask events in event mask bitmap 3564 * @mrioc: Adapter instance reference 3565 * @event: MPI event ID 3566 * 3567 * Un mask the specific event by resetting the event_mask 3568 * bitmap. 3569 * 3570 * Return: 0 on success, non-zero on failures. 3571 */ 3572 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event) 3573 { 3574 u32 desired_event; 3575 u8 word; 3576 3577 if (event >= 128) 3578 return; 3579 3580 desired_event = (1 << (event % 32)); 3581 word = event / 32; 3582 3583 mrioc->event_masks[word] &= ~desired_event; 3584 } 3585 3586 /** 3587 * mpi3mr_issue_event_notification - Send event notification 3588 * @mrioc: Adapter instance reference 3589 * 3590 * Issue event notification MPI request through admin queue and 3591 * wait for the completion of it or time out. 3592 * 3593 * Return: 0 on success, non-zero on failures. 3594 */ 3595 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) 3596 { 3597 struct mpi3_event_notification_request evtnotify_req; 3598 int retval = 0; 3599 u8 i; 3600 3601 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 3602 mutex_lock(&mrioc->init_cmds.mutex); 3603 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3604 retval = -1; 3605 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n"); 3606 mutex_unlock(&mrioc->init_cmds.mutex); 3607 goto out; 3608 } 3609 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3610 mrioc->init_cmds.is_waiting = 1; 3611 mrioc->init_cmds.callback = NULL; 3612 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3613 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION; 3614 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3615 evtnotify_req.event_masks[i] = 3616 cpu_to_le32(mrioc->event_masks[i]); 3617 init_completion(&mrioc->init_cmds.done); 3618 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req, 3619 sizeof(evtnotify_req), 1); 3620 if (retval) { 3621 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n"); 3622 goto out_unlock; 3623 } 3624 wait_for_completion_timeout(&mrioc->init_cmds.done, 3625 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3626 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3627 ioc_err(mrioc, "event notification timed out\n"); 3628 mpi3mr_check_rh_fault_ioc(mrioc, 3629 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 3630 retval = -1; 3631 goto out_unlock; 3632 } 3633 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3634 != MPI3_IOCSTATUS_SUCCESS) { 3635 ioc_err(mrioc, 3636 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3637 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3638 mrioc->init_cmds.ioc_loginfo); 3639 retval = -1; 3640 goto out_unlock; 3641 } 3642 3643 out_unlock: 3644 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3645 mutex_unlock(&mrioc->init_cmds.mutex); 3646 out: 3647 return retval; 3648 } 3649 3650 /** 3651 * mpi3mr_process_event_ack - Process event acknowledgment 3652 * @mrioc: Adapter instance reference 3653 * @event: MPI3 event ID 3654 * @event_ctx: event context 3655 * 3656 * Send event acknowledgment through admin queue and wait for 3657 * it to complete. 3658 * 3659 * Return: 0 on success, non-zero on failures. 3660 */ 3661 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 3662 u32 event_ctx) 3663 { 3664 struct mpi3_event_ack_request evtack_req; 3665 int retval = 0; 3666 3667 memset(&evtack_req, 0, sizeof(evtack_req)); 3668 mutex_lock(&mrioc->init_cmds.mutex); 3669 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3670 retval = -1; 3671 ioc_err(mrioc, "Send EvtAck: Init command is in use\n"); 3672 mutex_unlock(&mrioc->init_cmds.mutex); 3673 goto out; 3674 } 3675 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3676 mrioc->init_cmds.is_waiting = 1; 3677 mrioc->init_cmds.callback = NULL; 3678 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3679 evtack_req.function = MPI3_FUNCTION_EVENT_ACK; 3680 evtack_req.event = event; 3681 evtack_req.event_context = cpu_to_le32(event_ctx); 3682 3683 init_completion(&mrioc->init_cmds.done); 3684 retval = mpi3mr_admin_request_post(mrioc, &evtack_req, 3685 sizeof(evtack_req), 1); 3686 if (retval) { 3687 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n"); 3688 goto out_unlock; 3689 } 3690 wait_for_completion_timeout(&mrioc->init_cmds.done, 3691 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3692 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3693 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 3694 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 3695 mpi3mr_check_rh_fault_ioc(mrioc, 3696 MPI3MR_RESET_FROM_EVTACK_TIMEOUT); 3697 retval = -1; 3698 goto out_unlock; 3699 } 3700 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3701 != MPI3_IOCSTATUS_SUCCESS) { 3702 ioc_err(mrioc, 3703 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3704 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3705 mrioc->init_cmds.ioc_loginfo); 3706 retval = -1; 3707 goto out_unlock; 3708 } 3709 3710 out_unlock: 3711 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3712 mutex_unlock(&mrioc->init_cmds.mutex); 3713 out: 3714 return retval; 3715 } 3716 3717 /** 3718 * mpi3mr_alloc_chain_bufs - Allocate chain buffers 3719 * @mrioc: Adapter instance reference 3720 * 3721 * Allocate chain buffers and set a bitmap to indicate free 3722 * chain buffers. Chain buffers are used to pass the SGE 3723 * information along with MPI3 SCSI IO requests for host I/O. 3724 * 3725 * Return: 0 on success, non-zero on failure 3726 */ 3727 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) 3728 { 3729 int retval = 0; 3730 u32 sz, i; 3731 u16 num_chains; 3732 3733 if (mrioc->chain_sgl_list) 3734 return retval; 3735 3736 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR; 3737 3738 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION 3739 | SHOST_DIX_TYPE1_PROTECTION 3740 | SHOST_DIX_TYPE2_PROTECTION 3741 | SHOST_DIX_TYPE3_PROTECTION)) 3742 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR); 3743 3744 mrioc->chain_buf_count = num_chains; 3745 sz = sizeof(struct chain_element) * num_chains; 3746 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL); 3747 if (!mrioc->chain_sgl_list) 3748 goto out_failed; 3749 3750 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length / 3751 MPI3MR_PAGE_SIZE_4K)) 3752 mrioc->max_sgl_entries = mrioc->facts.max_data_length / 3753 MPI3MR_PAGE_SIZE_4K; 3754 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common); 3755 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n", 3756 mrioc->max_sgl_entries, sz/1024); 3757 3758 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool", 3759 &mrioc->pdev->dev, sz, 16, 0); 3760 if (!mrioc->chain_buf_pool) { 3761 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n"); 3762 goto out_failed; 3763 } 3764 3765 for (i = 0; i < num_chains; i++) { 3766 mrioc->chain_sgl_list[i].addr = 3767 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL, 3768 &mrioc->chain_sgl_list[i].dma_addr); 3769 3770 if (!mrioc->chain_sgl_list[i].addr) 3771 goto out_failed; 3772 } 3773 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL); 3774 if (!mrioc->chain_bitmap) 3775 goto out_failed; 3776 return retval; 3777 out_failed: 3778 retval = -1; 3779 return retval; 3780 } 3781 3782 /** 3783 * mpi3mr_port_enable_complete - Mark port enable complete 3784 * @mrioc: Adapter instance reference 3785 * @drv_cmd: Internal command tracker 3786 * 3787 * Call back for asynchronous port enable request sets the 3788 * driver command to indicate port enable request is complete. 3789 * 3790 * Return: Nothing 3791 */ 3792 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc, 3793 struct mpi3mr_drv_cmd *drv_cmd) 3794 { 3795 drv_cmd->callback = NULL; 3796 mrioc->scan_started = 0; 3797 if (drv_cmd->state & MPI3MR_CMD_RESET) 3798 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR; 3799 else 3800 mrioc->scan_failed = drv_cmd->ioc_status; 3801 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3802 } 3803 3804 /** 3805 * mpi3mr_issue_port_enable - Issue Port Enable 3806 * @mrioc: Adapter instance reference 3807 * @async: Flag to wait for completion or not 3808 * 3809 * Issue Port Enable MPI request through admin queue and if the 3810 * async flag is not set wait for the completion of the port 3811 * enable or time out. 3812 * 3813 * Return: 0 on success, non-zero on failures. 3814 */ 3815 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) 3816 { 3817 struct mpi3_port_enable_request pe_req; 3818 int retval = 0; 3819 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT; 3820 3821 memset(&pe_req, 0, sizeof(pe_req)); 3822 mutex_lock(&mrioc->init_cmds.mutex); 3823 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3824 retval = -1; 3825 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n"); 3826 mutex_unlock(&mrioc->init_cmds.mutex); 3827 goto out; 3828 } 3829 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3830 if (async) { 3831 mrioc->init_cmds.is_waiting = 0; 3832 mrioc->init_cmds.callback = mpi3mr_port_enable_complete; 3833 } else { 3834 mrioc->init_cmds.is_waiting = 1; 3835 mrioc->init_cmds.callback = NULL; 3836 init_completion(&mrioc->init_cmds.done); 3837 } 3838 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3839 pe_req.function = MPI3_FUNCTION_PORT_ENABLE; 3840 3841 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1); 3842 if (retval) { 3843 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n"); 3844 goto out_unlock; 3845 } 3846 if (async) { 3847 mutex_unlock(&mrioc->init_cmds.mutex); 3848 goto out; 3849 } 3850 3851 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ)); 3852 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3853 ioc_err(mrioc, "port enable timed out\n"); 3854 retval = -1; 3855 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3856 goto out_unlock; 3857 } 3858 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds); 3859 3860 out_unlock: 3861 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3862 mutex_unlock(&mrioc->init_cmds.mutex); 3863 out: 3864 return retval; 3865 } 3866 3867 /* Protocol type to name mapper structure */ 3868 static const struct { 3869 u8 protocol; 3870 char *name; 3871 } mpi3mr_protocols[] = { 3872 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" }, 3873 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" }, 3874 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" }, 3875 }; 3876 3877 /* Capability to name mapper structure*/ 3878 static const struct { 3879 u32 capability; 3880 char *name; 3881 } mpi3mr_capabilities[] = { 3882 { MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" }, 3883 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" }, 3884 }; 3885 3886 /** 3887 * mpi3mr_repost_diag_bufs - repost host diag buffers 3888 * @mrioc: Adapter instance reference 3889 * 3890 * repost firmware and trace diag buffers based on global 3891 * trigger flag from driver page 2 3892 * 3893 * Return: 0 on success, non-zero on failures. 3894 */ 3895 static int mpi3mr_repost_diag_bufs(struct mpi3mr_ioc *mrioc) 3896 { 3897 u64 global_trigger; 3898 union mpi3mr_trigger_data prev_trigger_data; 3899 struct diag_buffer_desc *trace_hdb = NULL; 3900 struct diag_buffer_desc *fw_hdb = NULL; 3901 int retval = 0; 3902 bool trace_repost_needed = false; 3903 bool fw_repost_needed = false; 3904 u8 prev_trigger_type; 3905 3906 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT); 3907 if (retval) 3908 return -1; 3909 3910 trace_hdb = mpi3mr_diag_buffer_for_type(mrioc, 3911 MPI3_DIAG_BUFFER_TYPE_TRACE); 3912 3913 if (trace_hdb && 3914 trace_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED && 3915 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL && 3916 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT) 3917 trace_repost_needed = true; 3918 3919 fw_hdb = mpi3mr_diag_buffer_for_type(mrioc, MPI3_DIAG_BUFFER_TYPE_FW); 3920 3921 if (fw_hdb && fw_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED && 3922 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL && 3923 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT) 3924 fw_repost_needed = true; 3925 3926 if (trace_repost_needed || fw_repost_needed) { 3927 global_trigger = le64_to_cpu(mrioc->driver_pg2->global_trigger); 3928 if (global_trigger & 3929 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED) 3930 trace_repost_needed = false; 3931 if (global_trigger & 3932 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED) 3933 fw_repost_needed = false; 3934 } 3935 3936 if (trace_repost_needed) { 3937 prev_trigger_type = trace_hdb->trigger_type; 3938 memcpy(&prev_trigger_data, &trace_hdb->trigger_data, 3939 sizeof(trace_hdb->trigger_data)); 3940 retval = mpi3mr_issue_diag_buf_post(mrioc, trace_hdb); 3941 if (!retval) { 3942 dprint_init(mrioc, "trace diag buffer reposted"); 3943 mpi3mr_set_trigger_data_in_hdb(trace_hdb, 3944 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1); 3945 } else { 3946 trace_hdb->trigger_type = prev_trigger_type; 3947 memcpy(&trace_hdb->trigger_data, &prev_trigger_data, 3948 sizeof(prev_trigger_data)); 3949 ioc_err(mrioc, "trace diag buffer repost failed"); 3950 return -1; 3951 } 3952 } 3953 3954 if (fw_repost_needed) { 3955 prev_trigger_type = fw_hdb->trigger_type; 3956 memcpy(&prev_trigger_data, &fw_hdb->trigger_data, 3957 sizeof(fw_hdb->trigger_data)); 3958 retval = mpi3mr_issue_diag_buf_post(mrioc, fw_hdb); 3959 if (!retval) { 3960 dprint_init(mrioc, "firmware diag buffer reposted"); 3961 mpi3mr_set_trigger_data_in_hdb(fw_hdb, 3962 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1); 3963 } else { 3964 fw_hdb->trigger_type = prev_trigger_type; 3965 memcpy(&fw_hdb->trigger_data, &prev_trigger_data, 3966 sizeof(prev_trigger_data)); 3967 ioc_err(mrioc, "firmware diag buffer repost failed"); 3968 return -1; 3969 } 3970 } 3971 return retval; 3972 } 3973 3974 /** 3975 * mpi3mr_read_tsu_interval - Update time stamp interval 3976 * @mrioc: Adapter instance reference 3977 * 3978 * Update time stamp interval if its defined in driver page 1, 3979 * otherwise use default value. 3980 * 3981 * Return: Nothing 3982 */ 3983 static void 3984 mpi3mr_read_tsu_interval(struct mpi3mr_ioc *mrioc) 3985 { 3986 struct mpi3_driver_page1 driver_pg1; 3987 u16 pg_sz = sizeof(driver_pg1); 3988 int retval = 0; 3989 3990 mrioc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL; 3991 3992 retval = mpi3mr_cfg_get_driver_pg1(mrioc, &driver_pg1, pg_sz); 3993 if (!retval && driver_pg1.time_stamp_update) 3994 mrioc->ts_update_interval = (driver_pg1.time_stamp_update * 60); 3995 } 3996 3997 /** 3998 * mpi3mr_print_ioc_info - Display controller information 3999 * @mrioc: Adapter instance reference 4000 * 4001 * Display controller personality, capability, supported 4002 * protocols etc. 4003 * 4004 * Return: Nothing 4005 */ 4006 static void 4007 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc) 4008 { 4009 int i = 0, bytes_written = 0; 4010 const char *personality; 4011 char protocol[50] = {0}; 4012 char capabilities[100] = {0}; 4013 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver; 4014 4015 switch (mrioc->facts.personality) { 4016 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 4017 personality = "Enhanced HBA"; 4018 break; 4019 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 4020 personality = "RAID"; 4021 break; 4022 default: 4023 personality = "Unknown"; 4024 break; 4025 } 4026 4027 ioc_info(mrioc, "Running in %s Personality", personality); 4028 4029 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n", 4030 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 4031 fwver->ph_minor, fwver->cust_id, fwver->build_num); 4032 4033 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) { 4034 if (mrioc->facts.protocol_flags & 4035 mpi3mr_protocols[i].protocol) { 4036 bytes_written += scnprintf(protocol + bytes_written, 4037 sizeof(protocol) - bytes_written, "%s%s", 4038 bytes_written ? "," : "", 4039 mpi3mr_protocols[i].name); 4040 } 4041 } 4042 4043 bytes_written = 0; 4044 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) { 4045 if (mrioc->facts.protocol_flags & 4046 mpi3mr_capabilities[i].capability) { 4047 bytes_written += scnprintf(capabilities + bytes_written, 4048 sizeof(capabilities) - bytes_written, "%s%s", 4049 bytes_written ? "," : "", 4050 mpi3mr_capabilities[i].name); 4051 } 4052 } 4053 4054 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n", 4055 protocol, capabilities); 4056 } 4057 4058 /** 4059 * mpi3mr_cleanup_resources - Free PCI resources 4060 * @mrioc: Adapter instance reference 4061 * 4062 * Unmap PCI device memory and disable PCI device. 4063 * 4064 * Return: 0 on success and non-zero on failure. 4065 */ 4066 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc) 4067 { 4068 struct pci_dev *pdev = mrioc->pdev; 4069 4070 mpi3mr_cleanup_isr(mrioc); 4071 4072 if (mrioc->sysif_regs) { 4073 iounmap((void __iomem *)mrioc->sysif_regs); 4074 mrioc->sysif_regs = NULL; 4075 } 4076 4077 if (pci_is_enabled(pdev)) { 4078 if (mrioc->bars) 4079 pci_release_selected_regions(pdev, mrioc->bars); 4080 pci_disable_device(pdev); 4081 } 4082 } 4083 4084 /** 4085 * mpi3mr_setup_resources - Enable PCI resources 4086 * @mrioc: Adapter instance reference 4087 * 4088 * Enable PCI device memory, MSI-x registers and set DMA mask. 4089 * 4090 * Return: 0 on success and non-zero on failure. 4091 */ 4092 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) 4093 { 4094 struct pci_dev *pdev = mrioc->pdev; 4095 u32 memap_sz = 0; 4096 int i, retval = 0, capb = 0; 4097 u16 message_control; 4098 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask : 4099 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); 4100 4101 if (pci_enable_device_mem(pdev)) { 4102 ioc_err(mrioc, "pci_enable_device_mem: failed\n"); 4103 retval = -ENODEV; 4104 goto out_failed; 4105 } 4106 4107 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 4108 if (!capb) { 4109 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n"); 4110 retval = -ENODEV; 4111 goto out_failed; 4112 } 4113 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 4114 4115 if (pci_request_selected_regions(pdev, mrioc->bars, 4116 mrioc->driver_name)) { 4117 ioc_err(mrioc, "pci_request_selected_regions: failed\n"); 4118 retval = -ENODEV; 4119 goto out_failed; 4120 } 4121 4122 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) { 4123 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 4124 mrioc->sysif_regs_phys = pci_resource_start(pdev, i); 4125 memap_sz = pci_resource_len(pdev, i); 4126 mrioc->sysif_regs = 4127 ioremap(mrioc->sysif_regs_phys, memap_sz); 4128 break; 4129 } 4130 } 4131 4132 pci_set_master(pdev); 4133 4134 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 4135 if (retval) { 4136 if (dma_mask != DMA_BIT_MASK(32)) { 4137 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n"); 4138 dma_mask = DMA_BIT_MASK(32); 4139 retval = dma_set_mask_and_coherent(&pdev->dev, 4140 dma_mask); 4141 } 4142 if (retval) { 4143 mrioc->dma_mask = 0; 4144 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n"); 4145 goto out_failed; 4146 } 4147 } 4148 mrioc->dma_mask = dma_mask; 4149 4150 if (!mrioc->sysif_regs) { 4151 ioc_err(mrioc, 4152 "Unable to map adapter memory or resource not found\n"); 4153 retval = -EINVAL; 4154 goto out_failed; 4155 } 4156 4157 pci_read_config_word(pdev, capb + 2, &message_control); 4158 mrioc->msix_count = (message_control & 0x3FF) + 1; 4159 4160 pci_save_state(pdev); 4161 4162 pci_set_drvdata(pdev, mrioc->shost); 4163 4164 mpi3mr_ioc_disable_intr(mrioc); 4165 4166 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 4167 (unsigned long long)mrioc->sysif_regs_phys, 4168 mrioc->sysif_regs, memap_sz); 4169 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n", 4170 mrioc->msix_count); 4171 4172 if (!reset_devices && poll_queues > 0) 4173 mrioc->requested_poll_qcount = min_t(int, poll_queues, 4174 mrioc->msix_count - 2); 4175 return retval; 4176 4177 out_failed: 4178 mpi3mr_cleanup_resources(mrioc); 4179 return retval; 4180 } 4181 4182 /** 4183 * mpi3mr_enable_events - Enable required events 4184 * @mrioc: Adapter instance reference 4185 * 4186 * This routine unmasks the events required by the driver by 4187 * sennding appropriate event mask bitmapt through an event 4188 * notification request. 4189 * 4190 * Return: 0 on success and non-zero on failure. 4191 */ 4192 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc) 4193 { 4194 int retval = 0; 4195 u32 i; 4196 4197 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4198 mrioc->event_masks[i] = -1; 4199 4200 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED); 4201 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED); 4202 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 4203 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 4204 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED); 4205 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 4206 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY); 4207 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 4208 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 4209 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 4210 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION); 4211 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET); 4212 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT); 4213 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE); 4214 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE); 4215 4216 retval = mpi3mr_issue_event_notification(mrioc); 4217 if (retval) 4218 ioc_err(mrioc, "failed to issue event notification %d\n", 4219 retval); 4220 return retval; 4221 } 4222 4223 /** 4224 * mpi3mr_init_ioc - Initialize the controller 4225 * @mrioc: Adapter instance reference 4226 * 4227 * This the controller initialization routine, executed either 4228 * after soft reset or from pci probe callback. 4229 * Setup the required resources, memory map the controller 4230 * registers, create admin and operational reply queue pairs, 4231 * allocate required memory for reply pool, sense buffer pool, 4232 * issue IOC init request to the firmware, unmask the events and 4233 * issue port enable to discover SAS/SATA/NVMe devies and RAID 4234 * volumes. 4235 * 4236 * Return: 0 on success and non-zero on failure. 4237 */ 4238 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) 4239 { 4240 int retval = 0; 4241 u8 retry = 0; 4242 struct mpi3_ioc_facts_data facts_data; 4243 u32 sz; 4244 4245 retry_init: 4246 retval = mpi3mr_bring_ioc_ready(mrioc); 4247 if (retval) { 4248 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n", 4249 retval); 4250 goto out_failed_noretry; 4251 } 4252 4253 retval = mpi3mr_setup_isr(mrioc, 1); 4254 if (retval) { 4255 ioc_err(mrioc, "Failed to setup ISR error %d\n", 4256 retval); 4257 goto out_failed_noretry; 4258 } 4259 4260 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 4261 if (retval) { 4262 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n", 4263 retval); 4264 goto out_failed; 4265 } 4266 4267 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD; 4268 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512; 4269 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group; 4270 atomic_set(&mrioc->pend_large_data_sz, 0); 4271 4272 if (reset_devices) 4273 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios, 4274 MPI3MR_HOST_IOS_KDUMP); 4275 4276 if (!(mrioc->facts.ioc_capabilities & 4277 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) { 4278 mrioc->sas_transport_enabled = 1; 4279 mrioc->scsi_device_channel = 1; 4280 mrioc->shost->max_channel = 1; 4281 mrioc->shost->transportt = mpi3mr_transport_template; 4282 } 4283 4284 if (mrioc->facts.max_req_limit) 4285 mrioc->prevent_reply_qfull = true; 4286 4287 if (mrioc->facts.ioc_capabilities & 4288 MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED) 4289 mrioc->seg_tb_support = true; 4290 4291 mrioc->reply_sz = mrioc->facts.reply_sz; 4292 4293 retval = mpi3mr_check_reset_dma_mask(mrioc); 4294 if (retval) { 4295 ioc_err(mrioc, "Resetting dma mask failed %d\n", 4296 retval); 4297 goto out_failed_noretry; 4298 } 4299 4300 mpi3mr_read_tsu_interval(mrioc); 4301 mpi3mr_print_ioc_info(mrioc); 4302 4303 dprint_init(mrioc, "allocating host diag buffers\n"); 4304 mpi3mr_alloc_diag_bufs(mrioc); 4305 4306 dprint_init(mrioc, "allocating ioctl dma buffers\n"); 4307 mpi3mr_alloc_ioctl_dma_memory(mrioc); 4308 4309 dprint_init(mrioc, "posting host diag buffers\n"); 4310 retval = mpi3mr_post_diag_bufs(mrioc); 4311 4312 if (retval) 4313 ioc_warn(mrioc, "failed to post host diag buffers\n"); 4314 4315 if (!mrioc->init_cmds.reply) { 4316 retval = mpi3mr_alloc_reply_sense_bufs(mrioc); 4317 if (retval) { 4318 ioc_err(mrioc, 4319 "%s :Failed to allocated reply sense buffers %d\n", 4320 __func__, retval); 4321 goto out_failed_noretry; 4322 } 4323 } 4324 4325 if (!mrioc->chain_sgl_list) { 4326 retval = mpi3mr_alloc_chain_bufs(mrioc); 4327 if (retval) { 4328 ioc_err(mrioc, "Failed to allocated chain buffers %d\n", 4329 retval); 4330 goto out_failed_noretry; 4331 } 4332 } 4333 4334 retval = mpi3mr_issue_iocinit(mrioc); 4335 if (retval) { 4336 ioc_err(mrioc, "Failed to Issue IOC Init %d\n", 4337 retval); 4338 goto out_failed; 4339 } 4340 4341 retval = mpi3mr_print_pkg_ver(mrioc); 4342 if (retval) { 4343 ioc_err(mrioc, "failed to get package version\n"); 4344 goto out_failed; 4345 } 4346 4347 retval = mpi3mr_setup_isr(mrioc, 0); 4348 if (retval) { 4349 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n", 4350 retval); 4351 goto out_failed_noretry; 4352 } 4353 4354 retval = mpi3mr_create_op_queues(mrioc); 4355 if (retval) { 4356 ioc_err(mrioc, "Failed to create OpQueues error %d\n", 4357 retval); 4358 goto out_failed; 4359 } 4360 4361 if (!mrioc->pel_seqnum_virt) { 4362 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n"); 4363 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4364 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4365 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4366 GFP_KERNEL); 4367 if (!mrioc->pel_seqnum_virt) { 4368 retval = -ENOMEM; 4369 goto out_failed_noretry; 4370 } 4371 } 4372 4373 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) { 4374 dprint_init(mrioc, "allocating memory for throttle groups\n"); 4375 sz = sizeof(struct mpi3mr_throttle_group_info); 4376 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL); 4377 if (!mrioc->throttle_groups) { 4378 retval = -1; 4379 goto out_failed_noretry; 4380 } 4381 } 4382 4383 retval = mpi3mr_enable_events(mrioc); 4384 if (retval) { 4385 ioc_err(mrioc, "failed to enable events %d\n", 4386 retval); 4387 goto out_failed; 4388 } 4389 4390 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT); 4391 if (retval) { 4392 ioc_err(mrioc, "failed to refresh triggers\n"); 4393 goto out_failed; 4394 } 4395 4396 ioc_info(mrioc, "controller initialization completed successfully\n"); 4397 return retval; 4398 out_failed: 4399 if (retry < 2) { 4400 retry++; 4401 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n", 4402 retry); 4403 mpi3mr_memset_buffers(mrioc); 4404 goto retry_init; 4405 } 4406 retval = -1; 4407 out_failed_noretry: 4408 ioc_err(mrioc, "controller initialization failed\n"); 4409 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4410 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4411 mrioc->unrecoverable = 1; 4412 return retval; 4413 } 4414 4415 /** 4416 * mpi3mr_reinit_ioc - Re-Initialize the controller 4417 * @mrioc: Adapter instance reference 4418 * @is_resume: Called from resume or reset path 4419 * 4420 * This the controller re-initialization routine, executed from 4421 * the soft reset handler or resume callback. Creates 4422 * operational reply queue pairs, allocate required memory for 4423 * reply pool, sense buffer pool, issue IOC init request to the 4424 * firmware, unmask the events and issue port enable to discover 4425 * SAS/SATA/NVMe devices and RAID volumes. 4426 * 4427 * Return: 0 on success and non-zero on failure. 4428 */ 4429 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume) 4430 { 4431 int retval = 0; 4432 u8 retry = 0; 4433 struct mpi3_ioc_facts_data facts_data; 4434 u32 pe_timeout, ioc_status; 4435 4436 retry_init: 4437 pe_timeout = 4438 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL); 4439 4440 dprint_reset(mrioc, "bringing up the controller to ready state\n"); 4441 retval = mpi3mr_bring_ioc_ready(mrioc); 4442 if (retval) { 4443 ioc_err(mrioc, "failed to bring to ready state\n"); 4444 goto out_failed_noretry; 4445 } 4446 4447 mrioc->io_admin_reset_sync = 0; 4448 if (is_resume || mrioc->block_on_pci_err) { 4449 dprint_reset(mrioc, "setting up single ISR\n"); 4450 retval = mpi3mr_setup_isr(mrioc, 1); 4451 if (retval) { 4452 ioc_err(mrioc, "failed to setup ISR\n"); 4453 goto out_failed_noretry; 4454 } 4455 } else 4456 mpi3mr_ioc_enable_intr(mrioc); 4457 4458 dprint_reset(mrioc, "getting ioc_facts\n"); 4459 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 4460 if (retval) { 4461 ioc_err(mrioc, "failed to get ioc_facts\n"); 4462 goto out_failed; 4463 } 4464 4465 dprint_reset(mrioc, "validating ioc_facts\n"); 4466 retval = mpi3mr_revalidate_factsdata(mrioc); 4467 if (retval) { 4468 ioc_err(mrioc, "failed to revalidate ioc_facts data\n"); 4469 goto out_failed_noretry; 4470 } 4471 4472 mpi3mr_read_tsu_interval(mrioc); 4473 mpi3mr_print_ioc_info(mrioc); 4474 4475 if (is_resume) { 4476 dprint_reset(mrioc, "posting host diag buffers\n"); 4477 retval = mpi3mr_post_diag_bufs(mrioc); 4478 if (retval) 4479 ioc_warn(mrioc, "failed to post host diag buffers\n"); 4480 } else { 4481 retval = mpi3mr_repost_diag_bufs(mrioc); 4482 if (retval) 4483 ioc_warn(mrioc, "failed to re post host diag buffers\n"); 4484 } 4485 4486 dprint_reset(mrioc, "sending ioc_init\n"); 4487 retval = mpi3mr_issue_iocinit(mrioc); 4488 if (retval) { 4489 ioc_err(mrioc, "failed to send ioc_init\n"); 4490 goto out_failed; 4491 } 4492 4493 dprint_reset(mrioc, "getting package version\n"); 4494 retval = mpi3mr_print_pkg_ver(mrioc); 4495 if (retval) { 4496 ioc_err(mrioc, "failed to get package version\n"); 4497 goto out_failed; 4498 } 4499 4500 if (is_resume || mrioc->block_on_pci_err) { 4501 dprint_reset(mrioc, "setting up multiple ISR\n"); 4502 retval = mpi3mr_setup_isr(mrioc, 0); 4503 if (retval) { 4504 ioc_err(mrioc, "failed to re-setup ISR\n"); 4505 goto out_failed_noretry; 4506 } 4507 } 4508 4509 dprint_reset(mrioc, "creating operational queue pairs\n"); 4510 retval = mpi3mr_create_op_queues(mrioc); 4511 if (retval) { 4512 ioc_err(mrioc, "failed to create operational queue pairs\n"); 4513 goto out_failed; 4514 } 4515 4516 if (!mrioc->pel_seqnum_virt) { 4517 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n"); 4518 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4519 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4520 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4521 GFP_KERNEL); 4522 if (!mrioc->pel_seqnum_virt) { 4523 retval = -ENOMEM; 4524 goto out_failed_noretry; 4525 } 4526 } 4527 4528 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) { 4529 ioc_err(mrioc, 4530 "cannot create minimum number of operational queues expected:%d created:%d\n", 4531 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q); 4532 retval = -1; 4533 goto out_failed_noretry; 4534 } 4535 4536 dprint_reset(mrioc, "enabling events\n"); 4537 retval = mpi3mr_enable_events(mrioc); 4538 if (retval) { 4539 ioc_err(mrioc, "failed to enable events\n"); 4540 goto out_failed; 4541 } 4542 4543 mrioc->device_refresh_on = 1; 4544 mpi3mr_add_event_wait_for_device_refresh(mrioc); 4545 4546 ioc_info(mrioc, "sending port enable\n"); 4547 retval = mpi3mr_issue_port_enable(mrioc, 1); 4548 if (retval) { 4549 ioc_err(mrioc, "failed to issue port enable\n"); 4550 goto out_failed; 4551 } 4552 do { 4553 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL); 4554 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED) 4555 break; 4556 if (!pci_device_is_present(mrioc->pdev)) 4557 mrioc->unrecoverable = 1; 4558 if (mrioc->unrecoverable) { 4559 retval = -1; 4560 goto out_failed_noretry; 4561 } 4562 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4563 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 4564 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 4565 mpi3mr_print_fault_info(mrioc); 4566 mrioc->init_cmds.is_waiting = 0; 4567 mrioc->init_cmds.callback = NULL; 4568 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4569 goto out_failed; 4570 } 4571 } while (--pe_timeout); 4572 4573 if (!pe_timeout) { 4574 ioc_err(mrioc, "port enable timed out\n"); 4575 mpi3mr_check_rh_fault_ioc(mrioc, 4576 MPI3MR_RESET_FROM_PE_TIMEOUT); 4577 mrioc->init_cmds.is_waiting = 0; 4578 mrioc->init_cmds.callback = NULL; 4579 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4580 goto out_failed; 4581 } else if (mrioc->scan_failed) { 4582 ioc_err(mrioc, 4583 "port enable failed with status=0x%04x\n", 4584 mrioc->scan_failed); 4585 } else 4586 ioc_info(mrioc, "port enable completed successfully\n"); 4587 4588 ioc_info(mrioc, "controller %s completed successfully\n", 4589 (is_resume)?"resume":"re-initialization"); 4590 return retval; 4591 out_failed: 4592 if (retry < 2) { 4593 retry++; 4594 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n", 4595 (is_resume)?"resume":"re-initialization", retry); 4596 mpi3mr_memset_buffers(mrioc); 4597 goto retry_init; 4598 } 4599 retval = -1; 4600 out_failed_noretry: 4601 ioc_err(mrioc, "controller %s is failed\n", 4602 (is_resume)?"resume":"re-initialization"); 4603 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4604 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4605 mrioc->unrecoverable = 1; 4606 return retval; 4607 } 4608 4609 /** 4610 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's 4611 * segments 4612 * @mrioc: Adapter instance reference 4613 * @qidx: Operational reply queue index 4614 * 4615 * Return: Nothing. 4616 */ 4617 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4618 { 4619 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 4620 struct segments *segments; 4621 int i, size; 4622 4623 if (!op_reply_q->q_segments) 4624 return; 4625 4626 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz; 4627 segments = op_reply_q->q_segments; 4628 for (i = 0; i < op_reply_q->num_segments; i++) 4629 memset(segments[i].segment, 0, size); 4630 } 4631 4632 /** 4633 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's 4634 * segments 4635 * @mrioc: Adapter instance reference 4636 * @qidx: Operational request queue index 4637 * 4638 * Return: Nothing. 4639 */ 4640 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4641 { 4642 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 4643 struct segments *segments; 4644 int i, size; 4645 4646 if (!op_req_q->q_segments) 4647 return; 4648 4649 size = op_req_q->segment_qd * mrioc->facts.op_req_sz; 4650 segments = op_req_q->q_segments; 4651 for (i = 0; i < op_req_q->num_segments; i++) 4652 memset(segments[i].segment, 0, size); 4653 } 4654 4655 /** 4656 * mpi3mr_memset_buffers - memset memory for a controller 4657 * @mrioc: Adapter instance reference 4658 * 4659 * clear all the memory allocated for a controller, typically 4660 * called post reset to reuse the memory allocated during the 4661 * controller init. 4662 * 4663 * Return: Nothing. 4664 */ 4665 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) 4666 { 4667 u16 i; 4668 struct mpi3mr_throttle_group_info *tg; 4669 4670 mrioc->change_count = 0; 4671 mrioc->active_poll_qcount = 0; 4672 mrioc->default_qcount = 0; 4673 if (mrioc->admin_req_base) 4674 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz); 4675 if (mrioc->admin_reply_base) 4676 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz); 4677 atomic_set(&mrioc->admin_reply_q_in_use, 0); 4678 atomic_set(&mrioc->admin_pend_isr, 0); 4679 4680 if (mrioc->init_cmds.reply) { 4681 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply)); 4682 memset(mrioc->bsg_cmds.reply, 0, 4683 sizeof(*mrioc->bsg_cmds.reply)); 4684 memset(mrioc->host_tm_cmds.reply, 0, 4685 sizeof(*mrioc->host_tm_cmds.reply)); 4686 memset(mrioc->pel_cmds.reply, 0, 4687 sizeof(*mrioc->pel_cmds.reply)); 4688 memset(mrioc->pel_abort_cmd.reply, 0, 4689 sizeof(*mrioc->pel_abort_cmd.reply)); 4690 memset(mrioc->transport_cmds.reply, 0, 4691 sizeof(*mrioc->transport_cmds.reply)); 4692 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 4693 memset(mrioc->dev_rmhs_cmds[i].reply, 0, 4694 sizeof(*mrioc->dev_rmhs_cmds[i].reply)); 4695 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 4696 memset(mrioc->evtack_cmds[i].reply, 0, 4697 sizeof(*mrioc->evtack_cmds[i].reply)); 4698 bitmap_clear(mrioc->removepend_bitmap, 0, 4699 mrioc->dev_handle_bitmap_bits); 4700 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 4701 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, 4702 MPI3MR_NUM_EVTACKCMD); 4703 } 4704 4705 for (i = 0; i < mrioc->num_queues; i++) { 4706 mrioc->op_reply_qinfo[i].qid = 0; 4707 mrioc->op_reply_qinfo[i].ci = 0; 4708 mrioc->op_reply_qinfo[i].num_replies = 0; 4709 mrioc->op_reply_qinfo[i].ephase = 0; 4710 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0); 4711 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0); 4712 mpi3mr_memset_op_reply_q_buffers(mrioc, i); 4713 4714 mrioc->req_qinfo[i].ci = 0; 4715 mrioc->req_qinfo[i].pi = 0; 4716 mrioc->req_qinfo[i].num_requests = 0; 4717 mrioc->req_qinfo[i].qid = 0; 4718 mrioc->req_qinfo[i].reply_qid = 0; 4719 spin_lock_init(&mrioc->req_qinfo[i].q_lock); 4720 mpi3mr_memset_op_req_q_buffers(mrioc, i); 4721 } 4722 4723 atomic_set(&mrioc->pend_large_data_sz, 0); 4724 if (mrioc->throttle_groups) { 4725 tg = mrioc->throttle_groups; 4726 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) { 4727 tg->id = 0; 4728 tg->fw_qd = 0; 4729 tg->modified_qd = 0; 4730 tg->io_divert = 0; 4731 tg->need_qd_reduction = 0; 4732 tg->high = 0; 4733 tg->low = 0; 4734 tg->qd_reduction = 0; 4735 atomic_set(&tg->pend_large_data_sz, 0); 4736 } 4737 } 4738 } 4739 4740 /** 4741 * mpi3mr_free_mem - Free memory allocated for a controller 4742 * @mrioc: Adapter instance reference 4743 * 4744 * Free all the memory allocated for a controller. 4745 * 4746 * Return: Nothing. 4747 */ 4748 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) 4749 { 4750 u16 i, j; 4751 struct mpi3mr_intr_info *intr_info; 4752 struct diag_buffer_desc *diag_buffer; 4753 4754 mpi3mr_free_enclosure_list(mrioc); 4755 mpi3mr_free_ioctl_dma_memory(mrioc); 4756 4757 if (mrioc->sense_buf_pool) { 4758 if (mrioc->sense_buf) 4759 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf, 4760 mrioc->sense_buf_dma); 4761 dma_pool_destroy(mrioc->sense_buf_pool); 4762 mrioc->sense_buf = NULL; 4763 mrioc->sense_buf_pool = NULL; 4764 } 4765 if (mrioc->sense_buf_q_pool) { 4766 if (mrioc->sense_buf_q) 4767 dma_pool_free(mrioc->sense_buf_q_pool, 4768 mrioc->sense_buf_q, mrioc->sense_buf_q_dma); 4769 dma_pool_destroy(mrioc->sense_buf_q_pool); 4770 mrioc->sense_buf_q = NULL; 4771 mrioc->sense_buf_q_pool = NULL; 4772 } 4773 4774 if (mrioc->reply_buf_pool) { 4775 if (mrioc->reply_buf) 4776 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf, 4777 mrioc->reply_buf_dma); 4778 dma_pool_destroy(mrioc->reply_buf_pool); 4779 mrioc->reply_buf = NULL; 4780 mrioc->reply_buf_pool = NULL; 4781 } 4782 if (mrioc->reply_free_q_pool) { 4783 if (mrioc->reply_free_q) 4784 dma_pool_free(mrioc->reply_free_q_pool, 4785 mrioc->reply_free_q, mrioc->reply_free_q_dma); 4786 dma_pool_destroy(mrioc->reply_free_q_pool); 4787 mrioc->reply_free_q = NULL; 4788 mrioc->reply_free_q_pool = NULL; 4789 } 4790 4791 for (i = 0; i < mrioc->num_op_req_q; i++) 4792 mpi3mr_free_op_req_q_segments(mrioc, i); 4793 4794 for (i = 0; i < mrioc->num_op_reply_q; i++) 4795 mpi3mr_free_op_reply_q_segments(mrioc, i); 4796 4797 for (i = 0; i < mrioc->intr_info_count; i++) { 4798 intr_info = mrioc->intr_info + i; 4799 intr_info->op_reply_q = NULL; 4800 } 4801 4802 kfree(mrioc->req_qinfo); 4803 mrioc->req_qinfo = NULL; 4804 mrioc->num_op_req_q = 0; 4805 4806 kfree(mrioc->op_reply_qinfo); 4807 mrioc->op_reply_qinfo = NULL; 4808 mrioc->num_op_reply_q = 0; 4809 4810 kfree(mrioc->init_cmds.reply); 4811 mrioc->init_cmds.reply = NULL; 4812 4813 kfree(mrioc->bsg_cmds.reply); 4814 mrioc->bsg_cmds.reply = NULL; 4815 4816 kfree(mrioc->host_tm_cmds.reply); 4817 mrioc->host_tm_cmds.reply = NULL; 4818 4819 kfree(mrioc->pel_cmds.reply); 4820 mrioc->pel_cmds.reply = NULL; 4821 4822 kfree(mrioc->pel_abort_cmd.reply); 4823 mrioc->pel_abort_cmd.reply = NULL; 4824 4825 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4826 kfree(mrioc->evtack_cmds[i].reply); 4827 mrioc->evtack_cmds[i].reply = NULL; 4828 } 4829 4830 bitmap_free(mrioc->removepend_bitmap); 4831 mrioc->removepend_bitmap = NULL; 4832 4833 bitmap_free(mrioc->devrem_bitmap); 4834 mrioc->devrem_bitmap = NULL; 4835 4836 bitmap_free(mrioc->evtack_cmds_bitmap); 4837 mrioc->evtack_cmds_bitmap = NULL; 4838 4839 bitmap_free(mrioc->chain_bitmap); 4840 mrioc->chain_bitmap = NULL; 4841 4842 kfree(mrioc->transport_cmds.reply); 4843 mrioc->transport_cmds.reply = NULL; 4844 4845 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4846 kfree(mrioc->dev_rmhs_cmds[i].reply); 4847 mrioc->dev_rmhs_cmds[i].reply = NULL; 4848 } 4849 4850 if (mrioc->chain_buf_pool) { 4851 for (i = 0; i < mrioc->chain_buf_count; i++) { 4852 if (mrioc->chain_sgl_list[i].addr) { 4853 dma_pool_free(mrioc->chain_buf_pool, 4854 mrioc->chain_sgl_list[i].addr, 4855 mrioc->chain_sgl_list[i].dma_addr); 4856 mrioc->chain_sgl_list[i].addr = NULL; 4857 } 4858 } 4859 dma_pool_destroy(mrioc->chain_buf_pool); 4860 mrioc->chain_buf_pool = NULL; 4861 } 4862 4863 kfree(mrioc->chain_sgl_list); 4864 mrioc->chain_sgl_list = NULL; 4865 4866 if (mrioc->admin_reply_base) { 4867 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 4868 mrioc->admin_reply_base, mrioc->admin_reply_dma); 4869 mrioc->admin_reply_base = NULL; 4870 } 4871 if (mrioc->admin_req_base) { 4872 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 4873 mrioc->admin_req_base, mrioc->admin_req_dma); 4874 mrioc->admin_req_base = NULL; 4875 } 4876 4877 if (mrioc->pel_seqnum_virt) { 4878 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz, 4879 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma); 4880 mrioc->pel_seqnum_virt = NULL; 4881 } 4882 4883 for (i = 0; i < MPI3MR_MAX_NUM_HDB; i++) { 4884 diag_buffer = &mrioc->diag_buffers[i]; 4885 if ((i == 0) && mrioc->seg_tb_support) { 4886 if (mrioc->trace_buf_pool) { 4887 for (j = 0; j < mrioc->num_tb_segs; j++) { 4888 if (mrioc->trace_buf[j].segment) { 4889 dma_pool_free(mrioc->trace_buf_pool, 4890 mrioc->trace_buf[j].segment, 4891 mrioc->trace_buf[j].segment_dma); 4892 mrioc->trace_buf[j].segment = NULL; 4893 } 4894 4895 mrioc->trace_buf[j].segment = NULL; 4896 } 4897 dma_pool_destroy(mrioc->trace_buf_pool); 4898 mrioc->trace_buf_pool = NULL; 4899 } 4900 4901 kfree(mrioc->trace_buf); 4902 mrioc->trace_buf = NULL; 4903 diag_buffer->size = sizeof(u64) * mrioc->num_tb_segs; 4904 } 4905 if (diag_buffer->addr) { 4906 dma_free_coherent(&mrioc->pdev->dev, 4907 diag_buffer->size, diag_buffer->addr, 4908 diag_buffer->dma_addr); 4909 diag_buffer->addr = NULL; 4910 diag_buffer->size = 0; 4911 diag_buffer->type = 0; 4912 diag_buffer->status = 0; 4913 } 4914 } 4915 4916 kfree(mrioc->throttle_groups); 4917 mrioc->throttle_groups = NULL; 4918 4919 kfree(mrioc->logdata_buf); 4920 mrioc->logdata_buf = NULL; 4921 4922 } 4923 4924 /** 4925 * mpi3mr_issue_ioc_shutdown - shutdown controller 4926 * @mrioc: Adapter instance reference 4927 * 4928 * Send shutodwn notification to the controller and wait for the 4929 * shutdown_timeout for it to be completed. 4930 * 4931 * Return: Nothing. 4932 */ 4933 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) 4934 { 4935 u32 ioc_config, ioc_status; 4936 u8 retval = 1; 4937 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 4938 4939 ioc_info(mrioc, "Issuing shutdown Notification\n"); 4940 if (mrioc->unrecoverable) { 4941 ioc_warn(mrioc, 4942 "IOC is unrecoverable shutdown is not issued\n"); 4943 return; 4944 } 4945 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4946 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4947 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 4948 ioc_info(mrioc, "shutdown already in progress\n"); 4949 return; 4950 } 4951 4952 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4953 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 4954 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 4955 4956 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 4957 4958 if (mrioc->facts.shutdown_timeout) 4959 timeout = mrioc->facts.shutdown_timeout * 10; 4960 4961 do { 4962 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4963 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4964 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 4965 retval = 0; 4966 break; 4967 } 4968 msleep(100); 4969 } while (--timeout); 4970 4971 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4972 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4973 4974 if (retval) { 4975 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4976 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 4977 ioc_warn(mrioc, 4978 "shutdown still in progress after timeout\n"); 4979 } 4980 4981 ioc_info(mrioc, 4982 "Base IOC Sts/Config after %s shutdown is (0x%08x)/(0x%08x)\n", 4983 (!retval) ? "successful" : "failed", ioc_status, 4984 ioc_config); 4985 } 4986 4987 /** 4988 * mpi3mr_cleanup_ioc - Cleanup controller 4989 * @mrioc: Adapter instance reference 4990 * 4991 * controller cleanup handler, Message unit reset or soft reset 4992 * and shutdown notification is issued to the controller. 4993 * 4994 * Return: Nothing. 4995 */ 4996 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc) 4997 { 4998 enum mpi3mr_iocstate ioc_state; 4999 5000 dprint_exit(mrioc, "cleaning up the controller\n"); 5001 mpi3mr_ioc_disable_intr(mrioc); 5002 5003 ioc_state = mpi3mr_get_iocstate(mrioc); 5004 5005 if (!mrioc->unrecoverable && !mrioc->reset_in_progress && 5006 !mrioc->pci_err_recovery && 5007 (ioc_state == MRIOC_STATE_READY)) { 5008 if (mpi3mr_issue_and_process_mur(mrioc, 5009 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 5010 mpi3mr_issue_reset(mrioc, 5011 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 5012 MPI3MR_RESET_FROM_MUR_FAILURE); 5013 mpi3mr_issue_ioc_shutdown(mrioc); 5014 } 5015 dprint_exit(mrioc, "controller cleanup completed\n"); 5016 } 5017 5018 /** 5019 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 5020 * @mrioc: Adapter instance reference 5021 * @cmdptr: Internal command tracker 5022 * 5023 * Complete an internal driver commands with state indicating it 5024 * is completed due to reset. 5025 * 5026 * Return: Nothing. 5027 */ 5028 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc, 5029 struct mpi3mr_drv_cmd *cmdptr) 5030 { 5031 if (cmdptr->state & MPI3MR_CMD_PENDING) { 5032 cmdptr->state |= MPI3MR_CMD_RESET; 5033 cmdptr->state &= ~MPI3MR_CMD_PENDING; 5034 if (cmdptr->is_waiting) { 5035 complete(&cmdptr->done); 5036 cmdptr->is_waiting = 0; 5037 } else if (cmdptr->callback) 5038 cmdptr->callback(mrioc, cmdptr); 5039 } 5040 } 5041 5042 /** 5043 * mpi3mr_flush_drv_cmds - Flush internaldriver commands 5044 * @mrioc: Adapter instance reference 5045 * 5046 * Flush all internal driver commands post reset 5047 * 5048 * Return: Nothing. 5049 */ 5050 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc) 5051 { 5052 struct mpi3mr_drv_cmd *cmdptr; 5053 u8 i; 5054 5055 cmdptr = &mrioc->init_cmds; 5056 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5057 5058 cmdptr = &mrioc->cfg_cmds; 5059 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5060 5061 cmdptr = &mrioc->bsg_cmds; 5062 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5063 cmdptr = &mrioc->host_tm_cmds; 5064 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5065 5066 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 5067 cmdptr = &mrioc->dev_rmhs_cmds[i]; 5068 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5069 } 5070 5071 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 5072 cmdptr = &mrioc->evtack_cmds[i]; 5073 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5074 } 5075 5076 cmdptr = &mrioc->pel_cmds; 5077 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5078 5079 cmdptr = &mrioc->pel_abort_cmd; 5080 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5081 5082 cmdptr = &mrioc->transport_cmds; 5083 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 5084 } 5085 5086 /** 5087 * mpi3mr_pel_wait_post - Issue PEL Wait 5088 * @mrioc: Adapter instance reference 5089 * @drv_cmd: Internal command tracker 5090 * 5091 * Issue PEL Wait MPI request through admin queue and return. 5092 * 5093 * Return: Nothing. 5094 */ 5095 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc, 5096 struct mpi3mr_drv_cmd *drv_cmd) 5097 { 5098 struct mpi3_pel_req_action_wait pel_wait; 5099 5100 mrioc->pel_abort_requested = false; 5101 5102 memset(&pel_wait, 0, sizeof(pel_wait)); 5103 drv_cmd->state = MPI3MR_CMD_PENDING; 5104 drv_cmd->is_waiting = 0; 5105 drv_cmd->callback = mpi3mr_pel_wait_complete; 5106 drv_cmd->ioc_status = 0; 5107 drv_cmd->ioc_loginfo = 0; 5108 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 5109 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 5110 pel_wait.action = MPI3_PEL_ACTION_WAIT; 5111 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum); 5112 pel_wait.locale = cpu_to_le16(mrioc->pel_locale); 5113 pel_wait.class = cpu_to_le16(mrioc->pel_class); 5114 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT; 5115 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n", 5116 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale); 5117 5118 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) { 5119 dprint_bsg_err(mrioc, 5120 "Issuing PELWait: Admin post failed\n"); 5121 drv_cmd->state = MPI3MR_CMD_NOTUSED; 5122 drv_cmd->callback = NULL; 5123 drv_cmd->retry_count = 0; 5124 mrioc->pel_enabled = false; 5125 } 5126 } 5127 5128 /** 5129 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number 5130 * @mrioc: Adapter instance reference 5131 * @drv_cmd: Internal command tracker 5132 * 5133 * Issue PEL get sequence number MPI request through admin queue 5134 * and return. 5135 * 5136 * Return: 0 on success, non-zero on failure. 5137 */ 5138 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 5139 struct mpi3mr_drv_cmd *drv_cmd) 5140 { 5141 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req; 5142 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 5143 int retval = 0; 5144 5145 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req)); 5146 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING; 5147 mrioc->pel_cmds.is_waiting = 0; 5148 mrioc->pel_cmds.ioc_status = 0; 5149 mrioc->pel_cmds.ioc_loginfo = 0; 5150 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete; 5151 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 5152 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 5153 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM; 5154 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags, 5155 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma); 5156 5157 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req, 5158 sizeof(pel_getseq_req), 0); 5159 if (retval) { 5160 if (drv_cmd) { 5161 drv_cmd->state = MPI3MR_CMD_NOTUSED; 5162 drv_cmd->callback = NULL; 5163 drv_cmd->retry_count = 0; 5164 } 5165 mrioc->pel_enabled = false; 5166 } 5167 5168 return retval; 5169 } 5170 5171 /** 5172 * mpi3mr_pel_wait_complete - PELWait Completion callback 5173 * @mrioc: Adapter instance reference 5174 * @drv_cmd: Internal command tracker 5175 * 5176 * This is a callback handler for the PELWait request and 5177 * firmware completes a PELWait request when it is aborted or a 5178 * new PEL entry is available. This sends AEN to the application 5179 * and if the PELwait completion is not due to PELAbort then 5180 * this will send a request for new PEL Sequence number 5181 * 5182 * Return: Nothing. 5183 */ 5184 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 5185 struct mpi3mr_drv_cmd *drv_cmd) 5186 { 5187 struct mpi3_pel_reply *pel_reply = NULL; 5188 u16 ioc_status, pe_log_status; 5189 bool do_retry = false; 5190 5191 if (drv_cmd->state & MPI3MR_CMD_RESET) 5192 goto cleanup_drv_cmd; 5193 5194 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5195 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5196 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 5197 __func__, ioc_status, drv_cmd->ioc_loginfo); 5198 dprint_bsg_err(mrioc, 5199 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 5200 ioc_status, drv_cmd->ioc_loginfo); 5201 do_retry = true; 5202 } 5203 5204 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 5205 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 5206 5207 if (!pel_reply) { 5208 dprint_bsg_err(mrioc, 5209 "pel_wait: failed due to no reply\n"); 5210 goto out_failed; 5211 } 5212 5213 pe_log_status = le16_to_cpu(pel_reply->pe_log_status); 5214 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) && 5215 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) { 5216 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n", 5217 __func__, pe_log_status); 5218 dprint_bsg_err(mrioc, 5219 "pel_wait: failed due to pel_log_status(0x%04x)\n", 5220 pe_log_status); 5221 do_retry = true; 5222 } 5223 5224 if (do_retry) { 5225 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 5226 drv_cmd->retry_count++; 5227 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n", 5228 drv_cmd->retry_count); 5229 mpi3mr_pel_wait_post(mrioc, drv_cmd); 5230 return; 5231 } 5232 dprint_bsg_err(mrioc, 5233 "pel_wait: failed after all retries(%d)\n", 5234 drv_cmd->retry_count); 5235 goto out_failed; 5236 } 5237 atomic64_inc(&event_counter); 5238 if (!mrioc->pel_abort_requested) { 5239 mrioc->pel_cmds.retry_count = 0; 5240 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds); 5241 } 5242 5243 return; 5244 out_failed: 5245 mrioc->pel_enabled = false; 5246 cleanup_drv_cmd: 5247 drv_cmd->state = MPI3MR_CMD_NOTUSED; 5248 drv_cmd->callback = NULL; 5249 drv_cmd->retry_count = 0; 5250 } 5251 5252 /** 5253 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback 5254 * @mrioc: Adapter instance reference 5255 * @drv_cmd: Internal command tracker 5256 * 5257 * This is a callback handler for the PEL get sequence number 5258 * request and a new PEL wait request will be issued to the 5259 * firmware from this 5260 * 5261 * Return: Nothing. 5262 */ 5263 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 5264 struct mpi3mr_drv_cmd *drv_cmd) 5265 { 5266 struct mpi3_pel_reply *pel_reply = NULL; 5267 struct mpi3_pel_seq *pel_seqnum_virt; 5268 u16 ioc_status; 5269 bool do_retry = false; 5270 5271 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt; 5272 5273 if (drv_cmd->state & MPI3MR_CMD_RESET) 5274 goto cleanup_drv_cmd; 5275 5276 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5277 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5278 dprint_bsg_err(mrioc, 5279 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 5280 ioc_status, drv_cmd->ioc_loginfo); 5281 do_retry = true; 5282 } 5283 5284 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 5285 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 5286 if (!pel_reply) { 5287 dprint_bsg_err(mrioc, 5288 "pel_get_seqnum: failed due to no reply\n"); 5289 goto out_failed; 5290 } 5291 5292 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) { 5293 dprint_bsg_err(mrioc, 5294 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n", 5295 le16_to_cpu(pel_reply->pe_log_status)); 5296 do_retry = true; 5297 } 5298 5299 if (do_retry) { 5300 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 5301 drv_cmd->retry_count++; 5302 dprint_bsg_err(mrioc, 5303 "pel_get_seqnum: retrying(%d)\n", 5304 drv_cmd->retry_count); 5305 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd); 5306 return; 5307 } 5308 5309 dprint_bsg_err(mrioc, 5310 "pel_get_seqnum: failed after all retries(%d)\n", 5311 drv_cmd->retry_count); 5312 goto out_failed; 5313 } 5314 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1; 5315 drv_cmd->retry_count = 0; 5316 mpi3mr_pel_wait_post(mrioc, drv_cmd); 5317 5318 return; 5319 out_failed: 5320 mrioc->pel_enabled = false; 5321 cleanup_drv_cmd: 5322 drv_cmd->state = MPI3MR_CMD_NOTUSED; 5323 drv_cmd->callback = NULL; 5324 drv_cmd->retry_count = 0; 5325 } 5326 5327 /** 5328 * mpi3mr_check_op_admin_proc - 5329 * @mrioc: Adapter instance reference 5330 * 5331 * Check if any of the operation reply queues 5332 * or the admin reply queue are currently in use. 5333 * If any queue is in use, this function waits for 5334 * a maximum of 10 seconds for them to become available. 5335 * 5336 * Return: 0 on success, non-zero on failure. 5337 */ 5338 static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc) 5339 { 5340 5341 u16 timeout = 10 * 10; 5342 u16 elapsed_time = 0; 5343 bool op_admin_in_use = false; 5344 5345 do { 5346 op_admin_in_use = false; 5347 5348 /* Check admin_reply queue first to exit early */ 5349 if (atomic_read(&mrioc->admin_reply_q_in_use) == 1) 5350 op_admin_in_use = true; 5351 else { 5352 /* Check op_reply queues */ 5353 int i; 5354 5355 for (i = 0; i < mrioc->num_queues; i++) { 5356 if (atomic_read(&mrioc->op_reply_qinfo[i].in_use) == 1) { 5357 op_admin_in_use = true; 5358 break; 5359 } 5360 } 5361 } 5362 5363 if (!op_admin_in_use) 5364 break; 5365 5366 msleep(100); 5367 5368 } while (++elapsed_time < timeout); 5369 5370 if (op_admin_in_use) 5371 return 1; 5372 5373 return 0; 5374 } 5375 5376 /** 5377 * mpi3mr_soft_reset_handler - Reset the controller 5378 * @mrioc: Adapter instance reference 5379 * @reset_reason: Reset reason code 5380 * @snapdump: Flag to generate snapdump in firmware or not 5381 * 5382 * This is an handler for recovering controller by issuing soft 5383 * reset are diag fault reset. This is a blocking function and 5384 * when one reset is executed if any other resets they will be 5385 * blocked. All BSG requests will be blocked during the reset. If 5386 * controller reset is successful then the controller will be 5387 * reinitalized, otherwise the controller will be marked as not 5388 * recoverable 5389 * 5390 * In snapdump bit is set, the controller is issued with diag 5391 * fault reset so that the firmware can create a snap dump and 5392 * post that the firmware will result in F000 fault and the 5393 * driver will issue soft reset to recover from that. 5394 * 5395 * Return: 0 on success, non-zero on failure. 5396 */ 5397 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 5398 u16 reset_reason, u8 snapdump) 5399 { 5400 int retval = 0, i; 5401 unsigned long flags; 5402 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 5403 union mpi3mr_trigger_data trigger_data; 5404 5405 /* Block the reset handler until diag save in progress*/ 5406 dprint_reset(mrioc, 5407 "soft_reset_handler: check and block on diagsave_timeout(%d)\n", 5408 mrioc->diagsave_timeout); 5409 while (mrioc->diagsave_timeout) 5410 ssleep(1); 5411 /* 5412 * Block new resets until the currently executing one is finished and 5413 * return the status of the existing reset for all blocked resets 5414 */ 5415 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n"); 5416 if (!mutex_trylock(&mrioc->reset_mutex)) { 5417 ioc_info(mrioc, 5418 "controller reset triggered by %s is blocked due to another reset in progress\n", 5419 mpi3mr_reset_rc_name(reset_reason)); 5420 do { 5421 ssleep(1); 5422 } while (mrioc->reset_in_progress == 1); 5423 ioc_info(mrioc, 5424 "returning previous reset result(%d) for the reset triggered by %s\n", 5425 mrioc->prev_reset_result, 5426 mpi3mr_reset_rc_name(reset_reason)); 5427 return mrioc->prev_reset_result; 5428 } 5429 ioc_info(mrioc, "controller reset is triggered by %s\n", 5430 mpi3mr_reset_rc_name(reset_reason)); 5431 5432 mrioc->device_refresh_on = 0; 5433 scsi_block_requests(mrioc->shost); 5434 mrioc->reset_in_progress = 1; 5435 mrioc->stop_bsgs = 1; 5436 mrioc->prev_reset_result = -1; 5437 memset(&trigger_data, 0, sizeof(trigger_data)); 5438 5439 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 5440 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 5441 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 5442 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 5443 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0); 5444 dprint_reset(mrioc, 5445 "soft_reset_handler: releasing host diagnostic buffers\n"); 5446 mpi3mr_release_diag_bufs(mrioc, 0); 5447 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5448 mrioc->event_masks[i] = -1; 5449 5450 dprint_reset(mrioc, "soft_reset_handler: masking events\n"); 5451 mpi3mr_issue_event_notification(mrioc); 5452 } 5453 5454 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT); 5455 5456 mpi3mr_ioc_disable_intr(mrioc); 5457 mrioc->io_admin_reset_sync = 1; 5458 5459 if (snapdump) { 5460 mpi3mr_set_diagsave(mrioc); 5461 retval = mpi3mr_issue_reset(mrioc, 5462 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5463 if (!retval) { 5464 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) & 5465 MPI3_SYSIF_FAULT_CODE_MASK); 5466 do { 5467 host_diagnostic = 5468 readl(&mrioc->sysif_regs->host_diagnostic); 5469 if (!(host_diagnostic & 5470 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 5471 break; 5472 msleep(100); 5473 } while (--timeout); 5474 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 5475 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0); 5476 } 5477 } 5478 5479 retval = mpi3mr_issue_reset(mrioc, 5480 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 5481 if (retval) { 5482 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n"); 5483 goto out; 5484 } 5485 5486 retval = mpi3mr_check_op_admin_proc(mrioc); 5487 if (retval) { 5488 ioc_err(mrioc, "Soft reset failed due to an Admin or I/O queue polling\n" 5489 "thread still processing replies even after a 10 second\n" 5490 "timeout. Marking the controller as unrecoverable!\n"); 5491 5492 goto out; 5493 } 5494 5495 if (mrioc->num_io_throttle_group != 5496 mrioc->facts.max_io_throttle_group) { 5497 ioc_err(mrioc, 5498 "max io throttle group doesn't match old(%d), new(%d)\n", 5499 mrioc->num_io_throttle_group, 5500 mrioc->facts.max_io_throttle_group); 5501 retval = -EPERM; 5502 goto out; 5503 } 5504 5505 mpi3mr_flush_delayed_cmd_lists(mrioc); 5506 mpi3mr_flush_drv_cmds(mrioc); 5507 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 5508 bitmap_clear(mrioc->removepend_bitmap, 0, 5509 mrioc->dev_handle_bitmap_bits); 5510 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD); 5511 mpi3mr_flush_host_io(mrioc); 5512 mpi3mr_cleanup_fwevt_list(mrioc); 5513 mpi3mr_invalidate_devhandles(mrioc); 5514 mpi3mr_free_enclosure_list(mrioc); 5515 5516 if (mrioc->prepare_for_reset) { 5517 mrioc->prepare_for_reset = 0; 5518 mrioc->prepare_for_reset_timeout_counter = 0; 5519 } 5520 mpi3mr_memset_buffers(mrioc); 5521 mpi3mr_release_diag_bufs(mrioc, 1); 5522 mrioc->fw_release_trigger_active = false; 5523 mrioc->trace_release_trigger_active = false; 5524 mrioc->snapdump_trigger_active = false; 5525 mpi3mr_set_trigger_data_in_all_hdb(mrioc, 5526 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0); 5527 5528 dprint_reset(mrioc, 5529 "soft_reset_handler: reinitializing the controller\n"); 5530 retval = mpi3mr_reinit_ioc(mrioc, 0); 5531 if (retval) { 5532 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n", 5533 mrioc->name, reset_reason); 5534 goto out; 5535 } 5536 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME); 5537 5538 out: 5539 if (!retval) { 5540 mrioc->diagsave_timeout = 0; 5541 mrioc->reset_in_progress = 0; 5542 scsi_unblock_requests(mrioc->shost); 5543 mrioc->pel_abort_requested = 0; 5544 if (mrioc->pel_enabled) { 5545 mrioc->pel_cmds.retry_count = 0; 5546 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds); 5547 } 5548 5549 mrioc->device_refresh_on = 0; 5550 5551 mrioc->ts_update_counter = 0; 5552 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 5553 if (mrioc->watchdog_work_q) 5554 queue_delayed_work(mrioc->watchdog_work_q, 5555 &mrioc->watchdog_work, 5556 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 5557 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 5558 mrioc->stop_bsgs = 0; 5559 if (mrioc->pel_enabled) 5560 atomic64_inc(&event_counter); 5561 } else { 5562 mpi3mr_issue_reset(mrioc, 5563 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5564 mrioc->device_refresh_on = 0; 5565 mrioc->unrecoverable = 1; 5566 mrioc->reset_in_progress = 0; 5567 scsi_unblock_requests(mrioc->shost); 5568 mrioc->stop_bsgs = 0; 5569 retval = -1; 5570 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 5571 } 5572 mrioc->prev_reset_result = retval; 5573 mutex_unlock(&mrioc->reset_mutex); 5574 ioc_info(mrioc, "controller reset is %s\n", 5575 ((retval == 0) ? "successful" : "failed")); 5576 return retval; 5577 } 5578 5579 /** 5580 * mpi3mr_post_cfg_req - Issue config requests and wait 5581 * @mrioc: Adapter instance reference 5582 * @cfg_req: Configuration request 5583 * @timeout: Timeout in seconds 5584 * @ioc_status: Pointer to return ioc status 5585 * 5586 * A generic function for posting MPI3 configuration request to 5587 * the firmware. This blocks for the completion of request for 5588 * timeout seconds and if the request times out this function 5589 * faults the controller with proper reason code. 5590 * 5591 * On successful completion of the request this function returns 5592 * appropriate ioc status from the firmware back to the caller. 5593 * 5594 * Return: 0 on success, non-zero on failure. 5595 */ 5596 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc, 5597 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status) 5598 { 5599 int retval = 0; 5600 5601 mutex_lock(&mrioc->cfg_cmds.mutex); 5602 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) { 5603 retval = -1; 5604 ioc_err(mrioc, "sending config request failed due to command in use\n"); 5605 mutex_unlock(&mrioc->cfg_cmds.mutex); 5606 goto out; 5607 } 5608 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING; 5609 mrioc->cfg_cmds.is_waiting = 1; 5610 mrioc->cfg_cmds.callback = NULL; 5611 mrioc->cfg_cmds.ioc_status = 0; 5612 mrioc->cfg_cmds.ioc_loginfo = 0; 5613 5614 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS); 5615 cfg_req->function = MPI3_FUNCTION_CONFIG; 5616 5617 init_completion(&mrioc->cfg_cmds.done); 5618 dprint_cfg_info(mrioc, "posting config request\n"); 5619 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5620 dprint_dump(cfg_req, sizeof(struct mpi3_config_request), 5621 "mpi3_cfg_req"); 5622 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1); 5623 if (retval) { 5624 ioc_err(mrioc, "posting config request failed\n"); 5625 goto out_unlock; 5626 } 5627 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ)); 5628 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) { 5629 mpi3mr_check_rh_fault_ioc(mrioc, 5630 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT); 5631 ioc_err(mrioc, "config request timed out\n"); 5632 retval = -1; 5633 goto out_unlock; 5634 } 5635 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5636 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS) 5637 dprint_cfg_err(mrioc, 5638 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n", 5639 *ioc_status, mrioc->cfg_cmds.ioc_loginfo); 5640 5641 out_unlock: 5642 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED; 5643 mutex_unlock(&mrioc->cfg_cmds.mutex); 5644 5645 out: 5646 return retval; 5647 } 5648 5649 /** 5650 * mpi3mr_process_cfg_req - config page request processor 5651 * @mrioc: Adapter instance reference 5652 * @cfg_req: Configuration request 5653 * @cfg_hdr: Configuration page header 5654 * @timeout: Timeout in seconds 5655 * @ioc_status: Pointer to return ioc status 5656 * @cfg_buf: Memory pointer to copy config page or header 5657 * @cfg_buf_sz: Size of the memory to get config page or header 5658 * 5659 * This is handler for config page read, write and config page 5660 * header read operations. 5661 * 5662 * This function expects the cfg_req to be populated with page 5663 * type, page number, action for the header read and with page 5664 * address for all other operations. 5665 * 5666 * The cfg_hdr can be passed as null for reading required header 5667 * details for read/write pages the cfg_hdr should point valid 5668 * configuration page header. 5669 * 5670 * This allocates dmaable memory based on the size of the config 5671 * buffer and set the SGE of the cfg_req. 5672 * 5673 * For write actions, the config page data has to be passed in 5674 * the cfg_buf and size of the data has to be mentioned in the 5675 * cfg_buf_sz. 5676 * 5677 * For read/header actions, on successful completion of the 5678 * request with successful ioc_status the data will be copied 5679 * into the cfg_buf limited to a minimum of actual page size and 5680 * cfg_buf_sz 5681 * 5682 * 5683 * Return: 0 on success, non-zero on failure. 5684 */ 5685 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc, 5686 struct mpi3_config_request *cfg_req, 5687 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status, 5688 void *cfg_buf, u32 cfg_buf_sz) 5689 { 5690 struct dma_memory_desc mem_desc; 5691 int retval = -1; 5692 u8 invalid_action = 0; 5693 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 5694 5695 memset(&mem_desc, 0, sizeof(struct dma_memory_desc)); 5696 5697 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER) 5698 mem_desc.size = sizeof(struct mpi3_config_page_header); 5699 else { 5700 if (!cfg_hdr) { 5701 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n", 5702 cfg_req->action, cfg_req->page_type, 5703 cfg_req->page_number); 5704 goto out; 5705 } 5706 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) { 5707 case MPI3_CONFIG_PAGEATTR_READ_ONLY: 5708 if (cfg_req->action 5709 != MPI3_CONFIG_ACTION_READ_CURRENT) 5710 invalid_action = 1; 5711 break; 5712 case MPI3_CONFIG_PAGEATTR_CHANGEABLE: 5713 if ((cfg_req->action == 5714 MPI3_CONFIG_ACTION_READ_PERSISTENT) || 5715 (cfg_req->action == 5716 MPI3_CONFIG_ACTION_WRITE_PERSISTENT)) 5717 invalid_action = 1; 5718 break; 5719 case MPI3_CONFIG_PAGEATTR_PERSISTENT: 5720 default: 5721 break; 5722 } 5723 if (invalid_action) { 5724 ioc_err(mrioc, 5725 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n", 5726 cfg_req->action, cfg_req->page_type, 5727 cfg_req->page_number, cfg_hdr->page_attribute); 5728 goto out; 5729 } 5730 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4; 5731 cfg_req->page_length = cfg_hdr->page_length; 5732 cfg_req->page_version = cfg_hdr->page_version; 5733 } 5734 5735 mem_desc.addr = dma_alloc_coherent(&mrioc->pdev->dev, 5736 mem_desc.size, &mem_desc.dma_addr, GFP_KERNEL); 5737 5738 if (!mem_desc.addr) 5739 return retval; 5740 5741 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size, 5742 mem_desc.dma_addr); 5743 5744 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) || 5745 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5746 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size, 5747 cfg_buf_sz)); 5748 dprint_cfg_info(mrioc, "config buffer to be written\n"); 5749 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5750 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5751 } 5752 5753 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status)) 5754 goto out; 5755 5756 retval = 0; 5757 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) && 5758 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) && 5759 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5760 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size, 5761 cfg_buf_sz)); 5762 dprint_cfg_info(mrioc, "config buffer read\n"); 5763 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5764 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5765 } 5766 5767 out: 5768 if (mem_desc.addr) { 5769 dma_free_coherent(&mrioc->pdev->dev, mem_desc.size, 5770 mem_desc.addr, mem_desc.dma_addr); 5771 mem_desc.addr = NULL; 5772 } 5773 5774 return retval; 5775 } 5776 5777 /** 5778 * mpi3mr_cfg_get_dev_pg0 - Read current device page0 5779 * @mrioc: Adapter instance reference 5780 * @ioc_status: Pointer to return ioc status 5781 * @dev_pg0: Pointer to return device page 0 5782 * @pg_sz: Size of the memory allocated to the page pointer 5783 * @form: The form to be used for addressing the page 5784 * @form_spec: Form specific information like device handle 5785 * 5786 * This is handler for config page read for a specific device 5787 * page0. The ioc_status has the controller returned ioc_status. 5788 * This routine doesn't check ioc_status to decide whether the 5789 * page read is success or not and it is the callers 5790 * responsibility. 5791 * 5792 * Return: 0 on success, non-zero on failure. 5793 */ 5794 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5795 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec) 5796 { 5797 struct mpi3_config_page_header cfg_hdr; 5798 struct mpi3_config_request cfg_req; 5799 u32 page_address; 5800 5801 memset(dev_pg0, 0, pg_sz); 5802 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5803 memset(&cfg_req, 0, sizeof(cfg_req)); 5804 5805 cfg_req.function = MPI3_FUNCTION_CONFIG; 5806 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5807 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE; 5808 cfg_req.page_number = 0; 5809 cfg_req.page_address = 0; 5810 5811 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5812 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5813 ioc_err(mrioc, "device page0 header read failed\n"); 5814 goto out_failed; 5815 } 5816 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5817 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n", 5818 *ioc_status); 5819 goto out_failed; 5820 } 5821 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5822 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) | 5823 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK)); 5824 cfg_req.page_address = cpu_to_le32(page_address); 5825 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5826 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) { 5827 ioc_err(mrioc, "device page0 read failed\n"); 5828 goto out_failed; 5829 } 5830 return 0; 5831 out_failed: 5832 return -1; 5833 } 5834 5835 5836 /** 5837 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0 5838 * @mrioc: Adapter instance reference 5839 * @ioc_status: Pointer to return ioc status 5840 * @phy_pg0: Pointer to return SAS Phy page 0 5841 * @pg_sz: Size of the memory allocated to the page pointer 5842 * @form: The form to be used for addressing the page 5843 * @form_spec: Form specific information like phy number 5844 * 5845 * This is handler for config page read for a specific SAS Phy 5846 * page0. The ioc_status has the controller returned ioc_status. 5847 * This routine doesn't check ioc_status to decide whether the 5848 * page read is success or not and it is the callers 5849 * responsibility. 5850 * 5851 * Return: 0 on success, non-zero on failure. 5852 */ 5853 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5854 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 5855 u32 form_spec) 5856 { 5857 struct mpi3_config_page_header cfg_hdr; 5858 struct mpi3_config_request cfg_req; 5859 u32 page_address; 5860 5861 memset(phy_pg0, 0, pg_sz); 5862 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5863 memset(&cfg_req, 0, sizeof(cfg_req)); 5864 5865 cfg_req.function = MPI3_FUNCTION_CONFIG; 5866 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5867 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5868 cfg_req.page_number = 0; 5869 cfg_req.page_address = 0; 5870 5871 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5872 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5873 ioc_err(mrioc, "sas phy page0 header read failed\n"); 5874 goto out_failed; 5875 } 5876 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5877 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n", 5878 *ioc_status); 5879 goto out_failed; 5880 } 5881 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5882 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5883 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5884 cfg_req.page_address = cpu_to_le32(page_address); 5885 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5886 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) { 5887 ioc_err(mrioc, "sas phy page0 read failed\n"); 5888 goto out_failed; 5889 } 5890 return 0; 5891 out_failed: 5892 return -1; 5893 } 5894 5895 /** 5896 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1 5897 * @mrioc: Adapter instance reference 5898 * @ioc_status: Pointer to return ioc status 5899 * @phy_pg1: Pointer to return SAS Phy page 1 5900 * @pg_sz: Size of the memory allocated to the page pointer 5901 * @form: The form to be used for addressing the page 5902 * @form_spec: Form specific information like phy number 5903 * 5904 * This is handler for config page read for a specific SAS Phy 5905 * page1. The ioc_status has the controller returned ioc_status. 5906 * This routine doesn't check ioc_status to decide whether the 5907 * page read is success or not and it is the callers 5908 * responsibility. 5909 * 5910 * Return: 0 on success, non-zero on failure. 5911 */ 5912 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5913 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 5914 u32 form_spec) 5915 { 5916 struct mpi3_config_page_header cfg_hdr; 5917 struct mpi3_config_request cfg_req; 5918 u32 page_address; 5919 5920 memset(phy_pg1, 0, pg_sz); 5921 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5922 memset(&cfg_req, 0, sizeof(cfg_req)); 5923 5924 cfg_req.function = MPI3_FUNCTION_CONFIG; 5925 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5926 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5927 cfg_req.page_number = 1; 5928 cfg_req.page_address = 0; 5929 5930 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5931 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5932 ioc_err(mrioc, "sas phy page1 header read failed\n"); 5933 goto out_failed; 5934 } 5935 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5936 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n", 5937 *ioc_status); 5938 goto out_failed; 5939 } 5940 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5941 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5942 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5943 cfg_req.page_address = cpu_to_le32(page_address); 5944 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5945 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) { 5946 ioc_err(mrioc, "sas phy page1 read failed\n"); 5947 goto out_failed; 5948 } 5949 return 0; 5950 out_failed: 5951 return -1; 5952 } 5953 5954 5955 /** 5956 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0 5957 * @mrioc: Adapter instance reference 5958 * @ioc_status: Pointer to return ioc status 5959 * @exp_pg0: Pointer to return SAS Expander page 0 5960 * @pg_sz: Size of the memory allocated to the page pointer 5961 * @form: The form to be used for addressing the page 5962 * @form_spec: Form specific information like device handle 5963 * 5964 * This is handler for config page read for a specific SAS 5965 * Expander page0. The ioc_status has the controller returned 5966 * ioc_status. This routine doesn't check ioc_status to decide 5967 * whether the page read is success or not and it is the callers 5968 * responsibility. 5969 * 5970 * Return: 0 on success, non-zero on failure. 5971 */ 5972 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5973 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 5974 u32 form_spec) 5975 { 5976 struct mpi3_config_page_header cfg_hdr; 5977 struct mpi3_config_request cfg_req; 5978 u32 page_address; 5979 5980 memset(exp_pg0, 0, pg_sz); 5981 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5982 memset(&cfg_req, 0, sizeof(cfg_req)); 5983 5984 cfg_req.function = MPI3_FUNCTION_CONFIG; 5985 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5986 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5987 cfg_req.page_number = 0; 5988 cfg_req.page_address = 0; 5989 5990 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5991 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5992 ioc_err(mrioc, "expander page0 header read failed\n"); 5993 goto out_failed; 5994 } 5995 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5996 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n", 5997 *ioc_status); 5998 goto out_failed; 5999 } 6000 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6001 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 6002 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 6003 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 6004 cfg_req.page_address = cpu_to_le32(page_address); 6005 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6006 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) { 6007 ioc_err(mrioc, "expander page0 read failed\n"); 6008 goto out_failed; 6009 } 6010 return 0; 6011 out_failed: 6012 return -1; 6013 } 6014 6015 /** 6016 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1 6017 * @mrioc: Adapter instance reference 6018 * @ioc_status: Pointer to return ioc status 6019 * @exp_pg1: Pointer to return SAS Expander page 1 6020 * @pg_sz: Size of the memory allocated to the page pointer 6021 * @form: The form to be used for addressing the page 6022 * @form_spec: Form specific information like phy number 6023 * 6024 * This is handler for config page read for a specific SAS 6025 * Expander page1. The ioc_status has the controller returned 6026 * ioc_status. This routine doesn't check ioc_status to decide 6027 * whether the page read is success or not and it is the callers 6028 * responsibility. 6029 * 6030 * Return: 0 on success, non-zero on failure. 6031 */ 6032 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 6033 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 6034 u32 form_spec) 6035 { 6036 struct mpi3_config_page_header cfg_hdr; 6037 struct mpi3_config_request cfg_req; 6038 u32 page_address; 6039 6040 memset(exp_pg1, 0, pg_sz); 6041 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6042 memset(&cfg_req, 0, sizeof(cfg_req)); 6043 6044 cfg_req.function = MPI3_FUNCTION_CONFIG; 6045 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6046 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 6047 cfg_req.page_number = 1; 6048 cfg_req.page_address = 0; 6049 6050 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6051 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6052 ioc_err(mrioc, "expander page1 header read failed\n"); 6053 goto out_failed; 6054 } 6055 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6056 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n", 6057 *ioc_status); 6058 goto out_failed; 6059 } 6060 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6061 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 6062 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 6063 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 6064 cfg_req.page_address = cpu_to_le32(page_address); 6065 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6066 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) { 6067 ioc_err(mrioc, "expander page1 read failed\n"); 6068 goto out_failed; 6069 } 6070 return 0; 6071 out_failed: 6072 return -1; 6073 } 6074 6075 /** 6076 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0 6077 * @mrioc: Adapter instance reference 6078 * @ioc_status: Pointer to return ioc status 6079 * @encl_pg0: Pointer to return Enclosure page 0 6080 * @pg_sz: Size of the memory allocated to the page pointer 6081 * @form: The form to be used for addressing the page 6082 * @form_spec: Form specific information like device handle 6083 * 6084 * This is handler for config page read for a specific Enclosure 6085 * page0. The ioc_status has the controller returned ioc_status. 6086 * This routine doesn't check ioc_status to decide whether the 6087 * page read is success or not and it is the callers 6088 * responsibility. 6089 * 6090 * Return: 0 on success, non-zero on failure. 6091 */ 6092 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 6093 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 6094 u32 form_spec) 6095 { 6096 struct mpi3_config_page_header cfg_hdr; 6097 struct mpi3_config_request cfg_req; 6098 u32 page_address; 6099 6100 memset(encl_pg0, 0, pg_sz); 6101 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6102 memset(&cfg_req, 0, sizeof(cfg_req)); 6103 6104 cfg_req.function = MPI3_FUNCTION_CONFIG; 6105 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6106 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE; 6107 cfg_req.page_number = 0; 6108 cfg_req.page_address = 0; 6109 6110 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6111 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6112 ioc_err(mrioc, "enclosure page0 header read failed\n"); 6113 goto out_failed; 6114 } 6115 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6116 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n", 6117 *ioc_status); 6118 goto out_failed; 6119 } 6120 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6121 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) | 6122 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK)); 6123 cfg_req.page_address = cpu_to_le32(page_address); 6124 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6125 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) { 6126 ioc_err(mrioc, "enclosure page0 read failed\n"); 6127 goto out_failed; 6128 } 6129 return 0; 6130 out_failed: 6131 return -1; 6132 } 6133 6134 6135 /** 6136 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0 6137 * @mrioc: Adapter instance reference 6138 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0 6139 * @pg_sz: Size of the memory allocated to the page pointer 6140 * 6141 * This is handler for config page read for the SAS IO Unit 6142 * page0. This routine checks ioc_status to decide whether the 6143 * page read is success or not. 6144 * 6145 * Return: 0 on success, non-zero on failure. 6146 */ 6147 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 6148 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz) 6149 { 6150 struct mpi3_config_page_header cfg_hdr; 6151 struct mpi3_config_request cfg_req; 6152 u16 ioc_status = 0; 6153 6154 memset(sas_io_unit_pg0, 0, pg_sz); 6155 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6156 memset(&cfg_req, 0, sizeof(cfg_req)); 6157 6158 cfg_req.function = MPI3_FUNCTION_CONFIG; 6159 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6160 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 6161 cfg_req.page_number = 0; 6162 cfg_req.page_address = 0; 6163 6164 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6165 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6166 ioc_err(mrioc, "sas io unit page0 header read failed\n"); 6167 goto out_failed; 6168 } 6169 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6170 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n", 6171 ioc_status); 6172 goto out_failed; 6173 } 6174 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6175 6176 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6177 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) { 6178 ioc_err(mrioc, "sas io unit page0 read failed\n"); 6179 goto out_failed; 6180 } 6181 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6182 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n", 6183 ioc_status); 6184 goto out_failed; 6185 } 6186 return 0; 6187 out_failed: 6188 return -1; 6189 } 6190 6191 /** 6192 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1 6193 * @mrioc: Adapter instance reference 6194 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1 6195 * @pg_sz: Size of the memory allocated to the page pointer 6196 * 6197 * This is handler for config page read for the SAS IO Unit 6198 * page1. This routine checks ioc_status to decide whether the 6199 * page read is success or not. 6200 * 6201 * Return: 0 on success, non-zero on failure. 6202 */ 6203 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 6204 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 6205 { 6206 struct mpi3_config_page_header cfg_hdr; 6207 struct mpi3_config_request cfg_req; 6208 u16 ioc_status = 0; 6209 6210 memset(sas_io_unit_pg1, 0, pg_sz); 6211 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6212 memset(&cfg_req, 0, sizeof(cfg_req)); 6213 6214 cfg_req.function = MPI3_FUNCTION_CONFIG; 6215 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6216 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 6217 cfg_req.page_number = 1; 6218 cfg_req.page_address = 0; 6219 6220 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6221 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6222 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 6223 goto out_failed; 6224 } 6225 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6226 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 6227 ioc_status); 6228 goto out_failed; 6229 } 6230 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6231 6232 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6233 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 6234 ioc_err(mrioc, "sas io unit page1 read failed\n"); 6235 goto out_failed; 6236 } 6237 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6238 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n", 6239 ioc_status); 6240 goto out_failed; 6241 } 6242 return 0; 6243 out_failed: 6244 return -1; 6245 } 6246 6247 /** 6248 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1 6249 * @mrioc: Adapter instance reference 6250 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write 6251 * @pg_sz: Size of the memory allocated to the page pointer 6252 * 6253 * This is handler for config page write for the SAS IO Unit 6254 * page1. This routine checks ioc_status to decide whether the 6255 * page read is success or not. This will modify both current 6256 * and persistent page. 6257 * 6258 * Return: 0 on success, non-zero on failure. 6259 */ 6260 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 6261 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 6262 { 6263 struct mpi3_config_page_header cfg_hdr; 6264 struct mpi3_config_request cfg_req; 6265 u16 ioc_status = 0; 6266 6267 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6268 memset(&cfg_req, 0, sizeof(cfg_req)); 6269 6270 cfg_req.function = MPI3_FUNCTION_CONFIG; 6271 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6272 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 6273 cfg_req.page_number = 1; 6274 cfg_req.page_address = 0; 6275 6276 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6277 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6278 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 6279 goto out_failed; 6280 } 6281 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6282 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 6283 ioc_status); 6284 goto out_failed; 6285 } 6286 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT; 6287 6288 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6289 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 6290 ioc_err(mrioc, "sas io unit page1 write current failed\n"); 6291 goto out_failed; 6292 } 6293 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6294 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n", 6295 ioc_status); 6296 goto out_failed; 6297 } 6298 6299 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT; 6300 6301 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6302 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 6303 ioc_err(mrioc, "sas io unit page1 write persistent failed\n"); 6304 goto out_failed; 6305 } 6306 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6307 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n", 6308 ioc_status); 6309 goto out_failed; 6310 } 6311 return 0; 6312 out_failed: 6313 return -1; 6314 } 6315 6316 /** 6317 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1 6318 * @mrioc: Adapter instance reference 6319 * @driver_pg1: Pointer to return Driver page 1 6320 * @pg_sz: Size of the memory allocated to the page pointer 6321 * 6322 * This is handler for config page read for the Driver page1. 6323 * This routine checks ioc_status to decide whether the page 6324 * read is success or not. 6325 * 6326 * Return: 0 on success, non-zero on failure. 6327 */ 6328 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 6329 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz) 6330 { 6331 struct mpi3_config_page_header cfg_hdr; 6332 struct mpi3_config_request cfg_req; 6333 u16 ioc_status = 0; 6334 6335 memset(driver_pg1, 0, pg_sz); 6336 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6337 memset(&cfg_req, 0, sizeof(cfg_req)); 6338 6339 cfg_req.function = MPI3_FUNCTION_CONFIG; 6340 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6341 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER; 6342 cfg_req.page_number = 1; 6343 cfg_req.page_address = 0; 6344 6345 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6346 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6347 ioc_err(mrioc, "driver page1 header read failed\n"); 6348 goto out_failed; 6349 } 6350 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6351 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n", 6352 ioc_status); 6353 goto out_failed; 6354 } 6355 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 6356 6357 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6358 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) { 6359 ioc_err(mrioc, "driver page1 read failed\n"); 6360 goto out_failed; 6361 } 6362 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6363 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n", 6364 ioc_status); 6365 goto out_failed; 6366 } 6367 return 0; 6368 out_failed: 6369 return -1; 6370 } 6371 6372 /** 6373 * mpi3mr_cfg_get_driver_pg2 - Read current driver page2 6374 * @mrioc: Adapter instance reference 6375 * @driver_pg2: Pointer to return driver page 2 6376 * @pg_sz: Size of the memory allocated to the page pointer 6377 * @page_action: Page action 6378 * 6379 * This is handler for config page read for the driver page2. 6380 * This routine checks ioc_status to decide whether the page 6381 * read is success or not. 6382 * 6383 * Return: 0 on success, non-zero on failure. 6384 */ 6385 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc, 6386 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_action) 6387 { 6388 struct mpi3_config_page_header cfg_hdr; 6389 struct mpi3_config_request cfg_req; 6390 u16 ioc_status = 0; 6391 6392 memset(driver_pg2, 0, pg_sz); 6393 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 6394 memset(&cfg_req, 0, sizeof(cfg_req)); 6395 6396 cfg_req.function = MPI3_FUNCTION_CONFIG; 6397 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 6398 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER; 6399 cfg_req.page_number = 2; 6400 cfg_req.page_address = 0; 6401 cfg_req.page_version = MPI3_DRIVER2_PAGEVERSION; 6402 6403 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 6404 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 6405 ioc_err(mrioc, "driver page2 header read failed\n"); 6406 goto out_failed; 6407 } 6408 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6409 ioc_err(mrioc, "driver page2 header read failed with\n" 6410 "ioc_status(0x%04x)\n", 6411 ioc_status); 6412 goto out_failed; 6413 } 6414 cfg_req.action = page_action; 6415 6416 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 6417 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg2, pg_sz)) { 6418 ioc_err(mrioc, "driver page2 read failed\n"); 6419 goto out_failed; 6420 } 6421 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 6422 ioc_err(mrioc, "driver page2 read failed with\n" 6423 "ioc_status(0x%04x)\n", 6424 ioc_status); 6425 goto out_failed; 6426 } 6427 return 0; 6428 out_failed: 6429 return -1; 6430 } 6431 6432