1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #include "mpi3mr.h" 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 13 static int 14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason); 15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc); 16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 17 struct mpi3_ioc_facts_data *facts_data); 18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 19 struct mpi3mr_drv_cmd *drv_cmd); 20 21 static int poll_queues; 22 module_param(poll_queues, int, 0444); 23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); 24 25 #if defined(writeq) && defined(CONFIG_64BIT) 26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 27 { 28 writeq(b, addr); 29 } 30 #else 31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 32 { 33 __u64 data_out = b; 34 35 writel((u32)(data_out), addr); 36 writel((u32)(data_out >> 32), (addr + 4)); 37 } 38 #endif 39 40 static inline bool 41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q) 42 { 43 u16 pi, ci, max_entries; 44 bool is_qfull = false; 45 46 pi = op_req_q->pi; 47 ci = READ_ONCE(op_req_q->ci); 48 max_entries = op_req_q->num_requests; 49 50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 51 is_qfull = true; 52 53 return is_qfull; 54 } 55 56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc) 57 { 58 u16 i, max_vectors; 59 60 max_vectors = mrioc->intr_info_count; 61 62 for (i = 0; i < max_vectors; i++) 63 synchronize_irq(pci_irq_vector(mrioc->pdev, i)); 64 } 65 66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc) 67 { 68 mrioc->intr_enabled = 0; 69 mpi3mr_sync_irqs(mrioc); 70 } 71 72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc) 73 { 74 mrioc->intr_enabled = 1; 75 } 76 77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) 78 { 79 u16 i; 80 81 mpi3mr_ioc_disable_intr(mrioc); 82 83 if (!mrioc->intr_info) 84 return; 85 86 for (i = 0; i < mrioc->intr_info_count; i++) 87 free_irq(pci_irq_vector(mrioc->pdev, i), 88 (mrioc->intr_info + i)); 89 90 kfree(mrioc->intr_info); 91 mrioc->intr_info = NULL; 92 mrioc->intr_info_count = 0; 93 mrioc->is_intr_info_set = false; 94 pci_free_irq_vectors(mrioc->pdev); 95 } 96 97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 98 dma_addr_t dma_addr) 99 { 100 struct mpi3_sge_common *sgel = paddr; 101 102 sgel->flags = flags; 103 sgel->length = cpu_to_le32(length); 104 sgel->address = cpu_to_le64(dma_addr); 105 } 106 107 void mpi3mr_build_zero_len_sge(void *paddr) 108 { 109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 110 111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 112 } 113 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 115 dma_addr_t phys_addr) 116 { 117 if (!phys_addr) 118 return NULL; 119 120 if ((phys_addr < mrioc->reply_buf_dma) || 121 (phys_addr > mrioc->reply_buf_dma_max_address)) 122 return NULL; 123 124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma); 125 } 126 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 128 dma_addr_t phys_addr) 129 { 130 if (!phys_addr) 131 return NULL; 132 133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma); 134 } 135 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, 137 u64 reply_dma) 138 { 139 u32 old_idx = 0; 140 unsigned long flags; 141 142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags); 143 old_idx = mrioc->reply_free_queue_host_index; 144 mrioc->reply_free_queue_host_index = ( 145 (mrioc->reply_free_queue_host_index == 146 (mrioc->reply_free_qsz - 1)) ? 0 : 147 (mrioc->reply_free_queue_host_index + 1)); 148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma); 149 writel(mrioc->reply_free_queue_host_index, 150 &mrioc->sysif_regs->reply_free_host_index); 151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags); 152 } 153 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 155 u64 sense_buf_dma) 156 { 157 u32 old_idx = 0; 158 unsigned long flags; 159 160 spin_lock_irqsave(&mrioc->sbq_lock, flags); 161 old_idx = mrioc->sbq_host_index; 162 mrioc->sbq_host_index = ((mrioc->sbq_host_index == 163 (mrioc->sense_buf_q_sz - 1)) ? 0 : 164 (mrioc->sbq_host_index + 1)); 165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma); 166 writel(mrioc->sbq_host_index, 167 &mrioc->sysif_regs->sense_buffer_free_host_index); 168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags); 169 } 170 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc, 172 struct mpi3_event_notification_reply *event_reply) 173 { 174 char *desc = NULL; 175 u16 event; 176 177 event = event_reply->event; 178 179 switch (event) { 180 case MPI3_EVENT_LOG_DATA: 181 desc = "Log Data"; 182 break; 183 case MPI3_EVENT_CHANGE: 184 desc = "Event Change"; 185 break; 186 case MPI3_EVENT_GPIO_INTERRUPT: 187 desc = "GPIO Interrupt"; 188 break; 189 case MPI3_EVENT_CABLE_MGMT: 190 desc = "Cable Management"; 191 break; 192 case MPI3_EVENT_ENERGY_PACK_CHANGE: 193 desc = "Energy Pack Change"; 194 break; 195 case MPI3_EVENT_DEVICE_ADDED: 196 { 197 struct mpi3_device_page0 *event_data = 198 (struct mpi3_device_page0 *)event_reply->event_data; 199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n", 200 event_data->dev_handle, event_data->device_form); 201 return; 202 } 203 case MPI3_EVENT_DEVICE_INFO_CHANGED: 204 { 205 struct mpi3_device_page0 *event_data = 206 (struct mpi3_device_page0 *)event_reply->event_data; 207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n", 208 event_data->dev_handle, event_data->device_form); 209 return; 210 } 211 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 212 { 213 struct mpi3_event_data_device_status_change *event_data = 214 (struct mpi3_event_data_device_status_change *)event_reply->event_data; 215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n", 216 event_data->dev_handle, event_data->reason_code); 217 return; 218 } 219 case MPI3_EVENT_SAS_DISCOVERY: 220 { 221 struct mpi3_event_data_sas_discovery *event_data = 222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data; 223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n", 224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 225 "start" : "stop", 226 le32_to_cpu(event_data->discovery_status)); 227 return; 228 } 229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 230 desc = "SAS Broadcast Primitive"; 231 break; 232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 233 desc = "SAS Notify Primitive"; 234 break; 235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 236 desc = "SAS Init Device Status Change"; 237 break; 238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 239 desc = "SAS Init Table Overflow"; 240 break; 241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 242 desc = "SAS Topology Change List"; 243 break; 244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 245 desc = "Enclosure Device Status Change"; 246 break; 247 case MPI3_EVENT_ENCL_DEVICE_ADDED: 248 desc = "Enclosure Added"; 249 break; 250 case MPI3_EVENT_HARD_RESET_RECEIVED: 251 desc = "Hard Reset Received"; 252 break; 253 case MPI3_EVENT_SAS_PHY_COUNTER: 254 desc = "SAS PHY Counter"; 255 break; 256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 257 desc = "SAS Device Discovery Error"; 258 break; 259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 260 desc = "PCIE Topology Change List"; 261 break; 262 case MPI3_EVENT_PCIE_ENUMERATION: 263 { 264 struct mpi3_event_data_pcie_enumeration *event_data = 265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data; 266 ioc_info(mrioc, "PCIE Enumeration: (%s)", 267 (event_data->reason_code == 268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop"); 269 if (event_data->enumeration_status) 270 ioc_info(mrioc, "enumeration_status(0x%08x)\n", 271 le32_to_cpu(event_data->enumeration_status)); 272 return; 273 } 274 case MPI3_EVENT_PREPARE_FOR_RESET: 275 desc = "Prepare For Reset"; 276 break; 277 } 278 279 if (!desc) 280 return; 281 282 ioc_info(mrioc, "%s\n", desc); 283 } 284 285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc, 286 struct mpi3_default_reply *def_reply) 287 { 288 struct mpi3_event_notification_reply *event_reply = 289 (struct mpi3_event_notification_reply *)def_reply; 290 291 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count); 292 mpi3mr_print_event_data(mrioc, event_reply); 293 mpi3mr_os_handle_events(mrioc, event_reply); 294 } 295 296 static struct mpi3mr_drv_cmd * 297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, 298 struct mpi3_default_reply *def_reply) 299 { 300 u16 idx; 301 302 switch (host_tag) { 303 case MPI3MR_HOSTTAG_INITCMDS: 304 return &mrioc->init_cmds; 305 case MPI3MR_HOSTTAG_CFG_CMDS: 306 return &mrioc->cfg_cmds; 307 case MPI3MR_HOSTTAG_BSG_CMDS: 308 return &mrioc->bsg_cmds; 309 case MPI3MR_HOSTTAG_BLK_TMS: 310 return &mrioc->host_tm_cmds; 311 case MPI3MR_HOSTTAG_PEL_ABORT: 312 return &mrioc->pel_abort_cmd; 313 case MPI3MR_HOSTTAG_PEL_WAIT: 314 return &mrioc->pel_cmds; 315 case MPI3MR_HOSTTAG_TRANSPORT_CMDS: 316 return &mrioc->transport_cmds; 317 case MPI3MR_HOSTTAG_INVALID: 318 if (def_reply && def_reply->function == 319 MPI3_FUNCTION_EVENT_NOTIFICATION) 320 mpi3mr_handle_events(mrioc, def_reply); 321 return NULL; 322 default: 323 break; 324 } 325 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 326 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) { 327 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 328 return &mrioc->dev_rmhs_cmds[idx]; 329 } 330 331 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 332 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 333 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 334 return &mrioc->evtack_cmds[idx]; 335 } 336 337 return NULL; 338 } 339 340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, 341 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma) 342 { 343 u16 reply_desc_type, host_tag = 0; 344 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 345 u32 ioc_loginfo = 0; 346 struct mpi3_status_reply_descriptor *status_desc; 347 struct mpi3_address_reply_descriptor *addr_desc; 348 struct mpi3_success_reply_descriptor *success_desc; 349 struct mpi3_default_reply *def_reply = NULL; 350 struct mpi3mr_drv_cmd *cmdptr = NULL; 351 struct mpi3_scsi_io_reply *scsi_reply; 352 u8 *sense_buf = NULL; 353 354 *reply_dma = 0; 355 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) & 356 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 357 switch (reply_desc_type) { 358 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 359 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc; 360 host_tag = le16_to_cpu(status_desc->host_tag); 361 ioc_status = le16_to_cpu(status_desc->ioc_status); 362 if (ioc_status & 363 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 364 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info); 365 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 366 break; 367 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 368 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc; 369 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address); 370 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma); 371 if (!def_reply) 372 goto out; 373 host_tag = le16_to_cpu(def_reply->host_tag); 374 ioc_status = le16_to_cpu(def_reply->ioc_status); 375 if (ioc_status & 376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 377 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info); 378 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 379 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) { 380 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply; 381 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc, 382 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 383 } 384 break; 385 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 386 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc; 387 host_tag = le16_to_cpu(success_desc->host_tag); 388 break; 389 default: 390 break; 391 } 392 393 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply); 394 if (cmdptr) { 395 if (cmdptr->state & MPI3MR_CMD_PENDING) { 396 cmdptr->state |= MPI3MR_CMD_COMPLETE; 397 cmdptr->ioc_loginfo = ioc_loginfo; 398 cmdptr->ioc_status = ioc_status; 399 cmdptr->state &= ~MPI3MR_CMD_PENDING; 400 if (def_reply) { 401 cmdptr->state |= MPI3MR_CMD_REPLY_VALID; 402 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply, 403 mrioc->reply_sz); 404 } 405 if (sense_buf && cmdptr->sensebuf) { 406 cmdptr->is_sense = 1; 407 memcpy(cmdptr->sensebuf, sense_buf, 408 MPI3MR_SENSE_BUF_SZ); 409 } 410 if (cmdptr->is_waiting) { 411 complete(&cmdptr->done); 412 cmdptr->is_waiting = 0; 413 } else if (cmdptr->callback) 414 cmdptr->callback(mrioc, cmdptr); 415 } 416 } 417 out: 418 if (sense_buf) 419 mpi3mr_repost_sense_buf(mrioc, 420 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 421 } 422 423 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc) 424 { 425 u32 exp_phase = mrioc->admin_reply_ephase; 426 u32 admin_reply_ci = mrioc->admin_reply_ci; 427 u32 num_admin_replies = 0; 428 u64 reply_dma = 0; 429 struct mpi3_default_reply_descriptor *reply_desc; 430 431 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1)) 432 return 0; 433 434 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 435 admin_reply_ci; 436 437 if ((le16_to_cpu(reply_desc->reply_flags) & 438 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 439 atomic_dec(&mrioc->admin_reply_q_in_use); 440 return 0; 441 } 442 443 do { 444 if (mrioc->unrecoverable) 445 break; 446 447 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci); 448 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma); 449 if (reply_dma) 450 mpi3mr_repost_reply_buf(mrioc, reply_dma); 451 num_admin_replies++; 452 if (++admin_reply_ci == mrioc->num_admin_replies) { 453 admin_reply_ci = 0; 454 exp_phase ^= 1; 455 } 456 reply_desc = 457 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 458 admin_reply_ci; 459 if ((le16_to_cpu(reply_desc->reply_flags) & 460 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 461 break; 462 } while (1); 463 464 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 465 mrioc->admin_reply_ci = admin_reply_ci; 466 mrioc->admin_reply_ephase = exp_phase; 467 atomic_dec(&mrioc->admin_reply_q_in_use); 468 469 return num_admin_replies; 470 } 471 472 /** 473 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to 474 * queue's consumer index from operational reply descriptor queue. 475 * @op_reply_q: op_reply_qinfo object 476 * @reply_ci: operational reply descriptor's queue consumer index 477 * 478 * Returns reply descriptor frame address 479 */ 480 static inline struct mpi3_default_reply_descriptor * 481 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) 482 { 483 void *segment_base_addr; 484 struct segments *segments = op_reply_q->q_segments; 485 struct mpi3_default_reply_descriptor *reply_desc = NULL; 486 487 segment_base_addr = 488 segments[reply_ci / op_reply_q->segment_qd].segment; 489 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr + 490 (reply_ci % op_reply_q->segment_qd); 491 return reply_desc; 492 } 493 494 /** 495 * mpi3mr_process_op_reply_q - Operational reply queue handler 496 * @mrioc: Adapter instance reference 497 * @op_reply_q: Operational reply queue info 498 * 499 * Checks the specific operational reply queue and drains the 500 * reply queue entries until the queue is empty and process the 501 * individual reply descriptors. 502 * 503 * Return: 0 if queue is already processed,or number of reply 504 * descriptors processed. 505 */ 506 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 507 struct op_reply_qinfo *op_reply_q) 508 { 509 struct op_req_qinfo *op_req_q; 510 u32 exp_phase; 511 u32 reply_ci; 512 u32 num_op_reply = 0; 513 u64 reply_dma = 0; 514 struct mpi3_default_reply_descriptor *reply_desc; 515 u16 req_q_idx = 0, reply_qidx; 516 517 reply_qidx = op_reply_q->qid - 1; 518 519 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1)) 520 return 0; 521 522 exp_phase = op_reply_q->ephase; 523 reply_ci = op_reply_q->ci; 524 525 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 526 if ((le16_to_cpu(reply_desc->reply_flags) & 527 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 528 atomic_dec(&op_reply_q->in_use); 529 return 0; 530 } 531 532 do { 533 if (mrioc->unrecoverable) 534 break; 535 536 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1; 537 op_req_q = &mrioc->req_qinfo[req_q_idx]; 538 539 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci)); 540 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma, 541 reply_qidx); 542 atomic_dec(&op_reply_q->pend_ios); 543 if (reply_dma) 544 mpi3mr_repost_reply_buf(mrioc, reply_dma); 545 num_op_reply++; 546 547 if (++reply_ci == op_reply_q->num_replies) { 548 reply_ci = 0; 549 exp_phase ^= 1; 550 } 551 552 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 553 554 if ((le16_to_cpu(reply_desc->reply_flags) & 555 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 556 break; 557 #ifndef CONFIG_PREEMPT_RT 558 /* 559 * Exit completion loop to avoid CPU lockup 560 * Ensure remaining completion happens from threaded ISR. 561 */ 562 if (num_op_reply > mrioc->max_host_ios) { 563 op_reply_q->enable_irq_poll = true; 564 break; 565 } 566 #endif 567 } while (1); 568 569 writel(reply_ci, 570 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 571 op_reply_q->ci = reply_ci; 572 op_reply_q->ephase = exp_phase; 573 574 atomic_dec(&op_reply_q->in_use); 575 return num_op_reply; 576 } 577 578 /** 579 * mpi3mr_blk_mq_poll - Operational reply queue handler 580 * @shost: SCSI Host reference 581 * @queue_num: Request queue number (w.r.t OS it is hardware context number) 582 * 583 * Checks the specific operational reply queue and drains the 584 * reply queue entries until the queue is empty and process the 585 * individual reply descriptors. 586 * 587 * Return: 0 if queue is already processed,or number of reply 588 * descriptors processed. 589 */ 590 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 591 { 592 int num_entries = 0; 593 struct mpi3mr_ioc *mrioc; 594 595 mrioc = (struct mpi3mr_ioc *)shost->hostdata; 596 597 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset || 598 mrioc->unrecoverable)) 599 return 0; 600 601 num_entries = mpi3mr_process_op_reply_q(mrioc, 602 &mrioc->op_reply_qinfo[queue_num]); 603 604 return num_entries; 605 } 606 607 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) 608 { 609 struct mpi3mr_intr_info *intr_info = privdata; 610 struct mpi3mr_ioc *mrioc; 611 u16 midx; 612 u32 num_admin_replies = 0, num_op_reply = 0; 613 614 if (!intr_info) 615 return IRQ_NONE; 616 617 mrioc = intr_info->mrioc; 618 619 if (!mrioc->intr_enabled) 620 return IRQ_NONE; 621 622 midx = intr_info->msix_index; 623 624 if (!midx) 625 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc); 626 if (intr_info->op_reply_q) 627 num_op_reply = mpi3mr_process_op_reply_q(mrioc, 628 intr_info->op_reply_q); 629 630 if (num_admin_replies || num_op_reply) 631 return IRQ_HANDLED; 632 else 633 return IRQ_NONE; 634 } 635 636 #ifndef CONFIG_PREEMPT_RT 637 638 static irqreturn_t mpi3mr_isr(int irq, void *privdata) 639 { 640 struct mpi3mr_intr_info *intr_info = privdata; 641 int ret; 642 643 if (!intr_info) 644 return IRQ_NONE; 645 646 /* Call primary ISR routine */ 647 ret = mpi3mr_isr_primary(irq, privdata); 648 649 /* 650 * If more IOs are expected, schedule IRQ polling thread. 651 * Otherwise exit from ISR. 652 */ 653 if (!intr_info->op_reply_q) 654 return ret; 655 656 if (!intr_info->op_reply_q->enable_irq_poll || 657 !atomic_read(&intr_info->op_reply_q->pend_ios)) 658 return ret; 659 660 disable_irq_nosync(intr_info->os_irq); 661 662 return IRQ_WAKE_THREAD; 663 } 664 665 /** 666 * mpi3mr_isr_poll - Reply queue polling routine 667 * @irq: IRQ 668 * @privdata: Interrupt info 669 * 670 * poll for pending I/O completions in a loop until pending I/Os 671 * present or controller queue depth I/Os are processed. 672 * 673 * Return: IRQ_NONE or IRQ_HANDLED 674 */ 675 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) 676 { 677 struct mpi3mr_intr_info *intr_info = privdata; 678 struct mpi3mr_ioc *mrioc; 679 u16 midx; 680 u32 num_op_reply = 0; 681 682 if (!intr_info || !intr_info->op_reply_q) 683 return IRQ_NONE; 684 685 mrioc = intr_info->mrioc; 686 midx = intr_info->msix_index; 687 688 /* Poll for pending IOs completions */ 689 do { 690 if (!mrioc->intr_enabled || mrioc->unrecoverable) 691 break; 692 693 if (!midx) 694 mpi3mr_process_admin_reply_q(mrioc); 695 if (intr_info->op_reply_q) 696 num_op_reply += 697 mpi3mr_process_op_reply_q(mrioc, 698 intr_info->op_reply_q); 699 700 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP); 701 702 } while (atomic_read(&intr_info->op_reply_q->pend_ios) && 703 (num_op_reply < mrioc->max_host_ios)); 704 705 intr_info->op_reply_q->enable_irq_poll = false; 706 enable_irq(intr_info->os_irq); 707 708 return IRQ_HANDLED; 709 } 710 711 #endif 712 713 /** 714 * mpi3mr_request_irq - Request IRQ and register ISR 715 * @mrioc: Adapter instance reference 716 * @index: IRQ vector index 717 * 718 * Request threaded ISR with primary ISR and secondary 719 * 720 * Return: 0 on success and non zero on failures. 721 */ 722 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) 723 { 724 struct pci_dev *pdev = mrioc->pdev; 725 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index; 726 int retval = 0; 727 728 intr_info->mrioc = mrioc; 729 intr_info->msix_index = index; 730 intr_info->op_reply_q = NULL; 731 732 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", 733 mrioc->driver_name, mrioc->id, index); 734 735 #ifndef CONFIG_PREEMPT_RT 736 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, 737 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); 738 #else 739 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary, 740 NULL, IRQF_SHARED, intr_info->name, intr_info); 741 #endif 742 if (retval) { 743 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", 744 intr_info->name, pci_irq_vector(pdev, index)); 745 return retval; 746 } 747 748 intr_info->os_irq = pci_irq_vector(pdev, index); 749 return retval; 750 } 751 752 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors) 753 { 754 if (!mrioc->requested_poll_qcount) 755 return; 756 757 /* Reserved for Admin and Default Queue */ 758 if (max_vectors > 2 && 759 (mrioc->requested_poll_qcount < max_vectors - 2)) { 760 ioc_info(mrioc, 761 "enabled polled queues (%d) msix (%d)\n", 762 mrioc->requested_poll_qcount, max_vectors); 763 } else { 764 ioc_info(mrioc, 765 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n", 766 mrioc->requested_poll_qcount, max_vectors); 767 mrioc->requested_poll_qcount = 0; 768 } 769 } 770 771 /** 772 * mpi3mr_setup_isr - Setup ISR for the controller 773 * @mrioc: Adapter instance reference 774 * @setup_one: Request one IRQ or more 775 * 776 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR 777 * 778 * Return: 0 on success and non zero on failures. 779 */ 780 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) 781 { 782 unsigned int irq_flags = PCI_IRQ_MSIX; 783 int max_vectors, min_vec; 784 int retval; 785 int i; 786 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 }; 787 788 if (mrioc->is_intr_info_set) 789 return 0; 790 791 mpi3mr_cleanup_isr(mrioc); 792 793 if (setup_one || reset_devices) { 794 max_vectors = 1; 795 retval = pci_alloc_irq_vectors(mrioc->pdev, 796 1, max_vectors, irq_flags); 797 if (retval < 0) { 798 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 799 retval); 800 goto out_failed; 801 } 802 } else { 803 max_vectors = 804 min_t(int, mrioc->cpu_count + 1 + 805 mrioc->requested_poll_qcount, mrioc->msix_count); 806 807 mpi3mr_calc_poll_queues(mrioc, max_vectors); 808 809 ioc_info(mrioc, 810 "MSI-X vectors supported: %d, no of cores: %d,", 811 mrioc->msix_count, mrioc->cpu_count); 812 ioc_info(mrioc, 813 "MSI-x vectors requested: %d poll_queues %d\n", 814 max_vectors, mrioc->requested_poll_qcount); 815 816 desc.post_vectors = mrioc->requested_poll_qcount; 817 min_vec = desc.pre_vectors + desc.post_vectors; 818 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 819 820 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev, 821 min_vec, max_vectors, irq_flags, &desc); 822 823 if (retval < 0) { 824 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 825 retval); 826 goto out_failed; 827 } 828 829 830 /* 831 * If only one MSI-x is allocated, then MSI-x 0 will be shared 832 * between Admin queue and operational queue 833 */ 834 if (retval == min_vec) 835 mrioc->op_reply_q_offset = 0; 836 else if (retval != (max_vectors)) { 837 ioc_info(mrioc, 838 "allocated vectors (%d) are less than configured (%d)\n", 839 retval, max_vectors); 840 } 841 842 max_vectors = retval; 843 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0; 844 845 mpi3mr_calc_poll_queues(mrioc, max_vectors); 846 847 } 848 849 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors, 850 GFP_KERNEL); 851 if (!mrioc->intr_info) { 852 retval = -ENOMEM; 853 pci_free_irq_vectors(mrioc->pdev); 854 goto out_failed; 855 } 856 for (i = 0; i < max_vectors; i++) { 857 retval = mpi3mr_request_irq(mrioc, i); 858 if (retval) { 859 mrioc->intr_info_count = i; 860 goto out_failed; 861 } 862 } 863 if (reset_devices || !setup_one) 864 mrioc->is_intr_info_set = true; 865 mrioc->intr_info_count = max_vectors; 866 mpi3mr_ioc_enable_intr(mrioc); 867 return 0; 868 869 out_failed: 870 mpi3mr_cleanup_isr(mrioc); 871 872 return retval; 873 } 874 875 static const struct { 876 enum mpi3mr_iocstate value; 877 char *name; 878 } mrioc_states[] = { 879 { MRIOC_STATE_READY, "ready" }, 880 { MRIOC_STATE_FAULT, "fault" }, 881 { MRIOC_STATE_RESET, "reset" }, 882 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 883 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 884 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" }, 885 }; 886 887 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 888 { 889 int i; 890 char *name = NULL; 891 892 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) { 893 if (mrioc_states[i].value == mrioc_state) { 894 name = mrioc_states[i].name; 895 break; 896 } 897 } 898 return name; 899 } 900 901 /* Reset reason to name mapper structure*/ 902 static const struct { 903 enum mpi3mr_reset_reason value; 904 char *name; 905 } mpi3mr_reset_reason_codes[] = { 906 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 907 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 908 { MPI3MR_RESET_FROM_APP, "application invocation" }, 909 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 910 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 911 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" }, 912 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 913 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 914 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 915 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 916 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 917 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 918 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 919 { 920 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 921 "create request queue timeout" 922 }, 923 { 924 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 925 "create reply queue timeout" 926 }, 927 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 928 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 929 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 930 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 931 { 932 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 933 "component image activation timeout" 934 }, 935 { 936 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 937 "get package version timeout" 938 }, 939 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 940 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 941 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" }, 942 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"}, 943 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" }, 944 }; 945 946 /** 947 * mpi3mr_reset_rc_name - get reset reason code name 948 * @reason_code: reset reason code value 949 * 950 * Map reset reason to an NULL terminated ASCII string 951 * 952 * Return: name corresponding to reset reason value or NULL. 953 */ 954 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 955 { 956 int i; 957 char *name = NULL; 958 959 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) { 960 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 961 name = mpi3mr_reset_reason_codes[i].name; 962 break; 963 } 964 } 965 return name; 966 } 967 968 /* Reset type to name mapper structure*/ 969 static const struct { 970 u16 reset_type; 971 char *name; 972 } mpi3mr_reset_types[] = { 973 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 974 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 975 }; 976 977 /** 978 * mpi3mr_reset_type_name - get reset type name 979 * @reset_type: reset type value 980 * 981 * Map reset type to an NULL terminated ASCII string 982 * 983 * Return: name corresponding to reset type value or NULL. 984 */ 985 static const char *mpi3mr_reset_type_name(u16 reset_type) 986 { 987 int i; 988 char *name = NULL; 989 990 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) { 991 if (mpi3mr_reset_types[i].reset_type == reset_type) { 992 name = mpi3mr_reset_types[i].name; 993 break; 994 } 995 } 996 return name; 997 } 998 999 /** 1000 * mpi3mr_print_fault_info - Display fault information 1001 * @mrioc: Adapter instance reference 1002 * 1003 * Display the controller fault information if there is a 1004 * controller fault. 1005 * 1006 * Return: Nothing. 1007 */ 1008 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc) 1009 { 1010 u32 ioc_status, code, code1, code2, code3; 1011 1012 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1013 1014 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1015 code = readl(&mrioc->sysif_regs->fault); 1016 code1 = readl(&mrioc->sysif_regs->fault_info[0]); 1017 code2 = readl(&mrioc->sysif_regs->fault_info[1]); 1018 code3 = readl(&mrioc->sysif_regs->fault_info[2]); 1019 1020 ioc_info(mrioc, 1021 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n", 1022 code, code1, code2, code3); 1023 } 1024 } 1025 1026 /** 1027 * mpi3mr_get_iocstate - Get IOC State 1028 * @mrioc: Adapter instance reference 1029 * 1030 * Return a proper IOC state enum based on the IOC status and 1031 * IOC configuration and unrcoverable state of the controller. 1032 * 1033 * Return: Current IOC state. 1034 */ 1035 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc) 1036 { 1037 u32 ioc_status, ioc_config; 1038 u8 ready, enabled; 1039 1040 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1041 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1042 1043 if (mrioc->unrecoverable) 1044 return MRIOC_STATE_UNRECOVERABLE; 1045 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1046 return MRIOC_STATE_FAULT; 1047 1048 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1049 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1050 1051 if (ready && enabled) 1052 return MRIOC_STATE_READY; 1053 if ((!ready) && (!enabled)) 1054 return MRIOC_STATE_RESET; 1055 if ((!ready) && (enabled)) 1056 return MRIOC_STATE_BECOMING_READY; 1057 1058 return MRIOC_STATE_RESET_REQUESTED; 1059 } 1060 1061 /** 1062 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma 1063 * @mrioc: Adapter instance reference 1064 * 1065 * Free the DMA memory allocated for IOCTL handling purpose. 1066 1067 * 1068 * Return: None 1069 */ 1070 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc) 1071 { 1072 struct dma_memory_desc *mem_desc; 1073 u16 i; 1074 1075 if (!mrioc->ioctl_dma_pool) 1076 return; 1077 1078 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) { 1079 mem_desc = &mrioc->ioctl_sge[i]; 1080 if (mem_desc->addr) { 1081 dma_pool_free(mrioc->ioctl_dma_pool, 1082 mem_desc->addr, 1083 mem_desc->dma_addr); 1084 mem_desc->addr = NULL; 1085 } 1086 } 1087 dma_pool_destroy(mrioc->ioctl_dma_pool); 1088 mrioc->ioctl_dma_pool = NULL; 1089 mem_desc = &mrioc->ioctl_chain_sge; 1090 1091 if (mem_desc->addr) { 1092 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 1093 mem_desc->addr, mem_desc->dma_addr); 1094 mem_desc->addr = NULL; 1095 } 1096 mem_desc = &mrioc->ioctl_resp_sge; 1097 if (mem_desc->addr) { 1098 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 1099 mem_desc->addr, mem_desc->dma_addr); 1100 mem_desc->addr = NULL; 1101 } 1102 1103 mrioc->ioctl_sges_allocated = false; 1104 } 1105 1106 /** 1107 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma 1108 * @mrioc: Adapter instance reference 1109 1110 * 1111 * This function allocates dmaable memory required to handle the 1112 * application issued MPI3 IOCTL requests. 1113 * 1114 * Return: None 1115 */ 1116 static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc) 1117 1118 { 1119 struct dma_memory_desc *mem_desc; 1120 u16 i; 1121 1122 mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool", 1123 &mrioc->pdev->dev, 1124 MPI3MR_IOCTL_SGE_SIZE, 1125 MPI3MR_PAGE_SIZE_4K, 0); 1126 1127 if (!mrioc->ioctl_dma_pool) { 1128 ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n"); 1129 goto out_failed; 1130 } 1131 1132 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) { 1133 mem_desc = &mrioc->ioctl_sge[i]; 1134 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE; 1135 mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool, 1136 GFP_KERNEL, 1137 &mem_desc->dma_addr); 1138 if (!mem_desc->addr) 1139 goto out_failed; 1140 } 1141 1142 mem_desc = &mrioc->ioctl_chain_sge; 1143 mem_desc->size = MPI3MR_PAGE_SIZE_4K; 1144 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 1145 mem_desc->size, 1146 &mem_desc->dma_addr, 1147 GFP_KERNEL); 1148 if (!mem_desc->addr) 1149 goto out_failed; 1150 1151 mem_desc = &mrioc->ioctl_resp_sge; 1152 mem_desc->size = MPI3MR_PAGE_SIZE_4K; 1153 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 1154 mem_desc->size, 1155 &mem_desc->dma_addr, 1156 GFP_KERNEL); 1157 if (!mem_desc->addr) 1158 goto out_failed; 1159 1160 mrioc->ioctl_sges_allocated = true; 1161 1162 return; 1163 out_failed: 1164 ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n" 1165 "from the applications, application interface for MPT command is disabled\n"); 1166 mpi3mr_free_ioctl_dma_memory(mrioc); 1167 } 1168 1169 /** 1170 * mpi3mr_clear_reset_history - clear reset history 1171 * @mrioc: Adapter instance reference 1172 * 1173 * Write the reset history bit in IOC status to clear the bit, 1174 * if it is already set. 1175 * 1176 * Return: Nothing. 1177 */ 1178 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) 1179 { 1180 u32 ioc_status; 1181 1182 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1183 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1184 writel(ioc_status, &mrioc->sysif_regs->ioc_status); 1185 } 1186 1187 /** 1188 * mpi3mr_issue_and_process_mur - Message unit Reset handler 1189 * @mrioc: Adapter instance reference 1190 * @reset_reason: Reset reason code 1191 * 1192 * Issue Message unit Reset to the controller and wait for it to 1193 * be complete. 1194 * 1195 * Return: 0 on success, -1 on failure. 1196 */ 1197 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, 1198 u32 reset_reason) 1199 { 1200 u32 ioc_config, timeout, ioc_status; 1201 int retval = -1; 1202 1203 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); 1204 if (mrioc->unrecoverable) { 1205 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n"); 1206 return retval; 1207 } 1208 mpi3mr_clear_reset_history(mrioc); 1209 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1210 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1211 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1212 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1213 1214 timeout = MPI3MR_MUR_TIMEOUT * 10; 1215 do { 1216 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1217 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1218 mpi3mr_clear_reset_history(mrioc); 1219 break; 1220 } 1221 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1222 mpi3mr_print_fault_info(mrioc); 1223 break; 1224 } 1225 msleep(100); 1226 } while (--timeout); 1227 1228 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1229 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1230 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1231 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1232 retval = 0; 1233 1234 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n", 1235 (!retval) ? "successful" : "failed", ioc_status, ioc_config); 1236 return retval; 1237 } 1238 1239 /** 1240 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters 1241 * during reset/resume 1242 * @mrioc: Adapter instance reference 1243 * 1244 * Return zero if the new IOCFacts parameters value is compatible with 1245 * older values else return -EPERM 1246 */ 1247 static int 1248 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc) 1249 { 1250 unsigned long *removepend_bitmap; 1251 1252 if (mrioc->facts.reply_sz > mrioc->reply_sz) { 1253 ioc_err(mrioc, 1254 "cannot increase reply size from %d to %d\n", 1255 mrioc->reply_sz, mrioc->facts.reply_sz); 1256 return -EPERM; 1257 } 1258 1259 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) { 1260 ioc_err(mrioc, 1261 "cannot reduce number of operational reply queues from %d to %d\n", 1262 mrioc->num_op_reply_q, 1263 mrioc->facts.max_op_reply_q); 1264 return -EPERM; 1265 } 1266 1267 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) { 1268 ioc_err(mrioc, 1269 "cannot reduce number of operational request queues from %d to %d\n", 1270 mrioc->num_op_req_q, mrioc->facts.max_op_req_q); 1271 return -EPERM; 1272 } 1273 1274 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512)) 1275 ioc_err(mrioc, "Warning: The maximum data transfer length\n" 1276 "\tchanged after reset: previous(%d), new(%d),\n" 1277 "the driver cannot change this at run time\n", 1278 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length); 1279 1280 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities & 1281 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) 1282 ioc_err(mrioc, 1283 "critical error: multipath capability is enabled at the\n" 1284 "\tcontroller while sas transport support is enabled at the\n" 1285 "\tdriver, please reboot the system or reload the driver\n"); 1286 1287 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) { 1288 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle, 1289 GFP_KERNEL); 1290 if (!removepend_bitmap) { 1291 ioc_err(mrioc, 1292 "failed to increase removepend_bitmap bits from %d to %d\n", 1293 mrioc->dev_handle_bitmap_bits, 1294 mrioc->facts.max_devhandle); 1295 return -EPERM; 1296 } 1297 bitmap_free(mrioc->removepend_bitmap); 1298 mrioc->removepend_bitmap = removepend_bitmap; 1299 ioc_info(mrioc, 1300 "increased bits of dev_handle_bitmap from %d to %d\n", 1301 mrioc->dev_handle_bitmap_bits, 1302 mrioc->facts.max_devhandle); 1303 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 1304 } 1305 1306 return 0; 1307 } 1308 1309 /** 1310 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1311 * @mrioc: Adapter instance reference 1312 * 1313 * Set Enable IOC bit in IOC configuration register and wait for 1314 * the controller to become ready. 1315 * 1316 * Return: 0 on success, appropriate error on failure. 1317 */ 1318 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc) 1319 { 1320 u32 ioc_config, ioc_status, timeout, host_diagnostic; 1321 int retval = 0; 1322 enum mpi3mr_iocstate ioc_state; 1323 u64 base_info; 1324 1325 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1326 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1327 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information); 1328 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n", 1329 ioc_status, ioc_config, base_info); 1330 1331 /*The timeout value is in 2sec unit, changing it to seconds*/ 1332 mrioc->ready_timeout = 1333 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 1334 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 1335 1336 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout); 1337 1338 ioc_state = mpi3mr_get_iocstate(mrioc); 1339 ioc_info(mrioc, "controller is in %s state during detection\n", 1340 mpi3mr_iocstate_name(ioc_state)); 1341 1342 if (ioc_state == MRIOC_STATE_BECOMING_READY || 1343 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 1344 timeout = mrioc->ready_timeout * 10; 1345 do { 1346 msleep(100); 1347 } while (--timeout); 1348 1349 if (!pci_device_is_present(mrioc->pdev)) { 1350 mrioc->unrecoverable = 1; 1351 ioc_err(mrioc, 1352 "controller is not present while waiting to reset\n"); 1353 retval = -1; 1354 goto out_device_not_present; 1355 } 1356 1357 ioc_state = mpi3mr_get_iocstate(mrioc); 1358 ioc_info(mrioc, 1359 "controller is in %s state after waiting to reset\n", 1360 mpi3mr_iocstate_name(ioc_state)); 1361 } 1362 1363 if (ioc_state == MRIOC_STATE_READY) { 1364 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n"); 1365 retval = mpi3mr_issue_and_process_mur(mrioc, 1366 MPI3MR_RESET_FROM_BRINGUP); 1367 ioc_state = mpi3mr_get_iocstate(mrioc); 1368 if (retval) 1369 ioc_err(mrioc, 1370 "message unit reset failed with error %d current state %s\n", 1371 retval, mpi3mr_iocstate_name(ioc_state)); 1372 } 1373 if (ioc_state != MRIOC_STATE_RESET) { 1374 if (ioc_state == MRIOC_STATE_FAULT) { 1375 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 1376 mpi3mr_print_fault_info(mrioc); 1377 do { 1378 host_diagnostic = 1379 readl(&mrioc->sysif_regs->host_diagnostic); 1380 if (!(host_diagnostic & 1381 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 1382 break; 1383 if (!pci_device_is_present(mrioc->pdev)) { 1384 mrioc->unrecoverable = 1; 1385 ioc_err(mrioc, "controller is not present at the bringup\n"); 1386 goto out_device_not_present; 1387 } 1388 msleep(100); 1389 } while (--timeout); 1390 } 1391 mpi3mr_print_fault_info(mrioc); 1392 ioc_info(mrioc, "issuing soft reset to bring to reset state\n"); 1393 retval = mpi3mr_issue_reset(mrioc, 1394 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 1395 MPI3MR_RESET_FROM_BRINGUP); 1396 if (retval) { 1397 ioc_err(mrioc, 1398 "soft reset failed with error %d\n", retval); 1399 goto out_failed; 1400 } 1401 } 1402 ioc_state = mpi3mr_get_iocstate(mrioc); 1403 if (ioc_state != MRIOC_STATE_RESET) { 1404 ioc_err(mrioc, 1405 "cannot bring controller to reset state, current state: %s\n", 1406 mpi3mr_iocstate_name(ioc_state)); 1407 goto out_failed; 1408 } 1409 mpi3mr_clear_reset_history(mrioc); 1410 retval = mpi3mr_setup_admin_qpair(mrioc); 1411 if (retval) { 1412 ioc_err(mrioc, "failed to setup admin queues: error %d\n", 1413 retval); 1414 goto out_failed; 1415 } 1416 1417 ioc_info(mrioc, "bringing controller to ready state\n"); 1418 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1419 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1420 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1421 1422 timeout = mrioc->ready_timeout * 10; 1423 do { 1424 ioc_state = mpi3mr_get_iocstate(mrioc); 1425 if (ioc_state == MRIOC_STATE_READY) { 1426 ioc_info(mrioc, 1427 "successfully transitioned to %s state\n", 1428 mpi3mr_iocstate_name(ioc_state)); 1429 return 0; 1430 } 1431 if (!pci_device_is_present(mrioc->pdev)) { 1432 mrioc->unrecoverable = 1; 1433 ioc_err(mrioc, 1434 "controller is not present at the bringup\n"); 1435 retval = -1; 1436 goto out_device_not_present; 1437 } 1438 msleep(100); 1439 } while (--timeout); 1440 1441 out_failed: 1442 ioc_state = mpi3mr_get_iocstate(mrioc); 1443 ioc_err(mrioc, 1444 "failed to bring to ready state, current state: %s\n", 1445 mpi3mr_iocstate_name(ioc_state)); 1446 out_device_not_present: 1447 return retval; 1448 } 1449 1450 /** 1451 * mpi3mr_soft_reset_success - Check softreset is success or not 1452 * @ioc_status: IOC status register value 1453 * @ioc_config: IOC config register value 1454 * 1455 * Check whether the soft reset is successful or not based on 1456 * IOC status and IOC config register values. 1457 * 1458 * Return: True when the soft reset is success, false otherwise. 1459 */ 1460 static inline bool 1461 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config) 1462 { 1463 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1464 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1465 return true; 1466 return false; 1467 } 1468 1469 /** 1470 * mpi3mr_diagfault_success - Check diag fault is success or not 1471 * @mrioc: Adapter reference 1472 * @ioc_status: IOC status register value 1473 * 1474 * Check whether the controller hit diag reset fault code. 1475 * 1476 * Return: True when there is diag fault, false otherwise. 1477 */ 1478 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc, 1479 u32 ioc_status) 1480 { 1481 u32 fault; 1482 1483 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1484 return false; 1485 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 1486 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) { 1487 mpi3mr_print_fault_info(mrioc); 1488 return true; 1489 } 1490 return false; 1491 } 1492 1493 /** 1494 * mpi3mr_set_diagsave - Set diag save bit for snapdump 1495 * @mrioc: Adapter reference 1496 * 1497 * Set diag save bit in IOC configuration register to enable 1498 * snapdump. 1499 * 1500 * Return: Nothing. 1501 */ 1502 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) 1503 { 1504 u32 ioc_config; 1505 1506 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1507 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 1508 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1509 } 1510 1511 /** 1512 * mpi3mr_issue_reset - Issue reset to the controller 1513 * @mrioc: Adapter reference 1514 * @reset_type: Reset type 1515 * @reset_reason: Reset reason code 1516 * 1517 * Unlock the host diagnostic registers and write the specific 1518 * reset type to that, wait for reset acknowledgment from the 1519 * controller, if the reset is not successful retry for the 1520 * predefined number of times. 1521 * 1522 * Return: 0 on success, non-zero on failure. 1523 */ 1524 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, 1525 u32 reset_reason) 1526 { 1527 int retval = -1; 1528 u8 unlock_retry_count = 0; 1529 u32 host_diagnostic, ioc_status, ioc_config; 1530 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1531 1532 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 1533 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 1534 return retval; 1535 if (mrioc->unrecoverable) 1536 return retval; 1537 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 1538 retval = 0; 1539 return retval; 1540 } 1541 1542 ioc_info(mrioc, "%s reset due to %s(0x%x)\n", 1543 mpi3mr_reset_type_name(reset_type), 1544 mpi3mr_reset_rc_name(reset_reason), reset_reason); 1545 1546 mpi3mr_clear_reset_history(mrioc); 1547 do { 1548 ioc_info(mrioc, 1549 "Write magic sequence to unlock host diag register (retry=%d)\n", 1550 ++unlock_retry_count); 1551 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 1552 ioc_err(mrioc, 1553 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n", 1554 mpi3mr_reset_type_name(reset_type), 1555 host_diagnostic); 1556 mrioc->unrecoverable = 1; 1557 return retval; 1558 } 1559 1560 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH, 1561 &mrioc->sysif_regs->write_sequence); 1562 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST, 1563 &mrioc->sysif_regs->write_sequence); 1564 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1565 &mrioc->sysif_regs->write_sequence); 1566 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD, 1567 &mrioc->sysif_regs->write_sequence); 1568 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH, 1569 &mrioc->sysif_regs->write_sequence); 1570 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH, 1571 &mrioc->sysif_regs->write_sequence); 1572 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH, 1573 &mrioc->sysif_regs->write_sequence); 1574 usleep_range(1000, 1100); 1575 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 1576 ioc_info(mrioc, 1577 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 1578 unlock_retry_count, host_diagnostic); 1579 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 1580 1581 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1582 writel(host_diagnostic | reset_type, 1583 &mrioc->sysif_regs->host_diagnostic); 1584 switch (reset_type) { 1585 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET: 1586 do { 1587 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1588 ioc_config = 1589 readl(&mrioc->sysif_regs->ioc_configuration); 1590 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1591 && mpi3mr_soft_reset_success(ioc_status, ioc_config) 1592 ) { 1593 mpi3mr_clear_reset_history(mrioc); 1594 retval = 0; 1595 break; 1596 } 1597 msleep(100); 1598 } while (--timeout); 1599 mpi3mr_print_fault_info(mrioc); 1600 break; 1601 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT: 1602 do { 1603 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1604 if (mpi3mr_diagfault_success(mrioc, ioc_status)) { 1605 retval = 0; 1606 break; 1607 } 1608 msleep(100); 1609 } while (--timeout); 1610 break; 1611 default: 1612 break; 1613 } 1614 1615 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1616 &mrioc->sysif_regs->write_sequence); 1617 1618 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1619 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1620 ioc_info(mrioc, 1621 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n", 1622 (!retval)?"successful":"failed", ioc_status, 1623 ioc_config); 1624 if (retval) 1625 mrioc->unrecoverable = 1; 1626 return retval; 1627 } 1628 1629 /** 1630 * mpi3mr_admin_request_post - Post request to admin queue 1631 * @mrioc: Adapter reference 1632 * @admin_req: MPI3 request 1633 * @admin_req_sz: Request size 1634 * @ignore_reset: Ignore reset in process 1635 * 1636 * Post the MPI3 request into admin request queue and 1637 * inform the controller, if the queue is full return 1638 * appropriate error. 1639 * 1640 * Return: 0 on success, non-zero on failure. 1641 */ 1642 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1643 u16 admin_req_sz, u8 ignore_reset) 1644 { 1645 u16 areq_pi = 0, areq_ci = 0, max_entries = 0; 1646 int retval = 0; 1647 unsigned long flags; 1648 u8 *areq_entry; 1649 1650 if (mrioc->unrecoverable) { 1651 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__); 1652 return -EFAULT; 1653 } 1654 1655 spin_lock_irqsave(&mrioc->admin_req_lock, flags); 1656 areq_pi = mrioc->admin_req_pi; 1657 areq_ci = mrioc->admin_req_ci; 1658 max_entries = mrioc->num_admin_req; 1659 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 1660 (areq_pi == (max_entries - 1)))) { 1661 ioc_err(mrioc, "AdminReqQ full condition detected\n"); 1662 retval = -EAGAIN; 1663 goto out; 1664 } 1665 if (!ignore_reset && mrioc->reset_in_progress) { 1666 ioc_err(mrioc, "AdminReqQ submit reset in progress\n"); 1667 retval = -EAGAIN; 1668 goto out; 1669 } 1670 areq_entry = (u8 *)mrioc->admin_req_base + 1671 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ); 1672 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ); 1673 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz); 1674 1675 if (++areq_pi == max_entries) 1676 areq_pi = 0; 1677 mrioc->admin_req_pi = areq_pi; 1678 1679 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 1680 1681 out: 1682 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags); 1683 1684 return retval; 1685 } 1686 1687 /** 1688 * mpi3mr_free_op_req_q_segments - free request memory segments 1689 * @mrioc: Adapter instance reference 1690 * @q_idx: operational request queue index 1691 * 1692 * Free memory segments allocated for operational request queue 1693 * 1694 * Return: Nothing. 1695 */ 1696 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1697 { 1698 u16 j; 1699 int size; 1700 struct segments *segments; 1701 1702 segments = mrioc->req_qinfo[q_idx].q_segments; 1703 if (!segments) 1704 return; 1705 1706 if (mrioc->enable_segqueue) { 1707 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1708 if (mrioc->req_qinfo[q_idx].q_segment_list) { 1709 dma_free_coherent(&mrioc->pdev->dev, 1710 MPI3MR_MAX_SEG_LIST_SIZE, 1711 mrioc->req_qinfo[q_idx].q_segment_list, 1712 mrioc->req_qinfo[q_idx].q_segment_list_dma); 1713 mrioc->req_qinfo[q_idx].q_segment_list = NULL; 1714 } 1715 } else 1716 size = mrioc->req_qinfo[q_idx].segment_qd * 1717 mrioc->facts.op_req_sz; 1718 1719 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) { 1720 if (!segments[j].segment) 1721 continue; 1722 dma_free_coherent(&mrioc->pdev->dev, 1723 size, segments[j].segment, segments[j].segment_dma); 1724 segments[j].segment = NULL; 1725 } 1726 kfree(mrioc->req_qinfo[q_idx].q_segments); 1727 mrioc->req_qinfo[q_idx].q_segments = NULL; 1728 mrioc->req_qinfo[q_idx].qid = 0; 1729 } 1730 1731 /** 1732 * mpi3mr_free_op_reply_q_segments - free reply memory segments 1733 * @mrioc: Adapter instance reference 1734 * @q_idx: operational reply queue index 1735 * 1736 * Free memory segments allocated for operational reply queue 1737 * 1738 * Return: Nothing. 1739 */ 1740 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1741 { 1742 u16 j; 1743 int size; 1744 struct segments *segments; 1745 1746 segments = mrioc->op_reply_qinfo[q_idx].q_segments; 1747 if (!segments) 1748 return; 1749 1750 if (mrioc->enable_segqueue) { 1751 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1752 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) { 1753 dma_free_coherent(&mrioc->pdev->dev, 1754 MPI3MR_MAX_SEG_LIST_SIZE, 1755 mrioc->op_reply_qinfo[q_idx].q_segment_list, 1756 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma); 1757 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 1758 } 1759 } else 1760 size = mrioc->op_reply_qinfo[q_idx].segment_qd * 1761 mrioc->op_reply_desc_sz; 1762 1763 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) { 1764 if (!segments[j].segment) 1765 continue; 1766 dma_free_coherent(&mrioc->pdev->dev, 1767 size, segments[j].segment, segments[j].segment_dma); 1768 segments[j].segment = NULL; 1769 } 1770 1771 kfree(mrioc->op_reply_qinfo[q_idx].q_segments); 1772 mrioc->op_reply_qinfo[q_idx].q_segments = NULL; 1773 mrioc->op_reply_qinfo[q_idx].qid = 0; 1774 } 1775 1776 /** 1777 * mpi3mr_delete_op_reply_q - delete operational reply queue 1778 * @mrioc: Adapter instance reference 1779 * @qidx: operational reply queue index 1780 * 1781 * Delete operatinal reply queue by issuing MPI request 1782 * through admin queue. 1783 * 1784 * Return: 0 on success, non-zero on failure. 1785 */ 1786 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1787 { 1788 struct mpi3_delete_reply_queue_request delq_req; 1789 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1790 int retval = 0; 1791 u16 reply_qid = 0, midx; 1792 1793 reply_qid = op_reply_q->qid; 1794 1795 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1796 1797 if (!reply_qid) { 1798 retval = -1; 1799 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n"); 1800 goto out; 1801 } 1802 1803 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- : 1804 mrioc->active_poll_qcount--; 1805 1806 memset(&delq_req, 0, sizeof(delq_req)); 1807 mutex_lock(&mrioc->init_cmds.mutex); 1808 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1809 retval = -1; 1810 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n"); 1811 mutex_unlock(&mrioc->init_cmds.mutex); 1812 goto out; 1813 } 1814 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1815 mrioc->init_cmds.is_waiting = 1; 1816 mrioc->init_cmds.callback = NULL; 1817 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1818 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 1819 delq_req.queue_id = cpu_to_le16(reply_qid); 1820 1821 init_completion(&mrioc->init_cmds.done); 1822 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req), 1823 1); 1824 if (retval) { 1825 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n"); 1826 goto out_unlock; 1827 } 1828 wait_for_completion_timeout(&mrioc->init_cmds.done, 1829 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1830 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1831 ioc_err(mrioc, "delete reply queue timed out\n"); 1832 mpi3mr_check_rh_fault_ioc(mrioc, 1833 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 1834 retval = -1; 1835 goto out_unlock; 1836 } 1837 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1838 != MPI3_IOCSTATUS_SUCCESS) { 1839 ioc_err(mrioc, 1840 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1841 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1842 mrioc->init_cmds.ioc_loginfo); 1843 retval = -1; 1844 goto out_unlock; 1845 } 1846 mrioc->intr_info[midx].op_reply_q = NULL; 1847 1848 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1849 out_unlock: 1850 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1851 mutex_unlock(&mrioc->init_cmds.mutex); 1852 out: 1853 1854 return retval; 1855 } 1856 1857 /** 1858 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool 1859 * @mrioc: Adapter instance reference 1860 * @qidx: request queue index 1861 * 1862 * Allocate segmented memory pools for operational reply 1863 * queue. 1864 * 1865 * Return: 0 on success, non-zero on failure. 1866 */ 1867 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1868 { 1869 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1870 int i, size; 1871 u64 *q_segment_list_entry = NULL; 1872 struct segments *segments; 1873 1874 if (mrioc->enable_segqueue) { 1875 op_reply_q->segment_qd = 1876 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz; 1877 1878 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1879 1880 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1881 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma, 1882 GFP_KERNEL); 1883 if (!op_reply_q->q_segment_list) 1884 return -ENOMEM; 1885 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list; 1886 } else { 1887 op_reply_q->segment_qd = op_reply_q->num_replies; 1888 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz; 1889 } 1890 1891 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies, 1892 op_reply_q->segment_qd); 1893 1894 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments, 1895 sizeof(struct segments), GFP_KERNEL); 1896 if (!op_reply_q->q_segments) 1897 return -ENOMEM; 1898 1899 segments = op_reply_q->q_segments; 1900 for (i = 0; i < op_reply_q->num_segments; i++) { 1901 segments[i].segment = 1902 dma_alloc_coherent(&mrioc->pdev->dev, 1903 size, &segments[i].segment_dma, GFP_KERNEL); 1904 if (!segments[i].segment) 1905 return -ENOMEM; 1906 if (mrioc->enable_segqueue) 1907 q_segment_list_entry[i] = 1908 (unsigned long)segments[i].segment_dma; 1909 } 1910 1911 return 0; 1912 } 1913 1914 /** 1915 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool. 1916 * @mrioc: Adapter instance reference 1917 * @qidx: request queue index 1918 * 1919 * Allocate segmented memory pools for operational request 1920 * queue. 1921 * 1922 * Return: 0 on success, non-zero on failure. 1923 */ 1924 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1925 { 1926 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 1927 int i, size; 1928 u64 *q_segment_list_entry = NULL; 1929 struct segments *segments; 1930 1931 if (mrioc->enable_segqueue) { 1932 op_req_q->segment_qd = 1933 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz; 1934 1935 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1936 1937 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1938 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma, 1939 GFP_KERNEL); 1940 if (!op_req_q->q_segment_list) 1941 return -ENOMEM; 1942 q_segment_list_entry = (u64 *)op_req_q->q_segment_list; 1943 1944 } else { 1945 op_req_q->segment_qd = op_req_q->num_requests; 1946 size = op_req_q->num_requests * mrioc->facts.op_req_sz; 1947 } 1948 1949 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests, 1950 op_req_q->segment_qd); 1951 1952 op_req_q->q_segments = kcalloc(op_req_q->num_segments, 1953 sizeof(struct segments), GFP_KERNEL); 1954 if (!op_req_q->q_segments) 1955 return -ENOMEM; 1956 1957 segments = op_req_q->q_segments; 1958 for (i = 0; i < op_req_q->num_segments; i++) { 1959 segments[i].segment = 1960 dma_alloc_coherent(&mrioc->pdev->dev, 1961 size, &segments[i].segment_dma, GFP_KERNEL); 1962 if (!segments[i].segment) 1963 return -ENOMEM; 1964 if (mrioc->enable_segqueue) 1965 q_segment_list_entry[i] = 1966 (unsigned long)segments[i].segment_dma; 1967 } 1968 1969 return 0; 1970 } 1971 1972 /** 1973 * mpi3mr_create_op_reply_q - create operational reply queue 1974 * @mrioc: Adapter instance reference 1975 * @qidx: operational reply queue index 1976 * 1977 * Create operatinal reply queue by issuing MPI request 1978 * through admin queue. 1979 * 1980 * Return: 0 on success, non-zero on failure. 1981 */ 1982 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1983 { 1984 struct mpi3_create_reply_queue_request create_req; 1985 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1986 int retval = 0; 1987 u16 reply_qid = 0, midx; 1988 1989 reply_qid = op_reply_q->qid; 1990 1991 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1992 1993 if (reply_qid) { 1994 retval = -1; 1995 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n", 1996 reply_qid); 1997 1998 return retval; 1999 } 2000 2001 reply_qid = qidx + 1; 2002 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 2003 if ((mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) && 2004 !mrioc->pdev->revision) 2005 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K; 2006 op_reply_q->ci = 0; 2007 op_reply_q->ephase = 1; 2008 atomic_set(&op_reply_q->pend_ios, 0); 2009 atomic_set(&op_reply_q->in_use, 0); 2010 op_reply_q->enable_irq_poll = false; 2011 2012 if (!op_reply_q->q_segments) { 2013 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx); 2014 if (retval) { 2015 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 2016 goto out; 2017 } 2018 } 2019 2020 memset(&create_req, 0, sizeof(create_req)); 2021 mutex_lock(&mrioc->init_cmds.mutex); 2022 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2023 retval = -1; 2024 ioc_err(mrioc, "CreateRepQ: Init command is in use\n"); 2025 goto out_unlock; 2026 } 2027 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2028 mrioc->init_cmds.is_waiting = 1; 2029 mrioc->init_cmds.callback = NULL; 2030 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2031 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 2032 create_req.queue_id = cpu_to_le16(reply_qid); 2033 2034 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount)) 2035 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE; 2036 else 2037 op_reply_q->qtype = MPI3MR_POLL_QUEUE; 2038 2039 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) { 2040 create_req.flags = 2041 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 2042 create_req.msix_index = 2043 cpu_to_le16(mrioc->intr_info[midx].msix_index); 2044 } else { 2045 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1); 2046 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n", 2047 reply_qid, midx); 2048 if (!mrioc->active_poll_qcount) 2049 disable_irq_nosync(pci_irq_vector(mrioc->pdev, 2050 mrioc->intr_info_count - 1)); 2051 } 2052 2053 if (mrioc->enable_segqueue) { 2054 create_req.flags |= 2055 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2056 create_req.base_address = cpu_to_le64( 2057 op_reply_q->q_segment_list_dma); 2058 } else 2059 create_req.base_address = cpu_to_le64( 2060 op_reply_q->q_segments[0].segment_dma); 2061 2062 create_req.size = cpu_to_le16(op_reply_q->num_replies); 2063 2064 init_completion(&mrioc->init_cmds.done); 2065 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2066 sizeof(create_req), 1); 2067 if (retval) { 2068 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n"); 2069 goto out_unlock; 2070 } 2071 wait_for_completion_timeout(&mrioc->init_cmds.done, 2072 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2073 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2074 ioc_err(mrioc, "create reply queue timed out\n"); 2075 mpi3mr_check_rh_fault_ioc(mrioc, 2076 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 2077 retval = -1; 2078 goto out_unlock; 2079 } 2080 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2081 != MPI3_IOCSTATUS_SUCCESS) { 2082 ioc_err(mrioc, 2083 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2084 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2085 mrioc->init_cmds.ioc_loginfo); 2086 retval = -1; 2087 goto out_unlock; 2088 } 2089 op_reply_q->qid = reply_qid; 2090 if (midx < mrioc->intr_info_count) 2091 mrioc->intr_info[midx].op_reply_q = op_reply_q; 2092 2093 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ : 2094 mrioc->active_poll_qcount++; 2095 2096 out_unlock: 2097 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2098 mutex_unlock(&mrioc->init_cmds.mutex); 2099 out: 2100 2101 return retval; 2102 } 2103 2104 /** 2105 * mpi3mr_create_op_req_q - create operational request queue 2106 * @mrioc: Adapter instance reference 2107 * @idx: operational request queue index 2108 * @reply_qid: Reply queue ID 2109 * 2110 * Create operatinal request queue by issuing MPI request 2111 * through admin queue. 2112 * 2113 * Return: 0 on success, non-zero on failure. 2114 */ 2115 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, 2116 u16 reply_qid) 2117 { 2118 struct mpi3_create_request_queue_request create_req; 2119 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx; 2120 int retval = 0; 2121 u16 req_qid = 0; 2122 2123 req_qid = op_req_q->qid; 2124 2125 if (req_qid) { 2126 retval = -1; 2127 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n", 2128 req_qid); 2129 2130 return retval; 2131 } 2132 req_qid = idx + 1; 2133 2134 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD; 2135 op_req_q->ci = 0; 2136 op_req_q->pi = 0; 2137 op_req_q->reply_qid = reply_qid; 2138 spin_lock_init(&op_req_q->q_lock); 2139 2140 if (!op_req_q->q_segments) { 2141 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx); 2142 if (retval) { 2143 mpi3mr_free_op_req_q_segments(mrioc, idx); 2144 goto out; 2145 } 2146 } 2147 2148 memset(&create_req, 0, sizeof(create_req)); 2149 mutex_lock(&mrioc->init_cmds.mutex); 2150 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2151 retval = -1; 2152 ioc_err(mrioc, "CreateReqQ: Init command is in use\n"); 2153 goto out_unlock; 2154 } 2155 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2156 mrioc->init_cmds.is_waiting = 1; 2157 mrioc->init_cmds.callback = NULL; 2158 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2159 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 2160 create_req.queue_id = cpu_to_le16(req_qid); 2161 if (mrioc->enable_segqueue) { 2162 create_req.flags = 2163 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2164 create_req.base_address = cpu_to_le64( 2165 op_req_q->q_segment_list_dma); 2166 } else 2167 create_req.base_address = cpu_to_le64( 2168 op_req_q->q_segments[0].segment_dma); 2169 create_req.reply_queue_id = cpu_to_le16(reply_qid); 2170 create_req.size = cpu_to_le16(op_req_q->num_requests); 2171 2172 init_completion(&mrioc->init_cmds.done); 2173 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2174 sizeof(create_req), 1); 2175 if (retval) { 2176 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n"); 2177 goto out_unlock; 2178 } 2179 wait_for_completion_timeout(&mrioc->init_cmds.done, 2180 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2181 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2182 ioc_err(mrioc, "create request queue timed out\n"); 2183 mpi3mr_check_rh_fault_ioc(mrioc, 2184 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 2185 retval = -1; 2186 goto out_unlock; 2187 } 2188 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2189 != MPI3_IOCSTATUS_SUCCESS) { 2190 ioc_err(mrioc, 2191 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2192 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2193 mrioc->init_cmds.ioc_loginfo); 2194 retval = -1; 2195 goto out_unlock; 2196 } 2197 op_req_q->qid = req_qid; 2198 2199 out_unlock: 2200 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2201 mutex_unlock(&mrioc->init_cmds.mutex); 2202 out: 2203 2204 return retval; 2205 } 2206 2207 /** 2208 * mpi3mr_create_op_queues - create operational queue pairs 2209 * @mrioc: Adapter instance reference 2210 * 2211 * Allocate memory for operational queue meta data and call 2212 * create request and reply queue functions. 2213 * 2214 * Return: 0 on success, non-zero on failures. 2215 */ 2216 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) 2217 { 2218 int retval = 0; 2219 u16 num_queues = 0, i = 0, msix_count_op_q = 1; 2220 2221 num_queues = min_t(int, mrioc->facts.max_op_reply_q, 2222 mrioc->facts.max_op_req_q); 2223 2224 msix_count_op_q = 2225 mrioc->intr_info_count - mrioc->op_reply_q_offset; 2226 if (!mrioc->num_queues) 2227 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q); 2228 /* 2229 * During reset set the num_queues to the number of queues 2230 * that was set before the reset. 2231 */ 2232 num_queues = mrioc->num_op_reply_q ? 2233 mrioc->num_op_reply_q : mrioc->num_queues; 2234 ioc_info(mrioc, "trying to create %d operational queue pairs\n", 2235 num_queues); 2236 2237 if (!mrioc->req_qinfo) { 2238 mrioc->req_qinfo = kcalloc(num_queues, 2239 sizeof(struct op_req_qinfo), GFP_KERNEL); 2240 if (!mrioc->req_qinfo) { 2241 retval = -1; 2242 goto out_failed; 2243 } 2244 2245 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) * 2246 num_queues, GFP_KERNEL); 2247 if (!mrioc->op_reply_qinfo) { 2248 retval = -1; 2249 goto out_failed; 2250 } 2251 } 2252 2253 if (mrioc->enable_segqueue) 2254 ioc_info(mrioc, 2255 "allocating operational queues through segmented queues\n"); 2256 2257 for (i = 0; i < num_queues; i++) { 2258 if (mpi3mr_create_op_reply_q(mrioc, i)) { 2259 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i); 2260 break; 2261 } 2262 if (mpi3mr_create_op_req_q(mrioc, i, 2263 mrioc->op_reply_qinfo[i].qid)) { 2264 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i); 2265 mpi3mr_delete_op_reply_q(mrioc, i); 2266 break; 2267 } 2268 } 2269 2270 if (i == 0) { 2271 /* Not even one queue is created successfully*/ 2272 retval = -1; 2273 goto out_failed; 2274 } 2275 mrioc->num_op_reply_q = mrioc->num_op_req_q = i; 2276 ioc_info(mrioc, 2277 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n", 2278 mrioc->num_op_reply_q, mrioc->default_qcount, 2279 mrioc->active_poll_qcount); 2280 2281 return retval; 2282 out_failed: 2283 kfree(mrioc->req_qinfo); 2284 mrioc->req_qinfo = NULL; 2285 2286 kfree(mrioc->op_reply_qinfo); 2287 mrioc->op_reply_qinfo = NULL; 2288 2289 return retval; 2290 } 2291 2292 /** 2293 * mpi3mr_op_request_post - Post request to operational queue 2294 * @mrioc: Adapter reference 2295 * @op_req_q: Operational request queue info 2296 * @req: MPI3 request 2297 * 2298 * Post the MPI3 request into operational request queue and 2299 * inform the controller, if the queue is full return 2300 * appropriate error. 2301 * 2302 * Return: 0 on success, non-zero on failure. 2303 */ 2304 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 2305 struct op_req_qinfo *op_req_q, u8 *req) 2306 { 2307 u16 pi = 0, max_entries, reply_qidx = 0, midx; 2308 int retval = 0; 2309 unsigned long flags; 2310 u8 *req_entry; 2311 void *segment_base_addr; 2312 u16 req_sz = mrioc->facts.op_req_sz; 2313 struct segments *segments = op_req_q->q_segments; 2314 2315 reply_qidx = op_req_q->reply_qid - 1; 2316 2317 if (mrioc->unrecoverable) 2318 return -EFAULT; 2319 2320 spin_lock_irqsave(&op_req_q->q_lock, flags); 2321 pi = op_req_q->pi; 2322 max_entries = op_req_q->num_requests; 2323 2324 if (mpi3mr_check_req_qfull(op_req_q)) { 2325 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX( 2326 reply_qidx, mrioc->op_reply_q_offset); 2327 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q); 2328 2329 if (mpi3mr_check_req_qfull(op_req_q)) { 2330 retval = -EAGAIN; 2331 goto out; 2332 } 2333 } 2334 2335 if (mrioc->reset_in_progress) { 2336 ioc_err(mrioc, "OpReqQ submit reset in progress\n"); 2337 retval = -EAGAIN; 2338 goto out; 2339 } 2340 2341 segment_base_addr = segments[pi / op_req_q->segment_qd].segment; 2342 req_entry = (u8 *)segment_base_addr + 2343 ((pi % op_req_q->segment_qd) * req_sz); 2344 2345 memset(req_entry, 0, req_sz); 2346 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ); 2347 2348 if (++pi == max_entries) 2349 pi = 0; 2350 op_req_q->pi = pi; 2351 2352 #ifndef CONFIG_PREEMPT_RT 2353 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) 2354 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) 2355 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; 2356 #else 2357 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios); 2358 #endif 2359 2360 writel(op_req_q->pi, 2361 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index); 2362 2363 out: 2364 spin_unlock_irqrestore(&op_req_q->q_lock, flags); 2365 return retval; 2366 } 2367 2368 /** 2369 * mpi3mr_check_rh_fault_ioc - check reset history and fault 2370 * controller 2371 * @mrioc: Adapter instance reference 2372 * @reason_code: reason code for the fault. 2373 * 2374 * This routine will save snapdump and fault the controller with 2375 * the given reason code if it is not already in the fault or 2376 * not asynchronosuly reset. This will be used to handle 2377 * initilaization time faults/resets/timeout as in those cases 2378 * immediate soft reset invocation is not required. 2379 * 2380 * Return: None. 2381 */ 2382 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code) 2383 { 2384 u32 ioc_status, host_diagnostic, timeout; 2385 2386 if (mrioc->unrecoverable) { 2387 ioc_err(mrioc, "controller is unrecoverable\n"); 2388 return; 2389 } 2390 2391 if (!pci_device_is_present(mrioc->pdev)) { 2392 mrioc->unrecoverable = 1; 2393 ioc_err(mrioc, "controller is not present\n"); 2394 return; 2395 } 2396 2397 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2398 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 2399 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 2400 mpi3mr_print_fault_info(mrioc); 2401 return; 2402 } 2403 mpi3mr_set_diagsave(mrioc); 2404 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2405 reason_code); 2406 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 2407 do { 2408 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2409 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 2410 break; 2411 msleep(100); 2412 } while (--timeout); 2413 } 2414 2415 /** 2416 * mpi3mr_sync_timestamp - Issue time stamp sync request 2417 * @mrioc: Adapter reference 2418 * 2419 * Issue IO unit control MPI request to synchornize firmware 2420 * timestamp with host time. 2421 * 2422 * Return: 0 on success, non-zero on failure. 2423 */ 2424 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc) 2425 { 2426 ktime_t current_time; 2427 struct mpi3_iounit_control_request iou_ctrl; 2428 int retval = 0; 2429 2430 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 2431 mutex_lock(&mrioc->init_cmds.mutex); 2432 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2433 retval = -1; 2434 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n"); 2435 mutex_unlock(&mrioc->init_cmds.mutex); 2436 goto out; 2437 } 2438 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2439 mrioc->init_cmds.is_waiting = 1; 2440 mrioc->init_cmds.callback = NULL; 2441 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2442 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL; 2443 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP; 2444 current_time = ktime_get_real(); 2445 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time)); 2446 2447 init_completion(&mrioc->init_cmds.done); 2448 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl, 2449 sizeof(iou_ctrl), 0); 2450 if (retval) { 2451 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n"); 2452 goto out_unlock; 2453 } 2454 2455 wait_for_completion_timeout(&mrioc->init_cmds.done, 2456 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2457 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2458 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n"); 2459 mrioc->init_cmds.is_waiting = 0; 2460 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 2461 mpi3mr_check_rh_fault_ioc(mrioc, 2462 MPI3MR_RESET_FROM_TSU_TIMEOUT); 2463 retval = -1; 2464 goto out_unlock; 2465 } 2466 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2467 != MPI3_IOCSTATUS_SUCCESS) { 2468 ioc_err(mrioc, 2469 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2470 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2471 mrioc->init_cmds.ioc_loginfo); 2472 retval = -1; 2473 goto out_unlock; 2474 } 2475 2476 out_unlock: 2477 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2478 mutex_unlock(&mrioc->init_cmds.mutex); 2479 2480 out: 2481 return retval; 2482 } 2483 2484 /** 2485 * mpi3mr_print_pkg_ver - display controller fw package version 2486 * @mrioc: Adapter reference 2487 * 2488 * Retrieve firmware package version from the component image 2489 * header of the controller flash and display it. 2490 * 2491 * Return: 0 on success and non-zero on failure. 2492 */ 2493 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc) 2494 { 2495 struct mpi3_ci_upload_request ci_upload; 2496 int retval = -1; 2497 void *data = NULL; 2498 dma_addr_t data_dma; 2499 struct mpi3_ci_manifest_mpi *manifest; 2500 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi); 2501 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2502 2503 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2504 GFP_KERNEL); 2505 if (!data) 2506 return -ENOMEM; 2507 2508 memset(&ci_upload, 0, sizeof(ci_upload)); 2509 mutex_lock(&mrioc->init_cmds.mutex); 2510 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2511 ioc_err(mrioc, "sending get package version failed due to command in use\n"); 2512 mutex_unlock(&mrioc->init_cmds.mutex); 2513 goto out; 2514 } 2515 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2516 mrioc->init_cmds.is_waiting = 1; 2517 mrioc->init_cmds.callback = NULL; 2518 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2519 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD; 2520 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 2521 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST); 2522 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE); 2523 ci_upload.segment_size = cpu_to_le32(data_len); 2524 2525 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len, 2526 data_dma); 2527 init_completion(&mrioc->init_cmds.done); 2528 retval = mpi3mr_admin_request_post(mrioc, &ci_upload, 2529 sizeof(ci_upload), 1); 2530 if (retval) { 2531 ioc_err(mrioc, "posting get package version failed\n"); 2532 goto out_unlock; 2533 } 2534 wait_for_completion_timeout(&mrioc->init_cmds.done, 2535 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2536 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2537 ioc_err(mrioc, "get package version timed out\n"); 2538 mpi3mr_check_rh_fault_ioc(mrioc, 2539 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2540 retval = -1; 2541 goto out_unlock; 2542 } 2543 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2544 == MPI3_IOCSTATUS_SUCCESS) { 2545 manifest = (struct mpi3_ci_manifest_mpi *) data; 2546 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) { 2547 ioc_info(mrioc, 2548 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n", 2549 manifest->package_version.gen_major, 2550 manifest->package_version.gen_minor, 2551 manifest->package_version.phase_major, 2552 manifest->package_version.phase_minor, 2553 manifest->package_version.customer_id, 2554 manifest->package_version.build_num); 2555 } 2556 } 2557 retval = 0; 2558 out_unlock: 2559 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2560 mutex_unlock(&mrioc->init_cmds.mutex); 2561 2562 out: 2563 if (data) 2564 dma_free_coherent(&mrioc->pdev->dev, data_len, data, 2565 data_dma); 2566 return retval; 2567 } 2568 2569 /** 2570 * mpi3mr_watchdog_work - watchdog thread to monitor faults 2571 * @work: work struct 2572 * 2573 * Watch dog work periodically executed (1 second interval) to 2574 * monitor firmware fault and to issue periodic timer sync to 2575 * the firmware. 2576 * 2577 * Return: Nothing. 2578 */ 2579 static void mpi3mr_watchdog_work(struct work_struct *work) 2580 { 2581 struct mpi3mr_ioc *mrioc = 2582 container_of(work, struct mpi3mr_ioc, watchdog_work.work); 2583 unsigned long flags; 2584 enum mpi3mr_iocstate ioc_state; 2585 u32 fault, host_diagnostic, ioc_status; 2586 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH; 2587 2588 if (mrioc->reset_in_progress) 2589 return; 2590 2591 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) { 2592 ioc_err(mrioc, "watchdog could not detect the controller\n"); 2593 mrioc->unrecoverable = 1; 2594 } 2595 2596 if (mrioc->unrecoverable) { 2597 ioc_err(mrioc, 2598 "flush pending commands for unrecoverable controller\n"); 2599 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 2600 return; 2601 } 2602 2603 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) { 2604 mrioc->ts_update_counter = 0; 2605 mpi3mr_sync_timestamp(mrioc); 2606 } 2607 2608 if ((mrioc->prepare_for_reset) && 2609 ((mrioc->prepare_for_reset_timeout_counter++) >= 2610 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 2611 mpi3mr_soft_reset_handler(mrioc, 2612 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 2613 return; 2614 } 2615 2616 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2617 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2618 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0); 2619 return; 2620 } 2621 2622 /*Check for fault state every one second and issue Soft reset*/ 2623 ioc_state = mpi3mr_get_iocstate(mrioc); 2624 if (ioc_state != MRIOC_STATE_FAULT) 2625 goto schedule_work; 2626 2627 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 2628 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2629 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 2630 if (!mrioc->diagsave_timeout) { 2631 mpi3mr_print_fault_info(mrioc); 2632 ioc_warn(mrioc, "diag save in progress\n"); 2633 } 2634 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 2635 goto schedule_work; 2636 } 2637 2638 mpi3mr_print_fault_info(mrioc); 2639 mrioc->diagsave_timeout = 0; 2640 2641 switch (fault) { 2642 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED: 2643 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED: 2644 ioc_warn(mrioc, 2645 "controller requires system power cycle, marking controller as unrecoverable\n"); 2646 mrioc->unrecoverable = 1; 2647 goto schedule_work; 2648 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS: 2649 goto schedule_work; 2650 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET: 2651 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT; 2652 break; 2653 default: 2654 break; 2655 } 2656 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0); 2657 return; 2658 2659 schedule_work: 2660 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2661 if (mrioc->watchdog_work_q) 2662 queue_delayed_work(mrioc->watchdog_work_q, 2663 &mrioc->watchdog_work, 2664 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2665 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2666 return; 2667 } 2668 2669 /** 2670 * mpi3mr_start_watchdog - Start watchdog 2671 * @mrioc: Adapter instance reference 2672 * 2673 * Create and start the watchdog thread to monitor controller 2674 * faults. 2675 * 2676 * Return: Nothing. 2677 */ 2678 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc) 2679 { 2680 if (mrioc->watchdog_work_q) 2681 return; 2682 2683 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work); 2684 snprintf(mrioc->watchdog_work_q_name, 2685 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name, 2686 mrioc->id); 2687 mrioc->watchdog_work_q = 2688 create_singlethread_workqueue(mrioc->watchdog_work_q_name); 2689 if (!mrioc->watchdog_work_q) { 2690 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__); 2691 return; 2692 } 2693 2694 if (mrioc->watchdog_work_q) 2695 queue_delayed_work(mrioc->watchdog_work_q, 2696 &mrioc->watchdog_work, 2697 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2698 } 2699 2700 /** 2701 * mpi3mr_stop_watchdog - Stop watchdog 2702 * @mrioc: Adapter instance reference 2703 * 2704 * Stop the watchdog thread created to monitor controller 2705 * faults. 2706 * 2707 * Return: Nothing. 2708 */ 2709 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) 2710 { 2711 unsigned long flags; 2712 struct workqueue_struct *wq; 2713 2714 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2715 wq = mrioc->watchdog_work_q; 2716 mrioc->watchdog_work_q = NULL; 2717 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2718 if (wq) { 2719 if (!cancel_delayed_work_sync(&mrioc->watchdog_work)) 2720 flush_workqueue(wq); 2721 destroy_workqueue(wq); 2722 } 2723 } 2724 2725 /** 2726 * mpi3mr_setup_admin_qpair - Setup admin queue pair 2727 * @mrioc: Adapter instance reference 2728 * 2729 * Allocate memory for admin queue pair if required and register 2730 * the admin queue with the controller. 2731 * 2732 * Return: 0 on success, non-zero on failures. 2733 */ 2734 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc) 2735 { 2736 int retval = 0; 2737 u32 num_admin_entries = 0; 2738 2739 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE; 2740 mrioc->num_admin_req = mrioc->admin_req_q_sz / 2741 MPI3MR_ADMIN_REQ_FRAME_SZ; 2742 mrioc->admin_req_ci = mrioc->admin_req_pi = 0; 2743 2744 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE; 2745 mrioc->num_admin_replies = mrioc->admin_reply_q_sz / 2746 MPI3MR_ADMIN_REPLY_FRAME_SZ; 2747 mrioc->admin_reply_ci = 0; 2748 mrioc->admin_reply_ephase = 1; 2749 atomic_set(&mrioc->admin_reply_q_in_use, 0); 2750 2751 if (!mrioc->admin_req_base) { 2752 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev, 2753 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL); 2754 2755 if (!mrioc->admin_req_base) { 2756 retval = -1; 2757 goto out_failed; 2758 } 2759 2760 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev, 2761 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma, 2762 GFP_KERNEL); 2763 2764 if (!mrioc->admin_reply_base) { 2765 retval = -1; 2766 goto out_failed; 2767 } 2768 } 2769 2770 num_admin_entries = (mrioc->num_admin_replies << 16) | 2771 (mrioc->num_admin_req); 2772 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); 2773 mpi3mr_writeq(mrioc->admin_req_dma, 2774 &mrioc->sysif_regs->admin_request_queue_address); 2775 mpi3mr_writeq(mrioc->admin_reply_dma, 2776 &mrioc->sysif_regs->admin_reply_queue_address); 2777 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 2778 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 2779 return retval; 2780 2781 out_failed: 2782 2783 if (mrioc->admin_reply_base) { 2784 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 2785 mrioc->admin_reply_base, mrioc->admin_reply_dma); 2786 mrioc->admin_reply_base = NULL; 2787 } 2788 if (mrioc->admin_req_base) { 2789 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 2790 mrioc->admin_req_base, mrioc->admin_req_dma); 2791 mrioc->admin_req_base = NULL; 2792 } 2793 return retval; 2794 } 2795 2796 /** 2797 * mpi3mr_issue_iocfacts - Send IOC Facts 2798 * @mrioc: Adapter instance reference 2799 * @facts_data: Cached IOC facts data 2800 * 2801 * Issue IOC Facts MPI request through admin queue and wait for 2802 * the completion of it or time out. 2803 * 2804 * Return: 0 on success, non-zero on failures. 2805 */ 2806 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, 2807 struct mpi3_ioc_facts_data *facts_data) 2808 { 2809 struct mpi3_ioc_facts_request iocfacts_req; 2810 void *data = NULL; 2811 dma_addr_t data_dma; 2812 u32 data_len = sizeof(*facts_data); 2813 int retval = 0; 2814 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2815 2816 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2817 GFP_KERNEL); 2818 2819 if (!data) { 2820 retval = -1; 2821 goto out; 2822 } 2823 2824 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 2825 mutex_lock(&mrioc->init_cmds.mutex); 2826 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2827 retval = -1; 2828 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n"); 2829 mutex_unlock(&mrioc->init_cmds.mutex); 2830 goto out; 2831 } 2832 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2833 mrioc->init_cmds.is_waiting = 1; 2834 mrioc->init_cmds.callback = NULL; 2835 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2836 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS; 2837 2838 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len, 2839 data_dma); 2840 2841 init_completion(&mrioc->init_cmds.done); 2842 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req, 2843 sizeof(iocfacts_req), 1); 2844 if (retval) { 2845 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n"); 2846 goto out_unlock; 2847 } 2848 wait_for_completion_timeout(&mrioc->init_cmds.done, 2849 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2850 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2851 ioc_err(mrioc, "ioc_facts timed out\n"); 2852 mpi3mr_check_rh_fault_ioc(mrioc, 2853 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 2854 retval = -1; 2855 goto out_unlock; 2856 } 2857 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2858 != MPI3_IOCSTATUS_SUCCESS) { 2859 ioc_err(mrioc, 2860 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2861 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2862 mrioc->init_cmds.ioc_loginfo); 2863 retval = -1; 2864 goto out_unlock; 2865 } 2866 memcpy(facts_data, (u8 *)data, data_len); 2867 mpi3mr_process_factsdata(mrioc, facts_data); 2868 out_unlock: 2869 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2870 mutex_unlock(&mrioc->init_cmds.mutex); 2871 2872 out: 2873 if (data) 2874 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma); 2875 2876 return retval; 2877 } 2878 2879 /** 2880 * mpi3mr_check_reset_dma_mask - Process IOC facts data 2881 * @mrioc: Adapter instance reference 2882 * 2883 * Check whether the new DMA mask requested through IOCFacts by 2884 * firmware needs to be set, if so set it . 2885 * 2886 * Return: 0 on success, non-zero on failure. 2887 */ 2888 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc) 2889 { 2890 struct pci_dev *pdev = mrioc->pdev; 2891 int r; 2892 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask); 2893 2894 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask)) 2895 return 0; 2896 2897 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n", 2898 mrioc->dma_mask, facts_dma_mask); 2899 2900 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask); 2901 if (r) { 2902 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n", 2903 facts_dma_mask, r); 2904 return r; 2905 } 2906 mrioc->dma_mask = facts_dma_mask; 2907 return r; 2908 } 2909 2910 /** 2911 * mpi3mr_process_factsdata - Process IOC facts data 2912 * @mrioc: Adapter instance reference 2913 * @facts_data: Cached IOC facts data 2914 * 2915 * Convert IOC facts data into cpu endianness and cache it in 2916 * the driver . 2917 * 2918 * Return: Nothing. 2919 */ 2920 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 2921 struct mpi3_ioc_facts_data *facts_data) 2922 { 2923 u32 ioc_config, req_sz, facts_flags; 2924 2925 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) != 2926 (sizeof(*facts_data) / 4)) { 2927 ioc_warn(mrioc, 2928 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n", 2929 sizeof(*facts_data), 2930 le16_to_cpu(facts_data->ioc_facts_data_length) * 4); 2931 } 2932 2933 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 2934 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 2935 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 2936 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) { 2937 ioc_err(mrioc, 2938 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n", 2939 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size)); 2940 } 2941 2942 memset(&mrioc->facts, 0, sizeof(mrioc->facts)); 2943 2944 facts_flags = le32_to_cpu(facts_data->flags); 2945 mrioc->facts.op_req_sz = req_sz; 2946 mrioc->op_reply_desc_sz = 1 << ((ioc_config & 2947 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 2948 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 2949 2950 mrioc->facts.ioc_num = facts_data->ioc_number; 2951 mrioc->facts.who_init = facts_data->who_init; 2952 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors); 2953 mrioc->facts.personality = (facts_flags & 2954 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 2955 mrioc->facts.dma_mask = (facts_flags & 2956 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 2957 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 2958 mrioc->facts.protocol_flags = facts_data->protocol_flags; 2959 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word); 2960 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests); 2961 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id); 2962 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; 2963 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); 2964 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); 2965 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); 2966 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); 2967 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds); 2968 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds); 2969 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); 2970 mrioc->facts.max_pcie_switches = 2971 le16_to_cpu(facts_data->max_pcie_switches); 2972 mrioc->facts.max_sasexpanders = 2973 le16_to_cpu(facts_data->max_sas_expanders); 2974 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length); 2975 mrioc->facts.max_sasinitiators = 2976 le16_to_cpu(facts_data->max_sas_initiators); 2977 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures); 2978 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle); 2979 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle); 2980 mrioc->facts.max_op_req_q = 2981 le16_to_cpu(facts_data->max_operational_request_queues); 2982 mrioc->facts.max_op_reply_q = 2983 le16_to_cpu(facts_data->max_operational_reply_queues); 2984 mrioc->facts.ioc_capabilities = 2985 le32_to_cpu(facts_data->ioc_capabilities); 2986 mrioc->facts.fw_ver.build_num = 2987 le16_to_cpu(facts_data->fw_version.build_num); 2988 mrioc->facts.fw_ver.cust_id = 2989 le16_to_cpu(facts_data->fw_version.customer_id); 2990 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor; 2991 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major; 2992 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor; 2993 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major; 2994 mrioc->msix_count = min_t(int, mrioc->msix_count, 2995 mrioc->facts.max_msix_vectors); 2996 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask; 2997 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value; 2998 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift; 2999 mrioc->facts.shutdown_timeout = 3000 le16_to_cpu(facts_data->shutdown_timeout); 3001 3002 mrioc->facts.max_dev_per_tg = 3003 facts_data->max_devices_per_throttle_group; 3004 mrioc->facts.io_throttle_data_length = 3005 le16_to_cpu(facts_data->io_throttle_data_length); 3006 mrioc->facts.max_io_throttle_group = 3007 le16_to_cpu(facts_data->max_io_throttle_group); 3008 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low); 3009 mrioc->facts.io_throttle_high = 3010 le16_to_cpu(facts_data->io_throttle_high); 3011 3012 if (mrioc->facts.max_data_length == 3013 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED) 3014 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE; 3015 else 3016 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K; 3017 /* Store in 512b block count */ 3018 if (mrioc->facts.io_throttle_data_length) 3019 mrioc->io_throttle_data_length = 3020 (mrioc->facts.io_throttle_data_length * 2 * 4); 3021 else 3022 /* set the length to 1MB + 1K to disable throttle */ 3023 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2; 3024 3025 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024); 3026 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024); 3027 3028 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),", 3029 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, 3030 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); 3031 ioc_info(mrioc, 3032 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n", 3033 mrioc->facts.max_reqs, mrioc->facts.min_devhandle, 3034 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids); 3035 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", 3036 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, 3037 mrioc->facts.sge_mod_shift); 3038 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n", 3039 mrioc->facts.dma_mask, (facts_flags & 3040 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length); 3041 ioc_info(mrioc, 3042 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n", 3043 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group); 3044 ioc_info(mrioc, 3045 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n", 3046 mrioc->facts.io_throttle_data_length * 4, 3047 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low); 3048 } 3049 3050 /** 3051 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init 3052 * @mrioc: Adapter instance reference 3053 * 3054 * Allocate and initialize the reply free buffers, sense 3055 * buffers, reply free queue and sense buffer queue. 3056 * 3057 * Return: 0 on success, non-zero on failures. 3058 */ 3059 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) 3060 { 3061 int retval = 0; 3062 u32 sz, i; 3063 3064 if (mrioc->init_cmds.reply) 3065 return retval; 3066 3067 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3068 if (!mrioc->init_cmds.reply) 3069 goto out_failed; 3070 3071 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3072 if (!mrioc->bsg_cmds.reply) 3073 goto out_failed; 3074 3075 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3076 if (!mrioc->transport_cmds.reply) 3077 goto out_failed; 3078 3079 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 3080 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz, 3081 GFP_KERNEL); 3082 if (!mrioc->dev_rmhs_cmds[i].reply) 3083 goto out_failed; 3084 } 3085 3086 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 3087 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz, 3088 GFP_KERNEL); 3089 if (!mrioc->evtack_cmds[i].reply) 3090 goto out_failed; 3091 } 3092 3093 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3094 if (!mrioc->host_tm_cmds.reply) 3095 goto out_failed; 3096 3097 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3098 if (!mrioc->pel_cmds.reply) 3099 goto out_failed; 3100 3101 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 3102 if (!mrioc->pel_abort_cmd.reply) 3103 goto out_failed; 3104 3105 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle; 3106 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits, 3107 GFP_KERNEL); 3108 if (!mrioc->removepend_bitmap) 3109 goto out_failed; 3110 3111 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL); 3112 if (!mrioc->devrem_bitmap) 3113 goto out_failed; 3114 3115 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD, 3116 GFP_KERNEL); 3117 if (!mrioc->evtack_cmds_bitmap) 3118 goto out_failed; 3119 3120 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES; 3121 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1; 3122 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 3123 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1; 3124 3125 /* reply buffer pool, 16 byte align */ 3126 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3127 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool", 3128 &mrioc->pdev->dev, sz, 16, 0); 3129 if (!mrioc->reply_buf_pool) { 3130 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n"); 3131 goto out_failed; 3132 } 3133 3134 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL, 3135 &mrioc->reply_buf_dma); 3136 if (!mrioc->reply_buf) 3137 goto out_failed; 3138 3139 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz; 3140 3141 /* reply free queue, 8 byte align */ 3142 sz = mrioc->reply_free_qsz * 8; 3143 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool", 3144 &mrioc->pdev->dev, sz, 8, 0); 3145 if (!mrioc->reply_free_q_pool) { 3146 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n"); 3147 goto out_failed; 3148 } 3149 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool, 3150 GFP_KERNEL, &mrioc->reply_free_q_dma); 3151 if (!mrioc->reply_free_q) 3152 goto out_failed; 3153 3154 /* sense buffer pool, 4 byte align */ 3155 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3156 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", 3157 &mrioc->pdev->dev, sz, 4, 0); 3158 if (!mrioc->sense_buf_pool) { 3159 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n"); 3160 goto out_failed; 3161 } 3162 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL, 3163 &mrioc->sense_buf_dma); 3164 if (!mrioc->sense_buf) 3165 goto out_failed; 3166 3167 /* sense buffer queue, 8 byte align */ 3168 sz = mrioc->sense_buf_q_sz * 8; 3169 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool", 3170 &mrioc->pdev->dev, sz, 8, 0); 3171 if (!mrioc->sense_buf_q_pool) { 3172 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n"); 3173 goto out_failed; 3174 } 3175 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool, 3176 GFP_KERNEL, &mrioc->sense_buf_q_dma); 3177 if (!mrioc->sense_buf_q) 3178 goto out_failed; 3179 3180 return retval; 3181 3182 out_failed: 3183 retval = -1; 3184 return retval; 3185 } 3186 3187 /** 3188 * mpimr_initialize_reply_sbuf_queues - initialize reply sense 3189 * buffers 3190 * @mrioc: Adapter instance reference 3191 * 3192 * Helper function to initialize reply and sense buffers along 3193 * with some debug prints. 3194 * 3195 * Return: None. 3196 */ 3197 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc) 3198 { 3199 u32 sz, i; 3200 dma_addr_t phy_addr; 3201 3202 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3203 ioc_info(mrioc, 3204 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3205 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz, 3206 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma); 3207 sz = mrioc->reply_free_qsz * 8; 3208 ioc_info(mrioc, 3209 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3210 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), 3211 (unsigned long long)mrioc->reply_free_q_dma); 3212 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3213 ioc_info(mrioc, 3214 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3215 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ, 3216 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma); 3217 sz = mrioc->sense_buf_q_sz * 8; 3218 ioc_info(mrioc, 3219 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3220 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024), 3221 (unsigned long long)mrioc->sense_buf_q_dma); 3222 3223 /* initialize Reply buffer Queue */ 3224 for (i = 0, phy_addr = mrioc->reply_buf_dma; 3225 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz) 3226 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr); 3227 mrioc->reply_free_q[i] = cpu_to_le64(0); 3228 3229 /* initialize Sense Buffer Queue */ 3230 for (i = 0, phy_addr = mrioc->sense_buf_dma; 3231 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ) 3232 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); 3233 mrioc->sense_buf_q[i] = cpu_to_le64(0); 3234 } 3235 3236 /** 3237 * mpi3mr_issue_iocinit - Send IOC Init 3238 * @mrioc: Adapter instance reference 3239 * 3240 * Issue IOC Init MPI request through admin queue and wait for 3241 * the completion of it or time out. 3242 * 3243 * Return: 0 on success, non-zero on failures. 3244 */ 3245 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) 3246 { 3247 struct mpi3_ioc_init_request iocinit_req; 3248 struct mpi3_driver_info_layout *drv_info; 3249 dma_addr_t data_dma; 3250 u32 data_len = sizeof(*drv_info); 3251 int retval = 0; 3252 ktime_t current_time; 3253 3254 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 3255 GFP_KERNEL); 3256 if (!drv_info) { 3257 retval = -1; 3258 goto out; 3259 } 3260 mpimr_initialize_reply_sbuf_queues(mrioc); 3261 3262 drv_info->information_length = cpu_to_le32(data_len); 3263 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature)); 3264 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name)); 3265 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version)); 3266 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name)); 3267 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version)); 3268 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE, 3269 sizeof(drv_info->driver_release_date)); 3270 drv_info->driver_capabilities = 0; 3271 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info, 3272 sizeof(mrioc->driver_info)); 3273 3274 memset(&iocinit_req, 0, sizeof(iocinit_req)); 3275 mutex_lock(&mrioc->init_cmds.mutex); 3276 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3277 retval = -1; 3278 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n"); 3279 mutex_unlock(&mrioc->init_cmds.mutex); 3280 goto out; 3281 } 3282 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3283 mrioc->init_cmds.is_waiting = 1; 3284 mrioc->init_cmds.callback = NULL; 3285 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3286 iocinit_req.function = MPI3_FUNCTION_IOC_INIT; 3287 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV; 3288 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT; 3289 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR; 3290 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR; 3291 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER; 3292 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); 3293 iocinit_req.reply_free_queue_address = 3294 cpu_to_le64(mrioc->reply_free_q_dma); 3295 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ); 3296 iocinit_req.sense_buffer_free_queue_depth = 3297 cpu_to_le16(mrioc->sense_buf_q_sz); 3298 iocinit_req.sense_buffer_free_queue_address = 3299 cpu_to_le64(mrioc->sense_buf_q_dma); 3300 iocinit_req.driver_information_address = cpu_to_le64(data_dma); 3301 3302 current_time = ktime_get_real(); 3303 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time)); 3304 3305 iocinit_req.msg_flags |= 3306 MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED; 3307 3308 init_completion(&mrioc->init_cmds.done); 3309 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, 3310 sizeof(iocinit_req), 1); 3311 if (retval) { 3312 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n"); 3313 goto out_unlock; 3314 } 3315 wait_for_completion_timeout(&mrioc->init_cmds.done, 3316 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3317 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3318 mpi3mr_check_rh_fault_ioc(mrioc, 3319 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 3320 ioc_err(mrioc, "ioc_init timed out\n"); 3321 retval = -1; 3322 goto out_unlock; 3323 } 3324 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3325 != MPI3_IOCSTATUS_SUCCESS) { 3326 ioc_err(mrioc, 3327 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3328 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3329 mrioc->init_cmds.ioc_loginfo); 3330 retval = -1; 3331 goto out_unlock; 3332 } 3333 3334 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs; 3335 writel(mrioc->reply_free_queue_host_index, 3336 &mrioc->sysif_regs->reply_free_host_index); 3337 3338 mrioc->sbq_host_index = mrioc->num_sense_bufs; 3339 writel(mrioc->sbq_host_index, 3340 &mrioc->sysif_regs->sense_buffer_free_host_index); 3341 out_unlock: 3342 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3343 mutex_unlock(&mrioc->init_cmds.mutex); 3344 3345 out: 3346 if (drv_info) 3347 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info, 3348 data_dma); 3349 3350 return retval; 3351 } 3352 3353 /** 3354 * mpi3mr_unmask_events - Unmask events in event mask bitmap 3355 * @mrioc: Adapter instance reference 3356 * @event: MPI event ID 3357 * 3358 * Un mask the specific event by resetting the event_mask 3359 * bitmap. 3360 * 3361 * Return: 0 on success, non-zero on failures. 3362 */ 3363 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event) 3364 { 3365 u32 desired_event; 3366 u8 word; 3367 3368 if (event >= 128) 3369 return; 3370 3371 desired_event = (1 << (event % 32)); 3372 word = event / 32; 3373 3374 mrioc->event_masks[word] &= ~desired_event; 3375 } 3376 3377 /** 3378 * mpi3mr_issue_event_notification - Send event notification 3379 * @mrioc: Adapter instance reference 3380 * 3381 * Issue event notification MPI request through admin queue and 3382 * wait for the completion of it or time out. 3383 * 3384 * Return: 0 on success, non-zero on failures. 3385 */ 3386 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) 3387 { 3388 struct mpi3_event_notification_request evtnotify_req; 3389 int retval = 0; 3390 u8 i; 3391 3392 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 3393 mutex_lock(&mrioc->init_cmds.mutex); 3394 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3395 retval = -1; 3396 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n"); 3397 mutex_unlock(&mrioc->init_cmds.mutex); 3398 goto out; 3399 } 3400 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3401 mrioc->init_cmds.is_waiting = 1; 3402 mrioc->init_cmds.callback = NULL; 3403 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3404 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION; 3405 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3406 evtnotify_req.event_masks[i] = 3407 cpu_to_le32(mrioc->event_masks[i]); 3408 init_completion(&mrioc->init_cmds.done); 3409 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req, 3410 sizeof(evtnotify_req), 1); 3411 if (retval) { 3412 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n"); 3413 goto out_unlock; 3414 } 3415 wait_for_completion_timeout(&mrioc->init_cmds.done, 3416 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3417 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3418 ioc_err(mrioc, "event notification timed out\n"); 3419 mpi3mr_check_rh_fault_ioc(mrioc, 3420 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 3421 retval = -1; 3422 goto out_unlock; 3423 } 3424 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3425 != MPI3_IOCSTATUS_SUCCESS) { 3426 ioc_err(mrioc, 3427 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3428 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3429 mrioc->init_cmds.ioc_loginfo); 3430 retval = -1; 3431 goto out_unlock; 3432 } 3433 3434 out_unlock: 3435 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3436 mutex_unlock(&mrioc->init_cmds.mutex); 3437 out: 3438 return retval; 3439 } 3440 3441 /** 3442 * mpi3mr_process_event_ack - Process event acknowledgment 3443 * @mrioc: Adapter instance reference 3444 * @event: MPI3 event ID 3445 * @event_ctx: event context 3446 * 3447 * Send event acknowledgment through admin queue and wait for 3448 * it to complete. 3449 * 3450 * Return: 0 on success, non-zero on failures. 3451 */ 3452 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 3453 u32 event_ctx) 3454 { 3455 struct mpi3_event_ack_request evtack_req; 3456 int retval = 0; 3457 3458 memset(&evtack_req, 0, sizeof(evtack_req)); 3459 mutex_lock(&mrioc->init_cmds.mutex); 3460 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3461 retval = -1; 3462 ioc_err(mrioc, "Send EvtAck: Init command is in use\n"); 3463 mutex_unlock(&mrioc->init_cmds.mutex); 3464 goto out; 3465 } 3466 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3467 mrioc->init_cmds.is_waiting = 1; 3468 mrioc->init_cmds.callback = NULL; 3469 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3470 evtack_req.function = MPI3_FUNCTION_EVENT_ACK; 3471 evtack_req.event = event; 3472 evtack_req.event_context = cpu_to_le32(event_ctx); 3473 3474 init_completion(&mrioc->init_cmds.done); 3475 retval = mpi3mr_admin_request_post(mrioc, &evtack_req, 3476 sizeof(evtack_req), 1); 3477 if (retval) { 3478 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n"); 3479 goto out_unlock; 3480 } 3481 wait_for_completion_timeout(&mrioc->init_cmds.done, 3482 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3483 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3484 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 3485 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 3486 mpi3mr_check_rh_fault_ioc(mrioc, 3487 MPI3MR_RESET_FROM_EVTACK_TIMEOUT); 3488 retval = -1; 3489 goto out_unlock; 3490 } 3491 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3492 != MPI3_IOCSTATUS_SUCCESS) { 3493 ioc_err(mrioc, 3494 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3495 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3496 mrioc->init_cmds.ioc_loginfo); 3497 retval = -1; 3498 goto out_unlock; 3499 } 3500 3501 out_unlock: 3502 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3503 mutex_unlock(&mrioc->init_cmds.mutex); 3504 out: 3505 return retval; 3506 } 3507 3508 /** 3509 * mpi3mr_alloc_chain_bufs - Allocate chain buffers 3510 * @mrioc: Adapter instance reference 3511 * 3512 * Allocate chain buffers and set a bitmap to indicate free 3513 * chain buffers. Chain buffers are used to pass the SGE 3514 * information along with MPI3 SCSI IO requests for host I/O. 3515 * 3516 * Return: 0 on success, non-zero on failure 3517 */ 3518 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) 3519 { 3520 int retval = 0; 3521 u32 sz, i; 3522 u16 num_chains; 3523 3524 if (mrioc->chain_sgl_list) 3525 return retval; 3526 3527 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR; 3528 3529 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION 3530 | SHOST_DIX_TYPE1_PROTECTION 3531 | SHOST_DIX_TYPE2_PROTECTION 3532 | SHOST_DIX_TYPE3_PROTECTION)) 3533 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR); 3534 3535 mrioc->chain_buf_count = num_chains; 3536 sz = sizeof(struct chain_element) * num_chains; 3537 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL); 3538 if (!mrioc->chain_sgl_list) 3539 goto out_failed; 3540 3541 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length / 3542 MPI3MR_PAGE_SIZE_4K)) 3543 mrioc->max_sgl_entries = mrioc->facts.max_data_length / 3544 MPI3MR_PAGE_SIZE_4K; 3545 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common); 3546 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n", 3547 mrioc->max_sgl_entries, sz/1024); 3548 3549 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool", 3550 &mrioc->pdev->dev, sz, 16, 0); 3551 if (!mrioc->chain_buf_pool) { 3552 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n"); 3553 goto out_failed; 3554 } 3555 3556 for (i = 0; i < num_chains; i++) { 3557 mrioc->chain_sgl_list[i].addr = 3558 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL, 3559 &mrioc->chain_sgl_list[i].dma_addr); 3560 3561 if (!mrioc->chain_sgl_list[i].addr) 3562 goto out_failed; 3563 } 3564 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL); 3565 if (!mrioc->chain_bitmap) 3566 goto out_failed; 3567 return retval; 3568 out_failed: 3569 retval = -1; 3570 return retval; 3571 } 3572 3573 /** 3574 * mpi3mr_port_enable_complete - Mark port enable complete 3575 * @mrioc: Adapter instance reference 3576 * @drv_cmd: Internal command tracker 3577 * 3578 * Call back for asynchronous port enable request sets the 3579 * driver command to indicate port enable request is complete. 3580 * 3581 * Return: Nothing 3582 */ 3583 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc, 3584 struct mpi3mr_drv_cmd *drv_cmd) 3585 { 3586 drv_cmd->callback = NULL; 3587 mrioc->scan_started = 0; 3588 if (drv_cmd->state & MPI3MR_CMD_RESET) 3589 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR; 3590 else 3591 mrioc->scan_failed = drv_cmd->ioc_status; 3592 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3593 } 3594 3595 /** 3596 * mpi3mr_issue_port_enable - Issue Port Enable 3597 * @mrioc: Adapter instance reference 3598 * @async: Flag to wait for completion or not 3599 * 3600 * Issue Port Enable MPI request through admin queue and if the 3601 * async flag is not set wait for the completion of the port 3602 * enable or time out. 3603 * 3604 * Return: 0 on success, non-zero on failures. 3605 */ 3606 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) 3607 { 3608 struct mpi3_port_enable_request pe_req; 3609 int retval = 0; 3610 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT; 3611 3612 memset(&pe_req, 0, sizeof(pe_req)); 3613 mutex_lock(&mrioc->init_cmds.mutex); 3614 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3615 retval = -1; 3616 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n"); 3617 mutex_unlock(&mrioc->init_cmds.mutex); 3618 goto out; 3619 } 3620 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3621 if (async) { 3622 mrioc->init_cmds.is_waiting = 0; 3623 mrioc->init_cmds.callback = mpi3mr_port_enable_complete; 3624 } else { 3625 mrioc->init_cmds.is_waiting = 1; 3626 mrioc->init_cmds.callback = NULL; 3627 init_completion(&mrioc->init_cmds.done); 3628 } 3629 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3630 pe_req.function = MPI3_FUNCTION_PORT_ENABLE; 3631 3632 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1); 3633 if (retval) { 3634 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n"); 3635 goto out_unlock; 3636 } 3637 if (async) { 3638 mutex_unlock(&mrioc->init_cmds.mutex); 3639 goto out; 3640 } 3641 3642 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ)); 3643 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3644 ioc_err(mrioc, "port enable timed out\n"); 3645 retval = -1; 3646 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3647 goto out_unlock; 3648 } 3649 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds); 3650 3651 out_unlock: 3652 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3653 mutex_unlock(&mrioc->init_cmds.mutex); 3654 out: 3655 return retval; 3656 } 3657 3658 /* Protocol type to name mapper structure */ 3659 static const struct { 3660 u8 protocol; 3661 char *name; 3662 } mpi3mr_protocols[] = { 3663 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" }, 3664 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" }, 3665 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" }, 3666 }; 3667 3668 /* Capability to name mapper structure*/ 3669 static const struct { 3670 u32 capability; 3671 char *name; 3672 } mpi3mr_capabilities[] = { 3673 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" }, 3674 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" }, 3675 }; 3676 3677 /** 3678 * mpi3mr_print_ioc_info - Display controller information 3679 * @mrioc: Adapter instance reference 3680 * 3681 * Display controller personalit, capability, supported 3682 * protocols etc. 3683 * 3684 * Return: Nothing 3685 */ 3686 static void 3687 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc) 3688 { 3689 int i = 0, bytes_written = 0; 3690 char personality[16]; 3691 char protocol[50] = {0}; 3692 char capabilities[100] = {0}; 3693 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver; 3694 3695 switch (mrioc->facts.personality) { 3696 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 3697 strncpy(personality, "Enhanced HBA", sizeof(personality)); 3698 break; 3699 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 3700 strncpy(personality, "RAID", sizeof(personality)); 3701 break; 3702 default: 3703 strncpy(personality, "Unknown", sizeof(personality)); 3704 break; 3705 } 3706 3707 ioc_info(mrioc, "Running in %s Personality", personality); 3708 3709 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n", 3710 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 3711 fwver->ph_minor, fwver->cust_id, fwver->build_num); 3712 3713 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) { 3714 if (mrioc->facts.protocol_flags & 3715 mpi3mr_protocols[i].protocol) { 3716 bytes_written += scnprintf(protocol + bytes_written, 3717 sizeof(protocol) - bytes_written, "%s%s", 3718 bytes_written ? "," : "", 3719 mpi3mr_protocols[i].name); 3720 } 3721 } 3722 3723 bytes_written = 0; 3724 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) { 3725 if (mrioc->facts.protocol_flags & 3726 mpi3mr_capabilities[i].capability) { 3727 bytes_written += scnprintf(capabilities + bytes_written, 3728 sizeof(capabilities) - bytes_written, "%s%s", 3729 bytes_written ? "," : "", 3730 mpi3mr_capabilities[i].name); 3731 } 3732 } 3733 3734 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n", 3735 protocol, capabilities); 3736 } 3737 3738 /** 3739 * mpi3mr_cleanup_resources - Free PCI resources 3740 * @mrioc: Adapter instance reference 3741 * 3742 * Unmap PCI device memory and disable PCI device. 3743 * 3744 * Return: 0 on success and non-zero on failure. 3745 */ 3746 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc) 3747 { 3748 struct pci_dev *pdev = mrioc->pdev; 3749 3750 mpi3mr_cleanup_isr(mrioc); 3751 3752 if (mrioc->sysif_regs) { 3753 iounmap((void __iomem *)mrioc->sysif_regs); 3754 mrioc->sysif_regs = NULL; 3755 } 3756 3757 if (pci_is_enabled(pdev)) { 3758 if (mrioc->bars) 3759 pci_release_selected_regions(pdev, mrioc->bars); 3760 pci_disable_device(pdev); 3761 } 3762 } 3763 3764 /** 3765 * mpi3mr_setup_resources - Enable PCI resources 3766 * @mrioc: Adapter instance reference 3767 * 3768 * Enable PCI device memory, MSI-x registers and set DMA mask. 3769 * 3770 * Return: 0 on success and non-zero on failure. 3771 */ 3772 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) 3773 { 3774 struct pci_dev *pdev = mrioc->pdev; 3775 u32 memap_sz = 0; 3776 int i, retval = 0, capb = 0; 3777 u16 message_control; 3778 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask : 3779 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); 3780 3781 if (pci_enable_device_mem(pdev)) { 3782 ioc_err(mrioc, "pci_enable_device_mem: failed\n"); 3783 retval = -ENODEV; 3784 goto out_failed; 3785 } 3786 3787 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 3788 if (!capb) { 3789 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n"); 3790 retval = -ENODEV; 3791 goto out_failed; 3792 } 3793 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 3794 3795 if (pci_request_selected_regions(pdev, mrioc->bars, 3796 mrioc->driver_name)) { 3797 ioc_err(mrioc, "pci_request_selected_regions: failed\n"); 3798 retval = -ENODEV; 3799 goto out_failed; 3800 } 3801 3802 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) { 3803 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 3804 mrioc->sysif_regs_phys = pci_resource_start(pdev, i); 3805 memap_sz = pci_resource_len(pdev, i); 3806 mrioc->sysif_regs = 3807 ioremap(mrioc->sysif_regs_phys, memap_sz); 3808 break; 3809 } 3810 } 3811 3812 pci_set_master(pdev); 3813 3814 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 3815 if (retval) { 3816 if (dma_mask != DMA_BIT_MASK(32)) { 3817 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n"); 3818 dma_mask = DMA_BIT_MASK(32); 3819 retval = dma_set_mask_and_coherent(&pdev->dev, 3820 dma_mask); 3821 } 3822 if (retval) { 3823 mrioc->dma_mask = 0; 3824 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n"); 3825 goto out_failed; 3826 } 3827 } 3828 mrioc->dma_mask = dma_mask; 3829 3830 if (!mrioc->sysif_regs) { 3831 ioc_err(mrioc, 3832 "Unable to map adapter memory or resource not found\n"); 3833 retval = -EINVAL; 3834 goto out_failed; 3835 } 3836 3837 pci_read_config_word(pdev, capb + 2, &message_control); 3838 mrioc->msix_count = (message_control & 0x3FF) + 1; 3839 3840 pci_save_state(pdev); 3841 3842 pci_set_drvdata(pdev, mrioc->shost); 3843 3844 mpi3mr_ioc_disable_intr(mrioc); 3845 3846 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 3847 (unsigned long long)mrioc->sysif_regs_phys, 3848 mrioc->sysif_regs, memap_sz); 3849 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n", 3850 mrioc->msix_count); 3851 3852 if (!reset_devices && poll_queues > 0) 3853 mrioc->requested_poll_qcount = min_t(int, poll_queues, 3854 mrioc->msix_count - 2); 3855 return retval; 3856 3857 out_failed: 3858 mpi3mr_cleanup_resources(mrioc); 3859 return retval; 3860 } 3861 3862 /** 3863 * mpi3mr_enable_events - Enable required events 3864 * @mrioc: Adapter instance reference 3865 * 3866 * This routine unmasks the events required by the driver by 3867 * sennding appropriate event mask bitmapt through an event 3868 * notification request. 3869 * 3870 * Return: 0 on success and non-zero on failure. 3871 */ 3872 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc) 3873 { 3874 int retval = 0; 3875 u32 i; 3876 3877 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3878 mrioc->event_masks[i] = -1; 3879 3880 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED); 3881 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED); 3882 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 3883 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 3884 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED); 3885 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 3886 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY); 3887 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 3888 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 3889 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 3890 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION); 3891 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET); 3892 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT); 3893 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE); 3894 3895 retval = mpi3mr_issue_event_notification(mrioc); 3896 if (retval) 3897 ioc_err(mrioc, "failed to issue event notification %d\n", 3898 retval); 3899 return retval; 3900 } 3901 3902 /** 3903 * mpi3mr_init_ioc - Initialize the controller 3904 * @mrioc: Adapter instance reference 3905 * 3906 * This the controller initialization routine, executed either 3907 * after soft reset or from pci probe callback. 3908 * Setup the required resources, memory map the controller 3909 * registers, create admin and operational reply queue pairs, 3910 * allocate required memory for reply pool, sense buffer pool, 3911 * issue IOC init request to the firmware, unmask the events and 3912 * issue port enable to discover SAS/SATA/NVMe devies and RAID 3913 * volumes. 3914 * 3915 * Return: 0 on success and non-zero on failure. 3916 */ 3917 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) 3918 { 3919 int retval = 0; 3920 u8 retry = 0; 3921 struct mpi3_ioc_facts_data facts_data; 3922 u32 sz; 3923 3924 retry_init: 3925 retval = mpi3mr_bring_ioc_ready(mrioc); 3926 if (retval) { 3927 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n", 3928 retval); 3929 goto out_failed_noretry; 3930 } 3931 3932 retval = mpi3mr_setup_isr(mrioc, 1); 3933 if (retval) { 3934 ioc_err(mrioc, "Failed to setup ISR error %d\n", 3935 retval); 3936 goto out_failed_noretry; 3937 } 3938 3939 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 3940 if (retval) { 3941 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n", 3942 retval); 3943 goto out_failed; 3944 } 3945 3946 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD; 3947 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512; 3948 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group; 3949 atomic_set(&mrioc->pend_large_data_sz, 0); 3950 3951 if (reset_devices) 3952 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios, 3953 MPI3MR_HOST_IOS_KDUMP); 3954 3955 if (!(mrioc->facts.ioc_capabilities & 3956 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) { 3957 mrioc->sas_transport_enabled = 1; 3958 mrioc->scsi_device_channel = 1; 3959 mrioc->shost->max_channel = 1; 3960 mrioc->shost->transportt = mpi3mr_transport_template; 3961 } 3962 3963 mrioc->reply_sz = mrioc->facts.reply_sz; 3964 3965 retval = mpi3mr_check_reset_dma_mask(mrioc); 3966 if (retval) { 3967 ioc_err(mrioc, "Resetting dma mask failed %d\n", 3968 retval); 3969 goto out_failed_noretry; 3970 } 3971 3972 mpi3mr_print_ioc_info(mrioc); 3973 3974 if (!mrioc->cfg_page) { 3975 dprint_init(mrioc, "allocating config page buffers\n"); 3976 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ; 3977 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev, 3978 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL); 3979 if (!mrioc->cfg_page) { 3980 retval = -1; 3981 goto out_failed_noretry; 3982 } 3983 } 3984 3985 dprint_init(mrioc, "allocating ioctl dma buffers\n"); 3986 mpi3mr_alloc_ioctl_dma_memory(mrioc); 3987 3988 if (!mrioc->init_cmds.reply) { 3989 retval = mpi3mr_alloc_reply_sense_bufs(mrioc); 3990 if (retval) { 3991 ioc_err(mrioc, 3992 "%s :Failed to allocated reply sense buffers %d\n", 3993 __func__, retval); 3994 goto out_failed_noretry; 3995 } 3996 } 3997 3998 if (!mrioc->chain_sgl_list) { 3999 retval = mpi3mr_alloc_chain_bufs(mrioc); 4000 if (retval) { 4001 ioc_err(mrioc, "Failed to allocated chain buffers %d\n", 4002 retval); 4003 goto out_failed_noretry; 4004 } 4005 } 4006 4007 retval = mpi3mr_issue_iocinit(mrioc); 4008 if (retval) { 4009 ioc_err(mrioc, "Failed to Issue IOC Init %d\n", 4010 retval); 4011 goto out_failed; 4012 } 4013 4014 retval = mpi3mr_print_pkg_ver(mrioc); 4015 if (retval) { 4016 ioc_err(mrioc, "failed to get package version\n"); 4017 goto out_failed; 4018 } 4019 4020 retval = mpi3mr_setup_isr(mrioc, 0); 4021 if (retval) { 4022 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n", 4023 retval); 4024 goto out_failed_noretry; 4025 } 4026 4027 retval = mpi3mr_create_op_queues(mrioc); 4028 if (retval) { 4029 ioc_err(mrioc, "Failed to create OpQueues error %d\n", 4030 retval); 4031 goto out_failed; 4032 } 4033 4034 if (!mrioc->pel_seqnum_virt) { 4035 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n"); 4036 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4037 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4038 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4039 GFP_KERNEL); 4040 if (!mrioc->pel_seqnum_virt) { 4041 retval = -ENOMEM; 4042 goto out_failed_noretry; 4043 } 4044 } 4045 4046 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) { 4047 dprint_init(mrioc, "allocating memory for throttle groups\n"); 4048 sz = sizeof(struct mpi3mr_throttle_group_info); 4049 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL); 4050 if (!mrioc->throttle_groups) { 4051 retval = -1; 4052 goto out_failed_noretry; 4053 } 4054 } 4055 4056 retval = mpi3mr_enable_events(mrioc); 4057 if (retval) { 4058 ioc_err(mrioc, "failed to enable events %d\n", 4059 retval); 4060 goto out_failed; 4061 } 4062 4063 ioc_info(mrioc, "controller initialization completed successfully\n"); 4064 return retval; 4065 out_failed: 4066 if (retry < 2) { 4067 retry++; 4068 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n", 4069 retry); 4070 mpi3mr_memset_buffers(mrioc); 4071 goto retry_init; 4072 } 4073 retval = -1; 4074 out_failed_noretry: 4075 ioc_err(mrioc, "controller initialization failed\n"); 4076 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4077 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4078 mrioc->unrecoverable = 1; 4079 return retval; 4080 } 4081 4082 /** 4083 * mpi3mr_reinit_ioc - Re-Initialize the controller 4084 * @mrioc: Adapter instance reference 4085 * @is_resume: Called from resume or reset path 4086 * 4087 * This the controller re-initialization routine, executed from 4088 * the soft reset handler or resume callback. Creates 4089 * operational reply queue pairs, allocate required memory for 4090 * reply pool, sense buffer pool, issue IOC init request to the 4091 * firmware, unmask the events and issue port enable to discover 4092 * SAS/SATA/NVMe devices and RAID volumes. 4093 * 4094 * Return: 0 on success and non-zero on failure. 4095 */ 4096 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume) 4097 { 4098 int retval = 0; 4099 u8 retry = 0; 4100 struct mpi3_ioc_facts_data facts_data; 4101 u32 pe_timeout, ioc_status; 4102 4103 retry_init: 4104 pe_timeout = 4105 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL); 4106 4107 dprint_reset(mrioc, "bringing up the controller to ready state\n"); 4108 retval = mpi3mr_bring_ioc_ready(mrioc); 4109 if (retval) { 4110 ioc_err(mrioc, "failed to bring to ready state\n"); 4111 goto out_failed_noretry; 4112 } 4113 4114 if (is_resume) { 4115 dprint_reset(mrioc, "setting up single ISR\n"); 4116 retval = mpi3mr_setup_isr(mrioc, 1); 4117 if (retval) { 4118 ioc_err(mrioc, "failed to setup ISR\n"); 4119 goto out_failed_noretry; 4120 } 4121 } else 4122 mpi3mr_ioc_enable_intr(mrioc); 4123 4124 dprint_reset(mrioc, "getting ioc_facts\n"); 4125 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 4126 if (retval) { 4127 ioc_err(mrioc, "failed to get ioc_facts\n"); 4128 goto out_failed; 4129 } 4130 4131 dprint_reset(mrioc, "validating ioc_facts\n"); 4132 retval = mpi3mr_revalidate_factsdata(mrioc); 4133 if (retval) { 4134 ioc_err(mrioc, "failed to revalidate ioc_facts data\n"); 4135 goto out_failed_noretry; 4136 } 4137 4138 mpi3mr_print_ioc_info(mrioc); 4139 4140 dprint_reset(mrioc, "sending ioc_init\n"); 4141 retval = mpi3mr_issue_iocinit(mrioc); 4142 if (retval) { 4143 ioc_err(mrioc, "failed to send ioc_init\n"); 4144 goto out_failed; 4145 } 4146 4147 dprint_reset(mrioc, "getting package version\n"); 4148 retval = mpi3mr_print_pkg_ver(mrioc); 4149 if (retval) { 4150 ioc_err(mrioc, "failed to get package version\n"); 4151 goto out_failed; 4152 } 4153 4154 if (is_resume) { 4155 dprint_reset(mrioc, "setting up multiple ISR\n"); 4156 retval = mpi3mr_setup_isr(mrioc, 0); 4157 if (retval) { 4158 ioc_err(mrioc, "failed to re-setup ISR\n"); 4159 goto out_failed_noretry; 4160 } 4161 } 4162 4163 dprint_reset(mrioc, "creating operational queue pairs\n"); 4164 retval = mpi3mr_create_op_queues(mrioc); 4165 if (retval) { 4166 ioc_err(mrioc, "failed to create operational queue pairs\n"); 4167 goto out_failed; 4168 } 4169 4170 if (!mrioc->pel_seqnum_virt) { 4171 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n"); 4172 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4173 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4174 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4175 GFP_KERNEL); 4176 if (!mrioc->pel_seqnum_virt) { 4177 retval = -ENOMEM; 4178 goto out_failed_noretry; 4179 } 4180 } 4181 4182 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) { 4183 ioc_err(mrioc, 4184 "cannot create minimum number of operational queues expected:%d created:%d\n", 4185 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q); 4186 retval = -1; 4187 goto out_failed_noretry; 4188 } 4189 4190 dprint_reset(mrioc, "enabling events\n"); 4191 retval = mpi3mr_enable_events(mrioc); 4192 if (retval) { 4193 ioc_err(mrioc, "failed to enable events\n"); 4194 goto out_failed; 4195 } 4196 4197 mrioc->device_refresh_on = 1; 4198 mpi3mr_add_event_wait_for_device_refresh(mrioc); 4199 4200 ioc_info(mrioc, "sending port enable\n"); 4201 retval = mpi3mr_issue_port_enable(mrioc, 1); 4202 if (retval) { 4203 ioc_err(mrioc, "failed to issue port enable\n"); 4204 goto out_failed; 4205 } 4206 do { 4207 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL); 4208 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED) 4209 break; 4210 if (!pci_device_is_present(mrioc->pdev)) 4211 mrioc->unrecoverable = 1; 4212 if (mrioc->unrecoverable) { 4213 retval = -1; 4214 goto out_failed_noretry; 4215 } 4216 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4217 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 4218 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 4219 mpi3mr_print_fault_info(mrioc); 4220 mrioc->init_cmds.is_waiting = 0; 4221 mrioc->init_cmds.callback = NULL; 4222 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4223 goto out_failed; 4224 } 4225 } while (--pe_timeout); 4226 4227 if (!pe_timeout) { 4228 ioc_err(mrioc, "port enable timed out\n"); 4229 mpi3mr_check_rh_fault_ioc(mrioc, 4230 MPI3MR_RESET_FROM_PE_TIMEOUT); 4231 mrioc->init_cmds.is_waiting = 0; 4232 mrioc->init_cmds.callback = NULL; 4233 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4234 goto out_failed; 4235 } else if (mrioc->scan_failed) { 4236 ioc_err(mrioc, 4237 "port enable failed with status=0x%04x\n", 4238 mrioc->scan_failed); 4239 } else 4240 ioc_info(mrioc, "port enable completed successfully\n"); 4241 4242 ioc_info(mrioc, "controller %s completed successfully\n", 4243 (is_resume)?"resume":"re-initialization"); 4244 return retval; 4245 out_failed: 4246 if (retry < 2) { 4247 retry++; 4248 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n", 4249 (is_resume)?"resume":"re-initialization", retry); 4250 mpi3mr_memset_buffers(mrioc); 4251 goto retry_init; 4252 } 4253 retval = -1; 4254 out_failed_noretry: 4255 ioc_err(mrioc, "controller %s is failed\n", 4256 (is_resume)?"resume":"re-initialization"); 4257 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4258 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4259 mrioc->unrecoverable = 1; 4260 return retval; 4261 } 4262 4263 /** 4264 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's 4265 * segments 4266 * @mrioc: Adapter instance reference 4267 * @qidx: Operational reply queue index 4268 * 4269 * Return: Nothing. 4270 */ 4271 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4272 { 4273 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 4274 struct segments *segments; 4275 int i, size; 4276 4277 if (!op_reply_q->q_segments) 4278 return; 4279 4280 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz; 4281 segments = op_reply_q->q_segments; 4282 for (i = 0; i < op_reply_q->num_segments; i++) 4283 memset(segments[i].segment, 0, size); 4284 } 4285 4286 /** 4287 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's 4288 * segments 4289 * @mrioc: Adapter instance reference 4290 * @qidx: Operational request queue index 4291 * 4292 * Return: Nothing. 4293 */ 4294 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4295 { 4296 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 4297 struct segments *segments; 4298 int i, size; 4299 4300 if (!op_req_q->q_segments) 4301 return; 4302 4303 size = op_req_q->segment_qd * mrioc->facts.op_req_sz; 4304 segments = op_req_q->q_segments; 4305 for (i = 0; i < op_req_q->num_segments; i++) 4306 memset(segments[i].segment, 0, size); 4307 } 4308 4309 /** 4310 * mpi3mr_memset_buffers - memset memory for a controller 4311 * @mrioc: Adapter instance reference 4312 * 4313 * clear all the memory allocated for a controller, typically 4314 * called post reset to reuse the memory allocated during the 4315 * controller init. 4316 * 4317 * Return: Nothing. 4318 */ 4319 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) 4320 { 4321 u16 i; 4322 struct mpi3mr_throttle_group_info *tg; 4323 4324 mrioc->change_count = 0; 4325 mrioc->active_poll_qcount = 0; 4326 mrioc->default_qcount = 0; 4327 if (mrioc->admin_req_base) 4328 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz); 4329 if (mrioc->admin_reply_base) 4330 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz); 4331 atomic_set(&mrioc->admin_reply_q_in_use, 0); 4332 4333 if (mrioc->init_cmds.reply) { 4334 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply)); 4335 memset(mrioc->bsg_cmds.reply, 0, 4336 sizeof(*mrioc->bsg_cmds.reply)); 4337 memset(mrioc->host_tm_cmds.reply, 0, 4338 sizeof(*mrioc->host_tm_cmds.reply)); 4339 memset(mrioc->pel_cmds.reply, 0, 4340 sizeof(*mrioc->pel_cmds.reply)); 4341 memset(mrioc->pel_abort_cmd.reply, 0, 4342 sizeof(*mrioc->pel_abort_cmd.reply)); 4343 memset(mrioc->transport_cmds.reply, 0, 4344 sizeof(*mrioc->transport_cmds.reply)); 4345 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 4346 memset(mrioc->dev_rmhs_cmds[i].reply, 0, 4347 sizeof(*mrioc->dev_rmhs_cmds[i].reply)); 4348 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 4349 memset(mrioc->evtack_cmds[i].reply, 0, 4350 sizeof(*mrioc->evtack_cmds[i].reply)); 4351 bitmap_clear(mrioc->removepend_bitmap, 0, 4352 mrioc->dev_handle_bitmap_bits); 4353 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 4354 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, 4355 MPI3MR_NUM_EVTACKCMD); 4356 } 4357 4358 for (i = 0; i < mrioc->num_queues; i++) { 4359 mrioc->op_reply_qinfo[i].qid = 0; 4360 mrioc->op_reply_qinfo[i].ci = 0; 4361 mrioc->op_reply_qinfo[i].num_replies = 0; 4362 mrioc->op_reply_qinfo[i].ephase = 0; 4363 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0); 4364 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0); 4365 mpi3mr_memset_op_reply_q_buffers(mrioc, i); 4366 4367 mrioc->req_qinfo[i].ci = 0; 4368 mrioc->req_qinfo[i].pi = 0; 4369 mrioc->req_qinfo[i].num_requests = 0; 4370 mrioc->req_qinfo[i].qid = 0; 4371 mrioc->req_qinfo[i].reply_qid = 0; 4372 spin_lock_init(&mrioc->req_qinfo[i].q_lock); 4373 mpi3mr_memset_op_req_q_buffers(mrioc, i); 4374 } 4375 4376 atomic_set(&mrioc->pend_large_data_sz, 0); 4377 if (mrioc->throttle_groups) { 4378 tg = mrioc->throttle_groups; 4379 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) { 4380 tg->id = 0; 4381 tg->fw_qd = 0; 4382 tg->modified_qd = 0; 4383 tg->io_divert = 0; 4384 tg->need_qd_reduction = 0; 4385 tg->high = 0; 4386 tg->low = 0; 4387 tg->qd_reduction = 0; 4388 atomic_set(&tg->pend_large_data_sz, 0); 4389 } 4390 } 4391 } 4392 4393 /** 4394 * mpi3mr_free_mem - Free memory allocated for a controller 4395 * @mrioc: Adapter instance reference 4396 * 4397 * Free all the memory allocated for a controller. 4398 * 4399 * Return: Nothing. 4400 */ 4401 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) 4402 { 4403 u16 i; 4404 struct mpi3mr_intr_info *intr_info; 4405 4406 mpi3mr_free_enclosure_list(mrioc); 4407 mpi3mr_free_ioctl_dma_memory(mrioc); 4408 4409 if (mrioc->sense_buf_pool) { 4410 if (mrioc->sense_buf) 4411 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf, 4412 mrioc->sense_buf_dma); 4413 dma_pool_destroy(mrioc->sense_buf_pool); 4414 mrioc->sense_buf = NULL; 4415 mrioc->sense_buf_pool = NULL; 4416 } 4417 if (mrioc->sense_buf_q_pool) { 4418 if (mrioc->sense_buf_q) 4419 dma_pool_free(mrioc->sense_buf_q_pool, 4420 mrioc->sense_buf_q, mrioc->sense_buf_q_dma); 4421 dma_pool_destroy(mrioc->sense_buf_q_pool); 4422 mrioc->sense_buf_q = NULL; 4423 mrioc->sense_buf_q_pool = NULL; 4424 } 4425 4426 if (mrioc->reply_buf_pool) { 4427 if (mrioc->reply_buf) 4428 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf, 4429 mrioc->reply_buf_dma); 4430 dma_pool_destroy(mrioc->reply_buf_pool); 4431 mrioc->reply_buf = NULL; 4432 mrioc->reply_buf_pool = NULL; 4433 } 4434 if (mrioc->reply_free_q_pool) { 4435 if (mrioc->reply_free_q) 4436 dma_pool_free(mrioc->reply_free_q_pool, 4437 mrioc->reply_free_q, mrioc->reply_free_q_dma); 4438 dma_pool_destroy(mrioc->reply_free_q_pool); 4439 mrioc->reply_free_q = NULL; 4440 mrioc->reply_free_q_pool = NULL; 4441 } 4442 4443 for (i = 0; i < mrioc->num_op_req_q; i++) 4444 mpi3mr_free_op_req_q_segments(mrioc, i); 4445 4446 for (i = 0; i < mrioc->num_op_reply_q; i++) 4447 mpi3mr_free_op_reply_q_segments(mrioc, i); 4448 4449 for (i = 0; i < mrioc->intr_info_count; i++) { 4450 intr_info = mrioc->intr_info + i; 4451 intr_info->op_reply_q = NULL; 4452 } 4453 4454 kfree(mrioc->req_qinfo); 4455 mrioc->req_qinfo = NULL; 4456 mrioc->num_op_req_q = 0; 4457 4458 kfree(mrioc->op_reply_qinfo); 4459 mrioc->op_reply_qinfo = NULL; 4460 mrioc->num_op_reply_q = 0; 4461 4462 kfree(mrioc->init_cmds.reply); 4463 mrioc->init_cmds.reply = NULL; 4464 4465 kfree(mrioc->bsg_cmds.reply); 4466 mrioc->bsg_cmds.reply = NULL; 4467 4468 kfree(mrioc->host_tm_cmds.reply); 4469 mrioc->host_tm_cmds.reply = NULL; 4470 4471 kfree(mrioc->pel_cmds.reply); 4472 mrioc->pel_cmds.reply = NULL; 4473 4474 kfree(mrioc->pel_abort_cmd.reply); 4475 mrioc->pel_abort_cmd.reply = NULL; 4476 4477 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4478 kfree(mrioc->evtack_cmds[i].reply); 4479 mrioc->evtack_cmds[i].reply = NULL; 4480 } 4481 4482 bitmap_free(mrioc->removepend_bitmap); 4483 mrioc->removepend_bitmap = NULL; 4484 4485 bitmap_free(mrioc->devrem_bitmap); 4486 mrioc->devrem_bitmap = NULL; 4487 4488 bitmap_free(mrioc->evtack_cmds_bitmap); 4489 mrioc->evtack_cmds_bitmap = NULL; 4490 4491 bitmap_free(mrioc->chain_bitmap); 4492 mrioc->chain_bitmap = NULL; 4493 4494 kfree(mrioc->transport_cmds.reply); 4495 mrioc->transport_cmds.reply = NULL; 4496 4497 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4498 kfree(mrioc->dev_rmhs_cmds[i].reply); 4499 mrioc->dev_rmhs_cmds[i].reply = NULL; 4500 } 4501 4502 if (mrioc->chain_buf_pool) { 4503 for (i = 0; i < mrioc->chain_buf_count; i++) { 4504 if (mrioc->chain_sgl_list[i].addr) { 4505 dma_pool_free(mrioc->chain_buf_pool, 4506 mrioc->chain_sgl_list[i].addr, 4507 mrioc->chain_sgl_list[i].dma_addr); 4508 mrioc->chain_sgl_list[i].addr = NULL; 4509 } 4510 } 4511 dma_pool_destroy(mrioc->chain_buf_pool); 4512 mrioc->chain_buf_pool = NULL; 4513 } 4514 4515 kfree(mrioc->chain_sgl_list); 4516 mrioc->chain_sgl_list = NULL; 4517 4518 if (mrioc->admin_reply_base) { 4519 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 4520 mrioc->admin_reply_base, mrioc->admin_reply_dma); 4521 mrioc->admin_reply_base = NULL; 4522 } 4523 if (mrioc->admin_req_base) { 4524 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 4525 mrioc->admin_req_base, mrioc->admin_req_dma); 4526 mrioc->admin_req_base = NULL; 4527 } 4528 if (mrioc->cfg_page) { 4529 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz, 4530 mrioc->cfg_page, mrioc->cfg_page_dma); 4531 mrioc->cfg_page = NULL; 4532 } 4533 if (mrioc->pel_seqnum_virt) { 4534 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz, 4535 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma); 4536 mrioc->pel_seqnum_virt = NULL; 4537 } 4538 4539 kfree(mrioc->throttle_groups); 4540 mrioc->throttle_groups = NULL; 4541 4542 kfree(mrioc->logdata_buf); 4543 mrioc->logdata_buf = NULL; 4544 4545 } 4546 4547 /** 4548 * mpi3mr_issue_ioc_shutdown - shutdown controller 4549 * @mrioc: Adapter instance reference 4550 * 4551 * Send shutodwn notification to the controller and wait for the 4552 * shutdown_timeout for it to be completed. 4553 * 4554 * Return: Nothing. 4555 */ 4556 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) 4557 { 4558 u32 ioc_config, ioc_status; 4559 u8 retval = 1; 4560 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 4561 4562 ioc_info(mrioc, "Issuing shutdown Notification\n"); 4563 if (mrioc->unrecoverable) { 4564 ioc_warn(mrioc, 4565 "IOC is unrecoverable shutdown is not issued\n"); 4566 return; 4567 } 4568 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4569 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4570 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 4571 ioc_info(mrioc, "shutdown already in progress\n"); 4572 return; 4573 } 4574 4575 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4576 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 4577 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 4578 4579 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 4580 4581 if (mrioc->facts.shutdown_timeout) 4582 timeout = mrioc->facts.shutdown_timeout * 10; 4583 4584 do { 4585 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4586 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4587 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 4588 retval = 0; 4589 break; 4590 } 4591 msleep(100); 4592 } while (--timeout); 4593 4594 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4595 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4596 4597 if (retval) { 4598 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4599 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 4600 ioc_warn(mrioc, 4601 "shutdown still in progress after timeout\n"); 4602 } 4603 4604 ioc_info(mrioc, 4605 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n", 4606 (!retval) ? "successful" : "failed", ioc_status, 4607 ioc_config); 4608 } 4609 4610 /** 4611 * mpi3mr_cleanup_ioc - Cleanup controller 4612 * @mrioc: Adapter instance reference 4613 * 4614 * controller cleanup handler, Message unit reset or soft reset 4615 * and shutdown notification is issued to the controller. 4616 * 4617 * Return: Nothing. 4618 */ 4619 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc) 4620 { 4621 enum mpi3mr_iocstate ioc_state; 4622 4623 dprint_exit(mrioc, "cleaning up the controller\n"); 4624 mpi3mr_ioc_disable_intr(mrioc); 4625 4626 ioc_state = mpi3mr_get_iocstate(mrioc); 4627 4628 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) && 4629 (ioc_state == MRIOC_STATE_READY)) { 4630 if (mpi3mr_issue_and_process_mur(mrioc, 4631 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 4632 mpi3mr_issue_reset(mrioc, 4633 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 4634 MPI3MR_RESET_FROM_MUR_FAILURE); 4635 mpi3mr_issue_ioc_shutdown(mrioc); 4636 } 4637 dprint_exit(mrioc, "controller cleanup completed\n"); 4638 } 4639 4640 /** 4641 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 4642 * @mrioc: Adapter instance reference 4643 * @cmdptr: Internal command tracker 4644 * 4645 * Complete an internal driver commands with state indicating it 4646 * is completed due to reset. 4647 * 4648 * Return: Nothing. 4649 */ 4650 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc, 4651 struct mpi3mr_drv_cmd *cmdptr) 4652 { 4653 if (cmdptr->state & MPI3MR_CMD_PENDING) { 4654 cmdptr->state |= MPI3MR_CMD_RESET; 4655 cmdptr->state &= ~MPI3MR_CMD_PENDING; 4656 if (cmdptr->is_waiting) { 4657 complete(&cmdptr->done); 4658 cmdptr->is_waiting = 0; 4659 } else if (cmdptr->callback) 4660 cmdptr->callback(mrioc, cmdptr); 4661 } 4662 } 4663 4664 /** 4665 * mpi3mr_flush_drv_cmds - Flush internaldriver commands 4666 * @mrioc: Adapter instance reference 4667 * 4668 * Flush all internal driver commands post reset 4669 * 4670 * Return: Nothing. 4671 */ 4672 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc) 4673 { 4674 struct mpi3mr_drv_cmd *cmdptr; 4675 u8 i; 4676 4677 cmdptr = &mrioc->init_cmds; 4678 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4679 4680 cmdptr = &mrioc->cfg_cmds; 4681 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4682 4683 cmdptr = &mrioc->bsg_cmds; 4684 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4685 cmdptr = &mrioc->host_tm_cmds; 4686 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4687 4688 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4689 cmdptr = &mrioc->dev_rmhs_cmds[i]; 4690 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4691 } 4692 4693 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4694 cmdptr = &mrioc->evtack_cmds[i]; 4695 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4696 } 4697 4698 cmdptr = &mrioc->pel_cmds; 4699 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4700 4701 cmdptr = &mrioc->pel_abort_cmd; 4702 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4703 4704 cmdptr = &mrioc->transport_cmds; 4705 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4706 } 4707 4708 /** 4709 * mpi3mr_pel_wait_post - Issue PEL Wait 4710 * @mrioc: Adapter instance reference 4711 * @drv_cmd: Internal command tracker 4712 * 4713 * Issue PEL Wait MPI request through admin queue and return. 4714 * 4715 * Return: Nothing. 4716 */ 4717 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc, 4718 struct mpi3mr_drv_cmd *drv_cmd) 4719 { 4720 struct mpi3_pel_req_action_wait pel_wait; 4721 4722 mrioc->pel_abort_requested = false; 4723 4724 memset(&pel_wait, 0, sizeof(pel_wait)); 4725 drv_cmd->state = MPI3MR_CMD_PENDING; 4726 drv_cmd->is_waiting = 0; 4727 drv_cmd->callback = mpi3mr_pel_wait_complete; 4728 drv_cmd->ioc_status = 0; 4729 drv_cmd->ioc_loginfo = 0; 4730 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4731 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4732 pel_wait.action = MPI3_PEL_ACTION_WAIT; 4733 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum); 4734 pel_wait.locale = cpu_to_le16(mrioc->pel_locale); 4735 pel_wait.class = cpu_to_le16(mrioc->pel_class); 4736 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT; 4737 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n", 4738 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale); 4739 4740 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) { 4741 dprint_bsg_err(mrioc, 4742 "Issuing PELWait: Admin post failed\n"); 4743 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4744 drv_cmd->callback = NULL; 4745 drv_cmd->retry_count = 0; 4746 mrioc->pel_enabled = false; 4747 } 4748 } 4749 4750 /** 4751 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number 4752 * @mrioc: Adapter instance reference 4753 * @drv_cmd: Internal command tracker 4754 * 4755 * Issue PEL get sequence number MPI request through admin queue 4756 * and return. 4757 * 4758 * Return: 0 on success, non-zero on failure. 4759 */ 4760 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 4761 struct mpi3mr_drv_cmd *drv_cmd) 4762 { 4763 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req; 4764 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 4765 int retval = 0; 4766 4767 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req)); 4768 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING; 4769 mrioc->pel_cmds.is_waiting = 0; 4770 mrioc->pel_cmds.ioc_status = 0; 4771 mrioc->pel_cmds.ioc_loginfo = 0; 4772 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete; 4773 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4774 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4775 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM; 4776 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags, 4777 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma); 4778 4779 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req, 4780 sizeof(pel_getseq_req), 0); 4781 if (retval) { 4782 if (drv_cmd) { 4783 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4784 drv_cmd->callback = NULL; 4785 drv_cmd->retry_count = 0; 4786 } 4787 mrioc->pel_enabled = false; 4788 } 4789 4790 return retval; 4791 } 4792 4793 /** 4794 * mpi3mr_pel_wait_complete - PELWait Completion callback 4795 * @mrioc: Adapter instance reference 4796 * @drv_cmd: Internal command tracker 4797 * 4798 * This is a callback handler for the PELWait request and 4799 * firmware completes a PELWait request when it is aborted or a 4800 * new PEL entry is available. This sends AEN to the application 4801 * and if the PELwait completion is not due to PELAbort then 4802 * this will send a request for new PEL Sequence number 4803 * 4804 * Return: Nothing. 4805 */ 4806 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 4807 struct mpi3mr_drv_cmd *drv_cmd) 4808 { 4809 struct mpi3_pel_reply *pel_reply = NULL; 4810 u16 ioc_status, pe_log_status; 4811 bool do_retry = false; 4812 4813 if (drv_cmd->state & MPI3MR_CMD_RESET) 4814 goto cleanup_drv_cmd; 4815 4816 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 4817 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 4818 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 4819 __func__, ioc_status, drv_cmd->ioc_loginfo); 4820 dprint_bsg_err(mrioc, 4821 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 4822 ioc_status, drv_cmd->ioc_loginfo); 4823 do_retry = true; 4824 } 4825 4826 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 4827 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 4828 4829 if (!pel_reply) { 4830 dprint_bsg_err(mrioc, 4831 "pel_wait: failed due to no reply\n"); 4832 goto out_failed; 4833 } 4834 4835 pe_log_status = le16_to_cpu(pel_reply->pe_log_status); 4836 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) && 4837 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) { 4838 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n", 4839 __func__, pe_log_status); 4840 dprint_bsg_err(mrioc, 4841 "pel_wait: failed due to pel_log_status(0x%04x)\n", 4842 pe_log_status); 4843 do_retry = true; 4844 } 4845 4846 if (do_retry) { 4847 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 4848 drv_cmd->retry_count++; 4849 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n", 4850 drv_cmd->retry_count); 4851 mpi3mr_pel_wait_post(mrioc, drv_cmd); 4852 return; 4853 } 4854 dprint_bsg_err(mrioc, 4855 "pel_wait: failed after all retries(%d)\n", 4856 drv_cmd->retry_count); 4857 goto out_failed; 4858 } 4859 atomic64_inc(&event_counter); 4860 if (!mrioc->pel_abort_requested) { 4861 mrioc->pel_cmds.retry_count = 0; 4862 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds); 4863 } 4864 4865 return; 4866 out_failed: 4867 mrioc->pel_enabled = false; 4868 cleanup_drv_cmd: 4869 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4870 drv_cmd->callback = NULL; 4871 drv_cmd->retry_count = 0; 4872 } 4873 4874 /** 4875 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback 4876 * @mrioc: Adapter instance reference 4877 * @drv_cmd: Internal command tracker 4878 * 4879 * This is a callback handler for the PEL get sequence number 4880 * request and a new PEL wait request will be issued to the 4881 * firmware from this 4882 * 4883 * Return: Nothing. 4884 */ 4885 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 4886 struct mpi3mr_drv_cmd *drv_cmd) 4887 { 4888 struct mpi3_pel_reply *pel_reply = NULL; 4889 struct mpi3_pel_seq *pel_seqnum_virt; 4890 u16 ioc_status; 4891 bool do_retry = false; 4892 4893 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt; 4894 4895 if (drv_cmd->state & MPI3MR_CMD_RESET) 4896 goto cleanup_drv_cmd; 4897 4898 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 4899 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 4900 dprint_bsg_err(mrioc, 4901 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 4902 ioc_status, drv_cmd->ioc_loginfo); 4903 do_retry = true; 4904 } 4905 4906 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 4907 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 4908 if (!pel_reply) { 4909 dprint_bsg_err(mrioc, 4910 "pel_get_seqnum: failed due to no reply\n"); 4911 goto out_failed; 4912 } 4913 4914 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) { 4915 dprint_bsg_err(mrioc, 4916 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n", 4917 le16_to_cpu(pel_reply->pe_log_status)); 4918 do_retry = true; 4919 } 4920 4921 if (do_retry) { 4922 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 4923 drv_cmd->retry_count++; 4924 dprint_bsg_err(mrioc, 4925 "pel_get_seqnum: retrying(%d)\n", 4926 drv_cmd->retry_count); 4927 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd); 4928 return; 4929 } 4930 4931 dprint_bsg_err(mrioc, 4932 "pel_get_seqnum: failed after all retries(%d)\n", 4933 drv_cmd->retry_count); 4934 goto out_failed; 4935 } 4936 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1; 4937 drv_cmd->retry_count = 0; 4938 mpi3mr_pel_wait_post(mrioc, drv_cmd); 4939 4940 return; 4941 out_failed: 4942 mrioc->pel_enabled = false; 4943 cleanup_drv_cmd: 4944 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4945 drv_cmd->callback = NULL; 4946 drv_cmd->retry_count = 0; 4947 } 4948 4949 /** 4950 * mpi3mr_soft_reset_handler - Reset the controller 4951 * @mrioc: Adapter instance reference 4952 * @reset_reason: Reset reason code 4953 * @snapdump: Flag to generate snapdump in firmware or not 4954 * 4955 * This is an handler for recovering controller by issuing soft 4956 * reset are diag fault reset. This is a blocking function and 4957 * when one reset is executed if any other resets they will be 4958 * blocked. All BSG requests will be blocked during the reset. If 4959 * controller reset is successful then the controller will be 4960 * reinitalized, otherwise the controller will be marked as not 4961 * recoverable 4962 * 4963 * In snapdump bit is set, the controller is issued with diag 4964 * fault reset so that the firmware can create a snap dump and 4965 * post that the firmware will result in F000 fault and the 4966 * driver will issue soft reset to recover from that. 4967 * 4968 * Return: 0 on success, non-zero on failure. 4969 */ 4970 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 4971 u32 reset_reason, u8 snapdump) 4972 { 4973 int retval = 0, i; 4974 unsigned long flags; 4975 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 4976 4977 /* Block the reset handler until diag save in progress*/ 4978 dprint_reset(mrioc, 4979 "soft_reset_handler: check and block on diagsave_timeout(%d)\n", 4980 mrioc->diagsave_timeout); 4981 while (mrioc->diagsave_timeout) 4982 ssleep(1); 4983 /* 4984 * Block new resets until the currently executing one is finished and 4985 * return the status of the existing reset for all blocked resets 4986 */ 4987 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n"); 4988 if (!mutex_trylock(&mrioc->reset_mutex)) { 4989 ioc_info(mrioc, 4990 "controller reset triggered by %s is blocked due to another reset in progress\n", 4991 mpi3mr_reset_rc_name(reset_reason)); 4992 do { 4993 ssleep(1); 4994 } while (mrioc->reset_in_progress == 1); 4995 ioc_info(mrioc, 4996 "returning previous reset result(%d) for the reset triggered by %s\n", 4997 mrioc->prev_reset_result, 4998 mpi3mr_reset_rc_name(reset_reason)); 4999 return mrioc->prev_reset_result; 5000 } 5001 ioc_info(mrioc, "controller reset is triggered by %s\n", 5002 mpi3mr_reset_rc_name(reset_reason)); 5003 5004 mrioc->device_refresh_on = 0; 5005 mrioc->reset_in_progress = 1; 5006 mrioc->stop_bsgs = 1; 5007 mrioc->prev_reset_result = -1; 5008 5009 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 5010 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 5011 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 5012 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5013 mrioc->event_masks[i] = -1; 5014 5015 dprint_reset(mrioc, "soft_reset_handler: masking events\n"); 5016 mpi3mr_issue_event_notification(mrioc); 5017 } 5018 5019 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT); 5020 5021 mpi3mr_ioc_disable_intr(mrioc); 5022 5023 if (snapdump) { 5024 mpi3mr_set_diagsave(mrioc); 5025 retval = mpi3mr_issue_reset(mrioc, 5026 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5027 if (!retval) { 5028 do { 5029 host_diagnostic = 5030 readl(&mrioc->sysif_regs->host_diagnostic); 5031 if (!(host_diagnostic & 5032 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 5033 break; 5034 msleep(100); 5035 } while (--timeout); 5036 } 5037 } 5038 5039 retval = mpi3mr_issue_reset(mrioc, 5040 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 5041 if (retval) { 5042 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n"); 5043 goto out; 5044 } 5045 if (mrioc->num_io_throttle_group != 5046 mrioc->facts.max_io_throttle_group) { 5047 ioc_err(mrioc, 5048 "max io throttle group doesn't match old(%d), new(%d)\n", 5049 mrioc->num_io_throttle_group, 5050 mrioc->facts.max_io_throttle_group); 5051 retval = -EPERM; 5052 goto out; 5053 } 5054 5055 mpi3mr_flush_delayed_cmd_lists(mrioc); 5056 mpi3mr_flush_drv_cmds(mrioc); 5057 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD); 5058 bitmap_clear(mrioc->removepend_bitmap, 0, 5059 mrioc->dev_handle_bitmap_bits); 5060 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD); 5061 mpi3mr_flush_host_io(mrioc); 5062 mpi3mr_cleanup_fwevt_list(mrioc); 5063 mpi3mr_invalidate_devhandles(mrioc); 5064 mpi3mr_free_enclosure_list(mrioc); 5065 5066 if (mrioc->prepare_for_reset) { 5067 mrioc->prepare_for_reset = 0; 5068 mrioc->prepare_for_reset_timeout_counter = 0; 5069 } 5070 mpi3mr_memset_buffers(mrioc); 5071 retval = mpi3mr_reinit_ioc(mrioc, 0); 5072 if (retval) { 5073 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n", 5074 mrioc->name, reset_reason); 5075 goto out; 5076 } 5077 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME); 5078 5079 out: 5080 if (!retval) { 5081 mrioc->diagsave_timeout = 0; 5082 mrioc->reset_in_progress = 0; 5083 mrioc->pel_abort_requested = 0; 5084 if (mrioc->pel_enabled) { 5085 mrioc->pel_cmds.retry_count = 0; 5086 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds); 5087 } 5088 5089 mrioc->device_refresh_on = 0; 5090 5091 mrioc->ts_update_counter = 0; 5092 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 5093 if (mrioc->watchdog_work_q) 5094 queue_delayed_work(mrioc->watchdog_work_q, 5095 &mrioc->watchdog_work, 5096 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 5097 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 5098 mrioc->stop_bsgs = 0; 5099 if (mrioc->pel_enabled) 5100 atomic64_inc(&event_counter); 5101 } else { 5102 mpi3mr_issue_reset(mrioc, 5103 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5104 mrioc->device_refresh_on = 0; 5105 mrioc->unrecoverable = 1; 5106 mrioc->reset_in_progress = 0; 5107 retval = -1; 5108 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 5109 } 5110 mrioc->prev_reset_result = retval; 5111 mutex_unlock(&mrioc->reset_mutex); 5112 ioc_info(mrioc, "controller reset is %s\n", 5113 ((retval == 0) ? "successful" : "failed")); 5114 return retval; 5115 } 5116 5117 5118 /** 5119 * mpi3mr_free_config_dma_memory - free memory for config page 5120 * @mrioc: Adapter instance reference 5121 * @mem_desc: memory descriptor structure 5122 * 5123 * Check whether the size of the buffer specified by the memory 5124 * descriptor is greater than the default page size if so then 5125 * free the memory pointed by the descriptor. 5126 * 5127 * Return: Nothing. 5128 */ 5129 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc, 5130 struct dma_memory_desc *mem_desc) 5131 { 5132 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) { 5133 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 5134 mem_desc->addr, mem_desc->dma_addr); 5135 mem_desc->addr = NULL; 5136 } 5137 } 5138 5139 /** 5140 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page 5141 * @mrioc: Adapter instance reference 5142 * @mem_desc: Memory descriptor to hold dma memory info 5143 * 5144 * This function allocates new dmaable memory or provides the 5145 * default config page dmaable memory based on the memory size 5146 * described by the descriptor. 5147 * 5148 * Return: 0 on success, non-zero on failure. 5149 */ 5150 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc, 5151 struct dma_memory_desc *mem_desc) 5152 { 5153 if (mem_desc->size > mrioc->cfg_page_sz) { 5154 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 5155 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL); 5156 if (!mem_desc->addr) 5157 return -ENOMEM; 5158 } else { 5159 mem_desc->addr = mrioc->cfg_page; 5160 mem_desc->dma_addr = mrioc->cfg_page_dma; 5161 memset(mem_desc->addr, 0, mrioc->cfg_page_sz); 5162 } 5163 return 0; 5164 } 5165 5166 /** 5167 * mpi3mr_post_cfg_req - Issue config requests and wait 5168 * @mrioc: Adapter instance reference 5169 * @cfg_req: Configuration request 5170 * @timeout: Timeout in seconds 5171 * @ioc_status: Pointer to return ioc status 5172 * 5173 * A generic function for posting MPI3 configuration request to 5174 * the firmware. This blocks for the completion of request for 5175 * timeout seconds and if the request times out this function 5176 * faults the controller with proper reason code. 5177 * 5178 * On successful completion of the request this function returns 5179 * appropriate ioc status from the firmware back to the caller. 5180 * 5181 * Return: 0 on success, non-zero on failure. 5182 */ 5183 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc, 5184 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status) 5185 { 5186 int retval = 0; 5187 5188 mutex_lock(&mrioc->cfg_cmds.mutex); 5189 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) { 5190 retval = -1; 5191 ioc_err(mrioc, "sending config request failed due to command in use\n"); 5192 mutex_unlock(&mrioc->cfg_cmds.mutex); 5193 goto out; 5194 } 5195 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING; 5196 mrioc->cfg_cmds.is_waiting = 1; 5197 mrioc->cfg_cmds.callback = NULL; 5198 mrioc->cfg_cmds.ioc_status = 0; 5199 mrioc->cfg_cmds.ioc_loginfo = 0; 5200 5201 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS); 5202 cfg_req->function = MPI3_FUNCTION_CONFIG; 5203 5204 init_completion(&mrioc->cfg_cmds.done); 5205 dprint_cfg_info(mrioc, "posting config request\n"); 5206 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5207 dprint_dump(cfg_req, sizeof(struct mpi3_config_request), 5208 "mpi3_cfg_req"); 5209 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1); 5210 if (retval) { 5211 ioc_err(mrioc, "posting config request failed\n"); 5212 goto out_unlock; 5213 } 5214 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ)); 5215 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) { 5216 mpi3mr_check_rh_fault_ioc(mrioc, 5217 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT); 5218 ioc_err(mrioc, "config request timed out\n"); 5219 retval = -1; 5220 goto out_unlock; 5221 } 5222 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5223 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS) 5224 dprint_cfg_err(mrioc, 5225 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n", 5226 *ioc_status, mrioc->cfg_cmds.ioc_loginfo); 5227 5228 out_unlock: 5229 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED; 5230 mutex_unlock(&mrioc->cfg_cmds.mutex); 5231 5232 out: 5233 return retval; 5234 } 5235 5236 /** 5237 * mpi3mr_process_cfg_req - config page request processor 5238 * @mrioc: Adapter instance reference 5239 * @cfg_req: Configuration request 5240 * @cfg_hdr: Configuration page header 5241 * @timeout: Timeout in seconds 5242 * @ioc_status: Pointer to return ioc status 5243 * @cfg_buf: Memory pointer to copy config page or header 5244 * @cfg_buf_sz: Size of the memory to get config page or header 5245 * 5246 * This is handler for config page read, write and config page 5247 * header read operations. 5248 * 5249 * This function expects the cfg_req to be populated with page 5250 * type, page number, action for the header read and with page 5251 * address for all other operations. 5252 * 5253 * The cfg_hdr can be passed as null for reading required header 5254 * details for read/write pages the cfg_hdr should point valid 5255 * configuration page header. 5256 * 5257 * This allocates dmaable memory based on the size of the config 5258 * buffer and set the SGE of the cfg_req. 5259 * 5260 * For write actions, the config page data has to be passed in 5261 * the cfg_buf and size of the data has to be mentioned in the 5262 * cfg_buf_sz. 5263 * 5264 * For read/header actions, on successful completion of the 5265 * request with successful ioc_status the data will be copied 5266 * into the cfg_buf limited to a minimum of actual page size and 5267 * cfg_buf_sz 5268 * 5269 * 5270 * Return: 0 on success, non-zero on failure. 5271 */ 5272 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc, 5273 struct mpi3_config_request *cfg_req, 5274 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status, 5275 void *cfg_buf, u32 cfg_buf_sz) 5276 { 5277 struct dma_memory_desc mem_desc; 5278 int retval = -1; 5279 u8 invalid_action = 0; 5280 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 5281 5282 memset(&mem_desc, 0, sizeof(struct dma_memory_desc)); 5283 5284 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER) 5285 mem_desc.size = sizeof(struct mpi3_config_page_header); 5286 else { 5287 if (!cfg_hdr) { 5288 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n", 5289 cfg_req->action, cfg_req->page_type, 5290 cfg_req->page_number); 5291 goto out; 5292 } 5293 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) { 5294 case MPI3_CONFIG_PAGEATTR_READ_ONLY: 5295 if (cfg_req->action 5296 != MPI3_CONFIG_ACTION_READ_CURRENT) 5297 invalid_action = 1; 5298 break; 5299 case MPI3_CONFIG_PAGEATTR_CHANGEABLE: 5300 if ((cfg_req->action == 5301 MPI3_CONFIG_ACTION_READ_PERSISTENT) || 5302 (cfg_req->action == 5303 MPI3_CONFIG_ACTION_WRITE_PERSISTENT)) 5304 invalid_action = 1; 5305 break; 5306 case MPI3_CONFIG_PAGEATTR_PERSISTENT: 5307 default: 5308 break; 5309 } 5310 if (invalid_action) { 5311 ioc_err(mrioc, 5312 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n", 5313 cfg_req->action, cfg_req->page_type, 5314 cfg_req->page_number, cfg_hdr->page_attribute); 5315 goto out; 5316 } 5317 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4; 5318 cfg_req->page_length = cfg_hdr->page_length; 5319 cfg_req->page_version = cfg_hdr->page_version; 5320 } 5321 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc)) 5322 goto out; 5323 5324 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size, 5325 mem_desc.dma_addr); 5326 5327 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) || 5328 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5329 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size, 5330 cfg_buf_sz)); 5331 dprint_cfg_info(mrioc, "config buffer to be written\n"); 5332 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5333 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5334 } 5335 5336 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status)) 5337 goto out; 5338 5339 retval = 0; 5340 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) && 5341 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) && 5342 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5343 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size, 5344 cfg_buf_sz)); 5345 dprint_cfg_info(mrioc, "config buffer read\n"); 5346 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5347 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5348 } 5349 5350 out: 5351 mpi3mr_free_config_dma_memory(mrioc, &mem_desc); 5352 return retval; 5353 } 5354 5355 /** 5356 * mpi3mr_cfg_get_dev_pg0 - Read current device page0 5357 * @mrioc: Adapter instance reference 5358 * @ioc_status: Pointer to return ioc status 5359 * @dev_pg0: Pointer to return device page 0 5360 * @pg_sz: Size of the memory allocated to the page pointer 5361 * @form: The form to be used for addressing the page 5362 * @form_spec: Form specific information like device handle 5363 * 5364 * This is handler for config page read for a specific device 5365 * page0. The ioc_status has the controller returned ioc_status. 5366 * This routine doesn't check ioc_status to decide whether the 5367 * page read is success or not and it is the callers 5368 * responsibility. 5369 * 5370 * Return: 0 on success, non-zero on failure. 5371 */ 5372 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5373 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec) 5374 { 5375 struct mpi3_config_page_header cfg_hdr; 5376 struct mpi3_config_request cfg_req; 5377 u32 page_address; 5378 5379 memset(dev_pg0, 0, pg_sz); 5380 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5381 memset(&cfg_req, 0, sizeof(cfg_req)); 5382 5383 cfg_req.function = MPI3_FUNCTION_CONFIG; 5384 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5385 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE; 5386 cfg_req.page_number = 0; 5387 cfg_req.page_address = 0; 5388 5389 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5390 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5391 ioc_err(mrioc, "device page0 header read failed\n"); 5392 goto out_failed; 5393 } 5394 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5395 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n", 5396 *ioc_status); 5397 goto out_failed; 5398 } 5399 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5400 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) | 5401 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK)); 5402 cfg_req.page_address = cpu_to_le32(page_address); 5403 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5404 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) { 5405 ioc_err(mrioc, "device page0 read failed\n"); 5406 goto out_failed; 5407 } 5408 return 0; 5409 out_failed: 5410 return -1; 5411 } 5412 5413 5414 /** 5415 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0 5416 * @mrioc: Adapter instance reference 5417 * @ioc_status: Pointer to return ioc status 5418 * @phy_pg0: Pointer to return SAS Phy page 0 5419 * @pg_sz: Size of the memory allocated to the page pointer 5420 * @form: The form to be used for addressing the page 5421 * @form_spec: Form specific information like phy number 5422 * 5423 * This is handler for config page read for a specific SAS Phy 5424 * page0. The ioc_status has the controller returned ioc_status. 5425 * This routine doesn't check ioc_status to decide whether the 5426 * page read is success or not and it is the callers 5427 * responsibility. 5428 * 5429 * Return: 0 on success, non-zero on failure. 5430 */ 5431 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5432 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 5433 u32 form_spec) 5434 { 5435 struct mpi3_config_page_header cfg_hdr; 5436 struct mpi3_config_request cfg_req; 5437 u32 page_address; 5438 5439 memset(phy_pg0, 0, pg_sz); 5440 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5441 memset(&cfg_req, 0, sizeof(cfg_req)); 5442 5443 cfg_req.function = MPI3_FUNCTION_CONFIG; 5444 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5445 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5446 cfg_req.page_number = 0; 5447 cfg_req.page_address = 0; 5448 5449 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5450 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5451 ioc_err(mrioc, "sas phy page0 header read failed\n"); 5452 goto out_failed; 5453 } 5454 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5455 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n", 5456 *ioc_status); 5457 goto out_failed; 5458 } 5459 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5460 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5461 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5462 cfg_req.page_address = cpu_to_le32(page_address); 5463 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5464 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) { 5465 ioc_err(mrioc, "sas phy page0 read failed\n"); 5466 goto out_failed; 5467 } 5468 return 0; 5469 out_failed: 5470 return -1; 5471 } 5472 5473 /** 5474 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1 5475 * @mrioc: Adapter instance reference 5476 * @ioc_status: Pointer to return ioc status 5477 * @phy_pg1: Pointer to return SAS Phy page 1 5478 * @pg_sz: Size of the memory allocated to the page pointer 5479 * @form: The form to be used for addressing the page 5480 * @form_spec: Form specific information like phy number 5481 * 5482 * This is handler for config page read for a specific SAS Phy 5483 * page1. The ioc_status has the controller returned ioc_status. 5484 * This routine doesn't check ioc_status to decide whether the 5485 * page read is success or not and it is the callers 5486 * responsibility. 5487 * 5488 * Return: 0 on success, non-zero on failure. 5489 */ 5490 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5491 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 5492 u32 form_spec) 5493 { 5494 struct mpi3_config_page_header cfg_hdr; 5495 struct mpi3_config_request cfg_req; 5496 u32 page_address; 5497 5498 memset(phy_pg1, 0, pg_sz); 5499 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5500 memset(&cfg_req, 0, sizeof(cfg_req)); 5501 5502 cfg_req.function = MPI3_FUNCTION_CONFIG; 5503 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5504 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5505 cfg_req.page_number = 1; 5506 cfg_req.page_address = 0; 5507 5508 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5509 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5510 ioc_err(mrioc, "sas phy page1 header read failed\n"); 5511 goto out_failed; 5512 } 5513 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5514 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n", 5515 *ioc_status); 5516 goto out_failed; 5517 } 5518 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5519 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5520 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5521 cfg_req.page_address = cpu_to_le32(page_address); 5522 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5523 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) { 5524 ioc_err(mrioc, "sas phy page1 read failed\n"); 5525 goto out_failed; 5526 } 5527 return 0; 5528 out_failed: 5529 return -1; 5530 } 5531 5532 5533 /** 5534 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0 5535 * @mrioc: Adapter instance reference 5536 * @ioc_status: Pointer to return ioc status 5537 * @exp_pg0: Pointer to return SAS Expander page 0 5538 * @pg_sz: Size of the memory allocated to the page pointer 5539 * @form: The form to be used for addressing the page 5540 * @form_spec: Form specific information like device handle 5541 * 5542 * This is handler for config page read for a specific SAS 5543 * Expander page0. The ioc_status has the controller returned 5544 * ioc_status. This routine doesn't check ioc_status to decide 5545 * whether the page read is success or not and it is the callers 5546 * responsibility. 5547 * 5548 * Return: 0 on success, non-zero on failure. 5549 */ 5550 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5551 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 5552 u32 form_spec) 5553 { 5554 struct mpi3_config_page_header cfg_hdr; 5555 struct mpi3_config_request cfg_req; 5556 u32 page_address; 5557 5558 memset(exp_pg0, 0, pg_sz); 5559 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5560 memset(&cfg_req, 0, sizeof(cfg_req)); 5561 5562 cfg_req.function = MPI3_FUNCTION_CONFIG; 5563 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5564 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5565 cfg_req.page_number = 0; 5566 cfg_req.page_address = 0; 5567 5568 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5569 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5570 ioc_err(mrioc, "expander page0 header read failed\n"); 5571 goto out_failed; 5572 } 5573 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5574 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n", 5575 *ioc_status); 5576 goto out_failed; 5577 } 5578 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5579 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5580 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5581 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5582 cfg_req.page_address = cpu_to_le32(page_address); 5583 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5584 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) { 5585 ioc_err(mrioc, "expander page0 read failed\n"); 5586 goto out_failed; 5587 } 5588 return 0; 5589 out_failed: 5590 return -1; 5591 } 5592 5593 /** 5594 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1 5595 * @mrioc: Adapter instance reference 5596 * @ioc_status: Pointer to return ioc status 5597 * @exp_pg1: Pointer to return SAS Expander page 1 5598 * @pg_sz: Size of the memory allocated to the page pointer 5599 * @form: The form to be used for addressing the page 5600 * @form_spec: Form specific information like phy number 5601 * 5602 * This is handler for config page read for a specific SAS 5603 * Expander page1. The ioc_status has the controller returned 5604 * ioc_status. This routine doesn't check ioc_status to decide 5605 * whether the page read is success or not and it is the callers 5606 * responsibility. 5607 * 5608 * Return: 0 on success, non-zero on failure. 5609 */ 5610 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5611 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 5612 u32 form_spec) 5613 { 5614 struct mpi3_config_page_header cfg_hdr; 5615 struct mpi3_config_request cfg_req; 5616 u32 page_address; 5617 5618 memset(exp_pg1, 0, pg_sz); 5619 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5620 memset(&cfg_req, 0, sizeof(cfg_req)); 5621 5622 cfg_req.function = MPI3_FUNCTION_CONFIG; 5623 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5624 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5625 cfg_req.page_number = 1; 5626 cfg_req.page_address = 0; 5627 5628 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5629 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5630 ioc_err(mrioc, "expander page1 header read failed\n"); 5631 goto out_failed; 5632 } 5633 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5634 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n", 5635 *ioc_status); 5636 goto out_failed; 5637 } 5638 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5639 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5640 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5641 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5642 cfg_req.page_address = cpu_to_le32(page_address); 5643 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5644 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) { 5645 ioc_err(mrioc, "expander page1 read failed\n"); 5646 goto out_failed; 5647 } 5648 return 0; 5649 out_failed: 5650 return -1; 5651 } 5652 5653 /** 5654 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0 5655 * @mrioc: Adapter instance reference 5656 * @ioc_status: Pointer to return ioc status 5657 * @encl_pg0: Pointer to return Enclosure page 0 5658 * @pg_sz: Size of the memory allocated to the page pointer 5659 * @form: The form to be used for addressing the page 5660 * @form_spec: Form specific information like device handle 5661 * 5662 * This is handler for config page read for a specific Enclosure 5663 * page0. The ioc_status has the controller returned ioc_status. 5664 * This routine doesn't check ioc_status to decide whether the 5665 * page read is success or not and it is the callers 5666 * responsibility. 5667 * 5668 * Return: 0 on success, non-zero on failure. 5669 */ 5670 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5671 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 5672 u32 form_spec) 5673 { 5674 struct mpi3_config_page_header cfg_hdr; 5675 struct mpi3_config_request cfg_req; 5676 u32 page_address; 5677 5678 memset(encl_pg0, 0, pg_sz); 5679 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5680 memset(&cfg_req, 0, sizeof(cfg_req)); 5681 5682 cfg_req.function = MPI3_FUNCTION_CONFIG; 5683 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5684 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE; 5685 cfg_req.page_number = 0; 5686 cfg_req.page_address = 0; 5687 5688 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5689 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5690 ioc_err(mrioc, "enclosure page0 header read failed\n"); 5691 goto out_failed; 5692 } 5693 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5694 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n", 5695 *ioc_status); 5696 goto out_failed; 5697 } 5698 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5699 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) | 5700 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK)); 5701 cfg_req.page_address = cpu_to_le32(page_address); 5702 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5703 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) { 5704 ioc_err(mrioc, "enclosure page0 read failed\n"); 5705 goto out_failed; 5706 } 5707 return 0; 5708 out_failed: 5709 return -1; 5710 } 5711 5712 5713 /** 5714 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0 5715 * @mrioc: Adapter instance reference 5716 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0 5717 * @pg_sz: Size of the memory allocated to the page pointer 5718 * 5719 * This is handler for config page read for the SAS IO Unit 5720 * page0. This routine checks ioc_status to decide whether the 5721 * page read is success or not. 5722 * 5723 * Return: 0 on success, non-zero on failure. 5724 */ 5725 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 5726 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz) 5727 { 5728 struct mpi3_config_page_header cfg_hdr; 5729 struct mpi3_config_request cfg_req; 5730 u16 ioc_status = 0; 5731 5732 memset(sas_io_unit_pg0, 0, pg_sz); 5733 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5734 memset(&cfg_req, 0, sizeof(cfg_req)); 5735 5736 cfg_req.function = MPI3_FUNCTION_CONFIG; 5737 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5738 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5739 cfg_req.page_number = 0; 5740 cfg_req.page_address = 0; 5741 5742 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5743 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5744 ioc_err(mrioc, "sas io unit page0 header read failed\n"); 5745 goto out_failed; 5746 } 5747 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5748 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n", 5749 ioc_status); 5750 goto out_failed; 5751 } 5752 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5753 5754 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5755 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) { 5756 ioc_err(mrioc, "sas io unit page0 read failed\n"); 5757 goto out_failed; 5758 } 5759 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5760 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n", 5761 ioc_status); 5762 goto out_failed; 5763 } 5764 return 0; 5765 out_failed: 5766 return -1; 5767 } 5768 5769 /** 5770 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1 5771 * @mrioc: Adapter instance reference 5772 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1 5773 * @pg_sz: Size of the memory allocated to the page pointer 5774 * 5775 * This is handler for config page read for the SAS IO Unit 5776 * page1. This routine checks ioc_status to decide whether the 5777 * page read is success or not. 5778 * 5779 * Return: 0 on success, non-zero on failure. 5780 */ 5781 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 5782 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 5783 { 5784 struct mpi3_config_page_header cfg_hdr; 5785 struct mpi3_config_request cfg_req; 5786 u16 ioc_status = 0; 5787 5788 memset(sas_io_unit_pg1, 0, pg_sz); 5789 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5790 memset(&cfg_req, 0, sizeof(cfg_req)); 5791 5792 cfg_req.function = MPI3_FUNCTION_CONFIG; 5793 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5794 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5795 cfg_req.page_number = 1; 5796 cfg_req.page_address = 0; 5797 5798 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5799 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5800 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 5801 goto out_failed; 5802 } 5803 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5804 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 5805 ioc_status); 5806 goto out_failed; 5807 } 5808 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5809 5810 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5811 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5812 ioc_err(mrioc, "sas io unit page1 read failed\n"); 5813 goto out_failed; 5814 } 5815 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5816 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n", 5817 ioc_status); 5818 goto out_failed; 5819 } 5820 return 0; 5821 out_failed: 5822 return -1; 5823 } 5824 5825 /** 5826 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1 5827 * @mrioc: Adapter instance reference 5828 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write 5829 * @pg_sz: Size of the memory allocated to the page pointer 5830 * 5831 * This is handler for config page write for the SAS IO Unit 5832 * page1. This routine checks ioc_status to decide whether the 5833 * page read is success or not. This will modify both current 5834 * and persistent page. 5835 * 5836 * Return: 0 on success, non-zero on failure. 5837 */ 5838 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 5839 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 5840 { 5841 struct mpi3_config_page_header cfg_hdr; 5842 struct mpi3_config_request cfg_req; 5843 u16 ioc_status = 0; 5844 5845 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5846 memset(&cfg_req, 0, sizeof(cfg_req)); 5847 5848 cfg_req.function = MPI3_FUNCTION_CONFIG; 5849 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5850 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5851 cfg_req.page_number = 1; 5852 cfg_req.page_address = 0; 5853 5854 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5855 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5856 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 5857 goto out_failed; 5858 } 5859 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5860 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 5861 ioc_status); 5862 goto out_failed; 5863 } 5864 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT; 5865 5866 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5867 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5868 ioc_err(mrioc, "sas io unit page1 write current failed\n"); 5869 goto out_failed; 5870 } 5871 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5872 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n", 5873 ioc_status); 5874 goto out_failed; 5875 } 5876 5877 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT; 5878 5879 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5880 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5881 ioc_err(mrioc, "sas io unit page1 write persistent failed\n"); 5882 goto out_failed; 5883 } 5884 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5885 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n", 5886 ioc_status); 5887 goto out_failed; 5888 } 5889 return 0; 5890 out_failed: 5891 return -1; 5892 } 5893 5894 /** 5895 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1 5896 * @mrioc: Adapter instance reference 5897 * @driver_pg1: Pointer to return Driver page 1 5898 * @pg_sz: Size of the memory allocated to the page pointer 5899 * 5900 * This is handler for config page read for the Driver page1. 5901 * This routine checks ioc_status to decide whether the page 5902 * read is success or not. 5903 * 5904 * Return: 0 on success, non-zero on failure. 5905 */ 5906 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 5907 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz) 5908 { 5909 struct mpi3_config_page_header cfg_hdr; 5910 struct mpi3_config_request cfg_req; 5911 u16 ioc_status = 0; 5912 5913 memset(driver_pg1, 0, pg_sz); 5914 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5915 memset(&cfg_req, 0, sizeof(cfg_req)); 5916 5917 cfg_req.function = MPI3_FUNCTION_CONFIG; 5918 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5919 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER; 5920 cfg_req.page_number = 1; 5921 cfg_req.page_address = 0; 5922 5923 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5924 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5925 ioc_err(mrioc, "driver page1 header read failed\n"); 5926 goto out_failed; 5927 } 5928 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5929 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n", 5930 ioc_status); 5931 goto out_failed; 5932 } 5933 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5934 5935 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5936 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) { 5937 ioc_err(mrioc, "driver page1 read failed\n"); 5938 goto out_failed; 5939 } 5940 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5941 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n", 5942 ioc_status); 5943 goto out_failed; 5944 } 5945 return 0; 5946 out_failed: 5947 return -1; 5948 } 5949