1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2003 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#250 $ 41 */ 42 43 #ifdef __linux__ 44 #include "aic79xx_osm.h" 45 #include "aic79xx_inline.h" 46 #include "aicasm/aicasm_insformat.h" 47 #else 48 #include <dev/aic7xxx/aic79xx_osm.h> 49 #include <dev/aic7xxx/aic79xx_inline.h> 50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 51 #endif 52 53 54 /***************************** Lookup Tables **********************************/ 55 char *ahd_chip_names[] = 56 { 57 "NONE", 58 "aic7901", 59 "aic7902", 60 "aic7901A" 61 }; 62 static const u_int num_chip_names = ARRAY_SIZE(ahd_chip_names); 63 64 /* 65 * Hardware error codes. 66 */ 67 struct ahd_hard_error_entry { 68 uint8_t errno; 69 char *errmesg; 70 }; 71 72 static struct ahd_hard_error_entry ahd_hard_errors[] = { 73 { DSCTMOUT, "Discard Timer has timed out" }, 74 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 75 { SQPARERR, "Sequencer Parity Error" }, 76 { DPARERR, "Data-path Parity Error" }, 77 { MPARERR, "Scratch or SCB Memory Parity Error" }, 78 { CIOPARERR, "CIOBUS Parity Error" }, 79 }; 80 static const u_int num_errors = ARRAY_SIZE(ahd_hard_errors); 81 82 static struct ahd_phase_table_entry ahd_phase_table[] = 83 { 84 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 85 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 86 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 87 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 88 { P_COMMAND, MSG_NOOP, "in Command phase" }, 89 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 90 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 91 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 92 { P_BUSFREE, MSG_NOOP, "while idle" }, 93 { 0, MSG_NOOP, "in unknown phase" } 94 }; 95 96 /* 97 * In most cases we only wish to itterate over real phases, so 98 * exclude the last element from the count. 99 */ 100 static const u_int num_phases = ARRAY_SIZE(ahd_phase_table) - 1; 101 102 /* Our Sequencer Program */ 103 #include "aic79xx_seq.h" 104 105 /**************************** Function Declarations ***************************/ 106 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 107 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 108 u_int lqistat1); 109 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 110 u_int busfreetime); 111 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 112 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 113 static void ahd_force_renegotiation(struct ahd_softc *ahd, 114 struct ahd_devinfo *devinfo); 115 116 static struct ahd_tmode_tstate* 117 ahd_alloc_tstate(struct ahd_softc *ahd, 118 u_int scsi_id, char channel); 119 #ifdef AHD_TARGET_MODE 120 static void ahd_free_tstate(struct ahd_softc *ahd, 121 u_int scsi_id, char channel, int force); 122 #endif 123 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 124 struct ahd_initiator_tinfo *, 125 u_int *period, 126 u_int *ppr_options, 127 role_t role); 128 static void ahd_update_neg_table(struct ahd_softc *ahd, 129 struct ahd_devinfo *devinfo, 130 struct ahd_transinfo *tinfo); 131 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 132 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 133 struct ahd_devinfo *devinfo); 134 static void ahd_scb_devinfo(struct ahd_softc *ahd, 135 struct ahd_devinfo *devinfo, 136 struct scb *scb); 137 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 138 struct ahd_devinfo *devinfo, 139 struct scb *scb); 140 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 141 struct ahd_devinfo *devinfo); 142 static void ahd_construct_sdtr(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo, 144 u_int period, u_int offset); 145 static void ahd_construct_wdtr(struct ahd_softc *ahd, 146 struct ahd_devinfo *devinfo, 147 u_int bus_width); 148 static void ahd_construct_ppr(struct ahd_softc *ahd, 149 struct ahd_devinfo *devinfo, 150 u_int period, u_int offset, 151 u_int bus_width, u_int ppr_options); 152 static void ahd_clear_msg_state(struct ahd_softc *ahd); 153 static void ahd_handle_message_phase(struct ahd_softc *ahd); 154 typedef enum { 155 AHDMSG_1B, 156 AHDMSG_2B, 157 AHDMSG_EXT 158 } ahd_msgtype; 159 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 160 u_int msgval, int full); 161 static int ahd_parse_msg(struct ahd_softc *ahd, 162 struct ahd_devinfo *devinfo); 163 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 164 struct ahd_devinfo *devinfo); 165 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 166 struct ahd_devinfo *devinfo); 167 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 168 static void ahd_handle_devreset(struct ahd_softc *ahd, 169 struct ahd_devinfo *devinfo, 170 u_int lun, cam_status status, 171 char *message, int verbose_level); 172 #ifdef AHD_TARGET_MODE 173 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo, 175 struct scb *scb); 176 #endif 177 178 static u_int ahd_sglist_size(struct ahd_softc *ahd); 179 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 180 static bus_dmamap_callback_t 181 ahd_dmamap_cb; 182 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 183 static int ahd_init_scbdata(struct ahd_softc *ahd); 184 static void ahd_fini_scbdata(struct ahd_softc *ahd); 185 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 186 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 187 static void ahd_add_col_list(struct ahd_softc *ahd, 188 struct scb *scb, u_int col_idx); 189 static void ahd_rem_col_list(struct ahd_softc *ahd, 190 struct scb *scb); 191 static void ahd_chip_init(struct ahd_softc *ahd); 192 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 193 struct scb *prev_scb, 194 struct scb *scb); 195 static int ahd_qinfifo_count(struct ahd_softc *ahd); 196 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 197 char channel, int lun, u_int tag, 198 role_t role, uint32_t status, 199 ahd_search_action action, 200 u_int *list_head, u_int *list_tail, 201 u_int tid); 202 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 203 u_int tid_prev, u_int tid_cur, 204 u_int tid_next); 205 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 206 u_int scbid); 207 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 208 u_int prev, u_int next, u_int tid); 209 static void ahd_reset_current_bus(struct ahd_softc *ahd); 210 static ahd_callback_t ahd_stat_timer; 211 #ifdef AHD_DUMP_SEQ 212 static void ahd_dumpseq(struct ahd_softc *ahd); 213 #endif 214 static void ahd_loadseq(struct ahd_softc *ahd); 215 static int ahd_check_patch(struct ahd_softc *ahd, 216 struct patch **start_patch, 217 u_int start_instr, u_int *skip_addr); 218 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 219 u_int address); 220 static void ahd_download_instr(struct ahd_softc *ahd, 221 u_int instrptr, uint8_t *dconsts); 222 static int ahd_probe_stack_size(struct ahd_softc *ahd); 223 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd, 224 struct scb *scb); 225 static void ahd_run_data_fifo(struct ahd_softc *ahd, 226 struct scb *scb); 227 228 #ifdef AHD_TARGET_MODE 229 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 230 struct ahd_tmode_lstate *lstate, 231 u_int initiator_id, 232 u_int event_type, 233 u_int event_arg); 234 static void ahd_update_scsiid(struct ahd_softc *ahd, 235 u_int targid_mask); 236 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 237 struct target_cmd *cmd); 238 #endif 239 240 /******************************** Private Inlines *****************************/ 241 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 242 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 243 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 244 245 static __inline void 246 ahd_assert_atn(struct ahd_softc *ahd) 247 { 248 ahd_outb(ahd, SCSISIGO, ATNO); 249 } 250 251 /* 252 * Determine if the current connection has a packetized 253 * agreement. This does not necessarily mean that we 254 * are currently in a packetized transfer. We could 255 * just as easily be sending or receiving a message. 256 */ 257 static __inline int 258 ahd_currently_packetized(struct ahd_softc *ahd) 259 { 260 ahd_mode_state saved_modes; 261 int packetized; 262 263 saved_modes = ahd_save_modes(ahd); 264 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 265 /* 266 * The packetized bit refers to the last 267 * connection, not the current one. Check 268 * for non-zero LQISTATE instead. 269 */ 270 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 271 packetized = ahd_inb(ahd, LQISTATE) != 0; 272 } else { 273 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 274 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 275 } 276 ahd_restore_modes(ahd, saved_modes); 277 return (packetized); 278 } 279 280 static __inline int 281 ahd_set_active_fifo(struct ahd_softc *ahd) 282 { 283 u_int active_fifo; 284 285 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 286 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 287 switch (active_fifo) { 288 case 0: 289 case 1: 290 ahd_set_modes(ahd, active_fifo, active_fifo); 291 return (1); 292 default: 293 return (0); 294 } 295 } 296 297 /************************* Sequencer Execution Control ************************/ 298 /* 299 * Restart the sequencer program from address zero 300 */ 301 void 302 ahd_restart(struct ahd_softc *ahd) 303 { 304 305 ahd_pause(ahd); 306 307 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 308 309 /* No more pending messages */ 310 ahd_clear_msg_state(ahd); 311 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 312 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 313 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 314 ahd_outb(ahd, SEQINTCTL, 0); 315 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 316 ahd_outb(ahd, SEQ_FLAGS, 0); 317 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 318 ahd_outb(ahd, SAVED_LUN, 0xFF); 319 320 /* 321 * Ensure that the sequencer's idea of TQINPOS 322 * matches our own. The sequencer increments TQINPOS 323 * only after it sees a DMA complete and a reset could 324 * occur before the increment leaving the kernel to believe 325 * the command arrived but the sequencer to not. 326 */ 327 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 328 329 /* Always allow reselection */ 330 ahd_outb(ahd, SCSISEQ1, 331 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 332 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 333 334 /* 335 * Clear any pending sequencer interrupt. It is no 336 * longer relevant since we're resetting the Program 337 * Counter. 338 */ 339 ahd_outb(ahd, CLRINT, CLRSEQINT); 340 341 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 342 ahd_unpause(ahd); 343 } 344 345 void 346 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 347 { 348 ahd_mode_state saved_modes; 349 350 #ifdef AHD_DEBUG 351 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 352 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 353 #endif 354 saved_modes = ahd_save_modes(ahd); 355 ahd_set_modes(ahd, fifo, fifo); 356 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 357 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 358 ahd_outb(ahd, CCSGCTL, CCSGRESET); 359 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 360 ahd_outb(ahd, SG_STATE, 0); 361 ahd_restore_modes(ahd, saved_modes); 362 } 363 364 /************************* Input/Output Queues ********************************/ 365 /* 366 * Flush and completed commands that are sitting in the command 367 * complete queues down on the chip but have yet to be dma'ed back up. 368 */ 369 void 370 ahd_flush_qoutfifo(struct ahd_softc *ahd) 371 { 372 struct scb *scb; 373 ahd_mode_state saved_modes; 374 u_int saved_scbptr; 375 u_int ccscbctl; 376 u_int scbid; 377 u_int next_scbid; 378 379 saved_modes = ahd_save_modes(ahd); 380 381 /* 382 * Flush the good status FIFO for completed packetized commands. 383 */ 384 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 385 saved_scbptr = ahd_get_scbptr(ahd); 386 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 387 u_int fifo_mode; 388 u_int i; 389 390 scbid = ahd_inw(ahd, GSFIFO); 391 scb = ahd_lookup_scb(ahd, scbid); 392 if (scb == NULL) { 393 printf("%s: Warning - GSFIFO SCB %d invalid\n", 394 ahd_name(ahd), scbid); 395 continue; 396 } 397 /* 398 * Determine if this transaction is still active in 399 * any FIFO. If it is, we must flush that FIFO to 400 * the host before completing the command. 401 */ 402 fifo_mode = 0; 403 rescan_fifos: 404 for (i = 0; i < 2; i++) { 405 /* Toggle to the other mode. */ 406 fifo_mode ^= 1; 407 ahd_set_modes(ahd, fifo_mode, fifo_mode); 408 409 if (ahd_scb_active_in_fifo(ahd, scb) == 0) 410 continue; 411 412 ahd_run_data_fifo(ahd, scb); 413 414 /* 415 * Running this FIFO may cause a CFG4DATA for 416 * this same transaction to assert in the other 417 * FIFO or a new snapshot SAVEPTRS interrupt 418 * in this FIFO. Even running a FIFO may not 419 * clear the transaction if we are still waiting 420 * for data to drain to the host. We must loop 421 * until the transaction is not active in either 422 * FIFO just to be sure. Reset our loop counter 423 * so we will visit both FIFOs again before 424 * declaring this transaction finished. We 425 * also delay a bit so that status has a chance 426 * to change before we look at this FIFO again. 427 */ 428 ahd_delay(200); 429 goto rescan_fifos; 430 } 431 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 432 ahd_set_scbptr(ahd, scbid); 433 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0 434 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0 435 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR) 436 & SG_LIST_NULL) != 0)) { 437 u_int comp_head; 438 439 /* 440 * The transfer completed with a residual. 441 * Place this SCB on the complete DMA list 442 * so that we update our in-core copy of the 443 * SCB before completing the command. 444 */ 445 ahd_outb(ahd, SCB_SCSI_STATUS, 0); 446 ahd_outb(ahd, SCB_SGPTR, 447 ahd_inb_scbram(ahd, SCB_SGPTR) 448 | SG_STATUS_VALID); 449 ahd_outw(ahd, SCB_TAG, scbid); 450 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL); 451 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 452 if (SCBID_IS_NULL(comp_head)) { 453 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid); 454 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 455 } else { 456 u_int tail; 457 458 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL); 459 ahd_set_scbptr(ahd, tail); 460 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid); 461 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 462 ahd_set_scbptr(ahd, scbid); 463 } 464 } else 465 ahd_complete_scb(ahd, scb); 466 } 467 ahd_set_scbptr(ahd, saved_scbptr); 468 469 /* 470 * Setup for command channel portion of flush. 471 */ 472 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 473 474 /* 475 * Wait for any inprogress DMA to complete and clear DMA state 476 * if this if for an SCB in the qinfifo. 477 */ 478 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 479 480 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 481 if ((ccscbctl & ARRDONE) != 0) 482 break; 483 } else if ((ccscbctl & CCSCBDONE) != 0) 484 break; 485 ahd_delay(200); 486 } 487 /* 488 * We leave the sequencer to cleanup in the case of DMA's to 489 * update the qoutfifo. In all other cases (DMA's to the 490 * chip or a push of an SCB from the COMPLETE_DMA_SCB list), 491 * we disable the DMA engine so that the sequencer will not 492 * attempt to handle the DMA completion. 493 */ 494 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0) 495 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 496 497 /* 498 * Complete any SCBs that just finished 499 * being DMA'ed into the qoutfifo. 500 */ 501 ahd_run_qoutfifo(ahd); 502 503 saved_scbptr = ahd_get_scbptr(ahd); 504 /* 505 * Manually update/complete any completed SCBs that are waiting to be 506 * DMA'ed back up to the host. 507 */ 508 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 509 while (!SCBID_IS_NULL(scbid)) { 510 uint8_t *hscb_ptr; 511 u_int i; 512 513 ahd_set_scbptr(ahd, scbid); 514 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 515 scb = ahd_lookup_scb(ahd, scbid); 516 if (scb == NULL) { 517 printf("%s: Warning - DMA-up and complete " 518 "SCB %d invalid\n", ahd_name(ahd), scbid); 519 continue; 520 } 521 hscb_ptr = (uint8_t *)scb->hscb; 522 for (i = 0; i < sizeof(struct hardware_scb); i++) 523 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 524 525 ahd_complete_scb(ahd, scb); 526 scbid = next_scbid; 527 } 528 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 529 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 530 531 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 532 while (!SCBID_IS_NULL(scbid)) { 533 534 ahd_set_scbptr(ahd, scbid); 535 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 536 scb = ahd_lookup_scb(ahd, scbid); 537 if (scb == NULL) { 538 printf("%s: Warning - Complete Qfrz SCB %d invalid\n", 539 ahd_name(ahd), scbid); 540 continue; 541 } 542 543 ahd_complete_scb(ahd, scb); 544 scbid = next_scbid; 545 } 546 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 547 548 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 549 while (!SCBID_IS_NULL(scbid)) { 550 551 ahd_set_scbptr(ahd, scbid); 552 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 553 scb = ahd_lookup_scb(ahd, scbid); 554 if (scb == NULL) { 555 printf("%s: Warning - Complete SCB %d invalid\n", 556 ahd_name(ahd), scbid); 557 continue; 558 } 559 560 ahd_complete_scb(ahd, scb); 561 scbid = next_scbid; 562 } 563 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 564 565 /* 566 * Restore state. 567 */ 568 ahd_set_scbptr(ahd, saved_scbptr); 569 ahd_restore_modes(ahd, saved_modes); 570 ahd->flags |= AHD_UPDATE_PEND_CMDS; 571 } 572 573 /* 574 * Determine if an SCB for a packetized transaction 575 * is active in a FIFO. 576 */ 577 static int 578 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb) 579 { 580 581 /* 582 * The FIFO is only active for our transaction if 583 * the SCBPTR matches the SCB's ID and the firmware 584 * has installed a handler for the FIFO or we have 585 * a pending SAVEPTRS or CFG4DATA interrupt. 586 */ 587 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb) 588 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0 589 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0)) 590 return (0); 591 592 return (1); 593 } 594 595 /* 596 * Run a data fifo to completion for a transaction we know 597 * has completed across the SCSI bus (good status has been 598 * received). We are already set to the correct FIFO mode 599 * on entry to this routine. 600 * 601 * This function attempts to operate exactly as the firmware 602 * would when running this FIFO. Care must be taken to update 603 * this routine any time the firmware's FIFO algorithm is 604 * changed. 605 */ 606 static void 607 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb) 608 { 609 u_int seqintsrc; 610 611 seqintsrc = ahd_inb(ahd, SEQINTSRC); 612 if ((seqintsrc & CFG4DATA) != 0) { 613 uint32_t datacnt; 614 uint32_t sgptr; 615 616 /* 617 * Clear full residual flag. 618 */ 619 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID; 620 ahd_outb(ahd, SCB_SGPTR, sgptr); 621 622 /* 623 * Load datacnt and address. 624 */ 625 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT); 626 if ((datacnt & AHD_DMA_LAST_SEG) != 0) { 627 sgptr |= LAST_SEG; 628 ahd_outb(ahd, SG_STATE, 0); 629 } else 630 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 631 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR)); 632 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK); 633 ahd_outb(ahd, SG_CACHE_PRE, sgptr); 634 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 635 636 /* 637 * Initialize Residual Fields. 638 */ 639 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24); 640 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK); 641 642 /* 643 * Mark the SCB as having a FIFO in use. 644 */ 645 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 646 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1); 647 648 /* 649 * Install a "fake" handler for this FIFO. 650 */ 651 ahd_outw(ahd, LONGJMP_ADDR, 0); 652 653 /* 654 * Notify the hardware that we have satisfied 655 * this sequencer interrupt. 656 */ 657 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA); 658 } else if ((seqintsrc & SAVEPTRS) != 0) { 659 uint32_t sgptr; 660 uint32_t resid; 661 662 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) { 663 /* 664 * Snapshot Save Pointers. All that 665 * is necessary to clear the snapshot 666 * is a CLRCHN. 667 */ 668 goto clrchn; 669 } 670 671 /* 672 * Disable S/G fetch so the DMA engine 673 * is available to future users. 674 */ 675 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 676 ahd_outb(ahd, CCSGCTL, 0); 677 ahd_outb(ahd, SG_STATE, 0); 678 679 /* 680 * Flush the data FIFO. Strickly only 681 * necessary for Rev A parts. 682 */ 683 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH); 684 685 /* 686 * Calculate residual. 687 */ 688 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 689 resid = ahd_inl(ahd, SHCNT); 690 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24; 691 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid); 692 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) { 693 /* 694 * Must back up to the correct S/G element. 695 * Typically this just means resetting our 696 * low byte to the offset in the SG_CACHE, 697 * but if we wrapped, we have to correct 698 * the other bytes of the sgptr too. 699 */ 700 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0 701 && (sgptr & 0x80) == 0) 702 sgptr -= 0x100; 703 sgptr &= ~0xFF; 704 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW) 705 & SG_ADDR_MASK; 706 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 707 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0); 708 } else if ((resid & AHD_SG_LEN_MASK) == 0) { 709 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, 710 sgptr | SG_LIST_NULL); 711 } 712 /* 713 * Save Pointers. 714 */ 715 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR)); 716 ahd_outl(ahd, SCB_DATACNT, resid); 717 ahd_outl(ahd, SCB_SGPTR, sgptr); 718 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS); 719 ahd_outb(ahd, SEQIMODE, 720 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS); 721 /* 722 * If the data is to the SCSI bus, we are 723 * done, otherwise wait for FIFOEMP. 724 */ 725 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0) 726 goto clrchn; 727 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) { 728 uint32_t sgptr; 729 uint64_t data_addr; 730 uint32_t data_len; 731 u_int dfcntrl; 732 733 /* 734 * Disable S/G fetch so the DMA engine 735 * is available to future users. We won't 736 * be using the DMA engine to load segments. 737 */ 738 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) { 739 ahd_outb(ahd, CCSGCTL, 0); 740 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 741 } 742 743 /* 744 * Wait for the DMA engine to notice that the 745 * host transfer is enabled and that there is 746 * space in the S/G FIFO for new segments before 747 * loading more segments. 748 */ 749 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0 750 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) { 751 752 /* 753 * Determine the offset of the next S/G 754 * element to load. 755 */ 756 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 757 sgptr &= SG_PTR_MASK; 758 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 759 struct ahd_dma64_seg *sg; 760 761 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 762 data_addr = sg->addr; 763 data_len = sg->len; 764 sgptr += sizeof(*sg); 765 } else { 766 struct ahd_dma_seg *sg; 767 768 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 769 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK; 770 data_addr <<= 8; 771 data_addr |= sg->addr; 772 data_len = sg->len; 773 sgptr += sizeof(*sg); 774 } 775 776 /* 777 * Update residual information. 778 */ 779 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24); 780 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 781 782 /* 783 * Load the S/G. 784 */ 785 if (data_len & AHD_DMA_LAST_SEG) { 786 sgptr |= LAST_SEG; 787 ahd_outb(ahd, SG_STATE, 0); 788 } 789 ahd_outq(ahd, HADDR, data_addr); 790 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK); 791 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF); 792 793 /* 794 * Advertise the segment to the hardware. 795 */ 796 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN; 797 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) { 798 /* 799 * Use SCSIENWRDIS so that SCSIEN 800 * is never modified by this 801 * operation. 802 */ 803 dfcntrl |= SCSIENWRDIS; 804 } 805 ahd_outb(ahd, DFCNTRL, dfcntrl); 806 } 807 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) { 808 809 /* 810 * Transfer completed to the end of SG list 811 * and has flushed to the host. 812 */ 813 ahd_outb(ahd, SCB_SGPTR, 814 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL); 815 goto clrchn; 816 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) { 817 clrchn: 818 /* 819 * Clear any handler for this FIFO, decrement 820 * the FIFO use count for the SCB, and release 821 * the FIFO. 822 */ 823 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 824 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 825 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1); 826 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 827 } 828 } 829 830 /* 831 * Look for entries in the QoutFIFO that have completed. 832 * The valid_tag completion field indicates the validity 833 * of the entry - the valid value toggles each time through 834 * the queue. We use the sg_status field in the completion 835 * entry to avoid referencing the hscb if the completion 836 * occurred with no errors and no residual. sg_status is 837 * a copy of the first byte (little endian) of the sgptr 838 * hscb field. 839 */ 840 void 841 ahd_run_qoutfifo(struct ahd_softc *ahd) 842 { 843 struct ahd_completion *completion; 844 struct scb *scb; 845 u_int scb_index; 846 847 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 848 panic("ahd_run_qoutfifo recursion"); 849 ahd->flags |= AHD_RUNNING_QOUTFIFO; 850 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 851 for (;;) { 852 completion = &ahd->qoutfifo[ahd->qoutfifonext]; 853 854 if (completion->valid_tag != ahd->qoutfifonext_valid_tag) 855 break; 856 857 scb_index = ahd_le16toh(completion->tag); 858 scb = ahd_lookup_scb(ahd, scb_index); 859 if (scb == NULL) { 860 printf("%s: WARNING no command for scb %d " 861 "(cmdcmplt)\nQOUTPOS = %d\n", 862 ahd_name(ahd), scb_index, 863 ahd->qoutfifonext); 864 ahd_dump_card_state(ahd); 865 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) { 866 ahd_handle_scb_status(ahd, scb); 867 } else { 868 ahd_done(ahd, scb); 869 } 870 871 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 872 if (ahd->qoutfifonext == 0) 873 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID; 874 } 875 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 876 } 877 878 /************************* Interrupt Handling *********************************/ 879 void 880 ahd_handle_hwerrint(struct ahd_softc *ahd) 881 { 882 /* 883 * Some catastrophic hardware error has occurred. 884 * Print it for the user and disable the controller. 885 */ 886 int i; 887 int error; 888 889 error = ahd_inb(ahd, ERROR); 890 for (i = 0; i < num_errors; i++) { 891 if ((error & ahd_hard_errors[i].errno) != 0) 892 printf("%s: hwerrint, %s\n", 893 ahd_name(ahd), ahd_hard_errors[i].errmesg); 894 } 895 896 ahd_dump_card_state(ahd); 897 panic("BRKADRINT"); 898 899 /* Tell everyone that this HBA is no longer available */ 900 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 901 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 902 CAM_NO_HBA); 903 904 /* Tell the system that this controller has gone away. */ 905 ahd_free(ahd); 906 } 907 908 void 909 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 910 { 911 u_int seqintcode; 912 913 /* 914 * Save the sequencer interrupt code and clear the SEQINT 915 * bit. We will unpause the sequencer, if appropriate, 916 * after servicing the request. 917 */ 918 seqintcode = ahd_inb(ahd, SEQINTCODE); 919 ahd_outb(ahd, CLRINT, CLRSEQINT); 920 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 921 /* 922 * Unpause the sequencer and let it clear 923 * SEQINT by writing NO_SEQINT to it. This 924 * will cause the sequencer to be paused again, 925 * which is the expected state of this routine. 926 */ 927 ahd_unpause(ahd); 928 while (!ahd_is_paused(ahd)) 929 ; 930 ahd_outb(ahd, CLRINT, CLRSEQINT); 931 } 932 ahd_update_modes(ahd); 933 #ifdef AHD_DEBUG 934 if ((ahd_debug & AHD_SHOW_MISC) != 0) 935 printf("%s: Handle Seqint Called for code %d\n", 936 ahd_name(ahd), seqintcode); 937 #endif 938 switch (seqintcode) { 939 case ENTERING_NONPACK: 940 { 941 struct scb *scb; 942 u_int scbid; 943 944 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 945 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 946 scbid = ahd_get_scbptr(ahd); 947 scb = ahd_lookup_scb(ahd, scbid); 948 if (scb == NULL) { 949 /* 950 * Somehow need to know if this 951 * is from a selection or reselection. 952 * From that, we can determine target 953 * ID so we at least have an I_T nexus. 954 */ 955 } else { 956 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 957 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 958 ahd_outb(ahd, SEQ_FLAGS, 0x0); 959 } 960 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 961 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 962 /* 963 * Phase change after read stream with 964 * CRC error with P0 asserted on last 965 * packet. 966 */ 967 #ifdef AHD_DEBUG 968 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 969 printf("%s: Assuming LQIPHASE_NLQ with " 970 "P0 assertion\n", ahd_name(ahd)); 971 #endif 972 } 973 #ifdef AHD_DEBUG 974 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 975 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 976 #endif 977 break; 978 } 979 case INVALID_SEQINT: 980 printf("%s: Invalid Sequencer interrupt occurred, " 981 "resetting channel.\n", 982 ahd_name(ahd)); 983 #ifdef AHD_DEBUG 984 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 985 ahd_dump_card_state(ahd); 986 #endif 987 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 988 break; 989 case STATUS_OVERRUN: 990 { 991 struct scb *scb; 992 u_int scbid; 993 994 scbid = ahd_get_scbptr(ahd); 995 scb = ahd_lookup_scb(ahd, scbid); 996 if (scb != NULL) 997 ahd_print_path(ahd, scb); 998 else 999 printf("%s: ", ahd_name(ahd)); 1000 printf("SCB %d Packetized Status Overrun", scbid); 1001 ahd_dump_card_state(ahd); 1002 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1003 break; 1004 } 1005 case CFG4ISTAT_INTR: 1006 { 1007 struct scb *scb; 1008 u_int scbid; 1009 1010 scbid = ahd_get_scbptr(ahd); 1011 scb = ahd_lookup_scb(ahd, scbid); 1012 if (scb == NULL) { 1013 ahd_dump_card_state(ahd); 1014 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 1015 panic("For safety"); 1016 } 1017 ahd_outq(ahd, HADDR, scb->sense_busaddr); 1018 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 1019 ahd_outb(ahd, HCNT + 2, 0); 1020 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 1021 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 1022 break; 1023 } 1024 case ILLEGAL_PHASE: 1025 { 1026 u_int bus_phase; 1027 1028 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1029 printf("%s: ILLEGAL_PHASE 0x%x\n", 1030 ahd_name(ahd), bus_phase); 1031 1032 switch (bus_phase) { 1033 case P_DATAOUT: 1034 case P_DATAIN: 1035 case P_DATAOUT_DT: 1036 case P_DATAIN_DT: 1037 case P_MESGOUT: 1038 case P_STATUS: 1039 case P_MESGIN: 1040 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1041 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 1042 break; 1043 case P_COMMAND: 1044 { 1045 struct ahd_devinfo devinfo; 1046 struct scb *scb; 1047 struct ahd_initiator_tinfo *targ_info; 1048 struct ahd_tmode_tstate *tstate; 1049 struct ahd_transinfo *tinfo; 1050 u_int scbid; 1051 1052 /* 1053 * If a target takes us into the command phase 1054 * assume that it has been externally reset and 1055 * has thus lost our previous packetized negotiation 1056 * agreement. 1057 * Revert to async/narrow transfers until we 1058 * can renegotiate with the device and notify 1059 * the OSM about the reset. 1060 */ 1061 scbid = ahd_get_scbptr(ahd); 1062 scb = ahd_lookup_scb(ahd, scbid); 1063 if (scb == NULL) { 1064 printf("Invalid phase with no valid SCB. " 1065 "Resetting bus.\n"); 1066 ahd_reset_channel(ahd, 'A', 1067 /*Initiate Reset*/TRUE); 1068 break; 1069 } 1070 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 1071 SCB_GET_TARGET(ahd, scb), 1072 SCB_GET_LUN(scb), 1073 SCB_GET_CHANNEL(ahd, scb), 1074 ROLE_INITIATOR); 1075 targ_info = ahd_fetch_transinfo(ahd, 1076 devinfo.channel, 1077 devinfo.our_scsiid, 1078 devinfo.target, 1079 &tstate); 1080 tinfo = &targ_info->curr; 1081 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 1082 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1083 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 1084 /*offset*/0, /*ppr_options*/0, 1085 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1086 scb->flags |= SCB_EXTERNAL_RESET; 1087 ahd_freeze_devq(ahd, scb); 1088 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1089 ahd_freeze_scb(scb); 1090 1091 /* Notify XPT */ 1092 ahd_send_async(ahd, devinfo.channel, devinfo.target, 1093 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 1094 1095 /* 1096 * Allow the sequencer to continue with 1097 * non-pack processing. 1098 */ 1099 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1100 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 1101 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1102 ahd_outb(ahd, CLRLQOINT1, 0); 1103 } 1104 #ifdef AHD_DEBUG 1105 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1106 ahd_print_path(ahd, scb); 1107 printf("Unexpected command phase from " 1108 "packetized target\n"); 1109 } 1110 #endif 1111 break; 1112 } 1113 } 1114 break; 1115 } 1116 case CFG4OVERRUN: 1117 { 1118 struct scb *scb; 1119 u_int scb_index; 1120 1121 #ifdef AHD_DEBUG 1122 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1123 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 1124 ahd_inb(ahd, MODE_PTR)); 1125 } 1126 #endif 1127 scb_index = ahd_get_scbptr(ahd); 1128 scb = ahd_lookup_scb(ahd, scb_index); 1129 if (scb == NULL) { 1130 /* 1131 * Attempt to transfer to an SCB that is 1132 * not outstanding. 1133 */ 1134 ahd_assert_atn(ahd); 1135 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1136 ahd->msgout_buf[0] = MSG_ABORT_TASK; 1137 ahd->msgout_len = 1; 1138 ahd->msgout_index = 0; 1139 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1140 /* 1141 * Clear status received flag to prevent any 1142 * attempt to complete this bogus SCB. 1143 */ 1144 ahd_outb(ahd, SCB_CONTROL, 1145 ahd_inb_scbram(ahd, SCB_CONTROL) 1146 & ~STATUS_RCVD); 1147 } 1148 break; 1149 } 1150 case DUMP_CARD_STATE: 1151 { 1152 ahd_dump_card_state(ahd); 1153 break; 1154 } 1155 case PDATA_REINIT: 1156 { 1157 #ifdef AHD_DEBUG 1158 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1159 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 1160 "SG_CACHE_SHADOW = 0x%x\n", 1161 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 1162 ahd_inb(ahd, SG_CACHE_SHADOW)); 1163 } 1164 #endif 1165 ahd_reinitialize_dataptrs(ahd); 1166 break; 1167 } 1168 case HOST_MSG_LOOP: 1169 { 1170 struct ahd_devinfo devinfo; 1171 1172 /* 1173 * The sequencer has encountered a message phase 1174 * that requires host assistance for completion. 1175 * While handling the message phase(s), we will be 1176 * notified by the sequencer after each byte is 1177 * transfered so we can track bus phase changes. 1178 * 1179 * If this is the first time we've seen a HOST_MSG_LOOP 1180 * interrupt, initialize the state of the host message 1181 * loop. 1182 */ 1183 ahd_fetch_devinfo(ahd, &devinfo); 1184 if (ahd->msg_type == MSG_TYPE_NONE) { 1185 struct scb *scb; 1186 u_int scb_index; 1187 u_int bus_phase; 1188 1189 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1190 if (bus_phase != P_MESGIN 1191 && bus_phase != P_MESGOUT) { 1192 printf("ahd_intr: HOST_MSG_LOOP bad " 1193 "phase 0x%x\n", bus_phase); 1194 /* 1195 * Probably transitioned to bus free before 1196 * we got here. Just punt the message. 1197 */ 1198 ahd_dump_card_state(ahd); 1199 ahd_clear_intstat(ahd); 1200 ahd_restart(ahd); 1201 return; 1202 } 1203 1204 scb_index = ahd_get_scbptr(ahd); 1205 scb = ahd_lookup_scb(ahd, scb_index); 1206 if (devinfo.role == ROLE_INITIATOR) { 1207 if (bus_phase == P_MESGOUT) 1208 ahd_setup_initiator_msgout(ahd, 1209 &devinfo, 1210 scb); 1211 else { 1212 ahd->msg_type = 1213 MSG_TYPE_INITIATOR_MSGIN; 1214 ahd->msgin_index = 0; 1215 } 1216 } 1217 #ifdef AHD_TARGET_MODE 1218 else { 1219 if (bus_phase == P_MESGOUT) { 1220 ahd->msg_type = 1221 MSG_TYPE_TARGET_MSGOUT; 1222 ahd->msgin_index = 0; 1223 } 1224 else 1225 ahd_setup_target_msgin(ahd, 1226 &devinfo, 1227 scb); 1228 } 1229 #endif 1230 } 1231 1232 ahd_handle_message_phase(ahd); 1233 break; 1234 } 1235 case NO_MATCH: 1236 { 1237 /* Ensure we don't leave the selection hardware on */ 1238 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 1239 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1240 1241 printf("%s:%c:%d: no active SCB for reconnecting " 1242 "target - issuing BUS DEVICE RESET\n", 1243 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 1244 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 1245 "REG0 == 0x%x ACCUM = 0x%x\n", 1246 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 1247 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 1248 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 1249 "SINDEX == 0x%x\n", 1250 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 1251 ahd_find_busy_tcl(ahd, 1252 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 1253 ahd_inb(ahd, SAVED_LUN))), 1254 ahd_inw(ahd, SINDEX)); 1255 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1256 "SCB_CONTROL == 0x%x\n", 1257 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 1258 ahd_inb_scbram(ahd, SCB_LUN), 1259 ahd_inb_scbram(ahd, SCB_CONTROL)); 1260 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 1261 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 1262 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 1263 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 1264 ahd_dump_card_state(ahd); 1265 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 1266 ahd->msgout_len = 1; 1267 ahd->msgout_index = 0; 1268 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1269 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1270 ahd_assert_atn(ahd); 1271 break; 1272 } 1273 case PROTO_VIOLATION: 1274 { 1275 ahd_handle_proto_violation(ahd); 1276 break; 1277 } 1278 case IGN_WIDE_RES: 1279 { 1280 struct ahd_devinfo devinfo; 1281 1282 ahd_fetch_devinfo(ahd, &devinfo); 1283 ahd_handle_ign_wide_residue(ahd, &devinfo); 1284 break; 1285 } 1286 case BAD_PHASE: 1287 { 1288 u_int lastphase; 1289 1290 lastphase = ahd_inb(ahd, LASTPHASE); 1291 printf("%s:%c:%d: unknown scsi bus phase %x, " 1292 "lastphase = 0x%x. Attempting to continue\n", 1293 ahd_name(ahd), 'A', 1294 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1295 lastphase, ahd_inb(ahd, SCSISIGI)); 1296 break; 1297 } 1298 case MISSED_BUSFREE: 1299 { 1300 u_int lastphase; 1301 1302 lastphase = ahd_inb(ahd, LASTPHASE); 1303 printf("%s:%c:%d: Missed busfree. " 1304 "Lastphase = 0x%x, Curphase = 0x%x\n", 1305 ahd_name(ahd), 'A', 1306 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1307 lastphase, ahd_inb(ahd, SCSISIGI)); 1308 ahd_restart(ahd); 1309 return; 1310 } 1311 case DATA_OVERRUN: 1312 { 1313 /* 1314 * When the sequencer detects an overrun, it 1315 * places the controller in "BITBUCKET" mode 1316 * and allows the target to complete its transfer. 1317 * Unfortunately, none of the counters get updated 1318 * when the controller is in this mode, so we have 1319 * no way of knowing how large the overrun was. 1320 */ 1321 struct scb *scb; 1322 u_int scbindex; 1323 #ifdef AHD_DEBUG 1324 u_int lastphase; 1325 #endif 1326 1327 scbindex = ahd_get_scbptr(ahd); 1328 scb = ahd_lookup_scb(ahd, scbindex); 1329 #ifdef AHD_DEBUG 1330 lastphase = ahd_inb(ahd, LASTPHASE); 1331 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1332 ahd_print_path(ahd, scb); 1333 printf("data overrun detected %s. Tag == 0x%x.\n", 1334 ahd_lookup_phase_entry(lastphase)->phasemsg, 1335 SCB_GET_TAG(scb)); 1336 ahd_print_path(ahd, scb); 1337 printf("%s seen Data Phase. Length = %ld. " 1338 "NumSGs = %d.\n", 1339 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1340 ? "Have" : "Haven't", 1341 ahd_get_transfer_length(scb), scb->sg_count); 1342 ahd_dump_sglist(scb); 1343 } 1344 #endif 1345 1346 /* 1347 * Set this and it will take effect when the 1348 * target does a command complete. 1349 */ 1350 ahd_freeze_devq(ahd, scb); 1351 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1352 ahd_freeze_scb(scb); 1353 break; 1354 } 1355 case MKMSG_FAILED: 1356 { 1357 struct ahd_devinfo devinfo; 1358 struct scb *scb; 1359 u_int scbid; 1360 1361 ahd_fetch_devinfo(ahd, &devinfo); 1362 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1363 ahd_name(ahd), devinfo.channel, devinfo.target, 1364 devinfo.lun); 1365 scbid = ahd_get_scbptr(ahd); 1366 scb = ahd_lookup_scb(ahd, scbid); 1367 if (scb != NULL 1368 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1369 /* 1370 * Ensure that we didn't put a second instance of this 1371 * SCB into the QINFIFO. 1372 */ 1373 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1374 SCB_GET_CHANNEL(ahd, scb), 1375 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1376 ROLE_INITIATOR, /*status*/0, 1377 SEARCH_REMOVE); 1378 ahd_outb(ahd, SCB_CONTROL, 1379 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1380 break; 1381 } 1382 case TASKMGMT_FUNC_COMPLETE: 1383 { 1384 u_int scbid; 1385 struct scb *scb; 1386 1387 scbid = ahd_get_scbptr(ahd); 1388 scb = ahd_lookup_scb(ahd, scbid); 1389 if (scb != NULL) { 1390 u_int lun; 1391 u_int tag; 1392 cam_status error; 1393 1394 ahd_print_path(ahd, scb); 1395 printf("Task Management Func 0x%x Complete\n", 1396 scb->hscb->task_management); 1397 lun = CAM_LUN_WILDCARD; 1398 tag = SCB_LIST_NULL; 1399 1400 switch (scb->hscb->task_management) { 1401 case SIU_TASKMGMT_ABORT_TASK: 1402 tag = SCB_GET_TAG(scb); 1403 case SIU_TASKMGMT_ABORT_TASK_SET: 1404 case SIU_TASKMGMT_CLEAR_TASK_SET: 1405 lun = scb->hscb->lun; 1406 error = CAM_REQ_ABORTED; 1407 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1408 'A', lun, tag, ROLE_INITIATOR, 1409 error); 1410 break; 1411 case SIU_TASKMGMT_LUN_RESET: 1412 lun = scb->hscb->lun; 1413 case SIU_TASKMGMT_TARGET_RESET: 1414 { 1415 struct ahd_devinfo devinfo; 1416 1417 ahd_scb_devinfo(ahd, &devinfo, scb); 1418 error = CAM_BDR_SENT; 1419 ahd_handle_devreset(ahd, &devinfo, lun, 1420 CAM_BDR_SENT, 1421 lun != CAM_LUN_WILDCARD 1422 ? "Lun Reset" 1423 : "Target Reset", 1424 /*verbose_level*/0); 1425 break; 1426 } 1427 default: 1428 panic("Unexpected TaskMgmt Func\n"); 1429 break; 1430 } 1431 } 1432 break; 1433 } 1434 case TASKMGMT_CMD_CMPLT_OKAY: 1435 { 1436 u_int scbid; 1437 struct scb *scb; 1438 1439 /* 1440 * An ABORT TASK TMF failed to be delivered before 1441 * the targeted command completed normally. 1442 */ 1443 scbid = ahd_get_scbptr(ahd); 1444 scb = ahd_lookup_scb(ahd, scbid); 1445 if (scb != NULL) { 1446 /* 1447 * Remove the second instance of this SCB from 1448 * the QINFIFO if it is still there. 1449 */ 1450 ahd_print_path(ahd, scb); 1451 printf("SCB completes before TMF\n"); 1452 /* 1453 * Handle losing the race. Wait until any 1454 * current selection completes. We will then 1455 * set the TMF back to zero in this SCB so that 1456 * the sequencer doesn't bother to issue another 1457 * sequencer interrupt for its completion. 1458 */ 1459 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1460 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1461 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1462 ; 1463 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1464 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1465 SCB_GET_CHANNEL(ahd, scb), 1466 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1467 ROLE_INITIATOR, /*status*/0, 1468 SEARCH_REMOVE); 1469 } 1470 break; 1471 } 1472 case TRACEPOINT0: 1473 case TRACEPOINT1: 1474 case TRACEPOINT2: 1475 case TRACEPOINT3: 1476 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1477 seqintcode - TRACEPOINT0); 1478 break; 1479 case NO_SEQINT: 1480 break; 1481 case SAW_HWERR: 1482 ahd_handle_hwerrint(ahd); 1483 break; 1484 default: 1485 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1486 seqintcode); 1487 break; 1488 } 1489 /* 1490 * The sequencer is paused immediately on 1491 * a SEQINT, so we should restart it when 1492 * we're done. 1493 */ 1494 ahd_unpause(ahd); 1495 } 1496 1497 void 1498 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1499 { 1500 struct scb *scb; 1501 u_int status0; 1502 u_int status3; 1503 u_int status; 1504 u_int lqistat1; 1505 u_int lqostat0; 1506 u_int scbid; 1507 u_int busfreetime; 1508 1509 ahd_update_modes(ahd); 1510 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1511 1512 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1513 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1514 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1515 lqistat1 = ahd_inb(ahd, LQISTAT1); 1516 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1517 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1518 1519 /* 1520 * Ignore external resets after a bus reset. 1521 */ 1522 if (((status & SCSIRSTI) != 0) && (ahd->flags & AHD_BUS_RESET_ACTIVE)) 1523 return; 1524 1525 /* 1526 * Clear bus reset flag 1527 */ 1528 ahd->flags &= ~AHD_BUS_RESET_ACTIVE; 1529 1530 if ((status0 & (SELDI|SELDO)) != 0) { 1531 u_int simode0; 1532 1533 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1534 simode0 = ahd_inb(ahd, SIMODE0); 1535 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1536 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1537 } 1538 scbid = ahd_get_scbptr(ahd); 1539 scb = ahd_lookup_scb(ahd, scbid); 1540 if (scb != NULL 1541 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1542 scb = NULL; 1543 1544 if ((status0 & IOERR) != 0) { 1545 u_int now_lvd; 1546 1547 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1548 printf("%s: Transceiver State Has Changed to %s mode\n", 1549 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1550 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1551 /* 1552 * A change in I/O mode is equivalent to a bus reset. 1553 */ 1554 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1555 ahd_pause(ahd); 1556 ahd_setup_iocell_workaround(ahd); 1557 ahd_unpause(ahd); 1558 } else if ((status0 & OVERRUN) != 0) { 1559 1560 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1561 ahd_name(ahd)); 1562 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1563 } else if ((status & SCSIRSTI) != 0) { 1564 1565 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1566 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1567 } else if ((status & SCSIPERR) != 0) { 1568 1569 /* Make sure the sequencer is in a safe location. */ 1570 ahd_clear_critical_section(ahd); 1571 1572 ahd_handle_transmission_error(ahd); 1573 } else if (lqostat0 != 0) { 1574 1575 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1576 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1577 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1578 ahd_outb(ahd, CLRLQOINT1, 0); 1579 } else if ((status & SELTO) != 0) { 1580 u_int scbid; 1581 1582 /* Stop the selection */ 1583 ahd_outb(ahd, SCSISEQ0, 0); 1584 1585 /* Make sure the sequencer is in a safe location. */ 1586 ahd_clear_critical_section(ahd); 1587 1588 /* No more pending messages */ 1589 ahd_clear_msg_state(ahd); 1590 1591 /* Clear interrupt state */ 1592 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1593 1594 /* 1595 * Although the driver does not care about the 1596 * 'Selection in Progress' status bit, the busy 1597 * LED does. SELINGO is only cleared by a sucessfull 1598 * selection, so we must manually clear it to insure 1599 * the LED turns off just incase no future successful 1600 * selections occur (e.g. no devices on the bus). 1601 */ 1602 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1603 1604 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1605 scb = ahd_lookup_scb(ahd, scbid); 1606 if (scb == NULL) { 1607 printf("%s: ahd_intr - referenced scb not " 1608 "valid during SELTO scb(0x%x)\n", 1609 ahd_name(ahd), scbid); 1610 ahd_dump_card_state(ahd); 1611 } else { 1612 struct ahd_devinfo devinfo; 1613 #ifdef AHD_DEBUG 1614 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1615 ahd_print_path(ahd, scb); 1616 printf("Saw Selection Timeout for SCB 0x%x\n", 1617 scbid); 1618 } 1619 #endif 1620 ahd_scb_devinfo(ahd, &devinfo, scb); 1621 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1622 ahd_freeze_devq(ahd, scb); 1623 1624 /* 1625 * Cancel any pending transactions on the device 1626 * now that it seems to be missing. This will 1627 * also revert us to async/narrow transfers until 1628 * we can renegotiate with the device. 1629 */ 1630 ahd_handle_devreset(ahd, &devinfo, 1631 CAM_LUN_WILDCARD, 1632 CAM_SEL_TIMEOUT, 1633 "Selection Timeout", 1634 /*verbose_level*/1); 1635 } 1636 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1637 ahd_iocell_first_selection(ahd); 1638 ahd_unpause(ahd); 1639 } else if ((status0 & (SELDI|SELDO)) != 0) { 1640 1641 ahd_iocell_first_selection(ahd); 1642 ahd_unpause(ahd); 1643 } else if (status3 != 0) { 1644 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1645 ahd_name(ahd), status3); 1646 ahd_outb(ahd, CLRSINT3, status3); 1647 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1648 1649 /* Make sure the sequencer is in a safe location. */ 1650 ahd_clear_critical_section(ahd); 1651 1652 ahd_handle_lqiphase_error(ahd, lqistat1); 1653 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1654 /* 1655 * This status can be delayed during some 1656 * streaming operations. The SCSIPHASE 1657 * handler has already dealt with this case 1658 * so just clear the error. 1659 */ 1660 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1661 } else if ((status & BUSFREE) != 0 1662 || (lqistat1 & LQOBUSFREE) != 0) { 1663 u_int lqostat1; 1664 int restart; 1665 int clear_fifo; 1666 int packetized; 1667 u_int mode; 1668 1669 /* 1670 * Clear our selection hardware as soon as possible. 1671 * We may have an entry in the waiting Q for this target, 1672 * that is affected by this busfree and we don't want to 1673 * go about selecting the target while we handle the event. 1674 */ 1675 ahd_outb(ahd, SCSISEQ0, 0); 1676 1677 /* Make sure the sequencer is in a safe location. */ 1678 ahd_clear_critical_section(ahd); 1679 1680 /* 1681 * Determine what we were up to at the time of 1682 * the busfree. 1683 */ 1684 mode = AHD_MODE_SCSI; 1685 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1686 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1687 switch (busfreetime) { 1688 case BUSFREE_DFF0: 1689 case BUSFREE_DFF1: 1690 { 1691 u_int scbid; 1692 struct scb *scb; 1693 1694 mode = busfreetime == BUSFREE_DFF0 1695 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1696 ahd_set_modes(ahd, mode, mode); 1697 scbid = ahd_get_scbptr(ahd); 1698 scb = ahd_lookup_scb(ahd, scbid); 1699 if (scb == NULL) { 1700 printf("%s: Invalid SCB %d in DFF%d " 1701 "during unexpected busfree\n", 1702 ahd_name(ahd), scbid, mode); 1703 packetized = 0; 1704 } else 1705 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1706 clear_fifo = 1; 1707 break; 1708 } 1709 case BUSFREE_LQO: 1710 clear_fifo = 0; 1711 packetized = 1; 1712 break; 1713 default: 1714 clear_fifo = 0; 1715 packetized = (lqostat1 & LQOBUSFREE) != 0; 1716 if (!packetized 1717 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE 1718 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0 1719 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0 1720 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0)) 1721 /* 1722 * Assume packetized if we are not 1723 * on the bus in a non-packetized 1724 * capacity and any pending selection 1725 * was a packetized selection. 1726 */ 1727 packetized = 1; 1728 break; 1729 } 1730 1731 #ifdef AHD_DEBUG 1732 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1733 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1734 busfreetime); 1735 #endif 1736 /* 1737 * Busfrees that occur in non-packetized phases are 1738 * handled by the nonpkt_busfree handler. 1739 */ 1740 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1741 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1742 } else { 1743 packetized = 0; 1744 restart = ahd_handle_nonpkt_busfree(ahd); 1745 } 1746 /* 1747 * Clear the busfree interrupt status. The setting of 1748 * the interrupt is a pulse, so in a perfect world, we 1749 * would not need to muck with the ENBUSFREE logic. This 1750 * would ensure that if the bus moves on to another 1751 * connection, busfree protection is still in force. If 1752 * BUSFREEREV is broken, however, we must manually clear 1753 * the ENBUSFREE if the busfree occurred during a non-pack 1754 * connection so that we don't get false positives during 1755 * future, packetized, connections. 1756 */ 1757 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1758 if (packetized == 0 1759 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1760 ahd_outb(ahd, SIMODE1, 1761 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1762 1763 if (clear_fifo) 1764 ahd_clear_fifo(ahd, mode); 1765 1766 ahd_clear_msg_state(ahd); 1767 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1768 if (restart) { 1769 ahd_restart(ahd); 1770 } else { 1771 ahd_unpause(ahd); 1772 } 1773 } else { 1774 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1775 ahd_name(ahd), status); 1776 ahd_dump_card_state(ahd); 1777 ahd_clear_intstat(ahd); 1778 ahd_unpause(ahd); 1779 } 1780 } 1781 1782 static void 1783 ahd_handle_transmission_error(struct ahd_softc *ahd) 1784 { 1785 struct scb *scb; 1786 u_int scbid; 1787 u_int lqistat1; 1788 u_int lqistat2; 1789 u_int msg_out; 1790 u_int curphase; 1791 u_int lastphase; 1792 u_int perrdiag; 1793 u_int cur_col; 1794 int silent; 1795 1796 scb = NULL; 1797 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1798 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1799 lqistat2 = ahd_inb(ahd, LQISTAT2); 1800 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1801 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1802 u_int lqistate; 1803 1804 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1805 lqistate = ahd_inb(ahd, LQISTATE); 1806 if ((lqistate >= 0x1E && lqistate <= 0x24) 1807 || (lqistate == 0x29)) { 1808 #ifdef AHD_DEBUG 1809 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1810 printf("%s: NLQCRC found via LQISTATE\n", 1811 ahd_name(ahd)); 1812 } 1813 #endif 1814 lqistat1 |= LQICRCI_NLQ; 1815 } 1816 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1817 } 1818 1819 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1820 lastphase = ahd_inb(ahd, LASTPHASE); 1821 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1822 perrdiag = ahd_inb(ahd, PERRDIAG); 1823 msg_out = MSG_INITIATOR_DET_ERR; 1824 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1825 1826 /* 1827 * Try to find the SCB associated with this error. 1828 */ 1829 silent = FALSE; 1830 if (lqistat1 == 0 1831 || (lqistat1 & LQICRCI_NLQ) != 0) { 1832 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1833 ahd_set_active_fifo(ahd); 1834 scbid = ahd_get_scbptr(ahd); 1835 scb = ahd_lookup_scb(ahd, scbid); 1836 if (scb != NULL && SCB_IS_SILENT(scb)) 1837 silent = TRUE; 1838 } 1839 1840 cur_col = 0; 1841 if (silent == FALSE) { 1842 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1843 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1844 ahd_lastphase_print(lastphase, &cur_col, 50); 1845 ahd_scsisigi_print(curphase, &cur_col, 50); 1846 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1847 printf("\n"); 1848 ahd_dump_card_state(ahd); 1849 } 1850 1851 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1852 if (silent == FALSE) { 1853 printf("%s: Gross protocol error during incoming " 1854 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1855 ahd_name(ahd), lqistat1); 1856 } 1857 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1858 return; 1859 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1860 /* 1861 * A CRC error has been detected on an incoming LQ. 1862 * The bus is currently hung on the last ACK. 1863 * Hit LQIRETRY to release the last ack, and 1864 * wait for the sequencer to determine that ATNO 1865 * is asserted while in message out to take us 1866 * to our host message loop. No NONPACKREQ or 1867 * LQIPHASE type errors will occur in this 1868 * scenario. After this first LQIRETRY, the LQI 1869 * manager will be in ISELO where it will 1870 * happily sit until another packet phase begins. 1871 * Unexpected bus free detection is enabled 1872 * through any phases that occur after we release 1873 * this last ack until the LQI manager sees a 1874 * packet phase. This implies we may have to 1875 * ignore a perfectly valid "unexected busfree" 1876 * after our "initiator detected error" message is 1877 * sent. A busfree is the expected response after 1878 * we tell the target that it's L_Q was corrupted. 1879 * (SPI4R09 10.7.3.3.3) 1880 */ 1881 ahd_outb(ahd, LQCTL2, LQIRETRY); 1882 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1883 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1884 /* 1885 * We detected a CRC error in a NON-LQ packet. 1886 * The hardware has varying behavior in this situation 1887 * depending on whether this packet was part of a 1888 * stream or not. 1889 * 1890 * PKT by PKT mode: 1891 * The hardware has already acked the complete packet. 1892 * If the target honors our outstanding ATN condition, 1893 * we should be (or soon will be) in MSGOUT phase. 1894 * This will trigger the LQIPHASE_LQ status bit as the 1895 * hardware was expecting another LQ. Unexpected 1896 * busfree detection is enabled. Once LQIPHASE_LQ is 1897 * true (first entry into host message loop is much 1898 * the same), we must clear LQIPHASE_LQ and hit 1899 * LQIRETRY so the hardware is ready to handle 1900 * a future LQ. NONPACKREQ will not be asserted again 1901 * once we hit LQIRETRY until another packet is 1902 * processed. The target may either go busfree 1903 * or start another packet in response to our message. 1904 * 1905 * Read Streaming P0 asserted: 1906 * If we raise ATN and the target completes the entire 1907 * stream (P0 asserted during the last packet), the 1908 * hardware will ack all data and return to the ISTART 1909 * state. When the target reponds to our ATN condition, 1910 * LQIPHASE_LQ will be asserted. We should respond to 1911 * this with an LQIRETRY to prepare for any future 1912 * packets. NONPACKREQ will not be asserted again 1913 * once we hit LQIRETRY until another packet is 1914 * processed. The target may either go busfree or 1915 * start another packet in response to our message. 1916 * Busfree detection is enabled. 1917 * 1918 * Read Streaming P0 not asserted: 1919 * If we raise ATN and the target transitions to 1920 * MSGOUT in or after a packet where P0 is not 1921 * asserted, the hardware will assert LQIPHASE_NLQ. 1922 * We should respond to the LQIPHASE_NLQ with an 1923 * LQIRETRY. Should the target stay in a non-pkt 1924 * phase after we send our message, the hardware 1925 * will assert LQIPHASE_LQ. Recovery is then just as 1926 * listed above for the read streaming with P0 asserted. 1927 * Busfree detection is enabled. 1928 */ 1929 if (silent == FALSE) 1930 printf("LQICRC_NLQ\n"); 1931 if (scb == NULL) { 1932 printf("%s: No SCB valid for LQICRC_NLQ. " 1933 "Resetting bus\n", ahd_name(ahd)); 1934 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1935 return; 1936 } 1937 } else if ((lqistat1 & LQIBADLQI) != 0) { 1938 printf("Need to handle BADLQI!\n"); 1939 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1940 return; 1941 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1942 if ((curphase & ~P_DATAIN_DT) != 0) { 1943 /* Ack the byte. So we can continue. */ 1944 if (silent == FALSE) 1945 printf("Acking %s to clear perror\n", 1946 ahd_lookup_phase_entry(curphase)->phasemsg); 1947 ahd_inb(ahd, SCSIDAT); 1948 } 1949 1950 if (curphase == P_MESGIN) 1951 msg_out = MSG_PARITY_ERROR; 1952 } 1953 1954 /* 1955 * We've set the hardware to assert ATN if we 1956 * get a parity error on "in" phases, so all we 1957 * need to do is stuff the message buffer with 1958 * the appropriate message. "In" phases have set 1959 * mesg_out to something other than MSG_NOP. 1960 */ 1961 ahd->send_msg_perror = msg_out; 1962 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1963 scb->flags |= SCB_TRANSMISSION_ERROR; 1964 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1965 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1966 ahd_unpause(ahd); 1967 } 1968 1969 static void 1970 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1971 { 1972 /* 1973 * Clear the sources of the interrupts. 1974 */ 1975 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1976 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1977 1978 /* 1979 * If the "illegal" phase changes were in response 1980 * to our ATN to flag a CRC error, AND we ended up 1981 * on packet boundaries, clear the error, restart the 1982 * LQI manager as appropriate, and go on our merry 1983 * way toward sending the message. Otherwise, reset 1984 * the bus to clear the error. 1985 */ 1986 ahd_set_active_fifo(ahd); 1987 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1988 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1989 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1990 printf("LQIRETRY for LQIPHASE_LQ\n"); 1991 ahd_outb(ahd, LQCTL2, LQIRETRY); 1992 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1993 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1994 ahd_outb(ahd, LQCTL2, LQIRETRY); 1995 } else 1996 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1997 ahd_dump_card_state(ahd); 1998 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1999 ahd_unpause(ahd); 2000 } else { 2001 printf("Reseting Channel for LQI Phase error\n"); 2002 ahd_dump_card_state(ahd); 2003 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2004 } 2005 } 2006 2007 /* 2008 * Packetized unexpected or expected busfree. 2009 * Entered in mode based on busfreetime. 2010 */ 2011 static int 2012 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 2013 { 2014 u_int lqostat1; 2015 2016 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2017 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2018 lqostat1 = ahd_inb(ahd, LQOSTAT1); 2019 if ((lqostat1 & LQOBUSFREE) != 0) { 2020 struct scb *scb; 2021 u_int scbid; 2022 u_int saved_scbptr; 2023 u_int waiting_h; 2024 u_int waiting_t; 2025 u_int next; 2026 2027 /* 2028 * The LQO manager detected an unexpected busfree 2029 * either: 2030 * 2031 * 1) During an outgoing LQ. 2032 * 2) After an outgoing LQ but before the first 2033 * REQ of the command packet. 2034 * 3) During an outgoing command packet. 2035 * 2036 * In all cases, CURRSCB is pointing to the 2037 * SCB that encountered the failure. Clean 2038 * up the queue, clear SELDO and LQOBUSFREE, 2039 * and allow the sequencer to restart the select 2040 * out at its lesure. 2041 */ 2042 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2043 scbid = ahd_inw(ahd, CURRSCB); 2044 scb = ahd_lookup_scb(ahd, scbid); 2045 if (scb == NULL) 2046 panic("SCB not valid during LQOBUSFREE"); 2047 /* 2048 * Clear the status. 2049 */ 2050 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 2051 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 2052 ahd_outb(ahd, CLRLQOINT1, 0); 2053 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2054 ahd_flush_device_writes(ahd); 2055 ahd_outb(ahd, CLRSINT0, CLRSELDO); 2056 2057 /* 2058 * Return the LQO manager to its idle loop. It will 2059 * not do this automatically if the busfree occurs 2060 * after the first REQ of either the LQ or command 2061 * packet or between the LQ and command packet. 2062 */ 2063 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 2064 2065 /* 2066 * Update the waiting for selection queue so 2067 * we restart on the correct SCB. 2068 */ 2069 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 2070 saved_scbptr = ahd_get_scbptr(ahd); 2071 if (waiting_h != scbid) { 2072 2073 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 2074 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 2075 if (waiting_t == waiting_h) { 2076 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 2077 next = SCB_LIST_NULL; 2078 } else { 2079 ahd_set_scbptr(ahd, waiting_h); 2080 next = ahd_inw_scbram(ahd, SCB_NEXT2); 2081 } 2082 ahd_set_scbptr(ahd, scbid); 2083 ahd_outw(ahd, SCB_NEXT2, next); 2084 } 2085 ahd_set_scbptr(ahd, saved_scbptr); 2086 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 2087 if (SCB_IS_SILENT(scb) == FALSE) { 2088 ahd_print_path(ahd, scb); 2089 printf("Probable outgoing LQ CRC error. " 2090 "Retrying command\n"); 2091 } 2092 scb->crc_retry_count++; 2093 } else { 2094 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 2095 ahd_freeze_scb(scb); 2096 ahd_freeze_devq(ahd, scb); 2097 } 2098 /* Return unpausing the sequencer. */ 2099 return (0); 2100 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 2101 /* 2102 * Ignore what are really parity errors that 2103 * occur on the last REQ of a free running 2104 * clock prior to going busfree. Some drives 2105 * do not properly active negate just before 2106 * going busfree resulting in a parity glitch. 2107 */ 2108 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 2109 #ifdef AHD_DEBUG 2110 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 2111 printf("%s: Parity on last REQ detected " 2112 "during busfree phase.\n", 2113 ahd_name(ahd)); 2114 #endif 2115 /* Return unpausing the sequencer. */ 2116 return (0); 2117 } 2118 if (ahd->src_mode != AHD_MODE_SCSI) { 2119 u_int scbid; 2120 struct scb *scb; 2121 2122 scbid = ahd_get_scbptr(ahd); 2123 scb = ahd_lookup_scb(ahd, scbid); 2124 ahd_print_path(ahd, scb); 2125 printf("Unexpected PKT busfree condition\n"); 2126 ahd_dump_card_state(ahd); 2127 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 2128 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 2129 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 2130 2131 /* Return restarting the sequencer. */ 2132 return (1); 2133 } 2134 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 2135 ahd_dump_card_state(ahd); 2136 /* Restart the sequencer. */ 2137 return (1); 2138 } 2139 2140 /* 2141 * Non-packetized unexpected or expected busfree. 2142 */ 2143 static int 2144 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 2145 { 2146 struct ahd_devinfo devinfo; 2147 struct scb *scb; 2148 u_int lastphase; 2149 u_int saved_scsiid; 2150 u_int saved_lun; 2151 u_int target; 2152 u_int initiator_role_id; 2153 u_int scbid; 2154 u_int ppr_busfree; 2155 int printerror; 2156 2157 /* 2158 * Look at what phase we were last in. If its message out, 2159 * chances are pretty good that the busfree was in response 2160 * to one of our abort requests. 2161 */ 2162 lastphase = ahd_inb(ahd, LASTPHASE); 2163 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 2164 saved_lun = ahd_inb(ahd, SAVED_LUN); 2165 target = SCSIID_TARGET(ahd, saved_scsiid); 2166 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 2167 ahd_compile_devinfo(&devinfo, initiator_role_id, 2168 target, saved_lun, 'A', ROLE_INITIATOR); 2169 printerror = 1; 2170 2171 scbid = ahd_get_scbptr(ahd); 2172 scb = ahd_lookup_scb(ahd, scbid); 2173 if (scb != NULL 2174 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 2175 scb = NULL; 2176 2177 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 2178 if (lastphase == P_MESGOUT) { 2179 u_int tag; 2180 2181 tag = SCB_LIST_NULL; 2182 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 2183 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 2184 int found; 2185 int sent_msg; 2186 2187 if (scb == NULL) { 2188 ahd_print_devinfo(ahd, &devinfo); 2189 printf("Abort for unidentified " 2190 "connection completed.\n"); 2191 /* restart the sequencer. */ 2192 return (1); 2193 } 2194 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 2195 ahd_print_path(ahd, scb); 2196 printf("SCB %d - Abort%s Completed.\n", 2197 SCB_GET_TAG(scb), 2198 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 2199 2200 if (sent_msg == MSG_ABORT_TAG) 2201 tag = SCB_GET_TAG(scb); 2202 2203 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 2204 tag, ROLE_INITIATOR, 2205 CAM_REQ_ABORTED); 2206 printf("found == 0x%x\n", found); 2207 printerror = 0; 2208 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 2209 MSG_BUS_DEV_RESET, TRUE)) { 2210 #ifdef __FreeBSD__ 2211 /* 2212 * Don't mark the user's request for this BDR 2213 * as completing with CAM_BDR_SENT. CAM3 2214 * specifies CAM_REQ_CMP. 2215 */ 2216 if (scb != NULL 2217 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 2218 && ahd_match_scb(ahd, scb, target, 'A', 2219 CAM_LUN_WILDCARD, SCB_LIST_NULL, 2220 ROLE_INITIATOR)) 2221 ahd_set_transaction_status(scb, CAM_REQ_CMP); 2222 #endif 2223 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 2224 CAM_BDR_SENT, "Bus Device Reset", 2225 /*verbose_level*/0); 2226 printerror = 0; 2227 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 2228 && ppr_busfree == 0) { 2229 struct ahd_initiator_tinfo *tinfo; 2230 struct ahd_tmode_tstate *tstate; 2231 2232 /* 2233 * PPR Rejected. 2234 * 2235 * If the previous negotiation was packetized, 2236 * this could be because the device has been 2237 * reset without our knowledge. Force our 2238 * current negotiation to async and retry the 2239 * negotiation. Otherwise retry the command 2240 * with non-ppr negotiation. 2241 */ 2242 #ifdef AHD_DEBUG 2243 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2244 printf("PPR negotiation rejected busfree.\n"); 2245 #endif 2246 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2247 devinfo.our_scsiid, 2248 devinfo.target, &tstate); 2249 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) { 2250 ahd_set_width(ahd, &devinfo, 2251 MSG_EXT_WDTR_BUS_8_BIT, 2252 AHD_TRANS_CUR, 2253 /*paused*/TRUE); 2254 ahd_set_syncrate(ahd, &devinfo, 2255 /*period*/0, /*offset*/0, 2256 /*ppr_options*/0, 2257 AHD_TRANS_CUR, 2258 /*paused*/TRUE); 2259 /* 2260 * The expect PPR busfree handler below 2261 * will effect the retry and necessary 2262 * abort. 2263 */ 2264 } else { 2265 tinfo->curr.transport_version = 2; 2266 tinfo->goal.transport_version = 2; 2267 tinfo->goal.ppr_options = 0; 2268 /* 2269 * Remove any SCBs in the waiting for selection 2270 * queue that may also be for this target so 2271 * that command ordering is preserved. 2272 */ 2273 ahd_freeze_devq(ahd, scb); 2274 ahd_qinfifo_requeue_tail(ahd, scb); 2275 printerror = 0; 2276 } 2277 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 2278 && ppr_busfree == 0) { 2279 /* 2280 * Negotiation Rejected. Go-narrow and 2281 * retry command. 2282 */ 2283 #ifdef AHD_DEBUG 2284 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2285 printf("WDTR negotiation rejected busfree.\n"); 2286 #endif 2287 ahd_set_width(ahd, &devinfo, 2288 MSG_EXT_WDTR_BUS_8_BIT, 2289 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2290 /*paused*/TRUE); 2291 /* 2292 * Remove any SCBs in the waiting for selection 2293 * queue that may also be for this target so that 2294 * command ordering is preserved. 2295 */ 2296 ahd_freeze_devq(ahd, scb); 2297 ahd_qinfifo_requeue_tail(ahd, scb); 2298 printerror = 0; 2299 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 2300 && ppr_busfree == 0) { 2301 /* 2302 * Negotiation Rejected. Go-async and 2303 * retry command. 2304 */ 2305 #ifdef AHD_DEBUG 2306 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2307 printf("SDTR negotiation rejected busfree.\n"); 2308 #endif 2309 ahd_set_syncrate(ahd, &devinfo, 2310 /*period*/0, /*offset*/0, 2311 /*ppr_options*/0, 2312 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2313 /*paused*/TRUE); 2314 /* 2315 * Remove any SCBs in the waiting for selection 2316 * queue that may also be for this target so that 2317 * command ordering is preserved. 2318 */ 2319 ahd_freeze_devq(ahd, scb); 2320 ahd_qinfifo_requeue_tail(ahd, scb); 2321 printerror = 0; 2322 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 2323 && ahd_sent_msg(ahd, AHDMSG_1B, 2324 MSG_INITIATOR_DET_ERR, TRUE)) { 2325 2326 #ifdef AHD_DEBUG 2327 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2328 printf("Expected IDE Busfree\n"); 2329 #endif 2330 printerror = 0; 2331 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 2332 && ahd_sent_msg(ahd, AHDMSG_1B, 2333 MSG_MESSAGE_REJECT, TRUE)) { 2334 2335 #ifdef AHD_DEBUG 2336 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2337 printf("Expected QAS Reject Busfree\n"); 2338 #endif 2339 printerror = 0; 2340 } 2341 } 2342 2343 /* 2344 * The busfree required flag is honored at the end of 2345 * the message phases. We check it last in case we 2346 * had to send some other message that caused a busfree. 2347 */ 2348 if (printerror != 0 2349 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 2350 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 2351 2352 ahd_freeze_devq(ahd, scb); 2353 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 2354 ahd_freeze_scb(scb); 2355 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 2356 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 2357 SCB_GET_CHANNEL(ahd, scb), 2358 SCB_GET_LUN(scb), SCB_LIST_NULL, 2359 ROLE_INITIATOR, CAM_REQ_ABORTED); 2360 } else { 2361 #ifdef AHD_DEBUG 2362 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2363 printf("PPR Negotiation Busfree.\n"); 2364 #endif 2365 ahd_done(ahd, scb); 2366 } 2367 printerror = 0; 2368 } 2369 if (printerror != 0) { 2370 int aborted; 2371 2372 aborted = 0; 2373 if (scb != NULL) { 2374 u_int tag; 2375 2376 if ((scb->hscb->control & TAG_ENB) != 0) 2377 tag = SCB_GET_TAG(scb); 2378 else 2379 tag = SCB_LIST_NULL; 2380 ahd_print_path(ahd, scb); 2381 aborted = ahd_abort_scbs(ahd, target, 'A', 2382 SCB_GET_LUN(scb), tag, 2383 ROLE_INITIATOR, 2384 CAM_UNEXP_BUSFREE); 2385 } else { 2386 /* 2387 * We had not fully identified this connection, 2388 * so we cannot abort anything. 2389 */ 2390 printf("%s: ", ahd_name(ahd)); 2391 } 2392 printf("Unexpected busfree %s, %d SCBs aborted, " 2393 "PRGMCNT == 0x%x\n", 2394 ahd_lookup_phase_entry(lastphase)->phasemsg, 2395 aborted, 2396 ahd_inw(ahd, PRGMCNT)); 2397 ahd_dump_card_state(ahd); 2398 if (lastphase != P_BUSFREE) 2399 ahd_force_renegotiation(ahd, &devinfo); 2400 } 2401 /* Always restart the sequencer. */ 2402 return (1); 2403 } 2404 2405 static void 2406 ahd_handle_proto_violation(struct ahd_softc *ahd) 2407 { 2408 struct ahd_devinfo devinfo; 2409 struct scb *scb; 2410 u_int scbid; 2411 u_int seq_flags; 2412 u_int curphase; 2413 u_int lastphase; 2414 int found; 2415 2416 ahd_fetch_devinfo(ahd, &devinfo); 2417 scbid = ahd_get_scbptr(ahd); 2418 scb = ahd_lookup_scb(ahd, scbid); 2419 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2420 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2421 lastphase = ahd_inb(ahd, LASTPHASE); 2422 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2423 2424 /* 2425 * The reconnecting target either did not send an 2426 * identify message, or did, but we didn't find an SCB 2427 * to match. 2428 */ 2429 ahd_print_devinfo(ahd, &devinfo); 2430 printf("Target did not send an IDENTIFY message. " 2431 "LASTPHASE = 0x%x.\n", lastphase); 2432 scb = NULL; 2433 } else if (scb == NULL) { 2434 /* 2435 * We don't seem to have an SCB active for this 2436 * transaction. Print an error and reset the bus. 2437 */ 2438 ahd_print_devinfo(ahd, &devinfo); 2439 printf("No SCB found during protocol violation\n"); 2440 goto proto_violation_reset; 2441 } else { 2442 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2443 if ((seq_flags & NO_CDB_SENT) != 0) { 2444 ahd_print_path(ahd, scb); 2445 printf("No or incomplete CDB sent to device.\n"); 2446 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2447 & STATUS_RCVD) == 0) { 2448 /* 2449 * The target never bothered to provide status to 2450 * us prior to completing the command. Since we don't 2451 * know the disposition of this command, we must attempt 2452 * to abort it. Assert ATN and prepare to send an abort 2453 * message. 2454 */ 2455 ahd_print_path(ahd, scb); 2456 printf("Completed command without status.\n"); 2457 } else { 2458 ahd_print_path(ahd, scb); 2459 printf("Unknown protocol violation.\n"); 2460 ahd_dump_card_state(ahd); 2461 } 2462 } 2463 if ((lastphase & ~P_DATAIN_DT) == 0 2464 || lastphase == P_COMMAND) { 2465 proto_violation_reset: 2466 /* 2467 * Target either went directly to data 2468 * phase or didn't respond to our ATN. 2469 * The only safe thing to do is to blow 2470 * it away with a bus reset. 2471 */ 2472 found = ahd_reset_channel(ahd, 'A', TRUE); 2473 printf("%s: Issued Channel %c Bus Reset. " 2474 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2475 } else { 2476 /* 2477 * Leave the selection hardware off in case 2478 * this abort attempt will affect yet to 2479 * be sent commands. 2480 */ 2481 ahd_outb(ahd, SCSISEQ0, 2482 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2483 ahd_assert_atn(ahd); 2484 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2485 if (scb == NULL) { 2486 ahd_print_devinfo(ahd, &devinfo); 2487 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2488 ahd->msgout_len = 1; 2489 ahd->msgout_index = 0; 2490 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2491 } else { 2492 ahd_print_path(ahd, scb); 2493 scb->flags |= SCB_ABORT; 2494 } 2495 printf("Protocol violation %s. Attempting to abort.\n", 2496 ahd_lookup_phase_entry(curphase)->phasemsg); 2497 } 2498 } 2499 2500 /* 2501 * Force renegotiation to occur the next time we initiate 2502 * a command to the current device. 2503 */ 2504 static void 2505 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2506 { 2507 struct ahd_initiator_tinfo *targ_info; 2508 struct ahd_tmode_tstate *tstate; 2509 2510 #ifdef AHD_DEBUG 2511 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2512 ahd_print_devinfo(ahd, devinfo); 2513 printf("Forcing renegotiation\n"); 2514 } 2515 #endif 2516 targ_info = ahd_fetch_transinfo(ahd, 2517 devinfo->channel, 2518 devinfo->our_scsiid, 2519 devinfo->target, 2520 &tstate); 2521 ahd_update_neg_request(ahd, devinfo, tstate, 2522 targ_info, AHD_NEG_IF_NON_ASYNC); 2523 } 2524 2525 #define AHD_MAX_STEPS 2000 2526 void 2527 ahd_clear_critical_section(struct ahd_softc *ahd) 2528 { 2529 ahd_mode_state saved_modes; 2530 int stepping; 2531 int steps; 2532 int first_instr; 2533 u_int simode0; 2534 u_int simode1; 2535 u_int simode3; 2536 u_int lqimode0; 2537 u_int lqimode1; 2538 u_int lqomode0; 2539 u_int lqomode1; 2540 2541 if (ahd->num_critical_sections == 0) 2542 return; 2543 2544 stepping = FALSE; 2545 steps = 0; 2546 first_instr = 0; 2547 simode0 = 0; 2548 simode1 = 0; 2549 simode3 = 0; 2550 lqimode0 = 0; 2551 lqimode1 = 0; 2552 lqomode0 = 0; 2553 lqomode1 = 0; 2554 saved_modes = ahd_save_modes(ahd); 2555 for (;;) { 2556 struct cs *cs; 2557 u_int seqaddr; 2558 u_int i; 2559 2560 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2561 seqaddr = ahd_inw(ahd, CURADDR); 2562 2563 cs = ahd->critical_sections; 2564 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2565 2566 if (cs->begin < seqaddr && cs->end >= seqaddr) 2567 break; 2568 } 2569 2570 if (i == ahd->num_critical_sections) 2571 break; 2572 2573 if (steps > AHD_MAX_STEPS) { 2574 printf("%s: Infinite loop in critical section\n" 2575 "%s: First Instruction 0x%x now 0x%x\n", 2576 ahd_name(ahd), ahd_name(ahd), first_instr, 2577 seqaddr); 2578 ahd_dump_card_state(ahd); 2579 panic("critical section loop"); 2580 } 2581 2582 steps++; 2583 #ifdef AHD_DEBUG 2584 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2585 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2586 seqaddr); 2587 #endif 2588 if (stepping == FALSE) { 2589 2590 first_instr = seqaddr; 2591 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2592 simode0 = ahd_inb(ahd, SIMODE0); 2593 simode3 = ahd_inb(ahd, SIMODE3); 2594 lqimode0 = ahd_inb(ahd, LQIMODE0); 2595 lqimode1 = ahd_inb(ahd, LQIMODE1); 2596 lqomode0 = ahd_inb(ahd, LQOMODE0); 2597 lqomode1 = ahd_inb(ahd, LQOMODE1); 2598 ahd_outb(ahd, SIMODE0, 0); 2599 ahd_outb(ahd, SIMODE3, 0); 2600 ahd_outb(ahd, LQIMODE0, 0); 2601 ahd_outb(ahd, LQIMODE1, 0); 2602 ahd_outb(ahd, LQOMODE0, 0); 2603 ahd_outb(ahd, LQOMODE1, 0); 2604 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2605 simode1 = ahd_inb(ahd, SIMODE1); 2606 /* 2607 * We don't clear ENBUSFREE. Unfortunately 2608 * we cannot re-enable busfree detection within 2609 * the current connection, so we must leave it 2610 * on while single stepping. 2611 */ 2612 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 2613 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2614 stepping = TRUE; 2615 } 2616 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2617 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2618 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2619 ahd_outb(ahd, HCNTRL, ahd->unpause); 2620 while (!ahd_is_paused(ahd)) 2621 ahd_delay(200); 2622 ahd_update_modes(ahd); 2623 } 2624 if (stepping) { 2625 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2626 ahd_outb(ahd, SIMODE0, simode0); 2627 ahd_outb(ahd, SIMODE3, simode3); 2628 ahd_outb(ahd, LQIMODE0, lqimode0); 2629 ahd_outb(ahd, LQIMODE1, lqimode1); 2630 ahd_outb(ahd, LQOMODE0, lqomode0); 2631 ahd_outb(ahd, LQOMODE1, lqomode1); 2632 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2633 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2634 ahd_outb(ahd, SIMODE1, simode1); 2635 /* 2636 * SCSIINT seems to glitch occassionally when 2637 * the interrupt masks are restored. Clear SCSIINT 2638 * one more time so that only persistent errors 2639 * are seen as a real interrupt. 2640 */ 2641 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2642 } 2643 ahd_restore_modes(ahd, saved_modes); 2644 } 2645 2646 /* 2647 * Clear any pending interrupt status. 2648 */ 2649 void 2650 ahd_clear_intstat(struct ahd_softc *ahd) 2651 { 2652 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2653 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2654 /* Clear any interrupt conditions this may have caused */ 2655 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2656 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2657 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2658 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2659 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2660 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2661 |CLRLQOATNPKT|CLRLQOTCRC); 2662 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2663 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2664 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2665 ahd_outb(ahd, CLRLQOINT0, 0); 2666 ahd_outb(ahd, CLRLQOINT1, 0); 2667 } 2668 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2669 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2670 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2671 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2672 |CLRIOERR|CLROVERRUN); 2673 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2674 } 2675 2676 /**************************** Debugging Routines ******************************/ 2677 #ifdef AHD_DEBUG 2678 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2679 #endif 2680 void 2681 ahd_print_scb(struct scb *scb) 2682 { 2683 struct hardware_scb *hscb; 2684 int i; 2685 2686 hscb = scb->hscb; 2687 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2688 (void *)scb, 2689 hscb->control, 2690 hscb->scsiid, 2691 hscb->lun, 2692 hscb->cdb_len); 2693 printf("Shared Data: "); 2694 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2695 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2696 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2697 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2698 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2699 ahd_le32toh(hscb->datacnt), 2700 ahd_le32toh(hscb->sgptr), 2701 SCB_GET_TAG(scb)); 2702 ahd_dump_sglist(scb); 2703 } 2704 2705 void 2706 ahd_dump_sglist(struct scb *scb) 2707 { 2708 int i; 2709 2710 if (scb->sg_count > 0) { 2711 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2712 struct ahd_dma64_seg *sg_list; 2713 2714 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2715 for (i = 0; i < scb->sg_count; i++) { 2716 uint64_t addr; 2717 uint32_t len; 2718 2719 addr = ahd_le64toh(sg_list[i].addr); 2720 len = ahd_le32toh(sg_list[i].len); 2721 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2722 i, 2723 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2724 (uint32_t)(addr & 0xFFFFFFFF), 2725 sg_list[i].len & AHD_SG_LEN_MASK, 2726 (sg_list[i].len & AHD_DMA_LAST_SEG) 2727 ? " Last" : ""); 2728 } 2729 } else { 2730 struct ahd_dma_seg *sg_list; 2731 2732 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2733 for (i = 0; i < scb->sg_count; i++) { 2734 uint32_t len; 2735 2736 len = ahd_le32toh(sg_list[i].len); 2737 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2738 i, 2739 (len & AHD_SG_HIGH_ADDR_MASK) >> 24, 2740 ahd_le32toh(sg_list[i].addr), 2741 len & AHD_SG_LEN_MASK, 2742 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2743 } 2744 } 2745 } 2746 } 2747 2748 /************************* Transfer Negotiation *******************************/ 2749 /* 2750 * Allocate per target mode instance (ID we respond to as a target) 2751 * transfer negotiation data structures. 2752 */ 2753 static struct ahd_tmode_tstate * 2754 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2755 { 2756 struct ahd_tmode_tstate *master_tstate; 2757 struct ahd_tmode_tstate *tstate; 2758 int i; 2759 2760 master_tstate = ahd->enabled_targets[ahd->our_id]; 2761 if (ahd->enabled_targets[scsi_id] != NULL 2762 && ahd->enabled_targets[scsi_id] != master_tstate) 2763 panic("%s: ahd_alloc_tstate - Target already allocated", 2764 ahd_name(ahd)); 2765 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 2766 if (tstate == NULL) 2767 return (NULL); 2768 2769 /* 2770 * If we have allocated a master tstate, copy user settings from 2771 * the master tstate (taken from SRAM or the EEPROM) for this 2772 * channel, but reset our current and goal settings to async/narrow 2773 * until an initiator talks to us. 2774 */ 2775 if (master_tstate != NULL) { 2776 memcpy(tstate, master_tstate, sizeof(*tstate)); 2777 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2778 for (i = 0; i < 16; i++) { 2779 memset(&tstate->transinfo[i].curr, 0, 2780 sizeof(tstate->transinfo[i].curr)); 2781 memset(&tstate->transinfo[i].goal, 0, 2782 sizeof(tstate->transinfo[i].goal)); 2783 } 2784 } else 2785 memset(tstate, 0, sizeof(*tstate)); 2786 ahd->enabled_targets[scsi_id] = tstate; 2787 return (tstate); 2788 } 2789 2790 #ifdef AHD_TARGET_MODE 2791 /* 2792 * Free per target mode instance (ID we respond to as a target) 2793 * transfer negotiation data structures. 2794 */ 2795 static void 2796 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2797 { 2798 struct ahd_tmode_tstate *tstate; 2799 2800 /* 2801 * Don't clean up our "master" tstate. 2802 * It has our default user settings. 2803 */ 2804 if (scsi_id == ahd->our_id 2805 && force == FALSE) 2806 return; 2807 2808 tstate = ahd->enabled_targets[scsi_id]; 2809 if (tstate != NULL) 2810 free(tstate, M_DEVBUF); 2811 ahd->enabled_targets[scsi_id] = NULL; 2812 } 2813 #endif 2814 2815 /* 2816 * Called when we have an active connection to a target on the bus, 2817 * this function finds the nearest period to the input period limited 2818 * by the capabilities of the bus connectivity of and sync settings for 2819 * the target. 2820 */ 2821 void 2822 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2823 struct ahd_initiator_tinfo *tinfo, 2824 u_int *period, u_int *ppr_options, role_t role) 2825 { 2826 struct ahd_transinfo *transinfo; 2827 u_int maxsync; 2828 2829 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2830 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2831 maxsync = AHD_SYNCRATE_PACED; 2832 } else { 2833 maxsync = AHD_SYNCRATE_ULTRA; 2834 /* Can't do DT related options on an SE bus */ 2835 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2836 } 2837 /* 2838 * Never allow a value higher than our current goal 2839 * period otherwise we may allow a target initiated 2840 * negotiation to go above the limit as set by the 2841 * user. In the case of an initiator initiated 2842 * sync negotiation, we limit based on the user 2843 * setting. This allows the system to still accept 2844 * incoming negotiations even if target initiated 2845 * negotiation is not performed. 2846 */ 2847 if (role == ROLE_TARGET) 2848 transinfo = &tinfo->user; 2849 else 2850 transinfo = &tinfo->goal; 2851 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2852 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2853 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2854 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2855 } 2856 if (transinfo->period == 0) { 2857 *period = 0; 2858 *ppr_options = 0; 2859 } else { 2860 *period = MAX(*period, transinfo->period); 2861 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2862 } 2863 } 2864 2865 /* 2866 * Look up the valid period to SCSIRATE conversion in our table. 2867 * Return the period and offset that should be sent to the target 2868 * if this was the beginning of an SDTR. 2869 */ 2870 void 2871 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2872 u_int *ppr_options, u_int maxsync) 2873 { 2874 if (*period < maxsync) 2875 *period = maxsync; 2876 2877 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2878 && *period > AHD_SYNCRATE_MIN_DT) 2879 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2880 2881 if (*period > AHD_SYNCRATE_MIN) 2882 *period = 0; 2883 2884 /* Honor PPR option conformance rules. */ 2885 if (*period > AHD_SYNCRATE_PACED) 2886 *ppr_options &= ~MSG_EXT_PPR_RTI; 2887 2888 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2889 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2890 2891 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2892 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2893 2894 /* Skip all PACED only entries if IU is not available */ 2895 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2896 && *period < AHD_SYNCRATE_DT) 2897 *period = AHD_SYNCRATE_DT; 2898 2899 /* Skip all DT only entries if DT is not available */ 2900 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2901 && *period < AHD_SYNCRATE_ULTRA2) 2902 *period = AHD_SYNCRATE_ULTRA2; 2903 } 2904 2905 /* 2906 * Truncate the given synchronous offset to a value the 2907 * current adapter type and syncrate are capable of. 2908 */ 2909 void 2910 ahd_validate_offset(struct ahd_softc *ahd, 2911 struct ahd_initiator_tinfo *tinfo, 2912 u_int period, u_int *offset, int wide, 2913 role_t role) 2914 { 2915 u_int maxoffset; 2916 2917 /* Limit offset to what we can do */ 2918 if (period == 0) 2919 maxoffset = 0; 2920 else if (period <= AHD_SYNCRATE_PACED) { 2921 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2922 maxoffset = MAX_OFFSET_PACED_BUG; 2923 else 2924 maxoffset = MAX_OFFSET_PACED; 2925 } else 2926 maxoffset = MAX_OFFSET_NON_PACED; 2927 *offset = MIN(*offset, maxoffset); 2928 if (tinfo != NULL) { 2929 if (role == ROLE_TARGET) 2930 *offset = MIN(*offset, tinfo->user.offset); 2931 else 2932 *offset = MIN(*offset, tinfo->goal.offset); 2933 } 2934 } 2935 2936 /* 2937 * Truncate the given transfer width parameter to a value the 2938 * current adapter type is capable of. 2939 */ 2940 void 2941 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2942 u_int *bus_width, role_t role) 2943 { 2944 switch (*bus_width) { 2945 default: 2946 if (ahd->features & AHD_WIDE) { 2947 /* Respond Wide */ 2948 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2949 break; 2950 } 2951 /* FALLTHROUGH */ 2952 case MSG_EXT_WDTR_BUS_8_BIT: 2953 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2954 break; 2955 } 2956 if (tinfo != NULL) { 2957 if (role == ROLE_TARGET) 2958 *bus_width = MIN(tinfo->user.width, *bus_width); 2959 else 2960 *bus_width = MIN(tinfo->goal.width, *bus_width); 2961 } 2962 } 2963 2964 /* 2965 * Update the bitmask of targets for which the controller should 2966 * negotiate with at the next convenient oportunity. This currently 2967 * means the next time we send the initial identify messages for 2968 * a new transaction. 2969 */ 2970 int 2971 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2972 struct ahd_tmode_tstate *tstate, 2973 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2974 { 2975 u_int auto_negotiate_orig; 2976 2977 auto_negotiate_orig = tstate->auto_negotiate; 2978 if (neg_type == AHD_NEG_ALWAYS) { 2979 /* 2980 * Force our "current" settings to be 2981 * unknown so that unless a bus reset 2982 * occurs the need to renegotiate is 2983 * recorded persistently. 2984 */ 2985 if ((ahd->features & AHD_WIDE) != 0) 2986 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2987 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2988 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2989 } 2990 if (tinfo->curr.period != tinfo->goal.period 2991 || tinfo->curr.width != tinfo->goal.width 2992 || tinfo->curr.offset != tinfo->goal.offset 2993 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2994 || (neg_type == AHD_NEG_IF_NON_ASYNC 2995 && (tinfo->goal.offset != 0 2996 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2997 || tinfo->goal.ppr_options != 0))) 2998 tstate->auto_negotiate |= devinfo->target_mask; 2999 else 3000 tstate->auto_negotiate &= ~devinfo->target_mask; 3001 3002 return (auto_negotiate_orig != tstate->auto_negotiate); 3003 } 3004 3005 /* 3006 * Update the user/goal/curr tables of synchronous negotiation 3007 * parameters as well as, in the case of a current or active update, 3008 * any data structures on the host controller. In the case of an 3009 * active update, the specified target is currently talking to us on 3010 * the bus, so the transfer parameter update must take effect 3011 * immediately. 3012 */ 3013 void 3014 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3015 u_int period, u_int offset, u_int ppr_options, 3016 u_int type, int paused) 3017 { 3018 struct ahd_initiator_tinfo *tinfo; 3019 struct ahd_tmode_tstate *tstate; 3020 u_int old_period; 3021 u_int old_offset; 3022 u_int old_ppr; 3023 int active; 3024 int update_needed; 3025 3026 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3027 update_needed = 0; 3028 3029 if (period == 0 || offset == 0) { 3030 period = 0; 3031 offset = 0; 3032 } 3033 3034 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3035 devinfo->target, &tstate); 3036 3037 if ((type & AHD_TRANS_USER) != 0) { 3038 tinfo->user.period = period; 3039 tinfo->user.offset = offset; 3040 tinfo->user.ppr_options = ppr_options; 3041 } 3042 3043 if ((type & AHD_TRANS_GOAL) != 0) { 3044 tinfo->goal.period = period; 3045 tinfo->goal.offset = offset; 3046 tinfo->goal.ppr_options = ppr_options; 3047 } 3048 3049 old_period = tinfo->curr.period; 3050 old_offset = tinfo->curr.offset; 3051 old_ppr = tinfo->curr.ppr_options; 3052 3053 if ((type & AHD_TRANS_CUR) != 0 3054 && (old_period != period 3055 || old_offset != offset 3056 || old_ppr != ppr_options)) { 3057 3058 update_needed++; 3059 3060 tinfo->curr.period = period; 3061 tinfo->curr.offset = offset; 3062 tinfo->curr.ppr_options = ppr_options; 3063 3064 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3065 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3066 if (bootverbose) { 3067 if (offset != 0) { 3068 int options; 3069 3070 printf("%s: target %d synchronous with " 3071 "period = 0x%x, offset = 0x%x", 3072 ahd_name(ahd), devinfo->target, 3073 period, offset); 3074 options = 0; 3075 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 3076 printf("(RDSTRM"); 3077 options++; 3078 } 3079 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 3080 printf("%s", options ? "|DT" : "(DT"); 3081 options++; 3082 } 3083 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 3084 printf("%s", options ? "|IU" : "(IU"); 3085 options++; 3086 } 3087 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 3088 printf("%s", options ? "|RTI" : "(RTI"); 3089 options++; 3090 } 3091 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 3092 printf("%s", options ? "|QAS" : "(QAS"); 3093 options++; 3094 } 3095 if (options != 0) 3096 printf(")\n"); 3097 else 3098 printf("\n"); 3099 } else { 3100 printf("%s: target %d using " 3101 "asynchronous transfers%s\n", 3102 ahd_name(ahd), devinfo->target, 3103 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 3104 ? "(QAS)" : ""); 3105 } 3106 } 3107 } 3108 /* 3109 * Always refresh the neg-table to handle the case of the 3110 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 3111 * We will always renegotiate in that case if this is a 3112 * packetized request. Also manage the busfree expected flag 3113 * from this common routine so that we catch changes due to 3114 * WDTR or SDTR messages. 3115 */ 3116 if ((type & AHD_TRANS_CUR) != 0) { 3117 if (!paused) 3118 ahd_pause(ahd); 3119 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3120 if (!paused) 3121 ahd_unpause(ahd); 3122 if (ahd->msg_type != MSG_TYPE_NONE) { 3123 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 3124 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 3125 #ifdef AHD_DEBUG 3126 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3127 ahd_print_devinfo(ahd, devinfo); 3128 printf("Expecting IU Change busfree\n"); 3129 } 3130 #endif 3131 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 3132 | MSG_FLAG_IU_REQ_CHANGED; 3133 } 3134 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 3135 #ifdef AHD_DEBUG 3136 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3137 printf("PPR with IU_REQ outstanding\n"); 3138 #endif 3139 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 3140 } 3141 } 3142 } 3143 3144 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3145 tinfo, AHD_NEG_TO_GOAL); 3146 3147 if (update_needed && active) 3148 ahd_update_pending_scbs(ahd); 3149 } 3150 3151 /* 3152 * Update the user/goal/curr tables of wide negotiation 3153 * parameters as well as, in the case of a current or active update, 3154 * any data structures on the host controller. In the case of an 3155 * active update, the specified target is currently talking to us on 3156 * the bus, so the transfer parameter update must take effect 3157 * immediately. 3158 */ 3159 void 3160 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3161 u_int width, u_int type, int paused) 3162 { 3163 struct ahd_initiator_tinfo *tinfo; 3164 struct ahd_tmode_tstate *tstate; 3165 u_int oldwidth; 3166 int active; 3167 int update_needed; 3168 3169 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3170 update_needed = 0; 3171 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3172 devinfo->target, &tstate); 3173 3174 if ((type & AHD_TRANS_USER) != 0) 3175 tinfo->user.width = width; 3176 3177 if ((type & AHD_TRANS_GOAL) != 0) 3178 tinfo->goal.width = width; 3179 3180 oldwidth = tinfo->curr.width; 3181 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 3182 3183 update_needed++; 3184 3185 tinfo->curr.width = width; 3186 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3187 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3188 if (bootverbose) { 3189 printf("%s: target %d using %dbit transfers\n", 3190 ahd_name(ahd), devinfo->target, 3191 8 * (0x01 << width)); 3192 } 3193 } 3194 3195 if ((type & AHD_TRANS_CUR) != 0) { 3196 if (!paused) 3197 ahd_pause(ahd); 3198 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3199 if (!paused) 3200 ahd_unpause(ahd); 3201 } 3202 3203 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3204 tinfo, AHD_NEG_TO_GOAL); 3205 if (update_needed && active) 3206 ahd_update_pending_scbs(ahd); 3207 3208 } 3209 3210 /* 3211 * Update the current state of tagged queuing for a given target. 3212 */ 3213 void 3214 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3215 ahd_queue_alg alg) 3216 { 3217 ahd_platform_set_tags(ahd, devinfo, alg); 3218 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3219 devinfo->lun, AC_TRANSFER_NEG, &alg); 3220 } 3221 3222 static void 3223 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3224 struct ahd_transinfo *tinfo) 3225 { 3226 ahd_mode_state saved_modes; 3227 u_int period; 3228 u_int ppr_opts; 3229 u_int con_opts; 3230 u_int offset; 3231 u_int saved_negoaddr; 3232 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 3233 3234 saved_modes = ahd_save_modes(ahd); 3235 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3236 3237 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 3238 ahd_outb(ahd, NEGOADDR, devinfo->target); 3239 period = tinfo->period; 3240 offset = tinfo->offset; 3241 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 3242 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 3243 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 3244 con_opts = 0; 3245 if (period == 0) 3246 period = AHD_SYNCRATE_ASYNC; 3247 if (period == AHD_SYNCRATE_160) { 3248 3249 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3250 /* 3251 * When the SPI4 spec was finalized, PACE transfers 3252 * was not made a configurable option in the PPR 3253 * message. Instead it is assumed to be enabled for 3254 * any syncrate faster than 80MHz. Nevertheless, 3255 * Harpoon2A4 allows this to be configurable. 3256 * 3257 * Harpoon2A4 also assumes at most 2 data bytes per 3258 * negotiated REQ/ACK offset. Paced transfers take 3259 * 4, so we must adjust our offset. 3260 */ 3261 ppr_opts |= PPROPT_PACE; 3262 offset *= 2; 3263 3264 /* 3265 * Harpoon2A assumed that there would be a 3266 * fallback rate between 160MHz and 80Mhz, 3267 * so 7 is used as the period factor rather 3268 * than 8 for 160MHz. 3269 */ 3270 period = AHD_SYNCRATE_REVA_160; 3271 } 3272 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 3273 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3274 ~AHD_PRECOMP_MASK; 3275 } else { 3276 /* 3277 * Precomp should be disabled for non-paced transfers. 3278 */ 3279 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 3280 3281 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 3282 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0 3283 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) { 3284 /* 3285 * Slow down our CRC interval to be 3286 * compatible with non-packetized 3287 * U160 devices that can't handle a 3288 * CRC at full speed. 3289 */ 3290 con_opts |= ENSLOWCRC; 3291 } 3292 3293 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3294 /* 3295 * On H2A4, revert to a slower slewrate 3296 * on non-paced transfers. 3297 */ 3298 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3299 ~AHD_SLEWRATE_MASK; 3300 } 3301 } 3302 3303 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 3304 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 3305 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 3306 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 3307 3308 ahd_outb(ahd, NEGPERIOD, period); 3309 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 3310 ahd_outb(ahd, NEGOFFSET, offset); 3311 3312 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 3313 con_opts |= WIDEXFER; 3314 3315 /* 3316 * Slow down our CRC interval to be 3317 * compatible with packetized U320 devices 3318 * that can't handle a CRC at full speed 3319 */ 3320 if (ahd->features & AHD_AIC79XXB_SLOWCRC) { 3321 con_opts |= ENSLOWCRC; 3322 } 3323 3324 /* 3325 * During packetized transfers, the target will 3326 * give us the oportunity to send command packets 3327 * without us asserting attention. 3328 */ 3329 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 3330 con_opts |= ENAUTOATNO; 3331 ahd_outb(ahd, NEGCONOPTS, con_opts); 3332 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 3333 ahd_restore_modes(ahd, saved_modes); 3334 } 3335 3336 /* 3337 * When the transfer settings for a connection change, setup for 3338 * negotiation in pending SCBs to effect the change as quickly as 3339 * possible. We also cancel any negotiations that are scheduled 3340 * for inflight SCBs that have not been started yet. 3341 */ 3342 static void 3343 ahd_update_pending_scbs(struct ahd_softc *ahd) 3344 { 3345 struct scb *pending_scb; 3346 int pending_scb_count; 3347 int paused; 3348 u_int saved_scbptr; 3349 ahd_mode_state saved_modes; 3350 3351 /* 3352 * Traverse the pending SCB list and ensure that all of the 3353 * SCBs there have the proper settings. We can only safely 3354 * clear the negotiation required flag (setting requires the 3355 * execution queue to be modified) and this is only possible 3356 * if we are not already attempting to select out for this 3357 * SCB. For this reason, all callers only call this routine 3358 * if we are changing the negotiation settings for the currently 3359 * active transaction on the bus. 3360 */ 3361 pending_scb_count = 0; 3362 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 3363 struct ahd_devinfo devinfo; 3364 struct ahd_initiator_tinfo *tinfo; 3365 struct ahd_tmode_tstate *tstate; 3366 3367 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 3368 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 3369 devinfo.our_scsiid, 3370 devinfo.target, &tstate); 3371 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 3372 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 3373 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 3374 pending_scb->hscb->control &= ~MK_MESSAGE; 3375 } 3376 ahd_sync_scb(ahd, pending_scb, 3377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3378 pending_scb_count++; 3379 } 3380 3381 if (pending_scb_count == 0) 3382 return; 3383 3384 if (ahd_is_paused(ahd)) { 3385 paused = 1; 3386 } else { 3387 paused = 0; 3388 ahd_pause(ahd); 3389 } 3390 3391 /* 3392 * Force the sequencer to reinitialize the selection for 3393 * the command at the head of the execution queue if it 3394 * has already been setup. The negotiation changes may 3395 * effect whether we select-out with ATN. It is only 3396 * safe to clear ENSELO when the bus is not free and no 3397 * selection is in progres or completed. 3398 */ 3399 saved_modes = ahd_save_modes(ahd); 3400 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3401 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0 3402 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 3403 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3404 saved_scbptr = ahd_get_scbptr(ahd); 3405 /* Ensure that the hscbs down on the card match the new information */ 3406 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 3407 u_int scb_tag; 3408 u_int control; 3409 3410 scb_tag = SCB_GET_TAG(pending_scb); 3411 ahd_set_scbptr(ahd, scb_tag); 3412 control = ahd_inb_scbram(ahd, SCB_CONTROL); 3413 control &= ~MK_MESSAGE; 3414 control |= pending_scb->hscb->control & MK_MESSAGE; 3415 ahd_outb(ahd, SCB_CONTROL, control); 3416 } 3417 ahd_set_scbptr(ahd, saved_scbptr); 3418 ahd_restore_modes(ahd, saved_modes); 3419 3420 if (paused == 0) 3421 ahd_unpause(ahd); 3422 } 3423 3424 /**************************** Pathing Information *****************************/ 3425 static void 3426 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3427 { 3428 ahd_mode_state saved_modes; 3429 u_int saved_scsiid; 3430 role_t role; 3431 int our_id; 3432 3433 saved_modes = ahd_save_modes(ahd); 3434 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3435 3436 if (ahd_inb(ahd, SSTAT0) & TARGET) 3437 role = ROLE_TARGET; 3438 else 3439 role = ROLE_INITIATOR; 3440 3441 if (role == ROLE_TARGET 3442 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3443 /* We were selected, so pull our id from TARGIDIN */ 3444 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3445 } else if (role == ROLE_TARGET) 3446 our_id = ahd_inb(ahd, TOWNID); 3447 else 3448 our_id = ahd_inb(ahd, IOWNID); 3449 3450 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3451 ahd_compile_devinfo(devinfo, 3452 our_id, 3453 SCSIID_TARGET(ahd, saved_scsiid), 3454 ahd_inb(ahd, SAVED_LUN), 3455 SCSIID_CHANNEL(ahd, saved_scsiid), 3456 role); 3457 ahd_restore_modes(ahd, saved_modes); 3458 } 3459 3460 void 3461 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3462 { 3463 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A', 3464 devinfo->target, devinfo->lun); 3465 } 3466 3467 struct ahd_phase_table_entry* 3468 ahd_lookup_phase_entry(int phase) 3469 { 3470 struct ahd_phase_table_entry *entry; 3471 struct ahd_phase_table_entry *last_entry; 3472 3473 /* 3474 * num_phases doesn't include the default entry which 3475 * will be returned if the phase doesn't match. 3476 */ 3477 last_entry = &ahd_phase_table[num_phases]; 3478 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3479 if (phase == entry->phase) 3480 break; 3481 } 3482 return (entry); 3483 } 3484 3485 void 3486 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3487 u_int lun, char channel, role_t role) 3488 { 3489 devinfo->our_scsiid = our_id; 3490 devinfo->target = target; 3491 devinfo->lun = lun; 3492 devinfo->target_offset = target; 3493 devinfo->channel = channel; 3494 devinfo->role = role; 3495 if (channel == 'B') 3496 devinfo->target_offset += 8; 3497 devinfo->target_mask = (0x01 << devinfo->target_offset); 3498 } 3499 3500 static void 3501 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3502 struct scb *scb) 3503 { 3504 role_t role; 3505 int our_id; 3506 3507 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3508 role = ROLE_INITIATOR; 3509 if ((scb->hscb->control & TARGET_SCB) != 0) 3510 role = ROLE_TARGET; 3511 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3512 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3513 } 3514 3515 3516 /************************ Message Phase Processing ****************************/ 3517 /* 3518 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3519 * or enters the initial message out phase, we are interrupted. Fill our 3520 * outgoing message buffer with the appropriate message and beging handing 3521 * the message phase(s) manually. 3522 */ 3523 static void 3524 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3525 struct scb *scb) 3526 { 3527 /* 3528 * To facilitate adding multiple messages together, 3529 * each routine should increment the index and len 3530 * variables instead of setting them explicitly. 3531 */ 3532 ahd->msgout_index = 0; 3533 ahd->msgout_len = 0; 3534 3535 if (ahd_currently_packetized(ahd)) 3536 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3537 3538 if (ahd->send_msg_perror 3539 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3540 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3541 ahd->msgout_len++; 3542 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3543 #ifdef AHD_DEBUG 3544 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3545 printf("Setting up for Parity Error delivery\n"); 3546 #endif 3547 return; 3548 } else if (scb == NULL) { 3549 printf("%s: WARNING. No pending message for " 3550 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3551 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3552 ahd->msgout_len++; 3553 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3554 return; 3555 } 3556 3557 if ((scb->flags & SCB_DEVICE_RESET) == 0 3558 && (scb->flags & SCB_PACKETIZED) == 0 3559 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3560 u_int identify_msg; 3561 3562 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3563 if ((scb->hscb->control & DISCENB) != 0) 3564 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3565 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3566 ahd->msgout_len++; 3567 3568 if ((scb->hscb->control & TAG_ENB) != 0) { 3569 ahd->msgout_buf[ahd->msgout_index++] = 3570 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3571 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3572 ahd->msgout_len += 2; 3573 } 3574 } 3575 3576 if (scb->flags & SCB_DEVICE_RESET) { 3577 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3578 ahd->msgout_len++; 3579 ahd_print_path(ahd, scb); 3580 printf("Bus Device Reset Message Sent\n"); 3581 /* 3582 * Clear our selection hardware in advance of 3583 * the busfree. We may have an entry in the waiting 3584 * Q for this target, and we don't want to go about 3585 * selecting while we handle the busfree and blow it 3586 * away. 3587 */ 3588 ahd_outb(ahd, SCSISEQ0, 0); 3589 } else if ((scb->flags & SCB_ABORT) != 0) { 3590 3591 if ((scb->hscb->control & TAG_ENB) != 0) { 3592 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3593 } else { 3594 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3595 } 3596 ahd->msgout_len++; 3597 ahd_print_path(ahd, scb); 3598 printf("Abort%s Message Sent\n", 3599 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3600 /* 3601 * Clear our selection hardware in advance of 3602 * the busfree. We may have an entry in the waiting 3603 * Q for this target, and we don't want to go about 3604 * selecting while we handle the busfree and blow it 3605 * away. 3606 */ 3607 ahd_outb(ahd, SCSISEQ0, 0); 3608 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3609 ahd_build_transfer_msg(ahd, devinfo); 3610 /* 3611 * Clear our selection hardware in advance of potential 3612 * PPR IU status change busfree. We may have an entry in 3613 * the waiting Q for this target, and we don't want to go 3614 * about selecting while we handle the busfree and blow 3615 * it away. 3616 */ 3617 ahd_outb(ahd, SCSISEQ0, 0); 3618 } else { 3619 printf("ahd_intr: AWAITING_MSG for an SCB that " 3620 "does not have a waiting message\n"); 3621 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3622 devinfo->target_mask); 3623 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3624 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3625 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3626 scb->flags); 3627 } 3628 3629 /* 3630 * Clear the MK_MESSAGE flag from the SCB so we aren't 3631 * asked to send this message again. 3632 */ 3633 ahd_outb(ahd, SCB_CONTROL, 3634 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3635 scb->hscb->control &= ~MK_MESSAGE; 3636 ahd->msgout_index = 0; 3637 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3638 } 3639 3640 /* 3641 * Build an appropriate transfer negotiation message for the 3642 * currently active target. 3643 */ 3644 static void 3645 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3646 { 3647 /* 3648 * We need to initiate transfer negotiations. 3649 * If our current and goal settings are identical, 3650 * we want to renegotiate due to a check condition. 3651 */ 3652 struct ahd_initiator_tinfo *tinfo; 3653 struct ahd_tmode_tstate *tstate; 3654 int dowide; 3655 int dosync; 3656 int doppr; 3657 u_int period; 3658 u_int ppr_options; 3659 u_int offset; 3660 3661 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3662 devinfo->target, &tstate); 3663 /* 3664 * Filter our period based on the current connection. 3665 * If we can't perform DT transfers on this segment (not in LVD 3666 * mode for instance), then our decision to issue a PPR message 3667 * may change. 3668 */ 3669 period = tinfo->goal.period; 3670 offset = tinfo->goal.offset; 3671 ppr_options = tinfo->goal.ppr_options; 3672 /* Target initiated PPR is not allowed in the SCSI spec */ 3673 if (devinfo->role == ROLE_TARGET) 3674 ppr_options = 0; 3675 ahd_devlimited_syncrate(ahd, tinfo, &period, 3676 &ppr_options, devinfo->role); 3677 dowide = tinfo->curr.width != tinfo->goal.width; 3678 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 3679 /* 3680 * Only use PPR if we have options that need it, even if the device 3681 * claims to support it. There might be an expander in the way 3682 * that doesn't. 3683 */ 3684 doppr = ppr_options != 0; 3685 3686 if (!dowide && !dosync && !doppr) { 3687 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3688 dosync = tinfo->goal.offset != 0; 3689 } 3690 3691 if (!dowide && !dosync && !doppr) { 3692 /* 3693 * Force async with a WDTR message if we have a wide bus, 3694 * or just issue an SDTR with a 0 offset. 3695 */ 3696 if ((ahd->features & AHD_WIDE) != 0) 3697 dowide = 1; 3698 else 3699 dosync = 1; 3700 3701 if (bootverbose) { 3702 ahd_print_devinfo(ahd, devinfo); 3703 printf("Ensuring async\n"); 3704 } 3705 } 3706 /* Target initiated PPR is not allowed in the SCSI spec */ 3707 if (devinfo->role == ROLE_TARGET) 3708 doppr = 0; 3709 3710 /* 3711 * Both the PPR message and SDTR message require the 3712 * goal syncrate to be limited to what the target device 3713 * is capable of handling (based on whether an LVD->SE 3714 * expander is on the bus), so combine these two cases. 3715 * Regardless, guarantee that if we are using WDTR and SDTR 3716 * messages that WDTR comes first. 3717 */ 3718 if (doppr || (dosync && !dowide)) { 3719 3720 offset = tinfo->goal.offset; 3721 ahd_validate_offset(ahd, tinfo, period, &offset, 3722 doppr ? tinfo->goal.width 3723 : tinfo->curr.width, 3724 devinfo->role); 3725 if (doppr) { 3726 ahd_construct_ppr(ahd, devinfo, period, offset, 3727 tinfo->goal.width, ppr_options); 3728 } else { 3729 ahd_construct_sdtr(ahd, devinfo, period, offset); 3730 } 3731 } else { 3732 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3733 } 3734 } 3735 3736 /* 3737 * Build a synchronous negotiation message in our message 3738 * buffer based on the input parameters. 3739 */ 3740 static void 3741 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3742 u_int period, u_int offset) 3743 { 3744 if (offset == 0) 3745 period = AHD_ASYNC_XFER_PERIOD; 3746 ahd->msgout_index += spi_populate_sync_msg( 3747 ahd->msgout_buf + ahd->msgout_index, period, offset); 3748 ahd->msgout_len += 5; 3749 if (bootverbose) { 3750 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3751 ahd_name(ahd), devinfo->channel, devinfo->target, 3752 devinfo->lun, period, offset); 3753 } 3754 } 3755 3756 /* 3757 * Build a wide negotiateion message in our message 3758 * buffer based on the input parameters. 3759 */ 3760 static void 3761 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3762 u_int bus_width) 3763 { 3764 ahd->msgout_index += spi_populate_width_msg( 3765 ahd->msgout_buf + ahd->msgout_index, bus_width); 3766 ahd->msgout_len += 4; 3767 if (bootverbose) { 3768 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3769 ahd_name(ahd), devinfo->channel, devinfo->target, 3770 devinfo->lun, bus_width); 3771 } 3772 } 3773 3774 /* 3775 * Build a parallel protocol request message in our message 3776 * buffer based on the input parameters. 3777 */ 3778 static void 3779 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3780 u_int period, u_int offset, u_int bus_width, 3781 u_int ppr_options) 3782 { 3783 /* 3784 * Always request precompensation from 3785 * the other target if we are running 3786 * at paced syncrates. 3787 */ 3788 if (period <= AHD_SYNCRATE_PACED) 3789 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3790 if (offset == 0) 3791 period = AHD_ASYNC_XFER_PERIOD; 3792 ahd->msgout_index += spi_populate_ppr_msg( 3793 ahd->msgout_buf + ahd->msgout_index, period, offset, 3794 bus_width, ppr_options); 3795 ahd->msgout_len += 8; 3796 if (bootverbose) { 3797 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 3798 "offset %x, ppr_options %x\n", ahd_name(ahd), 3799 devinfo->channel, devinfo->target, devinfo->lun, 3800 bus_width, period, offset, ppr_options); 3801 } 3802 } 3803 3804 /* 3805 * Clear any active message state. 3806 */ 3807 static void 3808 ahd_clear_msg_state(struct ahd_softc *ahd) 3809 { 3810 ahd_mode_state saved_modes; 3811 3812 saved_modes = ahd_save_modes(ahd); 3813 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3814 ahd->send_msg_perror = 0; 3815 ahd->msg_flags = MSG_FLAG_NONE; 3816 ahd->msgout_len = 0; 3817 ahd->msgin_index = 0; 3818 ahd->msg_type = MSG_TYPE_NONE; 3819 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3820 /* 3821 * The target didn't care to respond to our 3822 * message request, so clear ATN. 3823 */ 3824 ahd_outb(ahd, CLRSINT1, CLRATNO); 3825 } 3826 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3827 ahd_outb(ahd, SEQ_FLAGS2, 3828 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3829 ahd_restore_modes(ahd, saved_modes); 3830 } 3831 3832 /* 3833 * Manual message loop handler. 3834 */ 3835 static void 3836 ahd_handle_message_phase(struct ahd_softc *ahd) 3837 { 3838 struct ahd_devinfo devinfo; 3839 u_int bus_phase; 3840 int end_session; 3841 3842 ahd_fetch_devinfo(ahd, &devinfo); 3843 end_session = FALSE; 3844 bus_phase = ahd_inb(ahd, LASTPHASE); 3845 3846 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3847 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3848 ahd_outb(ahd, LQCTL2, LQIRETRY); 3849 } 3850 reswitch: 3851 switch (ahd->msg_type) { 3852 case MSG_TYPE_INITIATOR_MSGOUT: 3853 { 3854 int lastbyte; 3855 int phasemis; 3856 int msgdone; 3857 3858 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3859 panic("HOST_MSG_LOOP interrupt with no active message"); 3860 3861 #ifdef AHD_DEBUG 3862 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3863 ahd_print_devinfo(ahd, &devinfo); 3864 printf("INITIATOR_MSG_OUT"); 3865 } 3866 #endif 3867 phasemis = bus_phase != P_MESGOUT; 3868 if (phasemis) { 3869 #ifdef AHD_DEBUG 3870 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3871 printf(" PHASEMIS %s\n", 3872 ahd_lookup_phase_entry(bus_phase) 3873 ->phasemsg); 3874 } 3875 #endif 3876 if (bus_phase == P_MESGIN) { 3877 /* 3878 * Change gears and see if 3879 * this messages is of interest to 3880 * us or should be passed back to 3881 * the sequencer. 3882 */ 3883 ahd_outb(ahd, CLRSINT1, CLRATNO); 3884 ahd->send_msg_perror = 0; 3885 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3886 ahd->msgin_index = 0; 3887 goto reswitch; 3888 } 3889 end_session = TRUE; 3890 break; 3891 } 3892 3893 if (ahd->send_msg_perror) { 3894 ahd_outb(ahd, CLRSINT1, CLRATNO); 3895 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3896 #ifdef AHD_DEBUG 3897 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3898 printf(" byte 0x%x\n", ahd->send_msg_perror); 3899 #endif 3900 /* 3901 * If we are notifying the target of a CRC error 3902 * during packetized operations, the target is 3903 * within its rights to acknowledge our message 3904 * with a busfree. 3905 */ 3906 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3907 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3908 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3909 3910 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3911 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3912 break; 3913 } 3914 3915 msgdone = ahd->msgout_index == ahd->msgout_len; 3916 if (msgdone) { 3917 /* 3918 * The target has requested a retry. 3919 * Re-assert ATN, reset our message index to 3920 * 0, and try again. 3921 */ 3922 ahd->msgout_index = 0; 3923 ahd_assert_atn(ahd); 3924 } 3925 3926 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3927 if (lastbyte) { 3928 /* Last byte is signified by dropping ATN */ 3929 ahd_outb(ahd, CLRSINT1, CLRATNO); 3930 } 3931 3932 /* 3933 * Clear our interrupt status and present 3934 * the next byte on the bus. 3935 */ 3936 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3937 #ifdef AHD_DEBUG 3938 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3939 printf(" byte 0x%x\n", 3940 ahd->msgout_buf[ahd->msgout_index]); 3941 #endif 3942 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3943 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3944 break; 3945 } 3946 case MSG_TYPE_INITIATOR_MSGIN: 3947 { 3948 int phasemis; 3949 int message_done; 3950 3951 #ifdef AHD_DEBUG 3952 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3953 ahd_print_devinfo(ahd, &devinfo); 3954 printf("INITIATOR_MSG_IN"); 3955 } 3956 #endif 3957 phasemis = bus_phase != P_MESGIN; 3958 if (phasemis) { 3959 #ifdef AHD_DEBUG 3960 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3961 printf(" PHASEMIS %s\n", 3962 ahd_lookup_phase_entry(bus_phase) 3963 ->phasemsg); 3964 } 3965 #endif 3966 ahd->msgin_index = 0; 3967 if (bus_phase == P_MESGOUT 3968 && (ahd->send_msg_perror != 0 3969 || (ahd->msgout_len != 0 3970 && ahd->msgout_index == 0))) { 3971 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3972 goto reswitch; 3973 } 3974 end_session = TRUE; 3975 break; 3976 } 3977 3978 /* Pull the byte in without acking it */ 3979 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3980 #ifdef AHD_DEBUG 3981 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3982 printf(" byte 0x%x\n", 3983 ahd->msgin_buf[ahd->msgin_index]); 3984 #endif 3985 3986 message_done = ahd_parse_msg(ahd, &devinfo); 3987 3988 if (message_done) { 3989 /* 3990 * Clear our incoming message buffer in case there 3991 * is another message following this one. 3992 */ 3993 ahd->msgin_index = 0; 3994 3995 /* 3996 * If this message illicited a response, 3997 * assert ATN so the target takes us to the 3998 * message out phase. 3999 */ 4000 if (ahd->msgout_len != 0) { 4001 #ifdef AHD_DEBUG 4002 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4003 ahd_print_devinfo(ahd, &devinfo); 4004 printf("Asserting ATN for response\n"); 4005 } 4006 #endif 4007 ahd_assert_atn(ahd); 4008 } 4009 } else 4010 ahd->msgin_index++; 4011 4012 if (message_done == MSGLOOP_TERMINATED) { 4013 end_session = TRUE; 4014 } else { 4015 /* Ack the byte */ 4016 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 4017 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 4018 } 4019 break; 4020 } 4021 case MSG_TYPE_TARGET_MSGIN: 4022 { 4023 int msgdone; 4024 int msgout_request; 4025 4026 /* 4027 * By default, the message loop will continue. 4028 */ 4029 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4030 4031 if (ahd->msgout_len == 0) 4032 panic("Target MSGIN with no active message"); 4033 4034 /* 4035 * If we interrupted a mesgout session, the initiator 4036 * will not know this until our first REQ. So, we 4037 * only honor mesgout requests after we've sent our 4038 * first byte. 4039 */ 4040 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 4041 && ahd->msgout_index > 0) 4042 msgout_request = TRUE; 4043 else 4044 msgout_request = FALSE; 4045 4046 if (msgout_request) { 4047 4048 /* 4049 * Change gears and see if 4050 * this messages is of interest to 4051 * us or should be passed back to 4052 * the sequencer. 4053 */ 4054 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 4055 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 4056 ahd->msgin_index = 0; 4057 /* Dummy read to REQ for first byte */ 4058 ahd_inb(ahd, SCSIDAT); 4059 ahd_outb(ahd, SXFRCTL0, 4060 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4061 break; 4062 } 4063 4064 msgdone = ahd->msgout_index == ahd->msgout_len; 4065 if (msgdone) { 4066 ahd_outb(ahd, SXFRCTL0, 4067 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4068 end_session = TRUE; 4069 break; 4070 } 4071 4072 /* 4073 * Present the next byte on the bus. 4074 */ 4075 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4076 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 4077 break; 4078 } 4079 case MSG_TYPE_TARGET_MSGOUT: 4080 { 4081 int lastbyte; 4082 int msgdone; 4083 4084 /* 4085 * By default, the message loop will continue. 4086 */ 4087 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4088 4089 /* 4090 * The initiator signals that this is 4091 * the last byte by dropping ATN. 4092 */ 4093 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 4094 4095 /* 4096 * Read the latched byte, but turn off SPIOEN first 4097 * so that we don't inadvertently cause a REQ for the 4098 * next byte. 4099 */ 4100 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4101 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 4102 msgdone = ahd_parse_msg(ahd, &devinfo); 4103 if (msgdone == MSGLOOP_TERMINATED) { 4104 /* 4105 * The message is *really* done in that it caused 4106 * us to go to bus free. The sequencer has already 4107 * been reset at this point, so pull the ejection 4108 * handle. 4109 */ 4110 return; 4111 } 4112 4113 ahd->msgin_index++; 4114 4115 /* 4116 * XXX Read spec about initiator dropping ATN too soon 4117 * and use msgdone to detect it. 4118 */ 4119 if (msgdone == MSGLOOP_MSGCOMPLETE) { 4120 ahd->msgin_index = 0; 4121 4122 /* 4123 * If this message illicited a response, transition 4124 * to the Message in phase and send it. 4125 */ 4126 if (ahd->msgout_len != 0) { 4127 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 4128 ahd_outb(ahd, SXFRCTL0, 4129 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4130 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4131 ahd->msgin_index = 0; 4132 break; 4133 } 4134 } 4135 4136 if (lastbyte) 4137 end_session = TRUE; 4138 else { 4139 /* Ask for the next byte. */ 4140 ahd_outb(ahd, SXFRCTL0, 4141 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4142 } 4143 4144 break; 4145 } 4146 default: 4147 panic("Unknown REQINIT message type"); 4148 } 4149 4150 if (end_session) { 4151 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 4152 printf("%s: Returning to Idle Loop\n", 4153 ahd_name(ahd)); 4154 ahd_clear_msg_state(ahd); 4155 4156 /* 4157 * Perform the equivalent of a clear_target_state. 4158 */ 4159 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 4160 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); 4161 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 4162 } else { 4163 ahd_clear_msg_state(ahd); 4164 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 4165 } 4166 } 4167 } 4168 4169 /* 4170 * See if we sent a particular extended message to the target. 4171 * If "full" is true, return true only if the target saw the full 4172 * message. If "full" is false, return true if the target saw at 4173 * least the first byte of the message. 4174 */ 4175 static int 4176 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 4177 { 4178 int found; 4179 u_int index; 4180 4181 found = FALSE; 4182 index = 0; 4183 4184 while (index < ahd->msgout_len) { 4185 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 4186 u_int end_index; 4187 4188 end_index = index + 1 + ahd->msgout_buf[index + 1]; 4189 if (ahd->msgout_buf[index+2] == msgval 4190 && type == AHDMSG_EXT) { 4191 4192 if (full) { 4193 if (ahd->msgout_index > end_index) 4194 found = TRUE; 4195 } else if (ahd->msgout_index > index) 4196 found = TRUE; 4197 } 4198 index = end_index; 4199 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 4200 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 4201 4202 /* Skip tag type and tag id or residue param*/ 4203 index += 2; 4204 } else { 4205 /* Single byte message */ 4206 if (type == AHDMSG_1B 4207 && ahd->msgout_index > index 4208 && (ahd->msgout_buf[index] == msgval 4209 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 4210 && msgval == MSG_IDENTIFYFLAG))) 4211 found = TRUE; 4212 index++; 4213 } 4214 4215 if (found) 4216 break; 4217 } 4218 return (found); 4219 } 4220 4221 /* 4222 * Wait for a complete incoming message, parse it, and respond accordingly. 4223 */ 4224 static int 4225 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4226 { 4227 struct ahd_initiator_tinfo *tinfo; 4228 struct ahd_tmode_tstate *tstate; 4229 int reject; 4230 int done; 4231 int response; 4232 4233 done = MSGLOOP_IN_PROG; 4234 response = FALSE; 4235 reject = FALSE; 4236 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 4237 devinfo->target, &tstate); 4238 4239 /* 4240 * Parse as much of the message as is available, 4241 * rejecting it if we don't support it. When 4242 * the entire message is available and has been 4243 * handled, return MSGLOOP_MSGCOMPLETE, indicating 4244 * that we have parsed an entire message. 4245 * 4246 * In the case of extended messages, we accept the length 4247 * byte outright and perform more checking once we know the 4248 * extended message type. 4249 */ 4250 switch (ahd->msgin_buf[0]) { 4251 case MSG_DISCONNECT: 4252 case MSG_SAVEDATAPOINTER: 4253 case MSG_CMDCOMPLETE: 4254 case MSG_RESTOREPOINTERS: 4255 case MSG_IGN_WIDE_RESIDUE: 4256 /* 4257 * End our message loop as these are messages 4258 * the sequencer handles on its own. 4259 */ 4260 done = MSGLOOP_TERMINATED; 4261 break; 4262 case MSG_MESSAGE_REJECT: 4263 response = ahd_handle_msg_reject(ahd, devinfo); 4264 /* FALLTHROUGH */ 4265 case MSG_NOOP: 4266 done = MSGLOOP_MSGCOMPLETE; 4267 break; 4268 case MSG_EXTENDED: 4269 { 4270 /* Wait for enough of the message to begin validation */ 4271 if (ahd->msgin_index < 2) 4272 break; 4273 switch (ahd->msgin_buf[2]) { 4274 case MSG_EXT_SDTR: 4275 { 4276 u_int period; 4277 u_int ppr_options; 4278 u_int offset; 4279 u_int saved_offset; 4280 4281 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 4282 reject = TRUE; 4283 break; 4284 } 4285 4286 /* 4287 * Wait until we have both args before validating 4288 * and acting on this message. 4289 * 4290 * Add one to MSG_EXT_SDTR_LEN to account for 4291 * the extended message preamble. 4292 */ 4293 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 4294 break; 4295 4296 period = ahd->msgin_buf[3]; 4297 ppr_options = 0; 4298 saved_offset = offset = ahd->msgin_buf[4]; 4299 ahd_devlimited_syncrate(ahd, tinfo, &period, 4300 &ppr_options, devinfo->role); 4301 ahd_validate_offset(ahd, tinfo, period, &offset, 4302 tinfo->curr.width, devinfo->role); 4303 if (bootverbose) { 4304 printf("(%s:%c:%d:%d): Received " 4305 "SDTR period %x, offset %x\n\t" 4306 "Filtered to period %x, offset %x\n", 4307 ahd_name(ahd), devinfo->channel, 4308 devinfo->target, devinfo->lun, 4309 ahd->msgin_buf[3], saved_offset, 4310 period, offset); 4311 } 4312 ahd_set_syncrate(ahd, devinfo, period, 4313 offset, ppr_options, 4314 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4315 /*paused*/TRUE); 4316 4317 /* 4318 * See if we initiated Sync Negotiation 4319 * and didn't have to fall down to async 4320 * transfers. 4321 */ 4322 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 4323 /* We started it */ 4324 if (saved_offset != offset) { 4325 /* Went too low - force async */ 4326 reject = TRUE; 4327 } 4328 } else { 4329 /* 4330 * Send our own SDTR in reply 4331 */ 4332 if (bootverbose 4333 && devinfo->role == ROLE_INITIATOR) { 4334 printf("(%s:%c:%d:%d): Target " 4335 "Initiated SDTR\n", 4336 ahd_name(ahd), devinfo->channel, 4337 devinfo->target, devinfo->lun); 4338 } 4339 ahd->msgout_index = 0; 4340 ahd->msgout_len = 0; 4341 ahd_construct_sdtr(ahd, devinfo, 4342 period, offset); 4343 ahd->msgout_index = 0; 4344 response = TRUE; 4345 } 4346 done = MSGLOOP_MSGCOMPLETE; 4347 break; 4348 } 4349 case MSG_EXT_WDTR: 4350 { 4351 u_int bus_width; 4352 u_int saved_width; 4353 u_int sending_reply; 4354 4355 sending_reply = FALSE; 4356 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 4357 reject = TRUE; 4358 break; 4359 } 4360 4361 /* 4362 * Wait until we have our arg before validating 4363 * and acting on this message. 4364 * 4365 * Add one to MSG_EXT_WDTR_LEN to account for 4366 * the extended message preamble. 4367 */ 4368 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 4369 break; 4370 4371 bus_width = ahd->msgin_buf[3]; 4372 saved_width = bus_width; 4373 ahd_validate_width(ahd, tinfo, &bus_width, 4374 devinfo->role); 4375 if (bootverbose) { 4376 printf("(%s:%c:%d:%d): Received WDTR " 4377 "%x filtered to %x\n", 4378 ahd_name(ahd), devinfo->channel, 4379 devinfo->target, devinfo->lun, 4380 saved_width, bus_width); 4381 } 4382 4383 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 4384 /* 4385 * Don't send a WDTR back to the 4386 * target, since we asked first. 4387 * If the width went higher than our 4388 * request, reject it. 4389 */ 4390 if (saved_width > bus_width) { 4391 reject = TRUE; 4392 printf("(%s:%c:%d:%d): requested %dBit " 4393 "transfers. Rejecting...\n", 4394 ahd_name(ahd), devinfo->channel, 4395 devinfo->target, devinfo->lun, 4396 8 * (0x01 << bus_width)); 4397 bus_width = 0; 4398 } 4399 } else { 4400 /* 4401 * Send our own WDTR in reply 4402 */ 4403 if (bootverbose 4404 && devinfo->role == ROLE_INITIATOR) { 4405 printf("(%s:%c:%d:%d): Target " 4406 "Initiated WDTR\n", 4407 ahd_name(ahd), devinfo->channel, 4408 devinfo->target, devinfo->lun); 4409 } 4410 ahd->msgout_index = 0; 4411 ahd->msgout_len = 0; 4412 ahd_construct_wdtr(ahd, devinfo, bus_width); 4413 ahd->msgout_index = 0; 4414 response = TRUE; 4415 sending_reply = TRUE; 4416 } 4417 /* 4418 * After a wide message, we are async, but 4419 * some devices don't seem to honor this portion 4420 * of the spec. Force a renegotiation of the 4421 * sync component of our transfer agreement even 4422 * if our goal is async. By updating our width 4423 * after forcing the negotiation, we avoid 4424 * renegotiating for width. 4425 */ 4426 ahd_update_neg_request(ahd, devinfo, tstate, 4427 tinfo, AHD_NEG_ALWAYS); 4428 ahd_set_width(ahd, devinfo, bus_width, 4429 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4430 /*paused*/TRUE); 4431 if (sending_reply == FALSE && reject == FALSE) { 4432 4433 /* 4434 * We will always have an SDTR to send. 4435 */ 4436 ahd->msgout_index = 0; 4437 ahd->msgout_len = 0; 4438 ahd_build_transfer_msg(ahd, devinfo); 4439 ahd->msgout_index = 0; 4440 response = TRUE; 4441 } 4442 done = MSGLOOP_MSGCOMPLETE; 4443 break; 4444 } 4445 case MSG_EXT_PPR: 4446 { 4447 u_int period; 4448 u_int offset; 4449 u_int bus_width; 4450 u_int ppr_options; 4451 u_int saved_width; 4452 u_int saved_offset; 4453 u_int saved_ppr_options; 4454 4455 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4456 reject = TRUE; 4457 break; 4458 } 4459 4460 /* 4461 * Wait until we have all args before validating 4462 * and acting on this message. 4463 * 4464 * Add one to MSG_EXT_PPR_LEN to account for 4465 * the extended message preamble. 4466 */ 4467 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4468 break; 4469 4470 period = ahd->msgin_buf[3]; 4471 offset = ahd->msgin_buf[5]; 4472 bus_width = ahd->msgin_buf[6]; 4473 saved_width = bus_width; 4474 ppr_options = ahd->msgin_buf[7]; 4475 /* 4476 * According to the spec, a DT only 4477 * period factor with no DT option 4478 * set implies async. 4479 */ 4480 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4481 && period <= 9) 4482 offset = 0; 4483 saved_ppr_options = ppr_options; 4484 saved_offset = offset; 4485 4486 /* 4487 * Transfer options are only available if we 4488 * are negotiating wide. 4489 */ 4490 if (bus_width == 0) 4491 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4492 4493 ahd_validate_width(ahd, tinfo, &bus_width, 4494 devinfo->role); 4495 ahd_devlimited_syncrate(ahd, tinfo, &period, 4496 &ppr_options, devinfo->role); 4497 ahd_validate_offset(ahd, tinfo, period, &offset, 4498 bus_width, devinfo->role); 4499 4500 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4501 /* 4502 * If we are unable to do any of the 4503 * requested options (we went too low), 4504 * then we'll have to reject the message. 4505 */ 4506 if (saved_width > bus_width 4507 || saved_offset != offset 4508 || saved_ppr_options != ppr_options) { 4509 reject = TRUE; 4510 period = 0; 4511 offset = 0; 4512 bus_width = 0; 4513 ppr_options = 0; 4514 } 4515 } else { 4516 if (devinfo->role != ROLE_TARGET) 4517 printf("(%s:%c:%d:%d): Target " 4518 "Initiated PPR\n", 4519 ahd_name(ahd), devinfo->channel, 4520 devinfo->target, devinfo->lun); 4521 else 4522 printf("(%s:%c:%d:%d): Initiator " 4523 "Initiated PPR\n", 4524 ahd_name(ahd), devinfo->channel, 4525 devinfo->target, devinfo->lun); 4526 ahd->msgout_index = 0; 4527 ahd->msgout_len = 0; 4528 ahd_construct_ppr(ahd, devinfo, period, offset, 4529 bus_width, ppr_options); 4530 ahd->msgout_index = 0; 4531 response = TRUE; 4532 } 4533 if (bootverbose) { 4534 printf("(%s:%c:%d:%d): Received PPR width %x, " 4535 "period %x, offset %x,options %x\n" 4536 "\tFiltered to width %x, period %x, " 4537 "offset %x, options %x\n", 4538 ahd_name(ahd), devinfo->channel, 4539 devinfo->target, devinfo->lun, 4540 saved_width, ahd->msgin_buf[3], 4541 saved_offset, saved_ppr_options, 4542 bus_width, period, offset, ppr_options); 4543 } 4544 ahd_set_width(ahd, devinfo, bus_width, 4545 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4546 /*paused*/TRUE); 4547 ahd_set_syncrate(ahd, devinfo, period, 4548 offset, ppr_options, 4549 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4550 /*paused*/TRUE); 4551 4552 done = MSGLOOP_MSGCOMPLETE; 4553 break; 4554 } 4555 default: 4556 /* Unknown extended message. Reject it. */ 4557 reject = TRUE; 4558 break; 4559 } 4560 break; 4561 } 4562 #ifdef AHD_TARGET_MODE 4563 case MSG_BUS_DEV_RESET: 4564 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4565 CAM_BDR_SENT, 4566 "Bus Device Reset Received", 4567 /*verbose_level*/0); 4568 ahd_restart(ahd); 4569 done = MSGLOOP_TERMINATED; 4570 break; 4571 case MSG_ABORT_TAG: 4572 case MSG_ABORT: 4573 case MSG_CLEAR_QUEUE: 4574 { 4575 int tag; 4576 4577 /* Target mode messages */ 4578 if (devinfo->role != ROLE_TARGET) { 4579 reject = TRUE; 4580 break; 4581 } 4582 tag = SCB_LIST_NULL; 4583 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4584 tag = ahd_inb(ahd, INITIATOR_TAG); 4585 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4586 devinfo->lun, tag, ROLE_TARGET, 4587 CAM_REQ_ABORTED); 4588 4589 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4590 if (tstate != NULL) { 4591 struct ahd_tmode_lstate* lstate; 4592 4593 lstate = tstate->enabled_luns[devinfo->lun]; 4594 if (lstate != NULL) { 4595 ahd_queue_lstate_event(ahd, lstate, 4596 devinfo->our_scsiid, 4597 ahd->msgin_buf[0], 4598 /*arg*/tag); 4599 ahd_send_lstate_events(ahd, lstate); 4600 } 4601 } 4602 ahd_restart(ahd); 4603 done = MSGLOOP_TERMINATED; 4604 break; 4605 } 4606 #endif 4607 case MSG_QAS_REQUEST: 4608 #ifdef AHD_DEBUG 4609 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4610 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4611 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4612 #endif 4613 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4614 /* FALLTHROUGH */ 4615 case MSG_TERM_IO_PROC: 4616 default: 4617 reject = TRUE; 4618 break; 4619 } 4620 4621 if (reject) { 4622 /* 4623 * Setup to reject the message. 4624 */ 4625 ahd->msgout_index = 0; 4626 ahd->msgout_len = 1; 4627 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4628 done = MSGLOOP_MSGCOMPLETE; 4629 response = TRUE; 4630 } 4631 4632 if (done != MSGLOOP_IN_PROG && !response) 4633 /* Clear the outgoing message buffer */ 4634 ahd->msgout_len = 0; 4635 4636 return (done); 4637 } 4638 4639 /* 4640 * Process a message reject message. 4641 */ 4642 static int 4643 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4644 { 4645 /* 4646 * What we care about here is if we had an 4647 * outstanding SDTR or WDTR message for this 4648 * target. If we did, this is a signal that 4649 * the target is refusing negotiation. 4650 */ 4651 struct scb *scb; 4652 struct ahd_initiator_tinfo *tinfo; 4653 struct ahd_tmode_tstate *tstate; 4654 u_int scb_index; 4655 u_int last_msg; 4656 int response = 0; 4657 4658 scb_index = ahd_get_scbptr(ahd); 4659 scb = ahd_lookup_scb(ahd, scb_index); 4660 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4661 devinfo->our_scsiid, 4662 devinfo->target, &tstate); 4663 /* Might be necessary */ 4664 last_msg = ahd_inb(ahd, LAST_MSG); 4665 4666 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4667 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4668 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4669 /* 4670 * Target may not like our SPI-4 PPR Options. 4671 * Attempt to negotiate 80MHz which will turn 4672 * off these options. 4673 */ 4674 if (bootverbose) { 4675 printf("(%s:%c:%d:%d): PPR Rejected. " 4676 "Trying simple U160 PPR\n", 4677 ahd_name(ahd), devinfo->channel, 4678 devinfo->target, devinfo->lun); 4679 } 4680 tinfo->goal.period = AHD_SYNCRATE_DT; 4681 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4682 | MSG_EXT_PPR_QAS_REQ 4683 | MSG_EXT_PPR_DT_REQ; 4684 } else { 4685 /* 4686 * Target does not support the PPR message. 4687 * Attempt to negotiate SPI-2 style. 4688 */ 4689 if (bootverbose) { 4690 printf("(%s:%c:%d:%d): PPR Rejected. " 4691 "Trying WDTR/SDTR\n", 4692 ahd_name(ahd), devinfo->channel, 4693 devinfo->target, devinfo->lun); 4694 } 4695 tinfo->goal.ppr_options = 0; 4696 tinfo->curr.transport_version = 2; 4697 tinfo->goal.transport_version = 2; 4698 } 4699 ahd->msgout_index = 0; 4700 ahd->msgout_len = 0; 4701 ahd_build_transfer_msg(ahd, devinfo); 4702 ahd->msgout_index = 0; 4703 response = 1; 4704 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4705 4706 /* note 8bit xfers */ 4707 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4708 "8bit transfers\n", ahd_name(ahd), 4709 devinfo->channel, devinfo->target, devinfo->lun); 4710 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4711 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4712 /*paused*/TRUE); 4713 /* 4714 * No need to clear the sync rate. If the target 4715 * did not accept the command, our syncrate is 4716 * unaffected. If the target started the negotiation, 4717 * but rejected our response, we already cleared the 4718 * sync rate before sending our WDTR. 4719 */ 4720 if (tinfo->goal.offset != tinfo->curr.offset) { 4721 4722 /* Start the sync negotiation */ 4723 ahd->msgout_index = 0; 4724 ahd->msgout_len = 0; 4725 ahd_build_transfer_msg(ahd, devinfo); 4726 ahd->msgout_index = 0; 4727 response = 1; 4728 } 4729 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4730 /* note asynch xfers and clear flag */ 4731 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4732 /*offset*/0, /*ppr_options*/0, 4733 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4734 /*paused*/TRUE); 4735 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4736 "Using asynchronous transfers\n", 4737 ahd_name(ahd), devinfo->channel, 4738 devinfo->target, devinfo->lun); 4739 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4740 int tag_type; 4741 int mask; 4742 4743 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4744 4745 if (tag_type == MSG_SIMPLE_TASK) { 4746 printf("(%s:%c:%d:%d): refuses tagged commands. " 4747 "Performing non-tagged I/O\n", ahd_name(ahd), 4748 devinfo->channel, devinfo->target, devinfo->lun); 4749 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4750 mask = ~0x23; 4751 } else { 4752 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4753 "Performing simple queue tagged I/O only\n", 4754 ahd_name(ahd), devinfo->channel, devinfo->target, 4755 devinfo->lun, tag_type == MSG_ORDERED_TASK 4756 ? "ordered" : "head of queue"); 4757 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4758 mask = ~0x03; 4759 } 4760 4761 /* 4762 * Resend the identify for this CCB as the target 4763 * may believe that the selection is invalid otherwise. 4764 */ 4765 ahd_outb(ahd, SCB_CONTROL, 4766 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4767 scb->hscb->control &= mask; 4768 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4769 /*type*/MSG_SIMPLE_TASK); 4770 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4771 ahd_assert_atn(ahd); 4772 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4773 SCB_GET_TAG(scb)); 4774 4775 /* 4776 * Requeue all tagged commands for this target 4777 * currently in our posession so they can be 4778 * converted to untagged commands. 4779 */ 4780 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4781 SCB_GET_CHANNEL(ahd, scb), 4782 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4783 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4784 SEARCH_COMPLETE); 4785 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4786 /* 4787 * Most likely the device believes that we had 4788 * previously negotiated packetized. 4789 */ 4790 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4791 | MSG_FLAG_IU_REQ_CHANGED; 4792 4793 ahd_force_renegotiation(ahd, devinfo); 4794 ahd->msgout_index = 0; 4795 ahd->msgout_len = 0; 4796 ahd_build_transfer_msg(ahd, devinfo); 4797 ahd->msgout_index = 0; 4798 response = 1; 4799 } else { 4800 /* 4801 * Otherwise, we ignore it. 4802 */ 4803 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4804 ahd_name(ahd), devinfo->channel, devinfo->target, 4805 last_msg); 4806 } 4807 return (response); 4808 } 4809 4810 /* 4811 * Process an ingnore wide residue message. 4812 */ 4813 static void 4814 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4815 { 4816 u_int scb_index; 4817 struct scb *scb; 4818 4819 scb_index = ahd_get_scbptr(ahd); 4820 scb = ahd_lookup_scb(ahd, scb_index); 4821 /* 4822 * XXX Actually check data direction in the sequencer? 4823 * Perhaps add datadir to some spare bits in the hscb? 4824 */ 4825 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4826 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4827 /* 4828 * Ignore the message if we haven't 4829 * seen an appropriate data phase yet. 4830 */ 4831 } else { 4832 /* 4833 * If the residual occurred on the last 4834 * transfer and the transfer request was 4835 * expected to end on an odd count, do 4836 * nothing. Otherwise, subtract a byte 4837 * and update the residual count accordingly. 4838 */ 4839 uint32_t sgptr; 4840 4841 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4842 if ((sgptr & SG_LIST_NULL) != 0 4843 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4844 & SCB_XFERLEN_ODD) != 0) { 4845 /* 4846 * If the residual occurred on the last 4847 * transfer and the transfer request was 4848 * expected to end on an odd count, do 4849 * nothing. 4850 */ 4851 } else { 4852 uint32_t data_cnt; 4853 uint64_t data_addr; 4854 uint32_t sglen; 4855 4856 /* Pull in the rest of the sgptr */ 4857 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4858 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4859 if ((sgptr & SG_LIST_NULL) != 0) { 4860 /* 4861 * The residual data count is not updated 4862 * for the command run to completion case. 4863 * Explicitly zero the count. 4864 */ 4865 data_cnt &= ~AHD_SG_LEN_MASK; 4866 } 4867 data_addr = ahd_inq(ahd, SHADDR); 4868 data_cnt += 1; 4869 data_addr -= 1; 4870 sgptr &= SG_PTR_MASK; 4871 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4872 struct ahd_dma64_seg *sg; 4873 4874 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4875 4876 /* 4877 * The residual sg ptr points to the next S/G 4878 * to load so we must go back one. 4879 */ 4880 sg--; 4881 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4882 if (sg != scb->sg_list 4883 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4884 4885 sg--; 4886 sglen = ahd_le32toh(sg->len); 4887 /* 4888 * Preserve High Address and SG_LIST 4889 * bits while setting the count to 1. 4890 */ 4891 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4892 data_addr = ahd_le64toh(sg->addr) 4893 + (sglen & AHD_SG_LEN_MASK) 4894 - 1; 4895 4896 /* 4897 * Increment sg so it points to the 4898 * "next" sg. 4899 */ 4900 sg++; 4901 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4902 sg); 4903 } 4904 } else { 4905 struct ahd_dma_seg *sg; 4906 4907 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4908 4909 /* 4910 * The residual sg ptr points to the next S/G 4911 * to load so we must go back one. 4912 */ 4913 sg--; 4914 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4915 if (sg != scb->sg_list 4916 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4917 4918 sg--; 4919 sglen = ahd_le32toh(sg->len); 4920 /* 4921 * Preserve High Address and SG_LIST 4922 * bits while setting the count to 1. 4923 */ 4924 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4925 data_addr = ahd_le32toh(sg->addr) 4926 + (sglen & AHD_SG_LEN_MASK) 4927 - 1; 4928 4929 /* 4930 * Increment sg so it points to the 4931 * "next" sg. 4932 */ 4933 sg++; 4934 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4935 sg); 4936 } 4937 } 4938 /* 4939 * Toggle the "oddness" of the transfer length 4940 * to handle this mid-transfer ignore wide 4941 * residue. This ensures that the oddness is 4942 * correct for subsequent data transfers. 4943 */ 4944 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4945 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4946 ^ SCB_XFERLEN_ODD); 4947 4948 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4949 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4950 /* 4951 * The FIFO's pointers will be updated if/when the 4952 * sequencer re-enters a data phase. 4953 */ 4954 } 4955 } 4956 } 4957 4958 4959 /* 4960 * Reinitialize the data pointers for the active transfer 4961 * based on its current residual. 4962 */ 4963 static void 4964 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4965 { 4966 struct scb *scb; 4967 ahd_mode_state saved_modes; 4968 u_int scb_index; 4969 u_int wait; 4970 uint32_t sgptr; 4971 uint32_t resid; 4972 uint64_t dataptr; 4973 4974 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4975 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4976 4977 scb_index = ahd_get_scbptr(ahd); 4978 scb = ahd_lookup_scb(ahd, scb_index); 4979 4980 /* 4981 * Release and reacquire the FIFO so we 4982 * have a clean slate. 4983 */ 4984 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4985 wait = 1000; 4986 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) 4987 ahd_delay(100); 4988 if (wait == 0) { 4989 ahd_print_path(ahd, scb); 4990 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4991 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4992 } 4993 saved_modes = ahd_save_modes(ahd); 4994 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4995 ahd_outb(ahd, DFFSTAT, 4996 ahd_inb(ahd, DFFSTAT) 4997 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4998 4999 /* 5000 * Determine initial values for data_addr and data_cnt 5001 * for resuming the data phase. 5002 */ 5003 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 5004 sgptr &= SG_PTR_MASK; 5005 5006 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 5007 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 5008 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 5009 5010 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 5011 struct ahd_dma64_seg *sg; 5012 5013 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5014 5015 /* The residual sg_ptr always points to the next sg */ 5016 sg--; 5017 5018 dataptr = ahd_le64toh(sg->addr) 5019 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 5020 - resid; 5021 ahd_outl(ahd, HADDR + 4, dataptr >> 32); 5022 } else { 5023 struct ahd_dma_seg *sg; 5024 5025 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5026 5027 /* The residual sg_ptr always points to the next sg */ 5028 sg--; 5029 5030 dataptr = ahd_le32toh(sg->addr) 5031 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 5032 - resid; 5033 ahd_outb(ahd, HADDR + 4, 5034 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 5035 } 5036 ahd_outl(ahd, HADDR, dataptr); 5037 ahd_outb(ahd, HCNT + 2, resid >> 16); 5038 ahd_outb(ahd, HCNT + 1, resid >> 8); 5039 ahd_outb(ahd, HCNT, resid); 5040 } 5041 5042 /* 5043 * Handle the effects of issuing a bus device reset message. 5044 */ 5045 static void 5046 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5047 u_int lun, cam_status status, char *message, 5048 int verbose_level) 5049 { 5050 #ifdef AHD_TARGET_MODE 5051 struct ahd_tmode_tstate* tstate; 5052 #endif 5053 int found; 5054 5055 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 5056 lun, SCB_LIST_NULL, devinfo->role, 5057 status); 5058 5059 #ifdef AHD_TARGET_MODE 5060 /* 5061 * Send an immediate notify ccb to all target mord peripheral 5062 * drivers affected by this action. 5063 */ 5064 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 5065 if (tstate != NULL) { 5066 u_int cur_lun; 5067 u_int max_lun; 5068 5069 if (lun != CAM_LUN_WILDCARD) { 5070 cur_lun = 0; 5071 max_lun = AHD_NUM_LUNS - 1; 5072 } else { 5073 cur_lun = lun; 5074 max_lun = lun; 5075 } 5076 for (cur_lun <= max_lun; cur_lun++) { 5077 struct ahd_tmode_lstate* lstate; 5078 5079 lstate = tstate->enabled_luns[cur_lun]; 5080 if (lstate == NULL) 5081 continue; 5082 5083 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 5084 MSG_BUS_DEV_RESET, /*arg*/0); 5085 ahd_send_lstate_events(ahd, lstate); 5086 } 5087 } 5088 #endif 5089 5090 /* 5091 * Go back to async/narrow transfers and renegotiate. 5092 */ 5093 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5094 AHD_TRANS_CUR, /*paused*/TRUE); 5095 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 5096 /*ppr_options*/0, AHD_TRANS_CUR, 5097 /*paused*/TRUE); 5098 5099 if (status != CAM_SEL_TIMEOUT) 5100 ahd_send_async(ahd, devinfo->channel, devinfo->target, 5101 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 5102 5103 if (message != NULL && bootverbose) 5104 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 5105 message, devinfo->channel, devinfo->target, found); 5106 } 5107 5108 #ifdef AHD_TARGET_MODE 5109 static void 5110 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5111 struct scb *scb) 5112 { 5113 5114 /* 5115 * To facilitate adding multiple messages together, 5116 * each routine should increment the index and len 5117 * variables instead of setting them explicitly. 5118 */ 5119 ahd->msgout_index = 0; 5120 ahd->msgout_len = 0; 5121 5122 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 5123 ahd_build_transfer_msg(ahd, devinfo); 5124 else 5125 panic("ahd_intr: AWAITING target message with no message"); 5126 5127 ahd->msgout_index = 0; 5128 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 5129 } 5130 #endif 5131 /**************************** Initialization **********************************/ 5132 static u_int 5133 ahd_sglist_size(struct ahd_softc *ahd) 5134 { 5135 bus_size_t list_size; 5136 5137 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 5138 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5139 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 5140 return (list_size); 5141 } 5142 5143 /* 5144 * Calculate the optimum S/G List allocation size. S/G elements used 5145 * for a given transaction must be physically contiguous. Assume the 5146 * OS will allocate full pages to us, so it doesn't make sense to request 5147 * less than a page. 5148 */ 5149 static u_int 5150 ahd_sglist_allocsize(struct ahd_softc *ahd) 5151 { 5152 bus_size_t sg_list_increment; 5153 bus_size_t sg_list_size; 5154 bus_size_t max_list_size; 5155 bus_size_t best_list_size; 5156 5157 /* Start out with the minimum required for AHD_NSEG. */ 5158 sg_list_increment = ahd_sglist_size(ahd); 5159 sg_list_size = sg_list_increment; 5160 5161 /* Get us as close as possible to a page in size. */ 5162 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 5163 sg_list_size += sg_list_increment; 5164 5165 /* 5166 * Try to reduce the amount of wastage by allocating 5167 * multiple pages. 5168 */ 5169 best_list_size = sg_list_size; 5170 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 5171 if (max_list_size < 4 * PAGE_SIZE) 5172 max_list_size = 4 * PAGE_SIZE; 5173 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 5174 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 5175 while ((sg_list_size + sg_list_increment) <= max_list_size 5176 && (sg_list_size % PAGE_SIZE) != 0) { 5177 bus_size_t new_mod; 5178 bus_size_t best_mod; 5179 5180 sg_list_size += sg_list_increment; 5181 new_mod = sg_list_size % PAGE_SIZE; 5182 best_mod = best_list_size % PAGE_SIZE; 5183 if (new_mod > best_mod || new_mod == 0) { 5184 best_list_size = sg_list_size; 5185 } 5186 } 5187 return (best_list_size); 5188 } 5189 5190 /* 5191 * Allocate a controller structure for a new device 5192 * and perform initial initializion. 5193 */ 5194 struct ahd_softc * 5195 ahd_alloc(void *platform_arg, char *name) 5196 { 5197 struct ahd_softc *ahd; 5198 5199 #ifndef __FreeBSD__ 5200 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT); 5201 if (!ahd) { 5202 printf("aic7xxx: cannot malloc softc!\n"); 5203 free(name, M_DEVBUF); 5204 return NULL; 5205 } 5206 #else 5207 ahd = device_get_softc((device_t)platform_arg); 5208 #endif 5209 memset(ahd, 0, sizeof(*ahd)); 5210 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 5211 M_DEVBUF, M_NOWAIT); 5212 if (ahd->seep_config == NULL) { 5213 #ifndef __FreeBSD__ 5214 free(ahd, M_DEVBUF); 5215 #endif 5216 free(name, M_DEVBUF); 5217 return (NULL); 5218 } 5219 LIST_INIT(&ahd->pending_scbs); 5220 /* We don't know our unit number until the OSM sets it */ 5221 ahd->name = name; 5222 ahd->unit = -1; 5223 ahd->description = NULL; 5224 ahd->bus_description = NULL; 5225 ahd->channel = 'A'; 5226 ahd->chip = AHD_NONE; 5227 ahd->features = AHD_FENONE; 5228 ahd->bugs = AHD_BUGNONE; 5229 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 5230 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 5231 ahd_timer_init(&ahd->reset_timer); 5232 ahd_timer_init(&ahd->stat_timer); 5233 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 5234 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 5235 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 5236 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 5237 ahd->int_coalescing_stop_threshold = 5238 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 5239 5240 if (ahd_platform_alloc(ahd, platform_arg) != 0) { 5241 ahd_free(ahd); 5242 ahd = NULL; 5243 } 5244 #ifdef AHD_DEBUG 5245 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) { 5246 printf("%s: scb size = 0x%x, hscb size = 0x%x\n", 5247 ahd_name(ahd), (u_int)sizeof(struct scb), 5248 (u_int)sizeof(struct hardware_scb)); 5249 } 5250 #endif 5251 return (ahd); 5252 } 5253 5254 int 5255 ahd_softc_init(struct ahd_softc *ahd) 5256 { 5257 5258 ahd->unpause = 0; 5259 ahd->pause = PAUSE; 5260 return (0); 5261 } 5262 5263 void 5264 ahd_set_unit(struct ahd_softc *ahd, int unit) 5265 { 5266 ahd->unit = unit; 5267 } 5268 5269 void 5270 ahd_set_name(struct ahd_softc *ahd, char *name) 5271 { 5272 if (ahd->name != NULL) 5273 free(ahd->name, M_DEVBUF); 5274 ahd->name = name; 5275 } 5276 5277 void 5278 ahd_free(struct ahd_softc *ahd) 5279 { 5280 int i; 5281 5282 switch (ahd->init_level) { 5283 default: 5284 case 5: 5285 ahd_shutdown(ahd); 5286 /* FALLTHROUGH */ 5287 case 4: 5288 ahd_dmamap_unload(ahd, ahd->shared_data_dmat, 5289 ahd->shared_data_map.dmamap); 5290 /* FALLTHROUGH */ 5291 case 3: 5292 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo, 5293 ahd->shared_data_map.dmamap); 5294 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat, 5295 ahd->shared_data_map.dmamap); 5296 /* FALLTHROUGH */ 5297 case 2: 5298 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat); 5299 case 1: 5300 #ifndef __linux__ 5301 ahd_dma_tag_destroy(ahd, ahd->buffer_dmat); 5302 #endif 5303 break; 5304 case 0: 5305 break; 5306 } 5307 5308 #ifndef __linux__ 5309 ahd_dma_tag_destroy(ahd, ahd->parent_dmat); 5310 #endif 5311 ahd_platform_free(ahd); 5312 ahd_fini_scbdata(ahd); 5313 for (i = 0; i < AHD_NUM_TARGETS; i++) { 5314 struct ahd_tmode_tstate *tstate; 5315 5316 tstate = ahd->enabled_targets[i]; 5317 if (tstate != NULL) { 5318 #ifdef AHD_TARGET_MODE 5319 int j; 5320 5321 for (j = 0; j < AHD_NUM_LUNS; j++) { 5322 struct ahd_tmode_lstate *lstate; 5323 5324 lstate = tstate->enabled_luns[j]; 5325 if (lstate != NULL) { 5326 xpt_free_path(lstate->path); 5327 free(lstate, M_DEVBUF); 5328 } 5329 } 5330 #endif 5331 free(tstate, M_DEVBUF); 5332 } 5333 } 5334 #ifdef AHD_TARGET_MODE 5335 if (ahd->black_hole != NULL) { 5336 xpt_free_path(ahd->black_hole->path); 5337 free(ahd->black_hole, M_DEVBUF); 5338 } 5339 #endif 5340 if (ahd->name != NULL) 5341 free(ahd->name, M_DEVBUF); 5342 if (ahd->seep_config != NULL) 5343 free(ahd->seep_config, M_DEVBUF); 5344 if (ahd->saved_stack != NULL) 5345 free(ahd->saved_stack, M_DEVBUF); 5346 #ifndef __FreeBSD__ 5347 free(ahd, M_DEVBUF); 5348 #endif 5349 return; 5350 } 5351 5352 void 5353 ahd_shutdown(void *arg) 5354 { 5355 struct ahd_softc *ahd; 5356 5357 ahd = (struct ahd_softc *)arg; 5358 5359 /* 5360 * Stop periodic timer callbacks. 5361 */ 5362 ahd_timer_stop(&ahd->reset_timer); 5363 ahd_timer_stop(&ahd->stat_timer); 5364 5365 /* This will reset most registers to 0, but not all */ 5366 ahd_reset(ahd, /*reinit*/FALSE); 5367 } 5368 5369 /* 5370 * Reset the controller and record some information about it 5371 * that is only available just after a reset. If "reinit" is 5372 * non-zero, this reset occured after initial configuration 5373 * and the caller requests that the chip be fully reinitialized 5374 * to a runable state. Chip interrupts are *not* enabled after 5375 * a reinitialization. The caller must enable interrupts via 5376 * ahd_intr_enable(). 5377 */ 5378 int 5379 ahd_reset(struct ahd_softc *ahd, int reinit) 5380 { 5381 u_int sxfrctl1; 5382 int wait; 5383 uint32_t cmd; 5384 5385 /* 5386 * Preserve the value of the SXFRCTL1 register for all channels. 5387 * It contains settings that affect termination and we don't want 5388 * to disturb the integrity of the bus. 5389 */ 5390 ahd_pause(ahd); 5391 ahd_update_modes(ahd); 5392 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5393 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 5394 5395 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 5396 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5397 uint32_t mod_cmd; 5398 5399 /* 5400 * A4 Razor #632 5401 * During the assertion of CHIPRST, the chip 5402 * does not disable its parity logic prior to 5403 * the start of the reset. This may cause a 5404 * parity error to be detected and thus a 5405 * spurious SERR or PERR assertion. Disble 5406 * PERR and SERR responses during the CHIPRST. 5407 */ 5408 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN); 5409 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5410 mod_cmd, /*bytes*/2); 5411 } 5412 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 5413 5414 /* 5415 * Ensure that the reset has finished. We delay 1000us 5416 * prior to reading the register to make sure the chip 5417 * has sufficiently completed its reset to handle register 5418 * accesses. 5419 */ 5420 wait = 1000; 5421 do { 5422 ahd_delay(1000); 5423 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 5424 5425 if (wait == 0) { 5426 printf("%s: WARNING - Failed chip reset! " 5427 "Trying to initialize anyway.\n", ahd_name(ahd)); 5428 } 5429 ahd_outb(ahd, HCNTRL, ahd->pause); 5430 5431 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5432 /* 5433 * Clear any latched PCI error status and restore 5434 * previous SERR and PERR response enables. 5435 */ 5436 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 5437 0xFF, /*bytes*/1); 5438 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5439 cmd, /*bytes*/2); 5440 } 5441 5442 /* 5443 * Mode should be SCSI after a chip reset, but lets 5444 * set it just to be safe. We touch the MODE_PTR 5445 * register directly so as to bypass the lazy update 5446 * code in ahd_set_modes(). 5447 */ 5448 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5449 ahd_outb(ahd, MODE_PTR, 5450 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 5451 5452 /* 5453 * Restore SXFRCTL1. 5454 * 5455 * We must always initialize STPWEN to 1 before we 5456 * restore the saved values. STPWEN is initialized 5457 * to a tri-state condition which can only be cleared 5458 * by turning it on. 5459 */ 5460 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5461 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5462 5463 /* Determine chip configuration */ 5464 ahd->features &= ~AHD_WIDE; 5465 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5466 ahd->features |= AHD_WIDE; 5467 5468 /* 5469 * If a recovery action has forced a chip reset, 5470 * re-initialize the chip to our liking. 5471 */ 5472 if (reinit != 0) 5473 ahd_chip_init(ahd); 5474 5475 return (0); 5476 } 5477 5478 /* 5479 * Determine the number of SCBs available on the controller 5480 */ 5481 int 5482 ahd_probe_scbs(struct ahd_softc *ahd) { 5483 int i; 5484 5485 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5486 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5487 for (i = 0; i < AHD_SCB_MAX; i++) { 5488 int j; 5489 5490 ahd_set_scbptr(ahd, i); 5491 ahd_outw(ahd, SCB_BASE, i); 5492 for (j = 2; j < 64; j++) 5493 ahd_outb(ahd, SCB_BASE+j, 0); 5494 /* Start out life as unallocated (needing an abort) */ 5495 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5496 if (ahd_inw_scbram(ahd, SCB_BASE) != i) 5497 break; 5498 ahd_set_scbptr(ahd, 0); 5499 if (ahd_inw_scbram(ahd, SCB_BASE) != 0) 5500 break; 5501 } 5502 return (i); 5503 } 5504 5505 static void 5506 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 5507 { 5508 dma_addr_t *baddr; 5509 5510 baddr = (dma_addr_t *)arg; 5511 *baddr = segs->ds_addr; 5512 } 5513 5514 static void 5515 ahd_initialize_hscbs(struct ahd_softc *ahd) 5516 { 5517 int i; 5518 5519 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5520 ahd_set_scbptr(ahd, i); 5521 5522 /* Clear the control byte. */ 5523 ahd_outb(ahd, SCB_CONTROL, 0); 5524 5525 /* Set the next pointer */ 5526 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5527 } 5528 } 5529 5530 static int 5531 ahd_init_scbdata(struct ahd_softc *ahd) 5532 { 5533 struct scb_data *scb_data; 5534 int i; 5535 5536 scb_data = &ahd->scb_data; 5537 TAILQ_INIT(&scb_data->free_scbs); 5538 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5539 LIST_INIT(&scb_data->free_scb_lists[i]); 5540 LIST_INIT(&scb_data->any_dev_free_scb_list); 5541 SLIST_INIT(&scb_data->hscb_maps); 5542 SLIST_INIT(&scb_data->sg_maps); 5543 SLIST_INIT(&scb_data->sense_maps); 5544 5545 /* Determine the number of hardware SCBs and initialize them */ 5546 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5547 if (scb_data->maxhscbs == 0) { 5548 printf("%s: No SCB space found\n", ahd_name(ahd)); 5549 return (ENXIO); 5550 } 5551 5552 ahd_initialize_hscbs(ahd); 5553 5554 /* 5555 * Create our DMA tags. These tags define the kinds of device 5556 * accessible memory allocations and memory mappings we will 5557 * need to perform during normal operation. 5558 * 5559 * Unless we need to further restrict the allocation, we rely 5560 * on the restrictions of the parent dmat, hence the common 5561 * use of MAXADDR and MAXSIZE. 5562 */ 5563 5564 /* DMA tag for our hardware scb structures */ 5565 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5566 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5567 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5568 /*highaddr*/BUS_SPACE_MAXADDR, 5569 /*filter*/NULL, /*filterarg*/NULL, 5570 PAGE_SIZE, /*nsegments*/1, 5571 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5572 /*flags*/0, &scb_data->hscb_dmat) != 0) { 5573 goto error_exit; 5574 } 5575 5576 scb_data->init_level++; 5577 5578 /* DMA tag for our S/G structures. */ 5579 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8, 5580 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5581 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5582 /*highaddr*/BUS_SPACE_MAXADDR, 5583 /*filter*/NULL, /*filterarg*/NULL, 5584 ahd_sglist_allocsize(ahd), /*nsegments*/1, 5585 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5586 /*flags*/0, &scb_data->sg_dmat) != 0) { 5587 goto error_exit; 5588 } 5589 #ifdef AHD_DEBUG 5590 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) 5591 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd), 5592 ahd_sglist_allocsize(ahd)); 5593 #endif 5594 5595 scb_data->init_level++; 5596 5597 /* DMA tag for our sense buffers. We allocate in page sized chunks */ 5598 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5599 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5600 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5601 /*highaddr*/BUS_SPACE_MAXADDR, 5602 /*filter*/NULL, /*filterarg*/NULL, 5603 PAGE_SIZE, /*nsegments*/1, 5604 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5605 /*flags*/0, &scb_data->sense_dmat) != 0) { 5606 goto error_exit; 5607 } 5608 5609 scb_data->init_level++; 5610 5611 /* Perform initial CCB allocation */ 5612 ahd_alloc_scbs(ahd); 5613 5614 if (scb_data->numscbs == 0) { 5615 printf("%s: ahd_init_scbdata - " 5616 "Unable to allocate initial scbs\n", 5617 ahd_name(ahd)); 5618 goto error_exit; 5619 } 5620 5621 /* 5622 * Note that we were successfull 5623 */ 5624 return (0); 5625 5626 error_exit: 5627 5628 return (ENOMEM); 5629 } 5630 5631 static struct scb * 5632 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5633 { 5634 struct scb *scb; 5635 5636 /* 5637 * Look on the pending list. 5638 */ 5639 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5640 if (SCB_GET_TAG(scb) == tag) 5641 return (scb); 5642 } 5643 5644 /* 5645 * Then on all of the collision free lists. 5646 */ 5647 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5648 struct scb *list_scb; 5649 5650 list_scb = scb; 5651 do { 5652 if (SCB_GET_TAG(list_scb) == tag) 5653 return (list_scb); 5654 list_scb = LIST_NEXT(list_scb, collision_links); 5655 } while (list_scb); 5656 } 5657 5658 /* 5659 * And finally on the generic free list. 5660 */ 5661 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5662 if (SCB_GET_TAG(scb) == tag) 5663 return (scb); 5664 } 5665 5666 return (NULL); 5667 } 5668 5669 static void 5670 ahd_fini_scbdata(struct ahd_softc *ahd) 5671 { 5672 struct scb_data *scb_data; 5673 5674 scb_data = &ahd->scb_data; 5675 if (scb_data == NULL) 5676 return; 5677 5678 switch (scb_data->init_level) { 5679 default: 5680 case 7: 5681 { 5682 struct map_node *sns_map; 5683 5684 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5685 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5686 ahd_dmamap_unload(ahd, scb_data->sense_dmat, 5687 sns_map->dmamap); 5688 ahd_dmamem_free(ahd, scb_data->sense_dmat, 5689 sns_map->vaddr, sns_map->dmamap); 5690 free(sns_map, M_DEVBUF); 5691 } 5692 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat); 5693 /* FALLTHROUGH */ 5694 } 5695 case 6: 5696 { 5697 struct map_node *sg_map; 5698 5699 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5700 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5701 ahd_dmamap_unload(ahd, scb_data->sg_dmat, 5702 sg_map->dmamap); 5703 ahd_dmamem_free(ahd, scb_data->sg_dmat, 5704 sg_map->vaddr, sg_map->dmamap); 5705 free(sg_map, M_DEVBUF); 5706 } 5707 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat); 5708 /* FALLTHROUGH */ 5709 } 5710 case 5: 5711 { 5712 struct map_node *hscb_map; 5713 5714 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5715 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5716 ahd_dmamap_unload(ahd, scb_data->hscb_dmat, 5717 hscb_map->dmamap); 5718 ahd_dmamem_free(ahd, scb_data->hscb_dmat, 5719 hscb_map->vaddr, hscb_map->dmamap); 5720 free(hscb_map, M_DEVBUF); 5721 } 5722 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat); 5723 /* FALLTHROUGH */ 5724 } 5725 case 4: 5726 case 3: 5727 case 2: 5728 case 1: 5729 case 0: 5730 break; 5731 } 5732 } 5733 5734 /* 5735 * DSP filter Bypass must be enabled until the first selection 5736 * after a change in bus mode (Razor #491 and #493). 5737 */ 5738 static void 5739 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5740 { 5741 ahd_mode_state saved_modes; 5742 5743 saved_modes = ahd_save_modes(ahd); 5744 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5745 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5746 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5747 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5748 #ifdef AHD_DEBUG 5749 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5750 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5751 #endif 5752 ahd_restore_modes(ahd, saved_modes); 5753 ahd->flags &= ~AHD_HAD_FIRST_SEL; 5754 } 5755 5756 static void 5757 ahd_iocell_first_selection(struct ahd_softc *ahd) 5758 { 5759 ahd_mode_state saved_modes; 5760 u_int sblkctl; 5761 5762 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0) 5763 return; 5764 saved_modes = ahd_save_modes(ahd); 5765 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5766 sblkctl = ahd_inb(ahd, SBLKCTL); 5767 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5768 #ifdef AHD_DEBUG 5769 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5770 printf("%s: iocell first selection\n", ahd_name(ahd)); 5771 #endif 5772 if ((sblkctl & ENAB40) != 0) { 5773 ahd_outb(ahd, DSPDATACTL, 5774 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5775 #ifdef AHD_DEBUG 5776 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5777 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5778 #endif 5779 } 5780 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5781 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5782 ahd_restore_modes(ahd, saved_modes); 5783 ahd->flags |= AHD_HAD_FIRST_SEL; 5784 } 5785 5786 /*************************** SCB Management ***********************************/ 5787 static void 5788 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5789 { 5790 struct scb_list *free_list; 5791 struct scb_tailq *free_tailq; 5792 struct scb *first_scb; 5793 5794 scb->flags |= SCB_ON_COL_LIST; 5795 AHD_SET_SCB_COL_IDX(scb, col_idx); 5796 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5797 free_tailq = &ahd->scb_data.free_scbs; 5798 first_scb = LIST_FIRST(free_list); 5799 if (first_scb != NULL) { 5800 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5801 } else { 5802 LIST_INSERT_HEAD(free_list, scb, collision_links); 5803 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5804 } 5805 } 5806 5807 static void 5808 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5809 { 5810 struct scb_list *free_list; 5811 struct scb_tailq *free_tailq; 5812 struct scb *first_scb; 5813 u_int col_idx; 5814 5815 scb->flags &= ~SCB_ON_COL_LIST; 5816 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5817 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5818 free_tailq = &ahd->scb_data.free_scbs; 5819 first_scb = LIST_FIRST(free_list); 5820 if (first_scb == scb) { 5821 struct scb *next_scb; 5822 5823 /* 5824 * Maintain order in the collision free 5825 * lists for fairness if this device has 5826 * other colliding tags active. 5827 */ 5828 next_scb = LIST_NEXT(scb, collision_links); 5829 if (next_scb != NULL) { 5830 TAILQ_INSERT_AFTER(free_tailq, scb, 5831 next_scb, links.tqe); 5832 } 5833 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5834 } 5835 LIST_REMOVE(scb, collision_links); 5836 } 5837 5838 /* 5839 * Get a free scb. If there are none, see if we can allocate a new SCB. 5840 */ 5841 struct scb * 5842 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5843 { 5844 struct scb *scb; 5845 int tries; 5846 5847 tries = 0; 5848 look_again: 5849 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5850 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5851 ahd_rem_col_list(ahd, scb); 5852 goto found; 5853 } 5854 } 5855 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5856 5857 if (tries++ != 0) 5858 return (NULL); 5859 ahd_alloc_scbs(ahd); 5860 goto look_again; 5861 } 5862 LIST_REMOVE(scb, links.le); 5863 if (col_idx != AHD_NEVER_COL_IDX 5864 && (scb->col_scb != NULL) 5865 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5866 LIST_REMOVE(scb->col_scb, links.le); 5867 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5868 } 5869 found: 5870 scb->flags |= SCB_ACTIVE; 5871 return (scb); 5872 } 5873 5874 /* 5875 * Return an SCB resource to the free list. 5876 */ 5877 void 5878 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5879 { 5880 5881 /* Clean up for the next user */ 5882 scb->flags = SCB_FLAG_NONE; 5883 scb->hscb->control = 0; 5884 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5885 5886 if (scb->col_scb == NULL) { 5887 5888 /* 5889 * No collision possible. Just free normally. 5890 */ 5891 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5892 scb, links.le); 5893 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5894 5895 /* 5896 * The SCB we might have collided with is on 5897 * a free collision list. Put both SCBs on 5898 * the generic list. 5899 */ 5900 ahd_rem_col_list(ahd, scb->col_scb); 5901 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5902 scb, links.le); 5903 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5904 scb->col_scb, links.le); 5905 } else if ((scb->col_scb->flags 5906 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5907 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5908 5909 /* 5910 * The SCB we might collide with on the next allocation 5911 * is still active in a non-packetized, tagged, context. 5912 * Put us on the SCB collision list. 5913 */ 5914 ahd_add_col_list(ahd, scb, 5915 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5916 } else { 5917 /* 5918 * The SCB we might collide with on the next allocation 5919 * is either active in a packetized context, or free. 5920 * Since we can't collide, put this SCB on the generic 5921 * free list. 5922 */ 5923 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5924 scb, links.le); 5925 } 5926 5927 ahd_platform_scb_free(ahd, scb); 5928 } 5929 5930 void 5931 ahd_alloc_scbs(struct ahd_softc *ahd) 5932 { 5933 struct scb_data *scb_data; 5934 struct scb *next_scb; 5935 struct hardware_scb *hscb; 5936 struct map_node *hscb_map; 5937 struct map_node *sg_map; 5938 struct map_node *sense_map; 5939 uint8_t *segs; 5940 uint8_t *sense_data; 5941 dma_addr_t hscb_busaddr; 5942 dma_addr_t sg_busaddr; 5943 dma_addr_t sense_busaddr; 5944 int newcount; 5945 int i; 5946 5947 scb_data = &ahd->scb_data; 5948 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5949 /* Can't allocate any more */ 5950 return; 5951 5952 if (scb_data->scbs_left != 0) { 5953 int offset; 5954 5955 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5956 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5957 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5958 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5959 } else { 5960 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5961 5962 if (hscb_map == NULL) 5963 return; 5964 5965 /* Allocate the next batch of hardware SCBs */ 5966 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat, 5967 (void **)&hscb_map->vaddr, 5968 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) { 5969 free(hscb_map, M_DEVBUF); 5970 return; 5971 } 5972 5973 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5974 5975 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap, 5976 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 5977 &hscb_map->physaddr, /*flags*/0); 5978 5979 hscb = (struct hardware_scb *)hscb_map->vaddr; 5980 hscb_busaddr = hscb_map->physaddr; 5981 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5982 } 5983 5984 if (scb_data->sgs_left != 0) { 5985 int offset; 5986 5987 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 5988 - scb_data->sgs_left) * ahd_sglist_size(ahd); 5989 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5990 segs = sg_map->vaddr + offset; 5991 sg_busaddr = sg_map->physaddr + offset; 5992 } else { 5993 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5994 5995 if (sg_map == NULL) 5996 return; 5997 5998 /* Allocate the next batch of S/G lists */ 5999 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat, 6000 (void **)&sg_map->vaddr, 6001 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) { 6002 free(sg_map, M_DEVBUF); 6003 return; 6004 } 6005 6006 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 6007 6008 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap, 6009 sg_map->vaddr, ahd_sglist_allocsize(ahd), 6010 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0); 6011 6012 segs = sg_map->vaddr; 6013 sg_busaddr = sg_map->physaddr; 6014 scb_data->sgs_left = 6015 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 6016 #ifdef AHD_DEBUG 6017 if (ahd_debug & AHD_SHOW_MEMORY) 6018 printf("Mapped SG data\n"); 6019 #endif 6020 } 6021 6022 if (scb_data->sense_left != 0) { 6023 int offset; 6024 6025 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 6026 sense_map = SLIST_FIRST(&scb_data->sense_maps); 6027 sense_data = sense_map->vaddr + offset; 6028 sense_busaddr = sense_map->physaddr + offset; 6029 } else { 6030 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 6031 6032 if (sense_map == NULL) 6033 return; 6034 6035 /* Allocate the next batch of sense buffers */ 6036 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat, 6037 (void **)&sense_map->vaddr, 6038 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) { 6039 free(sense_map, M_DEVBUF); 6040 return; 6041 } 6042 6043 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 6044 6045 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap, 6046 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 6047 &sense_map->physaddr, /*flags*/0); 6048 6049 sense_data = sense_map->vaddr; 6050 sense_busaddr = sense_map->physaddr; 6051 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 6052 #ifdef AHD_DEBUG 6053 if (ahd_debug & AHD_SHOW_MEMORY) 6054 printf("Mapped sense data\n"); 6055 #endif 6056 } 6057 6058 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 6059 newcount = MIN(newcount, scb_data->sgs_left); 6060 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 6061 for (i = 0; i < newcount; i++) { 6062 struct scb_platform_data *pdata; 6063 u_int col_tag; 6064 #ifndef __linux__ 6065 int error; 6066 #endif 6067 6068 next_scb = (struct scb *)malloc(sizeof(*next_scb), 6069 M_DEVBUF, M_NOWAIT); 6070 if (next_scb == NULL) 6071 break; 6072 6073 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 6074 M_DEVBUF, M_NOWAIT); 6075 if (pdata == NULL) { 6076 free(next_scb, M_DEVBUF); 6077 break; 6078 } 6079 next_scb->platform_data = pdata; 6080 next_scb->hscb_map = hscb_map; 6081 next_scb->sg_map = sg_map; 6082 next_scb->sense_map = sense_map; 6083 next_scb->sg_list = segs; 6084 next_scb->sense_data = sense_data; 6085 next_scb->sense_busaddr = sense_busaddr; 6086 memset(hscb, 0, sizeof(*hscb)); 6087 next_scb->hscb = hscb; 6088 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 6089 6090 /* 6091 * The sequencer always starts with the second entry. 6092 * The first entry is embedded in the scb. 6093 */ 6094 next_scb->sg_list_busaddr = sg_busaddr; 6095 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 6096 next_scb->sg_list_busaddr 6097 += sizeof(struct ahd_dma64_seg); 6098 else 6099 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 6100 next_scb->ahd_softc = ahd; 6101 next_scb->flags = SCB_FLAG_NONE; 6102 #ifndef __linux__ 6103 error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0, 6104 &next_scb->dmamap); 6105 if (error != 0) { 6106 free(next_scb, M_DEVBUF); 6107 free(pdata, M_DEVBUF); 6108 break; 6109 } 6110 #endif 6111 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 6112 col_tag = scb_data->numscbs ^ 0x100; 6113 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 6114 if (next_scb->col_scb != NULL) 6115 next_scb->col_scb->col_scb = next_scb; 6116 ahd_free_scb(ahd, next_scb); 6117 hscb++; 6118 hscb_busaddr += sizeof(*hscb); 6119 segs += ahd_sglist_size(ahd); 6120 sg_busaddr += ahd_sglist_size(ahd); 6121 sense_data += AHD_SENSE_BUFSIZE; 6122 sense_busaddr += AHD_SENSE_BUFSIZE; 6123 scb_data->numscbs++; 6124 scb_data->sense_left--; 6125 scb_data->scbs_left--; 6126 scb_data->sgs_left--; 6127 } 6128 } 6129 6130 void 6131 ahd_controller_info(struct ahd_softc *ahd, char *buf) 6132 { 6133 const char *speed; 6134 const char *type; 6135 int len; 6136 6137 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 6138 buf += len; 6139 6140 speed = "Ultra320 "; 6141 if ((ahd->features & AHD_WIDE) != 0) { 6142 type = "Wide "; 6143 } else { 6144 type = "Single "; 6145 } 6146 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 6147 speed, type, ahd->channel, ahd->our_id); 6148 buf += len; 6149 6150 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 6151 ahd->scb_data.maxhscbs); 6152 } 6153 6154 static const char *channel_strings[] = { 6155 "Primary Low", 6156 "Primary High", 6157 "Secondary Low", 6158 "Secondary High" 6159 }; 6160 6161 static const char *termstat_strings[] = { 6162 "Terminated Correctly", 6163 "Over Terminated", 6164 "Under Terminated", 6165 "Not Configured" 6166 }; 6167 6168 /* 6169 * Start the board, ready for normal operation 6170 */ 6171 int 6172 ahd_init(struct ahd_softc *ahd) 6173 { 6174 uint8_t *next_vaddr; 6175 dma_addr_t next_baddr; 6176 size_t driver_data_size; 6177 int i; 6178 int error; 6179 u_int warn_user; 6180 uint8_t current_sensing; 6181 uint8_t fstat; 6182 6183 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6184 6185 ahd->stack_size = ahd_probe_stack_size(ahd); 6186 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 6187 M_DEVBUF, M_NOWAIT); 6188 if (ahd->saved_stack == NULL) 6189 return (ENOMEM); 6190 6191 /* 6192 * Verify that the compiler hasn't over-agressively 6193 * padded important structures. 6194 */ 6195 if (sizeof(struct hardware_scb) != 64) 6196 panic("Hardware SCB size is incorrect"); 6197 6198 #ifdef AHD_DEBUG 6199 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 6200 ahd->flags |= AHD_SEQUENCER_DEBUG; 6201 #endif 6202 6203 /* 6204 * Default to allowing initiator operations. 6205 */ 6206 ahd->flags |= AHD_INITIATORROLE; 6207 6208 /* 6209 * Only allow target mode features if this unit has them enabled. 6210 */ 6211 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 6212 ahd->features &= ~AHD_TARGETMODE; 6213 6214 #ifndef __linux__ 6215 /* DMA tag for mapping buffers into device visible space. */ 6216 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6217 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6218 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING 6219 ? (dma_addr_t)0x7FFFFFFFFFULL 6220 : BUS_SPACE_MAXADDR_32BIT, 6221 /*highaddr*/BUS_SPACE_MAXADDR, 6222 /*filter*/NULL, /*filterarg*/NULL, 6223 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE, 6224 /*nsegments*/AHD_NSEG, 6225 /*maxsegsz*/AHD_MAXTRANSFER_SIZE, 6226 /*flags*/BUS_DMA_ALLOCNOW, 6227 &ahd->buffer_dmat) != 0) { 6228 return (ENOMEM); 6229 } 6230 #endif 6231 6232 ahd->init_level++; 6233 6234 /* 6235 * DMA tag for our command fifos and other data in system memory 6236 * the card's sequencer must be able to access. For initiator 6237 * roles, we need to allocate space for the qoutfifo. When providing 6238 * for the target mode role, we must additionally provide space for 6239 * the incoming target command fifo. 6240 */ 6241 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo) 6242 + sizeof(struct hardware_scb); 6243 if ((ahd->features & AHD_TARGETMODE) != 0) 6244 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6245 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 6246 driver_data_size += PKT_OVERRUN_BUFSIZE; 6247 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6248 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6249 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 6250 /*highaddr*/BUS_SPACE_MAXADDR, 6251 /*filter*/NULL, /*filterarg*/NULL, 6252 driver_data_size, 6253 /*nsegments*/1, 6254 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 6255 /*flags*/0, &ahd->shared_data_dmat) != 0) { 6256 return (ENOMEM); 6257 } 6258 6259 ahd->init_level++; 6260 6261 /* Allocation of driver data */ 6262 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat, 6263 (void **)&ahd->shared_data_map.vaddr, 6264 BUS_DMA_NOWAIT, 6265 &ahd->shared_data_map.dmamap) != 0) { 6266 return (ENOMEM); 6267 } 6268 6269 ahd->init_level++; 6270 6271 /* And permanently map it in */ 6272 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap, 6273 ahd->shared_data_map.vaddr, driver_data_size, 6274 ahd_dmamap_cb, &ahd->shared_data_map.physaddr, 6275 /*flags*/0); 6276 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr; 6277 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 6278 next_baddr = ahd->shared_data_map.physaddr 6279 + AHD_QOUT_SIZE*sizeof(struct ahd_completion); 6280 if ((ahd->features & AHD_TARGETMODE) != 0) { 6281 ahd->targetcmds = (struct target_cmd *)next_vaddr; 6282 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6283 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6284 } 6285 6286 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 6287 ahd->overrun_buf = next_vaddr; 6288 next_vaddr += PKT_OVERRUN_BUFSIZE; 6289 next_baddr += PKT_OVERRUN_BUFSIZE; 6290 } 6291 6292 /* 6293 * We need one SCB to serve as the "next SCB". Since the 6294 * tag identifier in this SCB will never be used, there is 6295 * no point in using a valid HSCB tag from an SCB pulled from 6296 * the standard free pool. So, we allocate this "sentinel" 6297 * specially from the DMA safe memory chunk used for the QOUTFIFO. 6298 */ 6299 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 6300 ahd->next_queued_hscb_map = &ahd->shared_data_map; 6301 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); 6302 6303 ahd->init_level++; 6304 6305 /* Allocate SCB data now that buffer_dmat is initialized */ 6306 if (ahd_init_scbdata(ahd) != 0) 6307 return (ENOMEM); 6308 6309 if ((ahd->flags & AHD_INITIATORROLE) == 0) 6310 ahd->flags &= ~AHD_RESET_BUS_A; 6311 6312 /* 6313 * Before committing these settings to the chip, give 6314 * the OSM one last chance to modify our configuration. 6315 */ 6316 ahd_platform_init(ahd); 6317 6318 /* Bring up the chip. */ 6319 ahd_chip_init(ahd); 6320 6321 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6322 6323 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 6324 goto init_done; 6325 6326 /* 6327 * Verify termination based on current draw and 6328 * warn user if the bus is over/under terminated. 6329 */ 6330 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 6331 CURSENSE_ENB); 6332 if (error != 0) { 6333 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 6334 goto init_done; 6335 } 6336 for (i = 20, fstat = FLX_FSTAT_BUSY; 6337 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 6338 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 6339 if (error != 0) { 6340 printf("%s: current sensing timeout 2\n", 6341 ahd_name(ahd)); 6342 goto init_done; 6343 } 6344 } 6345 if (i == 0) { 6346 printf("%s: Timedout during current-sensing test\n", 6347 ahd_name(ahd)); 6348 goto init_done; 6349 } 6350 6351 /* Latch Current Sensing status. */ 6352 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 6353 if (error != 0) { 6354 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 6355 goto init_done; 6356 } 6357 6358 /* Diable current sensing. */ 6359 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 6360 6361 #ifdef AHD_DEBUG 6362 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 6363 printf("%s: current_sensing == 0x%x\n", 6364 ahd_name(ahd), current_sensing); 6365 } 6366 #endif 6367 warn_user = 0; 6368 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 6369 u_int term_stat; 6370 6371 term_stat = (current_sensing & FLX_CSTAT_MASK); 6372 switch (term_stat) { 6373 case FLX_CSTAT_OVER: 6374 case FLX_CSTAT_UNDER: 6375 warn_user++; 6376 case FLX_CSTAT_INVALID: 6377 case FLX_CSTAT_OKAY: 6378 if (warn_user == 0 && bootverbose == 0) 6379 break; 6380 printf("%s: %s Channel %s\n", ahd_name(ahd), 6381 channel_strings[i], termstat_strings[term_stat]); 6382 break; 6383 } 6384 } 6385 if (warn_user) { 6386 printf("%s: WARNING. Termination is not configured correctly.\n" 6387 "%s: WARNING. SCSI bus operations may FAIL.\n", 6388 ahd_name(ahd), ahd_name(ahd)); 6389 } 6390 init_done: 6391 ahd_restart(ahd); 6392 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 6393 ahd_stat_timer, ahd); 6394 return (0); 6395 } 6396 6397 /* 6398 * (Re)initialize chip state after a chip reset. 6399 */ 6400 static void 6401 ahd_chip_init(struct ahd_softc *ahd) 6402 { 6403 uint32_t busaddr; 6404 u_int sxfrctl1; 6405 u_int scsiseq_template; 6406 u_int wait; 6407 u_int i; 6408 u_int target; 6409 6410 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6411 /* 6412 * Take the LED out of diagnostic mode 6413 */ 6414 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 6415 6416 /* 6417 * Return HS_MAILBOX to its default value. 6418 */ 6419 ahd->hs_mailbox = 0; 6420 ahd_outb(ahd, HS_MAILBOX, 0); 6421 6422 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 6423 ahd_outb(ahd, IOWNID, ahd->our_id); 6424 ahd_outb(ahd, TOWNID, ahd->our_id); 6425 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 6426 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 6427 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 6428 && (ahd->seltime != STIMESEL_MIN)) { 6429 /* 6430 * The selection timer duration is twice as long 6431 * as it should be. Halve it by adding "1" to 6432 * the user specified setting. 6433 */ 6434 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 6435 } else { 6436 sxfrctl1 |= ahd->seltime; 6437 } 6438 6439 ahd_outb(ahd, SXFRCTL0, DFON); 6440 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 6441 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 6442 6443 /* 6444 * Now that termination is set, wait for up 6445 * to 500ms for our transceivers to settle. If 6446 * the adapter does not have a cable attached, 6447 * the transceivers may never settle, so don't 6448 * complain if we fail here. 6449 */ 6450 for (wait = 10000; 6451 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 6452 wait--) 6453 ahd_delay(100); 6454 6455 /* Clear any false bus resets due to the transceivers settling */ 6456 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 6457 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6458 6459 /* Initialize mode specific S/G state. */ 6460 for (i = 0; i < 2; i++) { 6461 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 6462 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 6463 ahd_outb(ahd, SG_STATE, 0); 6464 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 6465 ahd_outb(ahd, SEQIMODE, 6466 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 6467 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 6468 } 6469 6470 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6471 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 6472 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 6473 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 6474 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 6475 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 6476 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 6477 } else { 6478 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 6479 } 6480 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 6481 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 6482 /* 6483 * Do not issue a target abort when a split completion 6484 * error occurs. Let our PCIX interrupt handler deal 6485 * with it instead. H2A4 Razor #625 6486 */ 6487 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 6488 6489 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 6490 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 6491 6492 /* 6493 * Tweak IOCELL settings. 6494 */ 6495 if ((ahd->flags & AHD_HP_BOARD) != 0) { 6496 for (i = 0; i < NUMDSPS; i++) { 6497 ahd_outb(ahd, DSPSELECT, i); 6498 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 6499 } 6500 #ifdef AHD_DEBUG 6501 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6502 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 6503 WRTBIASCTL_HP_DEFAULT); 6504 #endif 6505 } 6506 ahd_setup_iocell_workaround(ahd); 6507 6508 /* 6509 * Enable LQI Manager interrupts. 6510 */ 6511 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 6512 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 6513 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 6514 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 6515 /* 6516 * We choose to have the sequencer catch LQOPHCHGINPKT errors 6517 * manually for the command phase at the start of a packetized 6518 * selection case. ENLQOBUSFREE should be made redundant by 6519 * the BUSFREE interrupt, but it seems that some LQOBUSFREE 6520 * events fail to assert the BUSFREE interrupt so we must 6521 * also enable LQOBUSFREE interrupts. 6522 */ 6523 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE); 6524 6525 /* 6526 * Setup sequencer interrupt handlers. 6527 */ 6528 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6529 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6530 6531 /* 6532 * Setup SCB Offset registers. 6533 */ 6534 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6535 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6536 pkt_long_lun)); 6537 } else { 6538 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6539 } 6540 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6541 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6542 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6543 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6544 shared_data.idata.cdb)); 6545 ahd_outb(ahd, QNEXTPTR, 6546 offsetof(struct hardware_scb, next_hscb_busaddr)); 6547 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6548 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6549 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6550 ahd_outb(ahd, LUNLEN, 6551 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6552 } else { 6553 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 6554 } 6555 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6556 ahd_outb(ahd, MAXCMD, 0xFF); 6557 ahd_outb(ahd, SCBAUTOPTR, 6558 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6559 6560 /* We haven't been enabled for target mode yet. */ 6561 ahd_outb(ahd, MULTARGID, 0); 6562 ahd_outb(ahd, MULTARGID + 1, 0); 6563 6564 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6565 /* Initialize the negotiation table. */ 6566 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6567 /* 6568 * Clear the spare bytes in the neg table to avoid 6569 * spurious parity errors. 6570 */ 6571 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6572 ahd_outb(ahd, NEGOADDR, target); 6573 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6574 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6575 ahd_outb(ahd, ANNEXDAT, 0); 6576 } 6577 } 6578 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6579 struct ahd_devinfo devinfo; 6580 struct ahd_initiator_tinfo *tinfo; 6581 struct ahd_tmode_tstate *tstate; 6582 6583 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6584 target, &tstate); 6585 ahd_compile_devinfo(&devinfo, ahd->our_id, 6586 target, CAM_LUN_WILDCARD, 6587 'A', ROLE_INITIATOR); 6588 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6589 } 6590 6591 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6592 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6593 6594 #ifdef NEEDS_MORE_TESTING 6595 /* 6596 * Always enable abort on incoming L_Qs if this feature is 6597 * supported. We use this to catch invalid SCB references. 6598 */ 6599 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6600 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6601 else 6602 #endif 6603 ahd_outb(ahd, LQCTL1, 0); 6604 6605 /* All of our queues are empty */ 6606 ahd->qoutfifonext = 0; 6607 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID; 6608 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID); 6609 for (i = 0; i < AHD_QOUT_SIZE; i++) 6610 ahd->qoutfifo[i].valid_tag = 0; 6611 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6612 6613 ahd->qinfifonext = 0; 6614 for (i = 0; i < AHD_QIN_SIZE; i++) 6615 ahd->qinfifo[i] = SCB_LIST_NULL; 6616 6617 if ((ahd->features & AHD_TARGETMODE) != 0) { 6618 /* All target command blocks start out invalid. */ 6619 for (i = 0; i < AHD_TMODE_CMDS; i++) 6620 ahd->targetcmds[i].cmd_valid = 0; 6621 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6622 ahd->tqinfifonext = 1; 6623 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6624 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6625 } 6626 6627 /* Initialize Scratch Ram. */ 6628 ahd_outb(ahd, SEQ_FLAGS, 0); 6629 ahd_outb(ahd, SEQ_FLAGS2, 0); 6630 6631 /* We don't have any waiting selections */ 6632 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6633 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6634 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL); 6635 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF); 6636 for (i = 0; i < AHD_NUM_TARGETS; i++) 6637 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6638 6639 /* 6640 * Nobody is waiting to be DMAed into the QOUTFIFO. 6641 */ 6642 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6643 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6644 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6645 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 6646 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 6647 6648 /* 6649 * The Freeze Count is 0. 6650 */ 6651 ahd->qfreeze_cnt = 0; 6652 ahd_outw(ahd, QFREEZE_COUNT, 0); 6653 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0); 6654 6655 /* 6656 * Tell the sequencer where it can find our arrays in memory. 6657 */ 6658 busaddr = ahd->shared_data_map.physaddr; 6659 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr); 6660 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr); 6661 6662 /* 6663 * Setup the allowed SCSI Sequences based on operational mode. 6664 * If we are a target, we'll enable select in operations once 6665 * we've had a lun enabled. 6666 */ 6667 scsiseq_template = ENAUTOATNP; 6668 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6669 scsiseq_template |= ENRSELI; 6670 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6671 6672 /* There are no busy SCBs yet. */ 6673 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6674 int lun; 6675 6676 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6677 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6678 } 6679 6680 /* 6681 * Initialize the group code to command length table. 6682 * Vendor Unique codes are set to 0 so we only capture 6683 * the first byte of the cdb. These can be overridden 6684 * when target mode is enabled. 6685 */ 6686 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6687 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6688 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6689 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6690 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6691 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6692 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6693 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6694 6695 /* Tell the sequencer of our initial queue positions */ 6696 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6697 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6698 ahd->qinfifonext = 0; 6699 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6700 ahd_set_hescb_qoff(ahd, 0); 6701 ahd_set_snscb_qoff(ahd, 0); 6702 ahd_set_sescb_qoff(ahd, 0); 6703 ahd_set_sdscb_qoff(ahd, 0); 6704 6705 /* 6706 * Tell the sequencer which SCB will be the next one it receives. 6707 */ 6708 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6709 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 6710 6711 /* 6712 * Default to coalescing disabled. 6713 */ 6714 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6715 ahd_outw(ahd, CMDS_PENDING, 0); 6716 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6717 ahd->int_coalescing_maxcmds, 6718 ahd->int_coalescing_mincmds); 6719 ahd_enable_coalescing(ahd, FALSE); 6720 6721 ahd_loadseq(ahd); 6722 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6723 6724 if (ahd->features & AHD_AIC79XXB_SLOWCRC) { 6725 u_int negodat3 = ahd_inb(ahd, NEGCONOPTS); 6726 6727 negodat3 |= ENSLOWCRC; 6728 ahd_outb(ahd, NEGCONOPTS, negodat3); 6729 negodat3 = ahd_inb(ahd, NEGCONOPTS); 6730 if (!(negodat3 & ENSLOWCRC)) 6731 printf("aic79xx: failed to set the SLOWCRC bit\n"); 6732 else 6733 printf("aic79xx: SLOWCRC bit set\n"); 6734 } 6735 } 6736 6737 /* 6738 * Setup default device and controller settings. 6739 * This should only be called if our probe has 6740 * determined that no configuration data is available. 6741 */ 6742 int 6743 ahd_default_config(struct ahd_softc *ahd) 6744 { 6745 int targ; 6746 6747 ahd->our_id = 7; 6748 6749 /* 6750 * Allocate a tstate to house information for our 6751 * initiator presence on the bus as well as the user 6752 * data for any target mode initiator. 6753 */ 6754 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6755 printf("%s: unable to allocate ahd_tmode_tstate. " 6756 "Failing attach\n", ahd_name(ahd)); 6757 return (ENOMEM); 6758 } 6759 6760 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6761 struct ahd_devinfo devinfo; 6762 struct ahd_initiator_tinfo *tinfo; 6763 struct ahd_tmode_tstate *tstate; 6764 uint16_t target_mask; 6765 6766 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6767 targ, &tstate); 6768 /* 6769 * We support SPC2 and SPI4. 6770 */ 6771 tinfo->user.protocol_version = 4; 6772 tinfo->user.transport_version = 4; 6773 6774 target_mask = 0x01 << targ; 6775 ahd->user_discenable |= target_mask; 6776 tstate->discenable |= target_mask; 6777 ahd->user_tagenable |= target_mask; 6778 #ifdef AHD_FORCE_160 6779 tinfo->user.period = AHD_SYNCRATE_DT; 6780 #else 6781 tinfo->user.period = AHD_SYNCRATE_160; 6782 #endif 6783 tinfo->user.offset = MAX_OFFSET; 6784 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM 6785 | MSG_EXT_PPR_WR_FLOW 6786 | MSG_EXT_PPR_HOLD_MCS 6787 | MSG_EXT_PPR_IU_REQ 6788 | MSG_EXT_PPR_QAS_REQ 6789 | MSG_EXT_PPR_DT_REQ; 6790 if ((ahd->features & AHD_RTI) != 0) 6791 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6792 6793 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6794 6795 /* 6796 * Start out Async/Narrow/Untagged and with 6797 * conservative protocol support. 6798 */ 6799 tinfo->goal.protocol_version = 2; 6800 tinfo->goal.transport_version = 2; 6801 tinfo->curr.protocol_version = 2; 6802 tinfo->curr.transport_version = 2; 6803 ahd_compile_devinfo(&devinfo, ahd->our_id, 6804 targ, CAM_LUN_WILDCARD, 6805 'A', ROLE_INITIATOR); 6806 tstate->tagenable &= ~target_mask; 6807 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6808 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6809 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6810 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6811 /*paused*/TRUE); 6812 } 6813 return (0); 6814 } 6815 6816 /* 6817 * Parse device configuration information. 6818 */ 6819 int 6820 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6821 { 6822 int targ; 6823 int max_targ; 6824 6825 max_targ = sc->max_targets & CFMAXTARG; 6826 ahd->our_id = sc->brtime_id & CFSCSIID; 6827 6828 /* 6829 * Allocate a tstate to house information for our 6830 * initiator presence on the bus as well as the user 6831 * data for any target mode initiator. 6832 */ 6833 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6834 printf("%s: unable to allocate ahd_tmode_tstate. " 6835 "Failing attach\n", ahd_name(ahd)); 6836 return (ENOMEM); 6837 } 6838 6839 for (targ = 0; targ < max_targ; targ++) { 6840 struct ahd_devinfo devinfo; 6841 struct ahd_initiator_tinfo *tinfo; 6842 struct ahd_transinfo *user_tinfo; 6843 struct ahd_tmode_tstate *tstate; 6844 uint16_t target_mask; 6845 6846 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6847 targ, &tstate); 6848 user_tinfo = &tinfo->user; 6849 6850 /* 6851 * We support SPC2 and SPI4. 6852 */ 6853 tinfo->user.protocol_version = 4; 6854 tinfo->user.transport_version = 4; 6855 6856 target_mask = 0x01 << targ; 6857 ahd->user_discenable &= ~target_mask; 6858 tstate->discenable &= ~target_mask; 6859 ahd->user_tagenable &= ~target_mask; 6860 if (sc->device_flags[targ] & CFDISC) { 6861 tstate->discenable |= target_mask; 6862 ahd->user_discenable |= target_mask; 6863 ahd->user_tagenable |= target_mask; 6864 } else { 6865 /* 6866 * Cannot be packetized without disconnection. 6867 */ 6868 sc->device_flags[targ] &= ~CFPACKETIZED; 6869 } 6870 6871 user_tinfo->ppr_options = 0; 6872 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6873 if (user_tinfo->period < CFXFER_ASYNC) { 6874 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6875 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6876 user_tinfo->offset = MAX_OFFSET; 6877 } else { 6878 user_tinfo->offset = 0; 6879 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6880 } 6881 #ifdef AHD_FORCE_160 6882 if (user_tinfo->period <= AHD_SYNCRATE_160) 6883 user_tinfo->period = AHD_SYNCRATE_DT; 6884 #endif 6885 6886 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6887 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM 6888 | MSG_EXT_PPR_WR_FLOW 6889 | MSG_EXT_PPR_HOLD_MCS 6890 | MSG_EXT_PPR_IU_REQ; 6891 if ((ahd->features & AHD_RTI) != 0) 6892 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6893 } 6894 6895 if ((sc->device_flags[targ] & CFQAS) != 0) 6896 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6897 6898 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6899 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6900 else 6901 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6902 #ifdef AHD_DEBUG 6903 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6904 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6905 user_tinfo->period, user_tinfo->offset, 6906 user_tinfo->ppr_options); 6907 #endif 6908 /* 6909 * Start out Async/Narrow/Untagged and with 6910 * conservative protocol support. 6911 */ 6912 tstate->tagenable &= ~target_mask; 6913 tinfo->goal.protocol_version = 2; 6914 tinfo->goal.transport_version = 2; 6915 tinfo->curr.protocol_version = 2; 6916 tinfo->curr.transport_version = 2; 6917 ahd_compile_devinfo(&devinfo, ahd->our_id, 6918 targ, CAM_LUN_WILDCARD, 6919 'A', ROLE_INITIATOR); 6920 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6921 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6922 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6923 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6924 /*paused*/TRUE); 6925 } 6926 6927 ahd->flags &= ~AHD_SPCHK_ENB_A; 6928 if (sc->bios_control & CFSPARITY) 6929 ahd->flags |= AHD_SPCHK_ENB_A; 6930 6931 ahd->flags &= ~AHD_RESET_BUS_A; 6932 if (sc->bios_control & CFRESETB) 6933 ahd->flags |= AHD_RESET_BUS_A; 6934 6935 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6936 if (sc->bios_control & CFEXTEND) 6937 ahd->flags |= AHD_EXTENDED_TRANS_A; 6938 6939 ahd->flags &= ~AHD_BIOS_ENABLED; 6940 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6941 ahd->flags |= AHD_BIOS_ENABLED; 6942 6943 ahd->flags &= ~AHD_STPWLEVEL_A; 6944 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6945 ahd->flags |= AHD_STPWLEVEL_A; 6946 6947 return (0); 6948 } 6949 6950 /* 6951 * Parse device configuration information. 6952 */ 6953 int 6954 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 6955 { 6956 int error; 6957 6958 error = ahd_verify_vpd_cksum(vpd); 6959 if (error == 0) 6960 return (EINVAL); 6961 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 6962 ahd->flags |= AHD_BOOT_CHANNEL; 6963 return (0); 6964 } 6965 6966 void 6967 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6968 { 6969 u_int hcntrl; 6970 6971 hcntrl = ahd_inb(ahd, HCNTRL); 6972 hcntrl &= ~INTEN; 6973 ahd->pause &= ~INTEN; 6974 ahd->unpause &= ~INTEN; 6975 if (enable) { 6976 hcntrl |= INTEN; 6977 ahd->pause |= INTEN; 6978 ahd->unpause |= INTEN; 6979 } 6980 ahd_outb(ahd, HCNTRL, hcntrl); 6981 } 6982 6983 void 6984 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6985 u_int mincmds) 6986 { 6987 if (timer > AHD_TIMER_MAX_US) 6988 timer = AHD_TIMER_MAX_US; 6989 ahd->int_coalescing_timer = timer; 6990 6991 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 6992 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 6993 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 6994 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 6995 ahd->int_coalescing_maxcmds = maxcmds; 6996 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6997 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 6998 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 6999 } 7000 7001 void 7002 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 7003 { 7004 7005 ahd->hs_mailbox &= ~ENINT_COALESCE; 7006 if (enable) 7007 ahd->hs_mailbox |= ENINT_COALESCE; 7008 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 7009 ahd_flush_device_writes(ahd); 7010 ahd_run_qoutfifo(ahd); 7011 } 7012 7013 /* 7014 * Ensure that the card is paused in a location 7015 * outside of all critical sections and that all 7016 * pending work is completed prior to returning. 7017 * This routine should only be called from outside 7018 * an interrupt context. 7019 */ 7020 void 7021 ahd_pause_and_flushwork(struct ahd_softc *ahd) 7022 { 7023 u_int intstat; 7024 u_int maxloops; 7025 7026 maxloops = 1000; 7027 ahd->flags |= AHD_ALL_INTERRUPTS; 7028 ahd_pause(ahd); 7029 /* 7030 * Freeze the outgoing selections. We do this only 7031 * until we are safely paused without further selections 7032 * pending. 7033 */ 7034 ahd->qfreeze_cnt--; 7035 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7036 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 7037 do { 7038 7039 ahd_unpause(ahd); 7040 /* 7041 * Give the sequencer some time to service 7042 * any active selections. 7043 */ 7044 ahd_delay(500); 7045 7046 ahd_intr(ahd); 7047 ahd_pause(ahd); 7048 intstat = ahd_inb(ahd, INTSTAT); 7049 if ((intstat & INT_PEND) == 0) { 7050 ahd_clear_critical_section(ahd); 7051 intstat = ahd_inb(ahd, INTSTAT); 7052 } 7053 } while (--maxloops 7054 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 7055 && ((intstat & INT_PEND) != 0 7056 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 7057 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 7058 7059 if (maxloops == 0) { 7060 printf("Infinite interrupt loop, INTSTAT = %x", 7061 ahd_inb(ahd, INTSTAT)); 7062 } 7063 ahd->qfreeze_cnt++; 7064 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7065 7066 ahd_flush_qoutfifo(ahd); 7067 7068 ahd->flags &= ~AHD_ALL_INTERRUPTS; 7069 } 7070 7071 int 7072 ahd_suspend(struct ahd_softc *ahd) 7073 { 7074 7075 ahd_pause_and_flushwork(ahd); 7076 7077 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 7078 ahd_unpause(ahd); 7079 return (EBUSY); 7080 } 7081 ahd_shutdown(ahd); 7082 return (0); 7083 } 7084 7085 int 7086 ahd_resume(struct ahd_softc *ahd) 7087 { 7088 7089 ahd_reset(ahd, /*reinit*/TRUE); 7090 ahd_intr_enable(ahd, TRUE); 7091 ahd_restart(ahd); 7092 return (0); 7093 } 7094 7095 /************************** Busy Target Table *********************************/ 7096 /* 7097 * Set SCBPTR to the SCB that contains the busy 7098 * table entry for TCL. Return the offset into 7099 * the SCB that contains the entry for TCL. 7100 * saved_scbid is dereferenced and set to the 7101 * scbid that should be restored once manipualtion 7102 * of the TCL entry is complete. 7103 */ 7104 static __inline u_int 7105 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 7106 { 7107 /* 7108 * Index to the SCB that contains the busy entry. 7109 */ 7110 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7111 *saved_scbid = ahd_get_scbptr(ahd); 7112 ahd_set_scbptr(ahd, TCL_LUN(tcl) 7113 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 7114 7115 /* 7116 * And now calculate the SCB offset to the entry. 7117 * Each entry is 2 bytes wide, hence the 7118 * multiplication by 2. 7119 */ 7120 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 7121 } 7122 7123 /* 7124 * Return the untagged transaction id for a given target/channel lun. 7125 */ 7126 u_int 7127 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 7128 { 7129 u_int scbid; 7130 u_int scb_offset; 7131 u_int saved_scbptr; 7132 7133 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7134 scbid = ahd_inw_scbram(ahd, scb_offset); 7135 ahd_set_scbptr(ahd, saved_scbptr); 7136 return (scbid); 7137 } 7138 7139 void 7140 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 7141 { 7142 u_int scb_offset; 7143 u_int saved_scbptr; 7144 7145 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7146 ahd_outw(ahd, scb_offset, scbid); 7147 ahd_set_scbptr(ahd, saved_scbptr); 7148 } 7149 7150 /************************** SCB and SCB queue management **********************/ 7151 int 7152 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 7153 char channel, int lun, u_int tag, role_t role) 7154 { 7155 int targ = SCB_GET_TARGET(ahd, scb); 7156 char chan = SCB_GET_CHANNEL(ahd, scb); 7157 int slun = SCB_GET_LUN(scb); 7158 int match; 7159 7160 match = ((chan == channel) || (channel == ALL_CHANNELS)); 7161 if (match != 0) 7162 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 7163 if (match != 0) 7164 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 7165 if (match != 0) { 7166 #ifdef AHD_TARGET_MODE 7167 int group; 7168 7169 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 7170 if (role == ROLE_INITIATOR) { 7171 match = (group != XPT_FC_GROUP_TMODE) 7172 && ((tag == SCB_GET_TAG(scb)) 7173 || (tag == SCB_LIST_NULL)); 7174 } else if (role == ROLE_TARGET) { 7175 match = (group == XPT_FC_GROUP_TMODE) 7176 && ((tag == scb->io_ctx->csio.tag_id) 7177 || (tag == SCB_LIST_NULL)); 7178 } 7179 #else /* !AHD_TARGET_MODE */ 7180 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 7181 #endif /* AHD_TARGET_MODE */ 7182 } 7183 7184 return match; 7185 } 7186 7187 void 7188 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 7189 { 7190 int target; 7191 char channel; 7192 int lun; 7193 7194 target = SCB_GET_TARGET(ahd, scb); 7195 lun = SCB_GET_LUN(scb); 7196 channel = SCB_GET_CHANNEL(ahd, scb); 7197 7198 ahd_search_qinfifo(ahd, target, channel, lun, 7199 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 7200 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7201 7202 ahd_platform_freeze_devq(ahd, scb); 7203 } 7204 7205 void 7206 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 7207 { 7208 struct scb *prev_scb; 7209 ahd_mode_state saved_modes; 7210 7211 saved_modes = ahd_save_modes(ahd); 7212 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7213 prev_scb = NULL; 7214 if (ahd_qinfifo_count(ahd) != 0) { 7215 u_int prev_tag; 7216 u_int prev_pos; 7217 7218 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 7219 prev_tag = ahd->qinfifo[prev_pos]; 7220 prev_scb = ahd_lookup_scb(ahd, prev_tag); 7221 } 7222 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7223 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7224 ahd_restore_modes(ahd, saved_modes); 7225 } 7226 7227 static void 7228 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 7229 struct scb *scb) 7230 { 7231 if (prev_scb == NULL) { 7232 uint32_t busaddr; 7233 7234 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 7235 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 7236 } else { 7237 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 7238 ahd_sync_scb(ahd, prev_scb, 7239 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7240 } 7241 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 7242 ahd->qinfifonext++; 7243 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 7244 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7245 } 7246 7247 static int 7248 ahd_qinfifo_count(struct ahd_softc *ahd) 7249 { 7250 u_int qinpos; 7251 u_int wrap_qinpos; 7252 u_int wrap_qinfifonext; 7253 7254 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7255 qinpos = ahd_get_snscb_qoff(ahd); 7256 wrap_qinpos = AHD_QIN_WRAP(qinpos); 7257 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 7258 if (wrap_qinfifonext >= wrap_qinpos) 7259 return (wrap_qinfifonext - wrap_qinpos); 7260 else 7261 return (wrap_qinfifonext 7262 + ARRAY_SIZE(ahd->qinfifo) - wrap_qinpos); 7263 } 7264 7265 void 7266 ahd_reset_cmds_pending(struct ahd_softc *ahd) 7267 { 7268 struct scb *scb; 7269 ahd_mode_state saved_modes; 7270 u_int pending_cmds; 7271 7272 saved_modes = ahd_save_modes(ahd); 7273 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7274 7275 /* 7276 * Don't count any commands as outstanding that the 7277 * sequencer has already marked for completion. 7278 */ 7279 ahd_flush_qoutfifo(ahd); 7280 7281 pending_cmds = 0; 7282 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 7283 pending_cmds++; 7284 } 7285 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 7286 ahd_restore_modes(ahd, saved_modes); 7287 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 7288 } 7289 7290 void 7291 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status) 7292 { 7293 cam_status ostat; 7294 cam_status cstat; 7295 7296 ostat = ahd_get_transaction_status(scb); 7297 if (ostat == CAM_REQ_INPROG) 7298 ahd_set_transaction_status(scb, status); 7299 cstat = ahd_get_transaction_status(scb); 7300 if (cstat != CAM_REQ_CMP) 7301 ahd_freeze_scb(scb); 7302 ahd_done(ahd, scb); 7303 } 7304 7305 int 7306 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 7307 int lun, u_int tag, role_t role, uint32_t status, 7308 ahd_search_action action) 7309 { 7310 struct scb *scb; 7311 struct scb *mk_msg_scb; 7312 struct scb *prev_scb; 7313 ahd_mode_state saved_modes; 7314 u_int qinstart; 7315 u_int qinpos; 7316 u_int qintail; 7317 u_int tid_next; 7318 u_int tid_prev; 7319 u_int scbid; 7320 u_int seq_flags2; 7321 u_int savedscbptr; 7322 uint32_t busaddr; 7323 int found; 7324 int targets; 7325 7326 /* Must be in CCHAN mode */ 7327 saved_modes = ahd_save_modes(ahd); 7328 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7329 7330 /* 7331 * Halt any pending SCB DMA. The sequencer will reinitiate 7332 * this dma if the qinfifo is not empty once we unpause. 7333 */ 7334 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 7335 == (CCARREN|CCSCBEN|CCSCBDIR)) { 7336 ahd_outb(ahd, CCSCBCTL, 7337 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 7338 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 7339 ; 7340 } 7341 /* Determine sequencer's position in the qinfifo. */ 7342 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 7343 qinstart = ahd_get_snscb_qoff(ahd); 7344 qinpos = AHD_QIN_WRAP(qinstart); 7345 found = 0; 7346 prev_scb = NULL; 7347 7348 if (action == SEARCH_PRINT) { 7349 printf("qinstart = %d qinfifonext = %d\nQINFIFO:", 7350 qinstart, ahd->qinfifonext); 7351 } 7352 7353 /* 7354 * Start with an empty queue. Entries that are not chosen 7355 * for removal will be re-added to the queue as we go. 7356 */ 7357 ahd->qinfifonext = qinstart; 7358 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7359 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 7360 7361 while (qinpos != qintail) { 7362 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 7363 if (scb == NULL) { 7364 printf("qinpos = %d, SCB index = %d\n", 7365 qinpos, ahd->qinfifo[qinpos]); 7366 panic("Loop 1\n"); 7367 } 7368 7369 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 7370 /* 7371 * We found an scb that needs to be acted on. 7372 */ 7373 found++; 7374 switch (action) { 7375 case SEARCH_COMPLETE: 7376 if ((scb->flags & SCB_ACTIVE) == 0) 7377 printf("Inactive SCB in qinfifo\n"); 7378 ahd_done_with_status(ahd, scb, status); 7379 /* FALLTHROUGH */ 7380 case SEARCH_REMOVE: 7381 break; 7382 case SEARCH_PRINT: 7383 printf(" 0x%x", ahd->qinfifo[qinpos]); 7384 /* FALLTHROUGH */ 7385 case SEARCH_COUNT: 7386 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7387 prev_scb = scb; 7388 break; 7389 } 7390 } else { 7391 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7392 prev_scb = scb; 7393 } 7394 qinpos = AHD_QIN_WRAP(qinpos+1); 7395 } 7396 7397 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7398 7399 if (action == SEARCH_PRINT) 7400 printf("\nWAITING_TID_QUEUES:\n"); 7401 7402 /* 7403 * Search waiting for selection lists. We traverse the 7404 * list of "their ids" waiting for selection and, if 7405 * appropriate, traverse the SCBs of each "their id" 7406 * looking for matches. 7407 */ 7408 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7409 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2); 7410 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) { 7411 scbid = ahd_inw(ahd, MK_MESSAGE_SCB); 7412 mk_msg_scb = ahd_lookup_scb(ahd, scbid); 7413 } else 7414 mk_msg_scb = NULL; 7415 savedscbptr = ahd_get_scbptr(ahd); 7416 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 7417 tid_prev = SCB_LIST_NULL; 7418 targets = 0; 7419 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 7420 u_int tid_head; 7421 u_int tid_tail; 7422 7423 targets++; 7424 if (targets > AHD_NUM_TARGETS) 7425 panic("TID LIST LOOP"); 7426 7427 if (scbid >= ahd->scb_data.numscbs) { 7428 printf("%s: Waiting TID List inconsistency. " 7429 "SCB index == 0x%x, yet numscbs == 0x%x.", 7430 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7431 ahd_dump_card_state(ahd); 7432 panic("for safety"); 7433 } 7434 scb = ahd_lookup_scb(ahd, scbid); 7435 if (scb == NULL) { 7436 printf("%s: SCB = 0x%x Not Active!\n", 7437 ahd_name(ahd), scbid); 7438 panic("Waiting TID List traversal\n"); 7439 } 7440 ahd_set_scbptr(ahd, scbid); 7441 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7442 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7443 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7444 tid_prev = scbid; 7445 continue; 7446 } 7447 7448 /* 7449 * We found a list of scbs that needs to be searched. 7450 */ 7451 if (action == SEARCH_PRINT) 7452 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7453 tid_head = scbid; 7454 found += ahd_search_scb_list(ahd, target, channel, 7455 lun, tag, role, status, 7456 action, &tid_head, &tid_tail, 7457 SCB_GET_TARGET(ahd, scb)); 7458 /* 7459 * Check any MK_MESSAGE SCB that is still waiting to 7460 * enter this target's waiting for selection queue. 7461 */ 7462 if (mk_msg_scb != NULL 7463 && ahd_match_scb(ahd, mk_msg_scb, target, channel, 7464 lun, tag, role)) { 7465 7466 /* 7467 * We found an scb that needs to be acted on. 7468 */ 7469 found++; 7470 switch (action) { 7471 case SEARCH_COMPLETE: 7472 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0) 7473 printf("Inactive SCB pending MK_MSG\n"); 7474 ahd_done_with_status(ahd, mk_msg_scb, status); 7475 /* FALLTHROUGH */ 7476 case SEARCH_REMOVE: 7477 { 7478 u_int tail_offset; 7479 7480 printf("Removing MK_MSG scb\n"); 7481 7482 /* 7483 * Reset our tail to the tail of the 7484 * main per-target list. 7485 */ 7486 tail_offset = WAITING_SCB_TAILS 7487 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb)); 7488 ahd_outw(ahd, tail_offset, tid_tail); 7489 7490 seq_flags2 &= ~PENDING_MK_MESSAGE; 7491 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2); 7492 ahd_outw(ahd, CMDS_PENDING, 7493 ahd_inw(ahd, CMDS_PENDING)-1); 7494 mk_msg_scb = NULL; 7495 break; 7496 } 7497 case SEARCH_PRINT: 7498 printf(" 0x%x", SCB_GET_TAG(scb)); 7499 /* FALLTHROUGH */ 7500 case SEARCH_COUNT: 7501 break; 7502 } 7503 } 7504 7505 if (mk_msg_scb != NULL 7506 && SCBID_IS_NULL(tid_head) 7507 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7508 SCB_LIST_NULL, ROLE_UNKNOWN)) { 7509 7510 /* 7511 * When removing the last SCB for a target 7512 * queue with a pending MK_MESSAGE scb, we 7513 * must queue the MK_MESSAGE scb. 7514 */ 7515 printf("Queueing mk_msg_scb\n"); 7516 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB); 7517 seq_flags2 &= ~PENDING_MK_MESSAGE; 7518 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2); 7519 mk_msg_scb = NULL; 7520 } 7521 if (tid_head != scbid) 7522 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7523 if (!SCBID_IS_NULL(tid_head)) 7524 tid_prev = tid_head; 7525 if (action == SEARCH_PRINT) 7526 printf(")\n"); 7527 } 7528 7529 /* Restore saved state. */ 7530 ahd_set_scbptr(ahd, savedscbptr); 7531 ahd_restore_modes(ahd, saved_modes); 7532 return (found); 7533 } 7534 7535 static int 7536 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7537 int lun, u_int tag, role_t role, uint32_t status, 7538 ahd_search_action action, u_int *list_head, 7539 u_int *list_tail, u_int tid) 7540 { 7541 struct scb *scb; 7542 u_int scbid; 7543 u_int next; 7544 u_int prev; 7545 int found; 7546 7547 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7548 found = 0; 7549 prev = SCB_LIST_NULL; 7550 next = *list_head; 7551 *list_tail = SCB_LIST_NULL; 7552 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7553 if (scbid >= ahd->scb_data.numscbs) { 7554 printf("%s:SCB List inconsistency. " 7555 "SCB == 0x%x, yet numscbs == 0x%x.", 7556 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7557 ahd_dump_card_state(ahd); 7558 panic("for safety"); 7559 } 7560 scb = ahd_lookup_scb(ahd, scbid); 7561 if (scb == NULL) { 7562 printf("%s: SCB = %d Not Active!\n", 7563 ahd_name(ahd), scbid); 7564 panic("Waiting List traversal\n"); 7565 } 7566 ahd_set_scbptr(ahd, scbid); 7567 *list_tail = scbid; 7568 next = ahd_inw_scbram(ahd, SCB_NEXT); 7569 if (ahd_match_scb(ahd, scb, target, channel, 7570 lun, SCB_LIST_NULL, role) == 0) { 7571 prev = scbid; 7572 continue; 7573 } 7574 found++; 7575 switch (action) { 7576 case SEARCH_COMPLETE: 7577 if ((scb->flags & SCB_ACTIVE) == 0) 7578 printf("Inactive SCB in Waiting List\n"); 7579 ahd_done_with_status(ahd, scb, status); 7580 /* FALLTHROUGH */ 7581 case SEARCH_REMOVE: 7582 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7583 *list_tail = prev; 7584 if (SCBID_IS_NULL(prev)) 7585 *list_head = next; 7586 break; 7587 case SEARCH_PRINT: 7588 printf("0x%x ", scbid); 7589 case SEARCH_COUNT: 7590 prev = scbid; 7591 break; 7592 } 7593 if (found > AHD_SCB_MAX) 7594 panic("SCB LIST LOOP"); 7595 } 7596 if (action == SEARCH_COMPLETE 7597 || action == SEARCH_REMOVE) 7598 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7599 return (found); 7600 } 7601 7602 static void 7603 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7604 u_int tid_cur, u_int tid_next) 7605 { 7606 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7607 7608 if (SCBID_IS_NULL(tid_cur)) { 7609 7610 /* Bypass current TID list */ 7611 if (SCBID_IS_NULL(tid_prev)) { 7612 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7613 } else { 7614 ahd_set_scbptr(ahd, tid_prev); 7615 ahd_outw(ahd, SCB_NEXT2, tid_next); 7616 } 7617 if (SCBID_IS_NULL(tid_next)) 7618 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7619 } else { 7620 7621 /* Stitch through tid_cur */ 7622 if (SCBID_IS_NULL(tid_prev)) { 7623 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7624 } else { 7625 ahd_set_scbptr(ahd, tid_prev); 7626 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7627 } 7628 ahd_set_scbptr(ahd, tid_cur); 7629 ahd_outw(ahd, SCB_NEXT2, tid_next); 7630 7631 if (SCBID_IS_NULL(tid_next)) 7632 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7633 } 7634 } 7635 7636 /* 7637 * Manipulate the waiting for selection list and return the 7638 * scb that follows the one that we remove. 7639 */ 7640 static u_int 7641 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7642 u_int prev, u_int next, u_int tid) 7643 { 7644 u_int tail_offset; 7645 7646 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7647 if (!SCBID_IS_NULL(prev)) { 7648 ahd_set_scbptr(ahd, prev); 7649 ahd_outw(ahd, SCB_NEXT, next); 7650 } 7651 7652 /* 7653 * SCBs that have MK_MESSAGE set in them may 7654 * cause the tail pointer to be updated without 7655 * setting the next pointer of the previous tail. 7656 * Only clear the tail if the removed SCB was 7657 * the tail. 7658 */ 7659 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7660 if (SCBID_IS_NULL(next) 7661 && ahd_inw(ahd, tail_offset) == scbid) 7662 ahd_outw(ahd, tail_offset, prev); 7663 7664 ahd_add_scb_to_free_list(ahd, scbid); 7665 return (next); 7666 } 7667 7668 /* 7669 * Add the SCB as selected by SCBPTR onto the on chip list of 7670 * free hardware SCBs. This list is empty/unused if we are not 7671 * performing SCB paging. 7672 */ 7673 static void 7674 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7675 { 7676 /* XXX Need some other mechanism to designate "free". */ 7677 /* 7678 * Invalidate the tag so that our abort 7679 * routines don't think it's active. 7680 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7681 */ 7682 } 7683 7684 /******************************** Error Handling ******************************/ 7685 /* 7686 * Abort all SCBs that match the given description (target/channel/lun/tag), 7687 * setting their status to the passed in status if the status has not already 7688 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7689 * is paused before it is called. 7690 */ 7691 int 7692 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7693 int lun, u_int tag, role_t role, uint32_t status) 7694 { 7695 struct scb *scbp; 7696 struct scb *scbp_next; 7697 u_int i, j; 7698 u_int maxtarget; 7699 u_int minlun; 7700 u_int maxlun; 7701 int found; 7702 ahd_mode_state saved_modes; 7703 7704 /* restore this when we're done */ 7705 saved_modes = ahd_save_modes(ahd); 7706 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7707 7708 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7709 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7710 7711 /* 7712 * Clean out the busy target table for any untagged commands. 7713 */ 7714 i = 0; 7715 maxtarget = 16; 7716 if (target != CAM_TARGET_WILDCARD) { 7717 i = target; 7718 if (channel == 'B') 7719 i += 8; 7720 maxtarget = i + 1; 7721 } 7722 7723 if (lun == CAM_LUN_WILDCARD) { 7724 minlun = 0; 7725 maxlun = AHD_NUM_LUNS_NONPKT; 7726 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7727 minlun = maxlun = 0; 7728 } else { 7729 minlun = lun; 7730 maxlun = lun + 1; 7731 } 7732 7733 if (role != ROLE_TARGET) { 7734 for (;i < maxtarget; i++) { 7735 for (j = minlun;j < maxlun; j++) { 7736 u_int scbid; 7737 u_int tcl; 7738 7739 tcl = BUILD_TCL_RAW(i, 'A', j); 7740 scbid = ahd_find_busy_tcl(ahd, tcl); 7741 scbp = ahd_lookup_scb(ahd, scbid); 7742 if (scbp == NULL 7743 || ahd_match_scb(ahd, scbp, target, channel, 7744 lun, tag, role) == 0) 7745 continue; 7746 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7747 } 7748 } 7749 } 7750 7751 /* 7752 * Don't abort commands that have already completed, 7753 * but haven't quite made it up to the host yet. 7754 */ 7755 ahd_flush_qoutfifo(ahd); 7756 7757 /* 7758 * Go through the pending CCB list and look for 7759 * commands for this target that are still active. 7760 * These are other tagged commands that were 7761 * disconnected when the reset occurred. 7762 */ 7763 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7764 while (scbp_next != NULL) { 7765 scbp = scbp_next; 7766 scbp_next = LIST_NEXT(scbp, pending_links); 7767 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7768 cam_status ostat; 7769 7770 ostat = ahd_get_transaction_status(scbp); 7771 if (ostat == CAM_REQ_INPROG) 7772 ahd_set_transaction_status(scbp, status); 7773 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7774 ahd_freeze_scb(scbp); 7775 if ((scbp->flags & SCB_ACTIVE) == 0) 7776 printf("Inactive SCB on pending list\n"); 7777 ahd_done(ahd, scbp); 7778 found++; 7779 } 7780 } 7781 ahd_restore_modes(ahd, saved_modes); 7782 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7783 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7784 return found; 7785 } 7786 7787 static void 7788 ahd_reset_current_bus(struct ahd_softc *ahd) 7789 { 7790 uint8_t scsiseq; 7791 7792 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7793 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7794 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7795 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7796 ahd_flush_device_writes(ahd); 7797 ahd_delay(AHD_BUSRESET_DELAY); 7798 /* Turn off the bus reset */ 7799 ahd_outb(ahd, SCSISEQ0, scsiseq); 7800 ahd_flush_device_writes(ahd); 7801 ahd_delay(AHD_BUSRESET_DELAY); 7802 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7803 /* 7804 * 2A Razor #474 7805 * Certain chip state is not cleared for 7806 * SCSI bus resets that we initiate, so 7807 * we must reset the chip. 7808 */ 7809 ahd_reset(ahd, /*reinit*/TRUE); 7810 ahd_intr_enable(ahd, /*enable*/TRUE); 7811 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7812 } 7813 7814 ahd_clear_intstat(ahd); 7815 } 7816 7817 int 7818 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7819 { 7820 struct ahd_devinfo devinfo; 7821 u_int initiator; 7822 u_int target; 7823 u_int max_scsiid; 7824 int found; 7825 u_int fifo; 7826 u_int next_fifo; 7827 uint8_t scsiseq; 7828 7829 /* 7830 * Check if the last bus reset is cleared 7831 */ 7832 if (ahd->flags & AHD_BUS_RESET_ACTIVE) { 7833 printf("%s: bus reset still active\n", 7834 ahd_name(ahd)); 7835 return 0; 7836 } 7837 ahd->flags |= AHD_BUS_RESET_ACTIVE; 7838 7839 ahd->pending_device = NULL; 7840 7841 ahd_compile_devinfo(&devinfo, 7842 CAM_TARGET_WILDCARD, 7843 CAM_TARGET_WILDCARD, 7844 CAM_LUN_WILDCARD, 7845 channel, ROLE_UNKNOWN); 7846 ahd_pause(ahd); 7847 7848 /* Make sure the sequencer is in a safe location. */ 7849 ahd_clear_critical_section(ahd); 7850 7851 /* 7852 * Run our command complete fifos to ensure that we perform 7853 * completion processing on any commands that 'completed' 7854 * before the reset occurred. 7855 */ 7856 ahd_run_qoutfifo(ahd); 7857 #ifdef AHD_TARGET_MODE 7858 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7859 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7860 } 7861 #endif 7862 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7863 7864 /* 7865 * Disable selections so no automatic hardware 7866 * functions will modify chip state. 7867 */ 7868 ahd_outb(ahd, SCSISEQ0, 0); 7869 ahd_outb(ahd, SCSISEQ1, 0); 7870 7871 /* 7872 * Safely shut down our DMA engines. Always start with 7873 * the FIFO that is not currently active (if any are 7874 * actively connected). 7875 */ 7876 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7877 if (next_fifo > CURRFIFO_1) 7878 /* If disconneced, arbitrarily start with FIFO1. */ 7879 next_fifo = fifo = 0; 7880 do { 7881 next_fifo ^= CURRFIFO_1; 7882 ahd_set_modes(ahd, next_fifo, next_fifo); 7883 ahd_outb(ahd, DFCNTRL, 7884 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7885 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7886 ahd_delay(10); 7887 /* 7888 * Set CURRFIFO to the now inactive channel. 7889 */ 7890 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7891 ahd_outb(ahd, DFFSTAT, next_fifo); 7892 } while (next_fifo != fifo); 7893 7894 /* 7895 * Reset the bus if we are initiating this reset 7896 */ 7897 ahd_clear_msg_state(ahd); 7898 ahd_outb(ahd, SIMODE1, 7899 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST)); 7900 7901 if (initiate_reset) 7902 ahd_reset_current_bus(ahd); 7903 7904 ahd_clear_intstat(ahd); 7905 7906 /* 7907 * Clean up all the state information for the 7908 * pending transactions on this bus. 7909 */ 7910 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7911 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7912 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7913 7914 /* 7915 * Cleanup anything left in the FIFOs. 7916 */ 7917 ahd_clear_fifo(ahd, 0); 7918 ahd_clear_fifo(ahd, 1); 7919 7920 /* 7921 * Reenable selections 7922 */ 7923 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7924 scsiseq = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7925 ahd_outb(ahd, SCSISEQ1, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 7926 7927 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7928 #ifdef AHD_TARGET_MODE 7929 /* 7930 * Send an immediate notify ccb to all target more peripheral 7931 * drivers affected by this action. 7932 */ 7933 for (target = 0; target <= max_scsiid; target++) { 7934 struct ahd_tmode_tstate* tstate; 7935 u_int lun; 7936 7937 tstate = ahd->enabled_targets[target]; 7938 if (tstate == NULL) 7939 continue; 7940 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7941 struct ahd_tmode_lstate* lstate; 7942 7943 lstate = tstate->enabled_luns[lun]; 7944 if (lstate == NULL) 7945 continue; 7946 7947 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7948 EVENT_TYPE_BUS_RESET, /*arg*/0); 7949 ahd_send_lstate_events(ahd, lstate); 7950 } 7951 } 7952 #endif 7953 /* Notify the XPT that a bus reset occurred */ 7954 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7955 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7956 7957 /* 7958 * Revert to async/narrow transfers until we renegotiate. 7959 */ 7960 for (target = 0; target <= max_scsiid; target++) { 7961 7962 if (ahd->enabled_targets[target] == NULL) 7963 continue; 7964 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7965 struct ahd_devinfo devinfo; 7966 7967 ahd_compile_devinfo(&devinfo, target, initiator, 7968 CAM_LUN_WILDCARD, 7969 'A', ROLE_UNKNOWN); 7970 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7971 AHD_TRANS_CUR, /*paused*/TRUE); 7972 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7973 /*offset*/0, /*ppr_options*/0, 7974 AHD_TRANS_CUR, /*paused*/TRUE); 7975 } 7976 } 7977 7978 ahd_restart(ahd); 7979 7980 return (found); 7981 } 7982 7983 /**************************** Statistics Processing ***************************/ 7984 static void 7985 ahd_stat_timer(void *arg) 7986 { 7987 struct ahd_softc *ahd = arg; 7988 u_long s; 7989 int enint_coal; 7990 7991 ahd_lock(ahd, &s); 7992 7993 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 7994 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 7995 enint_coal |= ENINT_COALESCE; 7996 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 7997 enint_coal &= ~ENINT_COALESCE; 7998 7999 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 8000 ahd_enable_coalescing(ahd, enint_coal); 8001 #ifdef AHD_DEBUG 8002 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 8003 printf("%s: Interrupt coalescing " 8004 "now %sabled. Cmds %d\n", 8005 ahd_name(ahd), 8006 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 8007 ahd->cmdcmplt_total); 8008 #endif 8009 } 8010 8011 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 8012 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 8013 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 8014 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 8015 ahd_stat_timer, ahd); 8016 ahd_unlock(ahd, &s); 8017 } 8018 8019 /****************************** Status Processing *****************************/ 8020 void 8021 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 8022 { 8023 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 8024 ahd_handle_scsi_status(ahd, scb); 8025 } else { 8026 ahd_calc_residual(ahd, scb); 8027 ahd_done(ahd, scb); 8028 } 8029 } 8030 8031 void 8032 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 8033 { 8034 struct hardware_scb *hscb; 8035 int paused; 8036 8037 /* 8038 * The sequencer freezes its select-out queue 8039 * anytime a SCSI status error occurs. We must 8040 * handle the error and increment our qfreeze count 8041 * to allow the sequencer to continue. We don't 8042 * bother clearing critical sections here since all 8043 * operations are on data structures that the sequencer 8044 * is not touching once the queue is frozen. 8045 */ 8046 hscb = scb->hscb; 8047 8048 if (ahd_is_paused(ahd)) { 8049 paused = 1; 8050 } else { 8051 paused = 0; 8052 ahd_pause(ahd); 8053 } 8054 8055 /* Freeze the queue until the client sees the error. */ 8056 ahd_freeze_devq(ahd, scb); 8057 ahd_freeze_scb(scb); 8058 ahd->qfreeze_cnt++; 8059 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 8060 8061 if (paused == 0) 8062 ahd_unpause(ahd); 8063 8064 /* Don't want to clobber the original sense code */ 8065 if ((scb->flags & SCB_SENSE) != 0) { 8066 /* 8067 * Clear the SCB_SENSE Flag and perform 8068 * a normal command completion. 8069 */ 8070 scb->flags &= ~SCB_SENSE; 8071 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 8072 ahd_done(ahd, scb); 8073 return; 8074 } 8075 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 8076 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 8077 switch (hscb->shared_data.istatus.scsi_status) { 8078 case STATUS_PKT_SENSE: 8079 { 8080 struct scsi_status_iu_header *siu; 8081 8082 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 8083 siu = (struct scsi_status_iu_header *)scb->sense_data; 8084 ahd_set_scsi_status(scb, siu->status); 8085 #ifdef AHD_DEBUG 8086 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 8087 ahd_print_path(ahd, scb); 8088 printf("SCB 0x%x Received PKT Status of 0x%x\n", 8089 SCB_GET_TAG(scb), siu->status); 8090 printf("\tflags = 0x%x, sense len = 0x%x, " 8091 "pktfail = 0x%x\n", 8092 siu->flags, scsi_4btoul(siu->sense_length), 8093 scsi_4btoul(siu->pkt_failures_length)); 8094 } 8095 #endif 8096 if ((siu->flags & SIU_RSPVALID) != 0) { 8097 ahd_print_path(ahd, scb); 8098 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 8099 printf("Unable to parse pkt_failures\n"); 8100 } else { 8101 8102 switch (SIU_PKTFAIL_CODE(siu)) { 8103 case SIU_PFC_NONE: 8104 printf("No packet failure found\n"); 8105 break; 8106 case SIU_PFC_CIU_FIELDS_INVALID: 8107 printf("Invalid Command IU Field\n"); 8108 break; 8109 case SIU_PFC_TMF_NOT_SUPPORTED: 8110 printf("TMF not supportd\n"); 8111 break; 8112 case SIU_PFC_TMF_FAILED: 8113 printf("TMF failed\n"); 8114 break; 8115 case SIU_PFC_INVALID_TYPE_CODE: 8116 printf("Invalid L_Q Type code\n"); 8117 break; 8118 case SIU_PFC_ILLEGAL_REQUEST: 8119 printf("Illegal request\n"); 8120 default: 8121 break; 8122 } 8123 } 8124 if (siu->status == SCSI_STATUS_OK) 8125 ahd_set_transaction_status(scb, 8126 CAM_REQ_CMP_ERR); 8127 } 8128 if ((siu->flags & SIU_SNSVALID) != 0) { 8129 scb->flags |= SCB_PKT_SENSE; 8130 #ifdef AHD_DEBUG 8131 if ((ahd_debug & AHD_SHOW_SENSE) != 0) 8132 printf("Sense data available\n"); 8133 #endif 8134 } 8135 ahd_done(ahd, scb); 8136 break; 8137 } 8138 case SCSI_STATUS_CMD_TERMINATED: 8139 case SCSI_STATUS_CHECK_COND: 8140 { 8141 struct ahd_devinfo devinfo; 8142 struct ahd_dma_seg *sg; 8143 struct scsi_sense *sc; 8144 struct ahd_initiator_tinfo *targ_info; 8145 struct ahd_tmode_tstate *tstate; 8146 struct ahd_transinfo *tinfo; 8147 #ifdef AHD_DEBUG 8148 if (ahd_debug & AHD_SHOW_SENSE) { 8149 ahd_print_path(ahd, scb); 8150 printf("SCB %d: requests Check Status\n", 8151 SCB_GET_TAG(scb)); 8152 } 8153 #endif 8154 8155 if (ahd_perform_autosense(scb) == 0) 8156 break; 8157 8158 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 8159 SCB_GET_TARGET(ahd, scb), 8160 SCB_GET_LUN(scb), 8161 SCB_GET_CHANNEL(ahd, scb), 8162 ROLE_INITIATOR); 8163 targ_info = ahd_fetch_transinfo(ahd, 8164 devinfo.channel, 8165 devinfo.our_scsiid, 8166 devinfo.target, 8167 &tstate); 8168 tinfo = &targ_info->curr; 8169 sg = scb->sg_list; 8170 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb; 8171 /* 8172 * Save off the residual if there is one. 8173 */ 8174 ahd_update_residual(ahd, scb); 8175 #ifdef AHD_DEBUG 8176 if (ahd_debug & AHD_SHOW_SENSE) { 8177 ahd_print_path(ahd, scb); 8178 printf("Sending Sense\n"); 8179 } 8180 #endif 8181 scb->sg_count = 0; 8182 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 8183 ahd_get_sense_bufsize(ahd, scb), 8184 /*last*/TRUE); 8185 sc->opcode = REQUEST_SENSE; 8186 sc->byte2 = 0; 8187 if (tinfo->protocol_version <= SCSI_REV_2 8188 && SCB_GET_LUN(scb) < 8) 8189 sc->byte2 = SCB_GET_LUN(scb) << 5; 8190 sc->unused[0] = 0; 8191 sc->unused[1] = 0; 8192 sc->length = ahd_get_sense_bufsize(ahd, scb); 8193 sc->control = 0; 8194 8195 /* 8196 * We can't allow the target to disconnect. 8197 * This will be an untagged transaction and 8198 * having the target disconnect will make this 8199 * transaction indestinguishable from outstanding 8200 * tagged transactions. 8201 */ 8202 hscb->control = 0; 8203 8204 /* 8205 * This request sense could be because the 8206 * the device lost power or in some other 8207 * way has lost our transfer negotiations. 8208 * Renegotiate if appropriate. Unit attention 8209 * errors will be reported before any data 8210 * phases occur. 8211 */ 8212 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 8213 ahd_update_neg_request(ahd, &devinfo, 8214 tstate, targ_info, 8215 AHD_NEG_IF_NON_ASYNC); 8216 } 8217 if (tstate->auto_negotiate & devinfo.target_mask) { 8218 hscb->control |= MK_MESSAGE; 8219 scb->flags &= 8220 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 8221 scb->flags |= SCB_AUTO_NEGOTIATE; 8222 } 8223 hscb->cdb_len = sizeof(*sc); 8224 ahd_setup_data_scb(ahd, scb); 8225 scb->flags |= SCB_SENSE; 8226 ahd_queue_scb(ahd, scb); 8227 break; 8228 } 8229 case SCSI_STATUS_OK: 8230 printf("%s: Interrupted for staus of 0???\n", 8231 ahd_name(ahd)); 8232 /* FALLTHROUGH */ 8233 default: 8234 ahd_done(ahd, scb); 8235 break; 8236 } 8237 } 8238 8239 /* 8240 * Calculate the residual for a just completed SCB. 8241 */ 8242 void 8243 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 8244 { 8245 struct hardware_scb *hscb; 8246 struct initiator_status *spkt; 8247 uint32_t sgptr; 8248 uint32_t resid_sgptr; 8249 uint32_t resid; 8250 8251 /* 8252 * 5 cases. 8253 * 1) No residual. 8254 * SG_STATUS_VALID clear in sgptr. 8255 * 2) Transferless command 8256 * 3) Never performed any transfers. 8257 * sgptr has SG_FULL_RESID set. 8258 * 4) No residual but target did not 8259 * save data pointers after the 8260 * last transfer, so sgptr was 8261 * never updated. 8262 * 5) We have a partial residual. 8263 * Use residual_sgptr to determine 8264 * where we are. 8265 */ 8266 8267 hscb = scb->hscb; 8268 sgptr = ahd_le32toh(hscb->sgptr); 8269 if ((sgptr & SG_STATUS_VALID) == 0) 8270 /* Case 1 */ 8271 return; 8272 sgptr &= ~SG_STATUS_VALID; 8273 8274 if ((sgptr & SG_LIST_NULL) != 0) 8275 /* Case 2 */ 8276 return; 8277 8278 /* 8279 * Residual fields are the same in both 8280 * target and initiator status packets, 8281 * so we can always use the initiator fields 8282 * regardless of the role for this SCB. 8283 */ 8284 spkt = &hscb->shared_data.istatus; 8285 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 8286 if ((sgptr & SG_FULL_RESID) != 0) { 8287 /* Case 3 */ 8288 resid = ahd_get_transfer_length(scb); 8289 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 8290 /* Case 4 */ 8291 return; 8292 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 8293 ahd_print_path(ahd, scb); 8294 printf("data overrun detected Tag == 0x%x.\n", 8295 SCB_GET_TAG(scb)); 8296 ahd_freeze_devq(ahd, scb); 8297 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 8298 ahd_freeze_scb(scb); 8299 return; 8300 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 8301 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 8302 /* NOTREACHED */ 8303 } else { 8304 struct ahd_dma_seg *sg; 8305 8306 /* 8307 * Remainder of the SG where the transfer 8308 * stopped. 8309 */ 8310 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 8311 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 8312 8313 /* The residual sg_ptr always points to the next sg */ 8314 sg--; 8315 8316 /* 8317 * Add up the contents of all residual 8318 * SG segments that are after the SG where 8319 * the transfer stopped. 8320 */ 8321 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 8322 sg++; 8323 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 8324 } 8325 } 8326 if ((scb->flags & SCB_SENSE) == 0) 8327 ahd_set_residual(scb, resid); 8328 else 8329 ahd_set_sense_residual(scb, resid); 8330 8331 #ifdef AHD_DEBUG 8332 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 8333 ahd_print_path(ahd, scb); 8334 printf("Handled %sResidual of %d bytes\n", 8335 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 8336 } 8337 #endif 8338 } 8339 8340 /******************************* Target Mode **********************************/ 8341 #ifdef AHD_TARGET_MODE 8342 /* 8343 * Add a target mode event to this lun's queue 8344 */ 8345 static void 8346 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 8347 u_int initiator_id, u_int event_type, u_int event_arg) 8348 { 8349 struct ahd_tmode_event *event; 8350 int pending; 8351 8352 xpt_freeze_devq(lstate->path, /*count*/1); 8353 if (lstate->event_w_idx >= lstate->event_r_idx) 8354 pending = lstate->event_w_idx - lstate->event_r_idx; 8355 else 8356 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 8357 - (lstate->event_r_idx - lstate->event_w_idx); 8358 8359 if (event_type == EVENT_TYPE_BUS_RESET 8360 || event_type == MSG_BUS_DEV_RESET) { 8361 /* 8362 * Any earlier events are irrelevant, so reset our buffer. 8363 * This has the effect of allowing us to deal with reset 8364 * floods (an external device holding down the reset line) 8365 * without losing the event that is really interesting. 8366 */ 8367 lstate->event_r_idx = 0; 8368 lstate->event_w_idx = 0; 8369 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 8370 } 8371 8372 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 8373 xpt_print_path(lstate->path); 8374 printf("immediate event %x:%x lost\n", 8375 lstate->event_buffer[lstate->event_r_idx].event_type, 8376 lstate->event_buffer[lstate->event_r_idx].event_arg); 8377 lstate->event_r_idx++; 8378 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8379 lstate->event_r_idx = 0; 8380 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 8381 } 8382 8383 event = &lstate->event_buffer[lstate->event_w_idx]; 8384 event->initiator_id = initiator_id; 8385 event->event_type = event_type; 8386 event->event_arg = event_arg; 8387 lstate->event_w_idx++; 8388 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8389 lstate->event_w_idx = 0; 8390 } 8391 8392 /* 8393 * Send any target mode events queued up waiting 8394 * for immediate notify resources. 8395 */ 8396 void 8397 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 8398 { 8399 struct ccb_hdr *ccbh; 8400 struct ccb_immed_notify *inot; 8401 8402 while (lstate->event_r_idx != lstate->event_w_idx 8403 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 8404 struct ahd_tmode_event *event; 8405 8406 event = &lstate->event_buffer[lstate->event_r_idx]; 8407 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 8408 inot = (struct ccb_immed_notify *)ccbh; 8409 switch (event->event_type) { 8410 case EVENT_TYPE_BUS_RESET: 8411 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 8412 break; 8413 default: 8414 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 8415 inot->message_args[0] = event->event_type; 8416 inot->message_args[1] = event->event_arg; 8417 break; 8418 } 8419 inot->initiator_id = event->initiator_id; 8420 inot->sense_len = 0; 8421 xpt_done((union ccb *)inot); 8422 lstate->event_r_idx++; 8423 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8424 lstate->event_r_idx = 0; 8425 } 8426 } 8427 #endif 8428 8429 /******************** Sequencer Program Patching/Download *********************/ 8430 8431 #ifdef AHD_DUMP_SEQ 8432 void 8433 ahd_dumpseq(struct ahd_softc* ahd) 8434 { 8435 int i; 8436 int max_prog; 8437 8438 max_prog = 2048; 8439 8440 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8441 ahd_outw(ahd, PRGMCNT, 0); 8442 for (i = 0; i < max_prog; i++) { 8443 uint8_t ins_bytes[4]; 8444 8445 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 8446 printf("0x%08x\n", ins_bytes[0] << 24 8447 | ins_bytes[1] << 16 8448 | ins_bytes[2] << 8 8449 | ins_bytes[3]); 8450 } 8451 } 8452 #endif 8453 8454 static void 8455 ahd_loadseq(struct ahd_softc *ahd) 8456 { 8457 struct cs cs_table[num_critical_sections]; 8458 u_int begin_set[num_critical_sections]; 8459 u_int end_set[num_critical_sections]; 8460 struct patch *cur_patch; 8461 u_int cs_count; 8462 u_int cur_cs; 8463 u_int i; 8464 int downloaded; 8465 u_int skip_addr; 8466 u_int sg_prefetch_cnt; 8467 u_int sg_prefetch_cnt_limit; 8468 u_int sg_prefetch_align; 8469 u_int sg_size; 8470 u_int cacheline_mask; 8471 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8472 8473 if (bootverbose) 8474 printf("%s: Downloading Sequencer Program...", 8475 ahd_name(ahd)); 8476 8477 #if DOWNLOAD_CONST_COUNT != 8 8478 #error "Download Const Mismatch" 8479 #endif 8480 /* 8481 * Start out with 0 critical sections 8482 * that apply to this firmware load. 8483 */ 8484 cs_count = 0; 8485 cur_cs = 0; 8486 memset(begin_set, 0, sizeof(begin_set)); 8487 memset(end_set, 0, sizeof(end_set)); 8488 8489 /* 8490 * Setup downloadable constant table. 8491 * 8492 * The computation for the S/G prefetch variables is 8493 * a bit complicated. We would like to always fetch 8494 * in terms of cachelined sized increments. However, 8495 * if the cacheline is not an even multiple of the 8496 * SG element size or is larger than our SG RAM, using 8497 * just the cache size might leave us with only a portion 8498 * of an SG element at the tail of a prefetch. If the 8499 * cacheline is larger than our S/G prefetch buffer less 8500 * the size of an SG element, we may round down to a cacheline 8501 * that doesn't contain any or all of the S/G of interest 8502 * within the bounds of our S/G ram. Provide variables to 8503 * the sequencer that will allow it to handle these edge 8504 * cases. 8505 */ 8506 /* Start by aligning to the nearest cacheline. */ 8507 sg_prefetch_align = ahd->pci_cachesize; 8508 if (sg_prefetch_align == 0) 8509 sg_prefetch_align = 8; 8510 /* Round down to the nearest power of 2. */ 8511 while (powerof2(sg_prefetch_align) == 0) 8512 sg_prefetch_align--; 8513 8514 cacheline_mask = sg_prefetch_align - 1; 8515 8516 /* 8517 * If the cacheline boundary is greater than half our prefetch RAM 8518 * we risk not being able to fetch even a single complete S/G 8519 * segment if we align to that boundary. 8520 */ 8521 if (sg_prefetch_align > CCSGADDR_MAX/2) 8522 sg_prefetch_align = CCSGADDR_MAX/2; 8523 /* Start by fetching a single cacheline. */ 8524 sg_prefetch_cnt = sg_prefetch_align; 8525 /* 8526 * Increment the prefetch count by cachelines until 8527 * at least one S/G element will fit. 8528 */ 8529 sg_size = sizeof(struct ahd_dma_seg); 8530 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8531 sg_size = sizeof(struct ahd_dma64_seg); 8532 while (sg_prefetch_cnt < sg_size) 8533 sg_prefetch_cnt += sg_prefetch_align; 8534 /* 8535 * If the cacheline is not an even multiple of 8536 * the S/G size, we may only get a partial S/G when 8537 * we align. Add a cacheline if this is the case. 8538 */ 8539 if ((sg_prefetch_align % sg_size) != 0 8540 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8541 sg_prefetch_cnt += sg_prefetch_align; 8542 /* 8543 * Lastly, compute a value that the sequencer can use 8544 * to determine if the remainder of the CCSGRAM buffer 8545 * has a full S/G element in it. 8546 */ 8547 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8548 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8549 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8550 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8551 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8552 download_consts[SG_SIZEOF] = sg_size; 8553 download_consts[PKT_OVERRUN_BUFOFFSET] = 8554 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8555 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8556 download_consts[CACHELINE_MASK] = cacheline_mask; 8557 cur_patch = patches; 8558 downloaded = 0; 8559 skip_addr = 0; 8560 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8561 ahd_outw(ahd, PRGMCNT, 0); 8562 8563 for (i = 0; i < sizeof(seqprog)/4; i++) { 8564 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8565 /* 8566 * Don't download this instruction as it 8567 * is in a patch that was removed. 8568 */ 8569 continue; 8570 } 8571 /* 8572 * Move through the CS table until we find a CS 8573 * that might apply to this instruction. 8574 */ 8575 for (; cur_cs < num_critical_sections; cur_cs++) { 8576 if (critical_sections[cur_cs].end <= i) { 8577 if (begin_set[cs_count] == TRUE 8578 && end_set[cs_count] == FALSE) { 8579 cs_table[cs_count].end = downloaded; 8580 end_set[cs_count] = TRUE; 8581 cs_count++; 8582 } 8583 continue; 8584 } 8585 if (critical_sections[cur_cs].begin <= i 8586 && begin_set[cs_count] == FALSE) { 8587 cs_table[cs_count].begin = downloaded; 8588 begin_set[cs_count] = TRUE; 8589 } 8590 break; 8591 } 8592 ahd_download_instr(ahd, i, download_consts); 8593 downloaded++; 8594 } 8595 8596 ahd->num_critical_sections = cs_count; 8597 if (cs_count != 0) { 8598 8599 cs_count *= sizeof(struct cs); 8600 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8601 if (ahd->critical_sections == NULL) 8602 panic("ahd_loadseq: Could not malloc"); 8603 memcpy(ahd->critical_sections, cs_table, cs_count); 8604 } 8605 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8606 8607 if (bootverbose) { 8608 printf(" %d instructions downloaded\n", downloaded); 8609 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8610 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8611 } 8612 } 8613 8614 static int 8615 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8616 u_int start_instr, u_int *skip_addr) 8617 { 8618 struct patch *cur_patch; 8619 struct patch *last_patch; 8620 u_int num_patches; 8621 8622 num_patches = ARRAY_SIZE(patches); 8623 last_patch = &patches[num_patches]; 8624 cur_patch = *start_patch; 8625 8626 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8627 8628 if (cur_patch->patch_func(ahd) == 0) { 8629 8630 /* Start rejecting code */ 8631 *skip_addr = start_instr + cur_patch->skip_instr; 8632 cur_patch += cur_patch->skip_patch; 8633 } else { 8634 /* Accepted this patch. Advance to the next 8635 * one and wait for our intruction pointer to 8636 * hit this point. 8637 */ 8638 cur_patch++; 8639 } 8640 } 8641 8642 *start_patch = cur_patch; 8643 if (start_instr < *skip_addr) 8644 /* Still skipping */ 8645 return (0); 8646 8647 return (1); 8648 } 8649 8650 static u_int 8651 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8652 { 8653 struct patch *cur_patch; 8654 int address_offset; 8655 u_int skip_addr; 8656 u_int i; 8657 8658 address_offset = 0; 8659 cur_patch = patches; 8660 skip_addr = 0; 8661 8662 for (i = 0; i < address;) { 8663 8664 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8665 8666 if (skip_addr > i) { 8667 int end_addr; 8668 8669 end_addr = MIN(address, skip_addr); 8670 address_offset += end_addr - i; 8671 i = skip_addr; 8672 } else { 8673 i++; 8674 } 8675 } 8676 return (address - address_offset); 8677 } 8678 8679 static void 8680 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8681 { 8682 union ins_formats instr; 8683 struct ins_format1 *fmt1_ins; 8684 struct ins_format3 *fmt3_ins; 8685 u_int opcode; 8686 8687 /* 8688 * The firmware is always compiled into a little endian format. 8689 */ 8690 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8691 8692 fmt1_ins = &instr.format1; 8693 fmt3_ins = NULL; 8694 8695 /* Pull the opcode */ 8696 opcode = instr.format1.opcode; 8697 switch (opcode) { 8698 case AIC_OP_JMP: 8699 case AIC_OP_JC: 8700 case AIC_OP_JNC: 8701 case AIC_OP_CALL: 8702 case AIC_OP_JNE: 8703 case AIC_OP_JNZ: 8704 case AIC_OP_JE: 8705 case AIC_OP_JZ: 8706 { 8707 fmt3_ins = &instr.format3; 8708 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8709 /* FALLTHROUGH */ 8710 } 8711 case AIC_OP_OR: 8712 case AIC_OP_AND: 8713 case AIC_OP_XOR: 8714 case AIC_OP_ADD: 8715 case AIC_OP_ADC: 8716 case AIC_OP_BMOV: 8717 if (fmt1_ins->parity != 0) { 8718 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8719 } 8720 fmt1_ins->parity = 0; 8721 /* FALLTHROUGH */ 8722 case AIC_OP_ROL: 8723 { 8724 int i, count; 8725 8726 /* Calculate odd parity for the instruction */ 8727 for (i = 0, count = 0; i < 31; i++) { 8728 uint32_t mask; 8729 8730 mask = 0x01 << i; 8731 if ((instr.integer & mask) != 0) 8732 count++; 8733 } 8734 if ((count & 0x01) == 0) 8735 instr.format1.parity = 1; 8736 8737 /* The sequencer is a little endian cpu */ 8738 instr.integer = ahd_htole32(instr.integer); 8739 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8740 break; 8741 } 8742 default: 8743 panic("Unknown opcode encountered in seq program"); 8744 break; 8745 } 8746 } 8747 8748 static int 8749 ahd_probe_stack_size(struct ahd_softc *ahd) 8750 { 8751 int last_probe; 8752 8753 last_probe = 0; 8754 while (1) { 8755 int i; 8756 8757 /* 8758 * We avoid using 0 as a pattern to avoid 8759 * confusion if the stack implementation 8760 * "back-fills" with zeros when "poping' 8761 * entries. 8762 */ 8763 for (i = 1; i <= last_probe+1; i++) { 8764 ahd_outb(ahd, STACK, i & 0xFF); 8765 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8766 } 8767 8768 /* Verify */ 8769 for (i = last_probe+1; i > 0; i--) { 8770 u_int stack_entry; 8771 8772 stack_entry = ahd_inb(ahd, STACK) 8773 |(ahd_inb(ahd, STACK) << 8); 8774 if (stack_entry != i) 8775 goto sized; 8776 } 8777 last_probe++; 8778 } 8779 sized: 8780 return (last_probe); 8781 } 8782 8783 int 8784 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8785 const char *name, u_int address, u_int value, 8786 u_int *cur_column, u_int wrap_point) 8787 { 8788 int printed; 8789 u_int printed_mask; 8790 8791 if (cur_column != NULL && *cur_column >= wrap_point) { 8792 printf("\n"); 8793 *cur_column = 0; 8794 } 8795 printed = printf("%s[0x%x]", name, value); 8796 if (table == NULL) { 8797 printed += printf(" "); 8798 *cur_column += printed; 8799 return (printed); 8800 } 8801 printed_mask = 0; 8802 while (printed_mask != 0xFF) { 8803 int entry; 8804 8805 for (entry = 0; entry < num_entries; entry++) { 8806 if (((value & table[entry].mask) 8807 != table[entry].value) 8808 || ((printed_mask & table[entry].mask) 8809 == table[entry].mask)) 8810 continue; 8811 8812 printed += printf("%s%s", 8813 printed_mask == 0 ? ":(" : "|", 8814 table[entry].name); 8815 printed_mask |= table[entry].mask; 8816 8817 break; 8818 } 8819 if (entry >= num_entries) 8820 break; 8821 } 8822 if (printed_mask != 0) 8823 printed += printf(") "); 8824 else 8825 printed += printf(" "); 8826 if (cur_column != NULL) 8827 *cur_column += printed; 8828 return (printed); 8829 } 8830 8831 void 8832 ahd_dump_card_state(struct ahd_softc *ahd) 8833 { 8834 struct scb *scb; 8835 ahd_mode_state saved_modes; 8836 u_int dffstat; 8837 int paused; 8838 u_int scb_index; 8839 u_int saved_scb_index; 8840 u_int cur_col; 8841 int i; 8842 8843 if (ahd_is_paused(ahd)) { 8844 paused = 1; 8845 } else { 8846 paused = 0; 8847 ahd_pause(ahd); 8848 } 8849 saved_modes = ahd_save_modes(ahd); 8850 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8851 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8852 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8853 ahd_name(ahd), 8854 ahd_inw(ahd, CURADDR), 8855 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8856 ahd->saved_dst_mode)); 8857 if (paused) 8858 printf("Card was paused\n"); 8859 8860 if (ahd_check_cmdcmpltqueues(ahd)) 8861 printf("Completions are pending\n"); 8862 8863 /* 8864 * Mode independent registers. 8865 */ 8866 cur_col = 0; 8867 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50); 8868 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50); 8869 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50); 8870 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8871 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8872 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8873 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8874 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8875 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8876 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8877 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8878 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8879 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8880 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8881 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8882 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8883 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8884 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8885 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50); 8886 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT), 8887 &cur_col, 50); 8888 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50); 8889 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID), 8890 &cur_col, 50); 8891 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8892 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8893 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8894 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8895 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8896 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8897 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8898 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8899 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8900 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8901 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8902 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8903 printf("\n"); 8904 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8905 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8906 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8907 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8908 ahd_inw(ahd, NEXTSCB)); 8909 cur_col = 0; 8910 /* QINFIFO */ 8911 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8912 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8913 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8914 saved_scb_index = ahd_get_scbptr(ahd); 8915 printf("Pending list:"); 8916 i = 0; 8917 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8918 if (i++ > AHD_SCB_MAX) 8919 break; 8920 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 8921 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT)); 8922 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8923 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL), 8924 &cur_col, 60); 8925 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID), 8926 &cur_col, 60); 8927 } 8928 printf("\nTotal %d\n", i); 8929 8930 printf("Kernel Free SCB list: "); 8931 i = 0; 8932 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8933 struct scb *list_scb; 8934 8935 list_scb = scb; 8936 do { 8937 printf("%d ", SCB_GET_TAG(list_scb)); 8938 list_scb = LIST_NEXT(list_scb, collision_links); 8939 } while (list_scb && i++ < AHD_SCB_MAX); 8940 } 8941 8942 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8943 if (i++ > AHD_SCB_MAX) 8944 break; 8945 printf("%d ", SCB_GET_TAG(scb)); 8946 } 8947 printf("\n"); 8948 8949 printf("Sequencer Complete DMA-inprog list: "); 8950 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8951 i = 0; 8952 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8953 ahd_set_scbptr(ahd, scb_index); 8954 printf("%d ", scb_index); 8955 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8956 } 8957 printf("\n"); 8958 8959 printf("Sequencer Complete list: "); 8960 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8961 i = 0; 8962 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8963 ahd_set_scbptr(ahd, scb_index); 8964 printf("%d ", scb_index); 8965 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8966 } 8967 printf("\n"); 8968 8969 8970 printf("Sequencer DMA-Up and Complete list: "); 8971 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8972 i = 0; 8973 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8974 ahd_set_scbptr(ahd, scb_index); 8975 printf("%d ", scb_index); 8976 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8977 } 8978 printf("\n"); 8979 printf("Sequencer On QFreeze and Complete list: "); 8980 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 8981 i = 0; 8982 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8983 ahd_set_scbptr(ahd, scb_index); 8984 printf("%d ", scb_index); 8985 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8986 } 8987 printf("\n"); 8988 ahd_set_scbptr(ahd, saved_scb_index); 8989 dffstat = ahd_inb(ahd, DFFSTAT); 8990 for (i = 0; i < 2; i++) { 8991 #ifdef AHD_DEBUG 8992 struct scb *fifo_scb; 8993 #endif 8994 u_int fifo_scbptr; 8995 8996 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8997 fifo_scbptr = ahd_get_scbptr(ahd); 8998 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 8999 ahd_name(ahd), i, 9000 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 9001 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 9002 cur_col = 0; 9003 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 9004 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 9005 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 9006 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 9007 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 9008 &cur_col, 50); 9009 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 9010 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 9011 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 9012 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 9013 if (cur_col > 50) { 9014 printf("\n"); 9015 cur_col = 0; 9016 } 9017 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ", 9018 ahd_inl(ahd, SHADDR+4), 9019 ahd_inl(ahd, SHADDR), 9020 (ahd_inb(ahd, SHCNT) 9021 | (ahd_inb(ahd, SHCNT + 1) << 8) 9022 | (ahd_inb(ahd, SHCNT + 2) << 16))); 9023 if (cur_col > 50) { 9024 printf("\n"); 9025 cur_col = 0; 9026 } 9027 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ", 9028 ahd_inl(ahd, HADDR+4), 9029 ahd_inl(ahd, HADDR), 9030 (ahd_inb(ahd, HCNT) 9031 | (ahd_inb(ahd, HCNT + 1) << 8) 9032 | (ahd_inb(ahd, HCNT + 2) << 16))); 9033 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 9034 #ifdef AHD_DEBUG 9035 if ((ahd_debug & AHD_SHOW_SG) != 0) { 9036 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 9037 if (fifo_scb != NULL) 9038 ahd_dump_sglist(fifo_scb); 9039 } 9040 #endif 9041 } 9042 printf("\nLQIN: "); 9043 for (i = 0; i < 20; i++) 9044 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 9045 printf("\n"); 9046 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 9047 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 9048 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 9049 ahd_inb(ahd, OPTIONMODE)); 9050 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 9051 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 9052 ahd_inb(ahd, MAXCMDCNT)); 9053 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n", 9054 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID), 9055 ahd_inb(ahd, SAVED_LUN)); 9056 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 9057 printf("\n"); 9058 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 9059 cur_col = 0; 9060 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50); 9061 printf("\n"); 9062 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 9063 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 9064 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 9065 ahd_inw(ahd, DINDEX)); 9066 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 9067 ahd_name(ahd), ahd_get_scbptr(ahd), 9068 ahd_inw_scbram(ahd, SCB_NEXT), 9069 ahd_inw_scbram(ahd, SCB_NEXT2)); 9070 printf("CDB %x %x %x %x %x %x\n", 9071 ahd_inb_scbram(ahd, SCB_CDB_STORE), 9072 ahd_inb_scbram(ahd, SCB_CDB_STORE+1), 9073 ahd_inb_scbram(ahd, SCB_CDB_STORE+2), 9074 ahd_inb_scbram(ahd, SCB_CDB_STORE+3), 9075 ahd_inb_scbram(ahd, SCB_CDB_STORE+4), 9076 ahd_inb_scbram(ahd, SCB_CDB_STORE+5)); 9077 printf("STACK:"); 9078 for (i = 0; i < ahd->stack_size; i++) { 9079 ahd->saved_stack[i] = 9080 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 9081 printf(" 0x%x", ahd->saved_stack[i]); 9082 } 9083 for (i = ahd->stack_size-1; i >= 0; i--) { 9084 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 9085 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 9086 } 9087 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 9088 ahd_restore_modes(ahd, saved_modes); 9089 if (paused == 0) 9090 ahd_unpause(ahd); 9091 } 9092 9093 void 9094 ahd_dump_scbs(struct ahd_softc *ahd) 9095 { 9096 ahd_mode_state saved_modes; 9097 u_int saved_scb_index; 9098 int i; 9099 9100 saved_modes = ahd_save_modes(ahd); 9101 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 9102 saved_scb_index = ahd_get_scbptr(ahd); 9103 for (i = 0; i < AHD_SCB_MAX; i++) { 9104 ahd_set_scbptr(ahd, i); 9105 printf("%3d", i); 9106 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 9107 ahd_inb_scbram(ahd, SCB_CONTROL), 9108 ahd_inb_scbram(ahd, SCB_SCSIID), 9109 ahd_inw_scbram(ahd, SCB_NEXT), 9110 ahd_inw_scbram(ahd, SCB_NEXT2), 9111 ahd_inl_scbram(ahd, SCB_SGPTR), 9112 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR)); 9113 } 9114 printf("\n"); 9115 ahd_set_scbptr(ahd, saved_scb_index); 9116 ahd_restore_modes(ahd, saved_modes); 9117 } 9118 9119 /**************************** Flexport Logic **********************************/ 9120 /* 9121 * Read count 16bit words from 16bit word address start_addr from the 9122 * SEEPROM attached to the controller, into buf, using the controller's 9123 * SEEPROM reading state machine. Optionally treat the data as a byte 9124 * stream in terms of byte order. 9125 */ 9126 int 9127 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 9128 u_int start_addr, u_int count, int bytestream) 9129 { 9130 u_int cur_addr; 9131 u_int end_addr; 9132 int error; 9133 9134 /* 9135 * If we never make it through the loop even once, 9136 * we were passed invalid arguments. 9137 */ 9138 error = EINVAL; 9139 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9140 end_addr = start_addr + count; 9141 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 9142 9143 ahd_outb(ahd, SEEADR, cur_addr); 9144 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 9145 9146 error = ahd_wait_seeprom(ahd); 9147 if (error) 9148 break; 9149 if (bytestream != 0) { 9150 uint8_t *bytestream_ptr; 9151 9152 bytestream_ptr = (uint8_t *)buf; 9153 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 9154 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 9155 } else { 9156 /* 9157 * ahd_inw() already handles machine byte order. 9158 */ 9159 *buf = ahd_inw(ahd, SEEDAT); 9160 } 9161 buf++; 9162 } 9163 return (error); 9164 } 9165 9166 /* 9167 * Write count 16bit words from buf, into SEEPROM attache to the 9168 * controller starting at 16bit word address start_addr, using the 9169 * controller's SEEPROM writing state machine. 9170 */ 9171 int 9172 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 9173 u_int start_addr, u_int count) 9174 { 9175 u_int cur_addr; 9176 u_int end_addr; 9177 int error; 9178 int retval; 9179 9180 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9181 error = ENOENT; 9182 9183 /* Place the chip into write-enable mode */ 9184 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 9185 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 9186 error = ahd_wait_seeprom(ahd); 9187 if (error) 9188 return (error); 9189 9190 /* 9191 * Write the data. If we don't get throught the loop at 9192 * least once, the arguments were invalid. 9193 */ 9194 retval = EINVAL; 9195 end_addr = start_addr + count; 9196 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 9197 ahd_outw(ahd, SEEDAT, *buf++); 9198 ahd_outb(ahd, SEEADR, cur_addr); 9199 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 9200 9201 retval = ahd_wait_seeprom(ahd); 9202 if (retval) 9203 break; 9204 } 9205 9206 /* 9207 * Disable writes. 9208 */ 9209 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 9210 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 9211 error = ahd_wait_seeprom(ahd); 9212 if (error) 9213 return (error); 9214 return (retval); 9215 } 9216 9217 /* 9218 * Wait ~100us for the serial eeprom to satisfy our request. 9219 */ 9220 int 9221 ahd_wait_seeprom(struct ahd_softc *ahd) 9222 { 9223 int cnt; 9224 9225 cnt = 5000; 9226 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 9227 ahd_delay(5); 9228 9229 if (cnt == 0) 9230 return (ETIMEDOUT); 9231 return (0); 9232 } 9233 9234 /* 9235 * Validate the two checksums in the per_channel 9236 * vital product data struct. 9237 */ 9238 int 9239 ahd_verify_vpd_cksum(struct vpd_config *vpd) 9240 { 9241 int i; 9242 int maxaddr; 9243 uint32_t checksum; 9244 uint8_t *vpdarray; 9245 9246 vpdarray = (uint8_t *)vpd; 9247 maxaddr = offsetof(struct vpd_config, vpd_checksum); 9248 checksum = 0; 9249 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 9250 checksum = checksum + vpdarray[i]; 9251 if (checksum == 0 9252 || (-checksum & 0xFF) != vpd->vpd_checksum) 9253 return (0); 9254 9255 checksum = 0; 9256 maxaddr = offsetof(struct vpd_config, checksum); 9257 for (i = offsetof(struct vpd_config, default_target_flags); 9258 i < maxaddr; i++) 9259 checksum = checksum + vpdarray[i]; 9260 if (checksum == 0 9261 || (-checksum & 0xFF) != vpd->checksum) 9262 return (0); 9263 return (1); 9264 } 9265 9266 int 9267 ahd_verify_cksum(struct seeprom_config *sc) 9268 { 9269 int i; 9270 int maxaddr; 9271 uint32_t checksum; 9272 uint16_t *scarray; 9273 9274 maxaddr = (sizeof(*sc)/2) - 1; 9275 checksum = 0; 9276 scarray = (uint16_t *)sc; 9277 9278 for (i = 0; i < maxaddr; i++) 9279 checksum = checksum + scarray[i]; 9280 if (checksum == 0 9281 || (checksum & 0xFFFF) != sc->checksum) { 9282 return (0); 9283 } else { 9284 return (1); 9285 } 9286 } 9287 9288 int 9289 ahd_acquire_seeprom(struct ahd_softc *ahd) 9290 { 9291 /* 9292 * We should be able to determine the SEEPROM type 9293 * from the flexport logic, but unfortunately not 9294 * all implementations have this logic and there is 9295 * no programatic method for determining if the logic 9296 * is present. 9297 */ 9298 return (1); 9299 #if 0 9300 uint8_t seetype; 9301 int error; 9302 9303 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 9304 if (error != 0 9305 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 9306 return (0); 9307 return (1); 9308 #endif 9309 } 9310 9311 void 9312 ahd_release_seeprom(struct ahd_softc *ahd) 9313 { 9314 /* Currently a no-op */ 9315 } 9316 9317 int 9318 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 9319 { 9320 int error; 9321 9322 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9323 if (addr > 7) 9324 panic("ahd_write_flexport: address out of range"); 9325 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9326 error = ahd_wait_flexport(ahd); 9327 if (error != 0) 9328 return (error); 9329 ahd_outb(ahd, BRDDAT, value); 9330 ahd_flush_device_writes(ahd); 9331 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 9332 ahd_flush_device_writes(ahd); 9333 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9334 ahd_flush_device_writes(ahd); 9335 ahd_outb(ahd, BRDCTL, 0); 9336 ahd_flush_device_writes(ahd); 9337 return (0); 9338 } 9339 9340 int 9341 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 9342 { 9343 int error; 9344 9345 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9346 if (addr > 7) 9347 panic("ahd_read_flexport: address out of range"); 9348 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 9349 error = ahd_wait_flexport(ahd); 9350 if (error != 0) 9351 return (error); 9352 *value = ahd_inb(ahd, BRDDAT); 9353 ahd_outb(ahd, BRDCTL, 0); 9354 ahd_flush_device_writes(ahd); 9355 return (0); 9356 } 9357 9358 /* 9359 * Wait at most 2 seconds for flexport arbitration to succeed. 9360 */ 9361 int 9362 ahd_wait_flexport(struct ahd_softc *ahd) 9363 { 9364 int cnt; 9365 9366 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9367 cnt = 1000000 * 2 / 5; 9368 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 9369 ahd_delay(5); 9370 9371 if (cnt == 0) 9372 return (ETIMEDOUT); 9373 return (0); 9374 } 9375 9376 /************************* Target Mode ****************************************/ 9377 #ifdef AHD_TARGET_MODE 9378 cam_status 9379 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 9380 struct ahd_tmode_tstate **tstate, 9381 struct ahd_tmode_lstate **lstate, 9382 int notfound_failure) 9383 { 9384 9385 if ((ahd->features & AHD_TARGETMODE) == 0) 9386 return (CAM_REQ_INVALID); 9387 9388 /* 9389 * Handle the 'black hole' device that sucks up 9390 * requests to unattached luns on enabled targets. 9391 */ 9392 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 9393 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 9394 *tstate = NULL; 9395 *lstate = ahd->black_hole; 9396 } else { 9397 u_int max_id; 9398 9399 max_id = (ahd->features & AHD_WIDE) ? 16 : 8; 9400 if (ccb->ccb_h.target_id >= max_id) 9401 return (CAM_TID_INVALID); 9402 9403 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 9404 return (CAM_LUN_INVALID); 9405 9406 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 9407 *lstate = NULL; 9408 if (*tstate != NULL) 9409 *lstate = 9410 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 9411 } 9412 9413 if (notfound_failure != 0 && *lstate == NULL) 9414 return (CAM_PATH_INVALID); 9415 9416 return (CAM_REQ_CMP); 9417 } 9418 9419 void 9420 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 9421 { 9422 #if NOT_YET 9423 struct ahd_tmode_tstate *tstate; 9424 struct ahd_tmode_lstate *lstate; 9425 struct ccb_en_lun *cel; 9426 cam_status status; 9427 u_int target; 9428 u_int lun; 9429 u_int target_mask; 9430 u_long s; 9431 char channel; 9432 9433 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 9434 /*notfound_failure*/FALSE); 9435 9436 if (status != CAM_REQ_CMP) { 9437 ccb->ccb_h.status = status; 9438 return; 9439 } 9440 9441 if ((ahd->features & AHD_MULTIROLE) != 0) { 9442 u_int our_id; 9443 9444 our_id = ahd->our_id; 9445 if (ccb->ccb_h.target_id != our_id) { 9446 if ((ahd->features & AHD_MULTI_TID) != 0 9447 && (ahd->flags & AHD_INITIATORROLE) != 0) { 9448 /* 9449 * Only allow additional targets if 9450 * the initiator role is disabled. 9451 * The hardware cannot handle a re-select-in 9452 * on the initiator id during a re-select-out 9453 * on a different target id. 9454 */ 9455 status = CAM_TID_INVALID; 9456 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 9457 || ahd->enabled_luns > 0) { 9458 /* 9459 * Only allow our target id to change 9460 * if the initiator role is not configured 9461 * and there are no enabled luns which 9462 * are attached to the currently registered 9463 * scsi id. 9464 */ 9465 status = CAM_TID_INVALID; 9466 } 9467 } 9468 } 9469 9470 if (status != CAM_REQ_CMP) { 9471 ccb->ccb_h.status = status; 9472 return; 9473 } 9474 9475 /* 9476 * We now have an id that is valid. 9477 * If we aren't in target mode, switch modes. 9478 */ 9479 if ((ahd->flags & AHD_TARGETROLE) == 0 9480 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9481 u_long s; 9482 9483 printf("Configuring Target Mode\n"); 9484 ahd_lock(ahd, &s); 9485 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9486 ccb->ccb_h.status = CAM_BUSY; 9487 ahd_unlock(ahd, &s); 9488 return; 9489 } 9490 ahd->flags |= AHD_TARGETROLE; 9491 if ((ahd->features & AHD_MULTIROLE) == 0) 9492 ahd->flags &= ~AHD_INITIATORROLE; 9493 ahd_pause(ahd); 9494 ahd_loadseq(ahd); 9495 ahd_restart(ahd); 9496 ahd_unlock(ahd, &s); 9497 } 9498 cel = &ccb->cel; 9499 target = ccb->ccb_h.target_id; 9500 lun = ccb->ccb_h.target_lun; 9501 channel = SIM_CHANNEL(ahd, sim); 9502 target_mask = 0x01 << target; 9503 if (channel == 'B') 9504 target_mask <<= 8; 9505 9506 if (cel->enable != 0) { 9507 u_int scsiseq1; 9508 9509 /* Are we already enabled?? */ 9510 if (lstate != NULL) { 9511 xpt_print_path(ccb->ccb_h.path); 9512 printf("Lun already enabled\n"); 9513 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9514 return; 9515 } 9516 9517 if (cel->grp6_len != 0 9518 || cel->grp7_len != 0) { 9519 /* 9520 * Don't (yet?) support vendor 9521 * specific commands. 9522 */ 9523 ccb->ccb_h.status = CAM_REQ_INVALID; 9524 printf("Non-zero Group Codes\n"); 9525 return; 9526 } 9527 9528 /* 9529 * Seems to be okay. 9530 * Setup our data structures. 9531 */ 9532 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9533 tstate = ahd_alloc_tstate(ahd, target, channel); 9534 if (tstate == NULL) { 9535 xpt_print_path(ccb->ccb_h.path); 9536 printf("Couldn't allocate tstate\n"); 9537 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9538 return; 9539 } 9540 } 9541 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9542 if (lstate == NULL) { 9543 xpt_print_path(ccb->ccb_h.path); 9544 printf("Couldn't allocate lstate\n"); 9545 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9546 return; 9547 } 9548 memset(lstate, 0, sizeof(*lstate)); 9549 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9550 xpt_path_path_id(ccb->ccb_h.path), 9551 xpt_path_target_id(ccb->ccb_h.path), 9552 xpt_path_lun_id(ccb->ccb_h.path)); 9553 if (status != CAM_REQ_CMP) { 9554 free(lstate, M_DEVBUF); 9555 xpt_print_path(ccb->ccb_h.path); 9556 printf("Couldn't allocate path\n"); 9557 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9558 return; 9559 } 9560 SLIST_INIT(&lstate->accept_tios); 9561 SLIST_INIT(&lstate->immed_notifies); 9562 ahd_lock(ahd, &s); 9563 ahd_pause(ahd); 9564 if (target != CAM_TARGET_WILDCARD) { 9565 tstate->enabled_luns[lun] = lstate; 9566 ahd->enabled_luns++; 9567 9568 if ((ahd->features & AHD_MULTI_TID) != 0) { 9569 u_int targid_mask; 9570 9571 targid_mask = ahd_inw(ahd, TARGID); 9572 targid_mask |= target_mask; 9573 ahd_outw(ahd, TARGID, targid_mask); 9574 ahd_update_scsiid(ahd, targid_mask); 9575 } else { 9576 u_int our_id; 9577 char channel; 9578 9579 channel = SIM_CHANNEL(ahd, sim); 9580 our_id = SIM_SCSI_ID(ahd, sim); 9581 9582 /* 9583 * This can only happen if selections 9584 * are not enabled 9585 */ 9586 if (target != our_id) { 9587 u_int sblkctl; 9588 char cur_channel; 9589 int swap; 9590 9591 sblkctl = ahd_inb(ahd, SBLKCTL); 9592 cur_channel = (sblkctl & SELBUSB) 9593 ? 'B' : 'A'; 9594 if ((ahd->features & AHD_TWIN) == 0) 9595 cur_channel = 'A'; 9596 swap = cur_channel != channel; 9597 ahd->our_id = target; 9598 9599 if (swap) 9600 ahd_outb(ahd, SBLKCTL, 9601 sblkctl ^ SELBUSB); 9602 9603 ahd_outb(ahd, SCSIID, target); 9604 9605 if (swap) 9606 ahd_outb(ahd, SBLKCTL, sblkctl); 9607 } 9608 } 9609 } else 9610 ahd->black_hole = lstate; 9611 /* Allow select-in operations */ 9612 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9613 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9614 scsiseq1 |= ENSELI; 9615 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9616 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9617 scsiseq1 |= ENSELI; 9618 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9619 } 9620 ahd_unpause(ahd); 9621 ahd_unlock(ahd, &s); 9622 ccb->ccb_h.status = CAM_REQ_CMP; 9623 xpt_print_path(ccb->ccb_h.path); 9624 printf("Lun now enabled for target mode\n"); 9625 } else { 9626 struct scb *scb; 9627 int i, empty; 9628 9629 if (lstate == NULL) { 9630 ccb->ccb_h.status = CAM_LUN_INVALID; 9631 return; 9632 } 9633 9634 ahd_lock(ahd, &s); 9635 9636 ccb->ccb_h.status = CAM_REQ_CMP; 9637 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9638 struct ccb_hdr *ccbh; 9639 9640 ccbh = &scb->io_ctx->ccb_h; 9641 if (ccbh->func_code == XPT_CONT_TARGET_IO 9642 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9643 printf("CTIO pending\n"); 9644 ccb->ccb_h.status = CAM_REQ_INVALID; 9645 ahd_unlock(ahd, &s); 9646 return; 9647 } 9648 } 9649 9650 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9651 printf("ATIOs pending\n"); 9652 ccb->ccb_h.status = CAM_REQ_INVALID; 9653 } 9654 9655 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9656 printf("INOTs pending\n"); 9657 ccb->ccb_h.status = CAM_REQ_INVALID; 9658 } 9659 9660 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9661 ahd_unlock(ahd, &s); 9662 return; 9663 } 9664 9665 xpt_print_path(ccb->ccb_h.path); 9666 printf("Target mode disabled\n"); 9667 xpt_free_path(lstate->path); 9668 free(lstate, M_DEVBUF); 9669 9670 ahd_pause(ahd); 9671 /* Can we clean up the target too? */ 9672 if (target != CAM_TARGET_WILDCARD) { 9673 tstate->enabled_luns[lun] = NULL; 9674 ahd->enabled_luns--; 9675 for (empty = 1, i = 0; i < 8; i++) 9676 if (tstate->enabled_luns[i] != NULL) { 9677 empty = 0; 9678 break; 9679 } 9680 9681 if (empty) { 9682 ahd_free_tstate(ahd, target, channel, 9683 /*force*/FALSE); 9684 if (ahd->features & AHD_MULTI_TID) { 9685 u_int targid_mask; 9686 9687 targid_mask = ahd_inw(ahd, TARGID); 9688 targid_mask &= ~target_mask; 9689 ahd_outw(ahd, TARGID, targid_mask); 9690 ahd_update_scsiid(ahd, targid_mask); 9691 } 9692 } 9693 } else { 9694 9695 ahd->black_hole = NULL; 9696 9697 /* 9698 * We can't allow selections without 9699 * our black hole device. 9700 */ 9701 empty = TRUE; 9702 } 9703 if (ahd->enabled_luns == 0) { 9704 /* Disallow select-in */ 9705 u_int scsiseq1; 9706 9707 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9708 scsiseq1 &= ~ENSELI; 9709 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9710 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9711 scsiseq1 &= ~ENSELI; 9712 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9713 9714 if ((ahd->features & AHD_MULTIROLE) == 0) { 9715 printf("Configuring Initiator Mode\n"); 9716 ahd->flags &= ~AHD_TARGETROLE; 9717 ahd->flags |= AHD_INITIATORROLE; 9718 ahd_pause(ahd); 9719 ahd_loadseq(ahd); 9720 ahd_restart(ahd); 9721 /* 9722 * Unpaused. The extra unpause 9723 * that follows is harmless. 9724 */ 9725 } 9726 } 9727 ahd_unpause(ahd); 9728 ahd_unlock(ahd, &s); 9729 } 9730 #endif 9731 } 9732 9733 static void 9734 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9735 { 9736 #if NOT_YET 9737 u_int scsiid_mask; 9738 u_int scsiid; 9739 9740 if ((ahd->features & AHD_MULTI_TID) == 0) 9741 panic("ahd_update_scsiid called on non-multitid unit\n"); 9742 9743 /* 9744 * Since we will rely on the TARGID mask 9745 * for selection enables, ensure that OID 9746 * in SCSIID is not set to some other ID 9747 * that we don't want to allow selections on. 9748 */ 9749 if ((ahd->features & AHD_ULTRA2) != 0) 9750 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9751 else 9752 scsiid = ahd_inb(ahd, SCSIID); 9753 scsiid_mask = 0x1 << (scsiid & OID); 9754 if ((targid_mask & scsiid_mask) == 0) { 9755 u_int our_id; 9756 9757 /* ffs counts from 1 */ 9758 our_id = ffs(targid_mask); 9759 if (our_id == 0) 9760 our_id = ahd->our_id; 9761 else 9762 our_id--; 9763 scsiid &= TID; 9764 scsiid |= our_id; 9765 } 9766 if ((ahd->features & AHD_ULTRA2) != 0) 9767 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9768 else 9769 ahd_outb(ahd, SCSIID, scsiid); 9770 #endif 9771 } 9772 9773 void 9774 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9775 { 9776 struct target_cmd *cmd; 9777 9778 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9779 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9780 9781 /* 9782 * Only advance through the queue if we 9783 * have the resources to process the command. 9784 */ 9785 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9786 break; 9787 9788 cmd->cmd_valid = 0; 9789 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 9790 ahd->shared_data_map.dmamap, 9791 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9792 sizeof(struct target_cmd), 9793 BUS_DMASYNC_PREREAD); 9794 ahd->tqinfifonext++; 9795 9796 /* 9797 * Lazily update our position in the target mode incoming 9798 * command queue as seen by the sequencer. 9799 */ 9800 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9801 u_int hs_mailbox; 9802 9803 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9804 hs_mailbox &= ~HOST_TQINPOS; 9805 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9806 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9807 } 9808 } 9809 } 9810 9811 static int 9812 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9813 { 9814 struct ahd_tmode_tstate *tstate; 9815 struct ahd_tmode_lstate *lstate; 9816 struct ccb_accept_tio *atio; 9817 uint8_t *byte; 9818 int initiator; 9819 int target; 9820 int lun; 9821 9822 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9823 target = SCSIID_OUR_ID(cmd->scsiid); 9824 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9825 9826 byte = cmd->bytes; 9827 tstate = ahd->enabled_targets[target]; 9828 lstate = NULL; 9829 if (tstate != NULL) 9830 lstate = tstate->enabled_luns[lun]; 9831 9832 /* 9833 * Commands for disabled luns go to the black hole driver. 9834 */ 9835 if (lstate == NULL) 9836 lstate = ahd->black_hole; 9837 9838 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9839 if (atio == NULL) { 9840 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9841 /* 9842 * Wait for more ATIOs from the peripheral driver for this lun. 9843 */ 9844 return (1); 9845 } else 9846 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9847 #ifdef AHD_DEBUG 9848 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9849 printf("Incoming command from %d for %d:%d%s\n", 9850 initiator, target, lun, 9851 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9852 #endif 9853 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9854 9855 if (lstate == ahd->black_hole) { 9856 /* Fill in the wildcards */ 9857 atio->ccb_h.target_id = target; 9858 atio->ccb_h.target_lun = lun; 9859 } 9860 9861 /* 9862 * Package it up and send it off to 9863 * whomever has this lun enabled. 9864 */ 9865 atio->sense_len = 0; 9866 atio->init_id = initiator; 9867 if (byte[0] != 0xFF) { 9868 /* Tag was included */ 9869 atio->tag_action = *byte++; 9870 atio->tag_id = *byte++; 9871 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9872 } else { 9873 atio->ccb_h.flags = 0; 9874 } 9875 byte++; 9876 9877 /* Okay. Now determine the cdb size based on the command code */ 9878 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9879 case 0: 9880 atio->cdb_len = 6; 9881 break; 9882 case 1: 9883 case 2: 9884 atio->cdb_len = 10; 9885 break; 9886 case 4: 9887 atio->cdb_len = 16; 9888 break; 9889 case 5: 9890 atio->cdb_len = 12; 9891 break; 9892 case 3: 9893 default: 9894 /* Only copy the opcode. */ 9895 atio->cdb_len = 1; 9896 printf("Reserved or VU command code type encountered\n"); 9897 break; 9898 } 9899 9900 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9901 9902 atio->ccb_h.status |= CAM_CDB_RECVD; 9903 9904 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9905 /* 9906 * We weren't allowed to disconnect. 9907 * We're hanging on the bus until a 9908 * continue target I/O comes in response 9909 * to this accept tio. 9910 */ 9911 #ifdef AHD_DEBUG 9912 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9913 printf("Received Immediate Command %d:%d:%d - %p\n", 9914 initiator, target, lun, ahd->pending_device); 9915 #endif 9916 ahd->pending_device = lstate; 9917 ahd_freeze_ccb((union ccb *)atio); 9918 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9919 } 9920 xpt_done((union ccb*)atio); 9921 return (0); 9922 } 9923 9924 #endif 9925