1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 /* 3 * Copyright (C) 2024 Amlogic, Inc. All rights reserved 4 * Author: Yiting Deng <yiting.deng@amlogic.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/rtc.h> 15 #include <linux/time64.h> 16 17 /* rtc oscillator rate */ 18 #define OSC_32K 32768 19 #define OSC_24M 24000000 20 21 #define RTC_CTRL (0x0 << 2) /* Control RTC */ 22 #define RTC_ALRM0_EN BIT(0) 23 #define RTC_OSC_SEL BIT(8) 24 #define RTC_ENABLE BIT(12) 25 26 #define RTC_COUNTER_REG (0x1 << 2) /* Program RTC counter initial value */ 27 28 #define RTC_ALARM0_REG (0x2 << 2) /* Program RTC alarm0 value */ 29 30 #define RTC_SEC_ADJUST_REG (0x6 << 2) /* Control second-based timing adjustment */ 31 #define RTC_MATCH_COUNTER GENMASK(18, 0) 32 #define RTC_SEC_ADJUST_CTRL GENMASK(20, 19) 33 #define RTC_ADJ_VALID BIT(23) 34 35 #define RTC_INT_MASK (0x8 << 2) /* RTC interrupt mask */ 36 #define RTC_ALRM0_IRQ_MSK BIT(0) 37 38 #define RTC_INT_CLR (0x9 << 2) /* Clear RTC interrupt */ 39 #define RTC_ALRM0_IRQ_CLR BIT(0) 40 41 #define RTC_OSCIN_CTRL0 (0xa << 2) /* Control RTC clk from 24M */ 42 #define RTC_OSCIN_CTRL1 (0xb << 2) /* Control RTC clk from 24M */ 43 #define RTC_OSCIN_IN_EN BIT(31) 44 #define RTC_OSCIN_OUT_CFG GENMASK(29, 28) 45 #define RTC_OSCIN_OUT_N0M0 GENMASK(11, 0) 46 #define RTC_OSCIN_OUT_N1M1 GENMASK(23, 12) 47 48 #define RTC_INT_STATUS (0xc << 2) /* RTC interrupt status */ 49 #define RTC_ALRM0_IRQ_STATUS BIT(0) 50 51 #define RTC_REAL_TIME (0xd << 2) /* RTC time value */ 52 53 #define RTC_OSCIN_OUT_32K_N0 0x2dc 54 #define RTC_OSCIN_OUT_32K_N1 0x2db 55 #define RTC_OSCIN_OUT_32K_M0 0x1 56 #define RTC_OSCIN_OUT_32K_M1 0x2 57 58 #define RTC_SWALLOW_SECOND 0x2 59 #define RTC_INSERT_SECOND 0x3 60 61 struct aml_rtc_config { 62 bool gray_stored; 63 }; 64 65 struct aml_rtc_data { 66 struct regmap *map; 67 struct rtc_device *rtc_dev; 68 int irq; 69 struct clk *rtc_clk; 70 struct clk *sys_clk; 71 int rtc_enabled; 72 const struct aml_rtc_config *config; 73 }; 74 75 static inline u32 gray_to_binary(u32 gray) 76 { 77 u32 bcd = gray; 78 int size = sizeof(bcd) * 8; 79 int i; 80 81 for (i = 0; (1 << i) < size; i++) 82 bcd ^= bcd >> (1 << i); 83 84 return bcd; 85 } 86 87 static inline u32 binary_to_gray(u32 bcd) 88 { 89 return bcd ^ (bcd >> 1); 90 } 91 92 static int aml_rtc_read_time(struct device *dev, struct rtc_time *tm) 93 { 94 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 95 u32 time_sec; 96 97 /* if RTC disabled, read time failed */ 98 if (!rtc->rtc_enabled) 99 return -EINVAL; 100 101 regmap_read(rtc->map, RTC_REAL_TIME, &time_sec); 102 if (rtc->config->gray_stored) 103 time_sec = gray_to_binary(time_sec); 104 rtc_time64_to_tm(time_sec, tm); 105 dev_dbg(dev, "%s: read time = %us\n", __func__, time_sec); 106 107 return 0; 108 } 109 110 static int aml_rtc_set_time(struct device *dev, struct rtc_time *tm) 111 { 112 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 113 u32 time_sec; 114 115 /* if RTC disabled, first enable it */ 116 if (!rtc->rtc_enabled) { 117 regmap_write_bits(rtc->map, RTC_CTRL, RTC_ENABLE, RTC_ENABLE); 118 usleep_range(100, 200); 119 rtc->rtc_enabled = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ENABLE); 120 if (!rtc->rtc_enabled) 121 return -EINVAL; 122 } 123 124 time_sec = rtc_tm_to_time64(tm); 125 if (rtc->config->gray_stored) 126 time_sec = binary_to_gray(time_sec); 127 regmap_write(rtc->map, RTC_COUNTER_REG, time_sec); 128 dev_dbg(dev, "%s: set time = %us\n", __func__, time_sec); 129 130 return 0; 131 } 132 133 static int aml_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 134 { 135 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 136 time64_t alarm_sec; 137 138 /* if RTC disabled, set alarm failed */ 139 if (!rtc->rtc_enabled) 140 return -EINVAL; 141 142 regmap_update_bits(rtc->map, RTC_CTRL, 143 RTC_ALRM0_EN, RTC_ALRM0_EN); 144 regmap_update_bits(rtc->map, RTC_INT_MASK, 145 RTC_ALRM0_IRQ_MSK, 0); 146 147 alarm_sec = rtc_tm_to_time64(&alarm->time); 148 if (rtc->config->gray_stored) 149 alarm_sec = binary_to_gray(alarm_sec); 150 regmap_write(rtc->map, RTC_ALARM0_REG, alarm_sec); 151 152 dev_dbg(dev, "%s: alarm->enabled=%d alarm_set=%llds\n", __func__, 153 alarm->enabled, alarm_sec); 154 155 return 0; 156 } 157 158 static int aml_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 159 { 160 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 161 u32 alarm_sec; 162 int alarm_enable; 163 int alarm_mask; 164 165 /* if RTC disabled, read alarm failed */ 166 if (!rtc->rtc_enabled) 167 return -EINVAL; 168 169 regmap_read(rtc->map, RTC_ALARM0_REG, &alarm_sec); 170 if (rtc->config->gray_stored) 171 alarm_sec = gray_to_binary(alarm_sec); 172 rtc_time64_to_tm(alarm_sec, &alarm->time); 173 174 alarm_enable = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN); 175 alarm_mask = regmap_test_bits(rtc->map, RTC_INT_MASK, RTC_ALRM0_IRQ_MSK); 176 alarm->enabled = (alarm_enable && !alarm_mask) ? 1 : 0; 177 dev_dbg(dev, "%s: alarm->enabled=%d alarm=%us\n", __func__, 178 alarm->enabled, alarm_sec); 179 180 return 0; 181 } 182 183 static int aml_rtc_read_offset(struct device *dev, long *offset) 184 { 185 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 186 u32 reg_val; 187 long val; 188 int sign, match_counter, enable; 189 190 /* if RTC disabled, read offset failed */ 191 if (!rtc->rtc_enabled) 192 return -EINVAL; 193 194 regmap_read(rtc->map, RTC_SEC_ADJUST_REG, ®_val); 195 enable = FIELD_GET(RTC_ADJ_VALID, reg_val); 196 if (!enable) { 197 val = 0; 198 } else { 199 sign = FIELD_GET(RTC_SEC_ADJUST_CTRL, reg_val); 200 match_counter = FIELD_GET(RTC_MATCH_COUNTER, reg_val); 201 val = 1000000000 / (match_counter + 1); 202 if (sign == RTC_SWALLOW_SECOND) 203 val = -val; 204 } 205 *offset = val; 206 207 return 0; 208 } 209 210 static int aml_rtc_set_offset(struct device *dev, long offset) 211 { 212 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 213 int sign = 0; 214 int match_counter = 0; 215 int enable = 0; 216 u32 reg_val; 217 218 /* if RTC disabled, set offset failed */ 219 if (!rtc->rtc_enabled) 220 return -EINVAL; 221 222 if (offset) { 223 enable = 1; 224 sign = offset < 0 ? RTC_SWALLOW_SECOND : RTC_INSERT_SECOND; 225 match_counter = 1000000000 / abs(offset) - 1; 226 if (match_counter < 0 || match_counter > RTC_MATCH_COUNTER) 227 return -EINVAL; 228 } 229 230 reg_val = FIELD_PREP(RTC_ADJ_VALID, enable) | 231 FIELD_PREP(RTC_SEC_ADJUST_CTRL, sign) | 232 FIELD_PREP(RTC_MATCH_COUNTER, match_counter); 233 regmap_write(rtc->map, RTC_SEC_ADJUST_REG, reg_val); 234 235 return 0; 236 } 237 238 static int aml_rtc_alarm_enable(struct device *dev, unsigned int enabled) 239 { 240 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 241 242 if (enabled) { 243 regmap_update_bits(rtc->map, RTC_CTRL, 244 RTC_ALRM0_EN, RTC_ALRM0_EN); 245 regmap_update_bits(rtc->map, RTC_INT_MASK, 246 RTC_ALRM0_IRQ_MSK, 0); 247 } else { 248 regmap_update_bits(rtc->map, RTC_INT_MASK, 249 RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); 250 regmap_update_bits(rtc->map, RTC_CTRL, 251 RTC_ALRM0_EN, 0); 252 } 253 254 return 0; 255 } 256 257 static const struct rtc_class_ops aml_rtc_ops = { 258 .read_time = aml_rtc_read_time, 259 .set_time = aml_rtc_set_time, 260 .read_alarm = aml_rtc_read_alarm, 261 .set_alarm = aml_rtc_set_alarm, 262 .alarm_irq_enable = aml_rtc_alarm_enable, 263 .read_offset = aml_rtc_read_offset, 264 .set_offset = aml_rtc_set_offset, 265 }; 266 267 static irqreturn_t aml_rtc_handler(int irq, void *data) 268 { 269 struct aml_rtc_data *rtc = (struct aml_rtc_data *)data; 270 271 regmap_write(rtc->map, RTC_ALARM0_REG, 0); 272 regmap_write(rtc->map, RTC_INT_CLR, RTC_ALRM0_IRQ_STATUS); 273 274 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); 275 276 return IRQ_HANDLED; 277 } 278 279 static void aml_rtc_init(struct aml_rtc_data *rtc) 280 { 281 u32 reg_val = 0; 282 283 rtc->rtc_enabled = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ENABLE); 284 if (!rtc->rtc_enabled) { 285 if (clk_get_rate(rtc->rtc_clk) == OSC_24M) { 286 /* select 24M oscillator */ 287 regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, RTC_OSC_SEL); 288 289 /* 290 * Set RTC oscillator to freq_out to freq_in/((N0*M0+N1*M1)/(M0+M1)) 291 * Enable clock_in gate of oscillator 24MHz 292 * Set N0 to 733, N1 to 732 293 */ 294 reg_val = FIELD_PREP(RTC_OSCIN_IN_EN, 1) 295 | FIELD_PREP(RTC_OSCIN_OUT_CFG, 1) 296 | FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_N0) 297 | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_N1); 298 regmap_write_bits(rtc->map, RTC_OSCIN_CTRL0, RTC_OSCIN_IN_EN 299 | RTC_OSCIN_OUT_CFG | RTC_OSCIN_OUT_N0M0 300 | RTC_OSCIN_OUT_N1M1, reg_val); 301 302 /* Set M0 to 2, M1 to 3, so freq_out = 32768 Hz*/ 303 reg_val = FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_M0) 304 | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_M1); 305 regmap_write_bits(rtc->map, RTC_OSCIN_CTRL1, RTC_OSCIN_OUT_N0M0 306 | RTC_OSCIN_OUT_N1M1, reg_val); 307 } else { 308 /* select 32K oscillator */ 309 regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, 0); 310 } 311 } 312 regmap_write_bits(rtc->map, RTC_INT_MASK, 313 RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); 314 regmap_write_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN, 0); 315 } 316 317 static int aml_rtc_probe(struct platform_device *pdev) 318 { 319 struct device *dev = &pdev->dev; 320 struct aml_rtc_data *rtc; 321 void __iomem *base; 322 int ret = 0; 323 324 const struct regmap_config aml_rtc_regmap_config = { 325 .reg_bits = 32, 326 .val_bits = 32, 327 .reg_stride = 4, 328 .max_register = RTC_REAL_TIME, 329 }; 330 331 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); 332 if (!rtc) 333 return -ENOMEM; 334 335 rtc->config = of_device_get_match_data(dev); 336 if (!rtc->config) 337 return -ENODEV; 338 339 base = devm_platform_ioremap_resource(pdev, 0); 340 if (IS_ERR(base)) 341 return dev_err_probe(dev, PTR_ERR(base), "resource ioremap failed\n"); 342 343 rtc->map = devm_regmap_init_mmio(dev, base, &aml_rtc_regmap_config); 344 if (IS_ERR(rtc->map)) 345 return dev_err_probe(dev, PTR_ERR(rtc->map), "regmap init failed\n"); 346 347 rtc->irq = platform_get_irq(pdev, 0); 348 if (rtc->irq < 0) 349 return rtc->irq; 350 351 rtc->rtc_clk = devm_clk_get(dev, "osc"); 352 if (IS_ERR(rtc->rtc_clk)) 353 return dev_err_probe(dev, PTR_ERR(rtc->rtc_clk), 354 "failed to find rtc clock\n"); 355 if (clk_get_rate(rtc->rtc_clk) != OSC_32K && clk_get_rate(rtc->rtc_clk) != OSC_24M) 356 return dev_err_probe(dev, -EINVAL, "Invalid clock configuration\n"); 357 358 rtc->sys_clk = devm_clk_get_enabled(dev, "sys"); 359 if (IS_ERR(rtc->sys_clk)) 360 return dev_err_probe(dev, PTR_ERR(rtc->sys_clk), 361 "failed to get_enable rtc sys clk\n"); 362 aml_rtc_init(rtc); 363 364 device_init_wakeup(dev, true); 365 platform_set_drvdata(pdev, rtc); 366 367 rtc->rtc_dev = devm_rtc_allocate_device(dev); 368 if (IS_ERR(rtc->rtc_dev)) { 369 ret = PTR_ERR(rtc->rtc_dev); 370 goto err_clk; 371 } 372 373 ret = devm_request_irq(dev, rtc->irq, aml_rtc_handler, 374 IRQF_ONESHOT, "aml-rtc alarm", rtc); 375 if (ret) { 376 dev_err_probe(dev, ret, "IRQ%d request failed, ret = %d\n", 377 rtc->irq, ret); 378 goto err_clk; 379 } 380 381 rtc->rtc_dev->ops = &aml_rtc_ops; 382 rtc->rtc_dev->range_min = 0; 383 rtc->rtc_dev->range_max = U32_MAX; 384 385 ret = devm_rtc_register_device(rtc->rtc_dev); 386 if (ret) { 387 dev_err_probe(&pdev->dev, ret, "Failed to register RTC device: %d\n", ret); 388 goto err_clk; 389 } 390 391 return 0; 392 err_clk: 393 clk_disable_unprepare(rtc->sys_clk); 394 device_init_wakeup(dev, false); 395 396 return ret; 397 } 398 399 #ifdef CONFIG_PM_SLEEP 400 static int aml_rtc_suspend(struct device *dev) 401 { 402 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 403 404 if (device_may_wakeup(dev)) 405 enable_irq_wake(rtc->irq); 406 407 return 0; 408 } 409 410 static int aml_rtc_resume(struct device *dev) 411 { 412 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 413 414 if (device_may_wakeup(dev)) 415 disable_irq_wake(rtc->irq); 416 417 return 0; 418 } 419 #endif 420 421 static SIMPLE_DEV_PM_OPS(aml_rtc_pm_ops, 422 aml_rtc_suspend, aml_rtc_resume); 423 424 static void aml_rtc_remove(struct platform_device *pdev) 425 { 426 struct aml_rtc_data *rtc = dev_get_drvdata(&pdev->dev); 427 428 clk_disable_unprepare(rtc->sys_clk); 429 device_init_wakeup(&pdev->dev, false); 430 } 431 432 static const struct aml_rtc_config a5_rtc_config = { 433 }; 434 435 static const struct aml_rtc_config a4_rtc_config = { 436 .gray_stored = true, 437 }; 438 439 static const struct of_device_id aml_rtc_device_id[] = { 440 { 441 .compatible = "amlogic,a4-rtc", 442 .data = &a4_rtc_config, 443 }, 444 { 445 .compatible = "amlogic,a5-rtc", 446 .data = &a5_rtc_config, 447 }, 448 { } 449 }; 450 MODULE_DEVICE_TABLE(of, aml_rtc_device_id); 451 452 static struct platform_driver aml_rtc_driver = { 453 .probe = aml_rtc_probe, 454 .remove = aml_rtc_remove, 455 .driver = { 456 .name = "aml-rtc", 457 .pm = &aml_rtc_pm_ops, 458 .of_match_table = aml_rtc_device_id, 459 }, 460 }; 461 462 module_platform_driver(aml_rtc_driver); 463 MODULE_DESCRIPTION("Amlogic RTC driver"); 464 MODULE_AUTHOR("Yiting Deng <yiting.deng@amlogic.com>"); 465 MODULE_LICENSE("GPL"); 466