1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 /* 3 * Copyright (C) 2024 Amlogic, Inc. All rights reserved 4 * Author: Yiting Deng <yiting.deng@amlogic.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/rtc.h> 15 #include <linux/time64.h> 16 17 /* rtc oscillator rate */ 18 #define OSC_32K 32768 19 #define OSC_24M 24000000 20 21 #define RTC_CTRL (0x0 << 2) /* Control RTC */ 22 #define RTC_ALRM0_EN BIT(0) 23 #define RTC_OSC_SEL BIT(8) 24 #define RTC_ENABLE BIT(12) 25 26 #define RTC_COUNTER_REG (0x1 << 2) /* Program RTC counter initial value */ 27 28 #define RTC_ALARM0_REG (0x2 << 2) /* Program RTC alarm0 value */ 29 30 #define RTC_SEC_ADJUST_REG (0x6 << 2) /* Control second-based timing adjustment */ 31 #define RTC_MATCH_COUNTER GENMASK(18, 0) 32 #define RTC_SEC_ADJUST_CTRL GENMASK(20, 19) 33 #define RTC_ADJ_VALID BIT(23) 34 35 #define RTC_INT_MASK (0x8 << 2) /* RTC interrupt mask */ 36 #define RTC_ALRM0_IRQ_MSK BIT(0) 37 38 #define RTC_INT_CLR (0x9 << 2) /* Clear RTC interrupt */ 39 #define RTC_ALRM0_IRQ_CLR BIT(0) 40 41 #define RTC_OSCIN_CTRL0 (0xa << 2) /* Control RTC clk from 24M */ 42 #define RTC_OSCIN_CTRL1 (0xb << 2) /* Control RTC clk from 24M */ 43 #define RTC_OSCIN_IN_EN BIT(31) 44 #define RTC_OSCIN_OUT_CFG GENMASK(29, 28) 45 #define RTC_OSCIN_OUT_N0M0 GENMASK(11, 0) 46 #define RTC_OSCIN_OUT_N1M1 GENMASK(23, 12) 47 48 #define RTC_INT_STATUS (0xc << 2) /* RTC interrupt status */ 49 #define RTC_ALRM0_IRQ_STATUS BIT(0) 50 51 #define RTC_REAL_TIME (0xd << 2) /* RTC time value */ 52 53 #define RTC_OSCIN_OUT_32K_N0 0x2dc 54 #define RTC_OSCIN_OUT_32K_N1 0x2db 55 #define RTC_OSCIN_OUT_32K_M0 0x1 56 #define RTC_OSCIN_OUT_32K_M1 0x2 57 58 #define RTC_SWALLOW_SECOND 0x2 59 #define RTC_INSERT_SECOND 0x3 60 61 struct aml_rtc_config { 62 bool gray_stored; 63 }; 64 65 struct aml_rtc_data { 66 struct regmap *map; 67 struct rtc_device *rtc_dev; 68 int irq; 69 struct clk *rtc_clk; 70 struct clk *sys_clk; 71 int rtc_enabled; 72 const struct aml_rtc_config *config; 73 }; 74 75 static const struct regmap_config aml_rtc_regmap_config = { 76 .reg_bits = 32, 77 .val_bits = 32, 78 .reg_stride = 4, 79 .max_register = RTC_REAL_TIME, 80 }; 81 82 static inline u32 gray_to_binary(u32 gray) 83 { 84 u32 bcd = gray; 85 int size = sizeof(bcd) * 8; 86 int i; 87 88 for (i = 0; (1 << i) < size; i++) 89 bcd ^= bcd >> (1 << i); 90 91 return bcd; 92 } 93 94 static inline u32 binary_to_gray(u32 bcd) 95 { 96 return bcd ^ (bcd >> 1); 97 } 98 99 static int aml_rtc_read_time(struct device *dev, struct rtc_time *tm) 100 { 101 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 102 u32 time_sec; 103 104 /* if RTC disabled, read time failed */ 105 if (!rtc->rtc_enabled) 106 return -EINVAL; 107 108 regmap_read(rtc->map, RTC_REAL_TIME, &time_sec); 109 if (rtc->config->gray_stored) 110 time_sec = gray_to_binary(time_sec); 111 rtc_time64_to_tm(time_sec, tm); 112 dev_dbg(dev, "%s: read time = %us\n", __func__, time_sec); 113 114 return 0; 115 } 116 117 static int aml_rtc_set_time(struct device *dev, struct rtc_time *tm) 118 { 119 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 120 u32 time_sec; 121 122 /* if RTC disabled, first enable it */ 123 if (!rtc->rtc_enabled) { 124 regmap_write_bits(rtc->map, RTC_CTRL, RTC_ENABLE, RTC_ENABLE); 125 usleep_range(100, 200); 126 rtc->rtc_enabled = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ENABLE); 127 if (!rtc->rtc_enabled) 128 return -EINVAL; 129 } 130 131 time_sec = rtc_tm_to_time64(tm); 132 if (rtc->config->gray_stored) 133 time_sec = binary_to_gray(time_sec); 134 regmap_write(rtc->map, RTC_COUNTER_REG, time_sec); 135 dev_dbg(dev, "%s: set time = %us\n", __func__, time_sec); 136 137 return 0; 138 } 139 140 static int aml_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 141 { 142 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 143 time64_t alarm_sec; 144 145 /* if RTC disabled, set alarm failed */ 146 if (!rtc->rtc_enabled) 147 return -EINVAL; 148 149 regmap_update_bits(rtc->map, RTC_CTRL, 150 RTC_ALRM0_EN, RTC_ALRM0_EN); 151 regmap_update_bits(rtc->map, RTC_INT_MASK, 152 RTC_ALRM0_IRQ_MSK, 0); 153 154 alarm_sec = rtc_tm_to_time64(&alarm->time); 155 if (rtc->config->gray_stored) 156 alarm_sec = binary_to_gray(alarm_sec); 157 regmap_write(rtc->map, RTC_ALARM0_REG, alarm_sec); 158 159 dev_dbg(dev, "%s: alarm->enabled=%d alarm_set=%llds\n", __func__, 160 alarm->enabled, alarm_sec); 161 162 return 0; 163 } 164 165 static int aml_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 166 { 167 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 168 u32 alarm_sec; 169 int alarm_enable; 170 int alarm_mask; 171 172 /* if RTC disabled, read alarm failed */ 173 if (!rtc->rtc_enabled) 174 return -EINVAL; 175 176 regmap_read(rtc->map, RTC_ALARM0_REG, &alarm_sec); 177 if (rtc->config->gray_stored) 178 alarm_sec = gray_to_binary(alarm_sec); 179 rtc_time64_to_tm(alarm_sec, &alarm->time); 180 181 alarm_enable = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN); 182 alarm_mask = regmap_test_bits(rtc->map, RTC_INT_MASK, RTC_ALRM0_IRQ_MSK); 183 alarm->enabled = (alarm_enable && !alarm_mask) ? 1 : 0; 184 dev_dbg(dev, "%s: alarm->enabled=%d alarm=%us\n", __func__, 185 alarm->enabled, alarm_sec); 186 187 return 0; 188 } 189 190 static int aml_rtc_read_offset(struct device *dev, long *offset) 191 { 192 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 193 u32 reg_val; 194 long val; 195 int sign, match_counter, enable; 196 197 /* if RTC disabled, read offset failed */ 198 if (!rtc->rtc_enabled) 199 return -EINVAL; 200 201 regmap_read(rtc->map, RTC_SEC_ADJUST_REG, ®_val); 202 enable = FIELD_GET(RTC_ADJ_VALID, reg_val); 203 if (!enable) { 204 val = 0; 205 } else { 206 sign = FIELD_GET(RTC_SEC_ADJUST_CTRL, reg_val); 207 match_counter = FIELD_GET(RTC_MATCH_COUNTER, reg_val); 208 val = 1000000000 / (match_counter + 1); 209 if (sign == RTC_SWALLOW_SECOND) 210 val = -val; 211 } 212 *offset = val; 213 214 return 0; 215 } 216 217 static int aml_rtc_set_offset(struct device *dev, long offset) 218 { 219 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 220 int sign = 0; 221 int match_counter = 0; 222 int enable = 0; 223 u32 reg_val; 224 225 /* if RTC disabled, set offset failed */ 226 if (!rtc->rtc_enabled) 227 return -EINVAL; 228 229 if (offset) { 230 enable = 1; 231 sign = offset < 0 ? RTC_SWALLOW_SECOND : RTC_INSERT_SECOND; 232 match_counter = 1000000000 / abs(offset) - 1; 233 if (match_counter < 0 || match_counter > RTC_MATCH_COUNTER) 234 return -EINVAL; 235 } 236 237 reg_val = FIELD_PREP(RTC_ADJ_VALID, enable) | 238 FIELD_PREP(RTC_SEC_ADJUST_CTRL, sign) | 239 FIELD_PREP(RTC_MATCH_COUNTER, match_counter); 240 regmap_write(rtc->map, RTC_SEC_ADJUST_REG, reg_val); 241 242 return 0; 243 } 244 245 static int aml_rtc_alarm_enable(struct device *dev, unsigned int enabled) 246 { 247 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 248 249 if (enabled) { 250 regmap_update_bits(rtc->map, RTC_CTRL, 251 RTC_ALRM0_EN, RTC_ALRM0_EN); 252 regmap_update_bits(rtc->map, RTC_INT_MASK, 253 RTC_ALRM0_IRQ_MSK, 0); 254 } else { 255 regmap_update_bits(rtc->map, RTC_INT_MASK, 256 RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); 257 regmap_update_bits(rtc->map, RTC_CTRL, 258 RTC_ALRM0_EN, 0); 259 } 260 261 return 0; 262 } 263 264 static const struct rtc_class_ops aml_rtc_ops = { 265 .read_time = aml_rtc_read_time, 266 .set_time = aml_rtc_set_time, 267 .read_alarm = aml_rtc_read_alarm, 268 .set_alarm = aml_rtc_set_alarm, 269 .alarm_irq_enable = aml_rtc_alarm_enable, 270 .read_offset = aml_rtc_read_offset, 271 .set_offset = aml_rtc_set_offset, 272 }; 273 274 static irqreturn_t aml_rtc_handler(int irq, void *data) 275 { 276 struct aml_rtc_data *rtc = (struct aml_rtc_data *)data; 277 278 regmap_write(rtc->map, RTC_ALARM0_REG, 0); 279 regmap_write(rtc->map, RTC_INT_CLR, RTC_ALRM0_IRQ_STATUS); 280 281 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); 282 283 return IRQ_HANDLED; 284 } 285 286 static void aml_rtc_init(struct aml_rtc_data *rtc) 287 { 288 u32 reg_val = 0; 289 290 rtc->rtc_enabled = regmap_test_bits(rtc->map, RTC_CTRL, RTC_ENABLE); 291 if (!rtc->rtc_enabled) { 292 if (clk_get_rate(rtc->rtc_clk) == OSC_24M) { 293 /* select 24M oscillator */ 294 regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, RTC_OSC_SEL); 295 296 /* 297 * Set RTC oscillator to freq_out to freq_in/((N0*M0+N1*M1)/(M0+M1)) 298 * Enable clock_in gate of oscillator 24MHz 299 * Set N0 to 733, N1 to 732 300 */ 301 reg_val = FIELD_PREP(RTC_OSCIN_IN_EN, 1) 302 | FIELD_PREP(RTC_OSCIN_OUT_CFG, 1) 303 | FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_N0) 304 | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_N1); 305 regmap_write_bits(rtc->map, RTC_OSCIN_CTRL0, RTC_OSCIN_IN_EN 306 | RTC_OSCIN_OUT_CFG | RTC_OSCIN_OUT_N0M0 307 | RTC_OSCIN_OUT_N1M1, reg_val); 308 309 /* Set M0 to 2, M1 to 3, so freq_out = 32768 Hz*/ 310 reg_val = FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_M0) 311 | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_M1); 312 regmap_write_bits(rtc->map, RTC_OSCIN_CTRL1, RTC_OSCIN_OUT_N0M0 313 | RTC_OSCIN_OUT_N1M1, reg_val); 314 } else { 315 /* select 32K oscillator */ 316 regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, 0); 317 } 318 } 319 regmap_write_bits(rtc->map, RTC_INT_MASK, 320 RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); 321 regmap_write_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN, 0); 322 } 323 324 static int aml_rtc_probe(struct platform_device *pdev) 325 { 326 struct device *dev = &pdev->dev; 327 struct aml_rtc_data *rtc; 328 void __iomem *base; 329 int ret = 0; 330 331 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); 332 if (!rtc) 333 return -ENOMEM; 334 335 rtc->config = of_device_get_match_data(dev); 336 if (!rtc->config) 337 return -ENODEV; 338 339 base = devm_platform_ioremap_resource(pdev, 0); 340 if (IS_ERR(base)) 341 return dev_err_probe(dev, PTR_ERR(base), "resource ioremap failed\n"); 342 343 rtc->map = devm_regmap_init_mmio(dev, base, &aml_rtc_regmap_config); 344 if (IS_ERR(rtc->map)) 345 return dev_err_probe(dev, PTR_ERR(rtc->map), "regmap init failed\n"); 346 347 rtc->irq = platform_get_irq(pdev, 0); 348 if (rtc->irq < 0) 349 return rtc->irq; 350 351 rtc->rtc_clk = devm_clk_get(dev, "osc"); 352 if (IS_ERR(rtc->rtc_clk)) 353 return dev_err_probe(dev, PTR_ERR(rtc->rtc_clk), 354 "failed to find rtc clock\n"); 355 if (clk_get_rate(rtc->rtc_clk) != OSC_32K && clk_get_rate(rtc->rtc_clk) != OSC_24M) 356 return dev_err_probe(dev, -EINVAL, "Invalid clock configuration\n"); 357 358 rtc->sys_clk = devm_clk_get_enabled(dev, "sys"); 359 if (IS_ERR(rtc->sys_clk)) 360 return dev_err_probe(dev, PTR_ERR(rtc->sys_clk), 361 "failed to get_enable rtc sys clk\n"); 362 aml_rtc_init(rtc); 363 364 device_init_wakeup(dev, 1); 365 platform_set_drvdata(pdev, rtc); 366 367 rtc->rtc_dev = devm_rtc_allocate_device(dev); 368 if (IS_ERR(rtc->rtc_dev)) { 369 ret = PTR_ERR(rtc->rtc_dev); 370 goto err_clk; 371 } 372 373 ret = devm_request_irq(dev, rtc->irq, aml_rtc_handler, 374 IRQF_ONESHOT, "aml-rtc alarm", rtc); 375 if (ret) { 376 dev_err_probe(dev, ret, "IRQ%d request failed, ret = %d\n", 377 rtc->irq, ret); 378 goto err_clk; 379 } 380 381 rtc->rtc_dev->ops = &aml_rtc_ops; 382 rtc->rtc_dev->range_min = 0; 383 rtc->rtc_dev->range_max = U32_MAX; 384 385 ret = devm_rtc_register_device(rtc->rtc_dev); 386 if (ret) { 387 dev_err_probe(&pdev->dev, ret, "Failed to register RTC device: %d\n", ret); 388 goto err_clk; 389 } 390 391 return 0; 392 err_clk: 393 clk_disable_unprepare(rtc->sys_clk); 394 device_init_wakeup(dev, 0); 395 396 return ret; 397 } 398 399 #ifdef CONFIG_PM_SLEEP 400 static int aml_rtc_suspend(struct device *dev) 401 { 402 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 403 404 if (device_may_wakeup(dev)) 405 enable_irq_wake(rtc->irq); 406 407 return 0; 408 } 409 410 static int aml_rtc_resume(struct device *dev) 411 { 412 struct aml_rtc_data *rtc = dev_get_drvdata(dev); 413 414 if (device_may_wakeup(dev)) 415 disable_irq_wake(rtc->irq); 416 417 return 0; 418 } 419 #endif 420 421 static SIMPLE_DEV_PM_OPS(aml_rtc_pm_ops, 422 aml_rtc_suspend, aml_rtc_resume); 423 424 static void aml_rtc_remove(struct platform_device *pdev) 425 { 426 struct aml_rtc_data *rtc = dev_get_drvdata(&pdev->dev); 427 428 clk_disable_unprepare(rtc->sys_clk); 429 device_init_wakeup(&pdev->dev, 0); 430 } 431 432 static const struct aml_rtc_config a5_rtc_config = { 433 }; 434 435 static const struct aml_rtc_config a4_rtc_config = { 436 .gray_stored = true, 437 }; 438 439 static const struct of_device_id aml_rtc_device_id[] = { 440 { 441 .compatible = "amlogic,a4-rtc", 442 .data = &a4_rtc_config, 443 }, 444 { 445 .compatible = "amlogic,a5-rtc", 446 .data = &a5_rtc_config, 447 }, 448 { } 449 }; 450 MODULE_DEVICE_TABLE(of, aml_rtc_device_id); 451 452 static struct platform_driver aml_rtc_driver = { 453 .probe = aml_rtc_probe, 454 .remove = aml_rtc_remove, 455 .driver = { 456 .name = "aml-rtc", 457 .pm = &aml_rtc_pm_ops, 458 .of_match_table = aml_rtc_device_id, 459 }, 460 }; 461 462 module_platform_driver(aml_rtc_driver); 463 MODULE_DESCRIPTION("Amlogic RTC driver"); 464 MODULE_AUTHOR("Yiting Deng <yiting.deng@amlogic.com>"); 465 MODULE_LICENSE("GPL"); 466