1 // SPDX-License-Identifier: GPL-2.0-only 2 3 /* SpacemiT K1 reset controller driver */ 4 5 #include <linux/module.h> 6 7 #include <dt-bindings/clock/spacemit,k1-syscon.h> 8 #include <soc/spacemit/k1-syscon.h> 9 10 #include "reset-spacemit-common.h" 11 12 static const struct ccu_reset_data k1_mpmu_resets[] = { 13 [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), 14 }; 15 16 static const struct ccu_reset_controller_data k1_mpmu_reset_data = { 17 .reset_data = k1_mpmu_resets, 18 .count = ARRAY_SIZE(k1_mpmu_resets), 19 }; 20 21 static const struct ccu_reset_data k1_apbc_resets[] = { 22 [RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), 23 [RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), 24 [RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), 25 [RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), 26 [RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), 27 [RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), 28 [RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), 29 [RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), 30 [RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), 31 [RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), 32 [RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), 33 [RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), 34 [RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), 35 [RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), 36 [RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), 37 [RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), 38 [RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), 39 [RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), 40 [RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), 41 [RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), 42 [RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), 43 [RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), 44 [RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), 45 [RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), 46 [RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), 47 [RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), 48 [RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), 49 [RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), 50 [RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), 51 [RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), 52 [RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), 53 [RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), 54 [RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), 55 [RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), 56 [RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), 57 [RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), 58 [RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), 59 [RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), 60 [RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), 61 [RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), 62 [RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), 63 [RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), 64 [RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), 65 [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), 66 [RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), 67 [RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), 68 [RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), 69 [RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), 70 [RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), 71 [RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), 72 [RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), 73 }; 74 75 static const struct ccu_reset_controller_data k1_apbc_reset_data = { 76 .reset_data = k1_apbc_resets, 77 .count = ARRAY_SIZE(k1_apbc_resets), 78 }; 79 80 static const struct ccu_reset_data k1_apmu_resets[] = { 81 [RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), 82 [RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), 83 [RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), 84 [RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), 85 [RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), 86 [RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), 87 [RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), 88 [RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), 89 [RESET_USB30_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)), 90 [RESET_USB30_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)), 91 [RESET_USB30_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)), 92 [RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), 93 [RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), 94 [RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), 95 [RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), 96 [RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), 97 [RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), 98 [RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), 99 [RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), 100 [RESET_AUDIO_SYS] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(0)), 101 [RESET_AUDIO_MCU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(2)), 102 [RESET_AUDIO_APMU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(3)), 103 [RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), 104 [RESET_PCIE0_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(3)), 105 [RESET_PCIE0_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(4)), 106 [RESET_PCIE0_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(5)), 107 [RESET_PCIE0_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0), 108 [RESET_PCIE1_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(3)), 109 [RESET_PCIE1_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(4)), 110 [RESET_PCIE1_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(5)), 111 [RESET_PCIE1_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), 0), 112 [RESET_PCIE2_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(3)), 113 [RESET_PCIE2_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(4)), 114 [RESET_PCIE2_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(5)), 115 [RESET_PCIE2_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), 0), 116 [RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), 117 [RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), 118 [RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), 119 [RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), 120 [RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), 121 [RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), 122 [RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), 123 [RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), 124 [RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), 125 [RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), 126 [RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), 127 [RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), 128 [RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), 129 [RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), 130 [RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), 131 [RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), 132 [RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), 133 [RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), 134 }; 135 136 static const struct ccu_reset_controller_data k1_apmu_reset_data = { 137 .reset_data = k1_apmu_resets, 138 .count = ARRAY_SIZE(k1_apmu_resets), 139 }; 140 141 static const struct ccu_reset_data k1_rcpu_resets[] = { 142 [RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), 143 [RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), 144 [RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), 145 [RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), 146 [RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), 147 [RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), 148 [RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), 149 }; 150 151 static const struct ccu_reset_controller_data k1_rcpu_reset_data = { 152 .reset_data = k1_rcpu_resets, 153 .count = ARRAY_SIZE(k1_rcpu_resets), 154 }; 155 156 static const struct ccu_reset_data k1_rcpu2_resets[] = { 157 [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 158 [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 159 [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 160 [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 161 [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 162 [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 163 [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 164 [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 165 [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 166 [RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), 167 }; 168 169 static const struct ccu_reset_controller_data k1_rcpu2_reset_data = { 170 .reset_data = k1_rcpu2_resets, 171 .count = ARRAY_SIZE(k1_rcpu2_resets), 172 }; 173 174 static const struct ccu_reset_data k1_apbc2_resets[] = { 175 [RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0), 176 [RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0), 177 [RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0), 178 [RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0), 179 [RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0), 180 [RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0), 181 [RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0), 182 }; 183 184 static const struct ccu_reset_controller_data k1_apbc2_reset_data = { 185 .reset_data = k1_apbc2_resets, 186 .count = ARRAY_SIZE(k1_apbc2_resets), 187 }; 188 189 #define K1_AUX_DEV_ID(_unit) \ 190 { \ 191 .name = "spacemit_ccu.k1-" #_unit "-reset", \ 192 .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ 193 } 194 195 static const struct auxiliary_device_id spacemit_k1_reset_ids[] = { 196 K1_AUX_DEV_ID(mpmu), 197 K1_AUX_DEV_ID(apbc), 198 K1_AUX_DEV_ID(apmu), 199 K1_AUX_DEV_ID(rcpu), 200 K1_AUX_DEV_ID(rcpu2), 201 K1_AUX_DEV_ID(apbc2), 202 { /* sentinel */ } 203 }; 204 MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids); 205 206 static struct auxiliary_driver spacemit_k1_reset_driver = { 207 .probe = spacemit_reset_probe, 208 .id_table = spacemit_k1_reset_ids, 209 }; 210 module_auxiliary_driver(spacemit_k1_reset_driver); 211 212 MODULE_IMPORT_NS("RESET_SPACEMIT"); 213 MODULE_AUTHOR("Alex Elder <elder@kernel.org>"); 214 MODULE_DESCRIPTION("SpacemiT K1 reset controller driver"); 215 MODULE_LICENSE("GPL"); 216