1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2024 NXP. 4 * NXP PF9453 pmic driver 5 */ 6 7 #include <linux/bits.h> 8 #include <linux/err.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/driver.h> 18 #include <linux/regulator/machine.h> 19 #include <linux/regulator/of_regulator.h> 20 21 struct pf9453_dvs_config { 22 unsigned int run_reg; /* dvs0 */ 23 unsigned int run_mask; 24 unsigned int standby_reg; /* dvs1 */ 25 unsigned int standby_mask; 26 }; 27 28 struct pf9453_regulator_desc { 29 struct regulator_desc desc; 30 const struct pf9453_dvs_config dvs; 31 }; 32 33 struct pf9453 { 34 struct device *dev; 35 struct regmap *regmap; 36 struct gpio_desc *sd_vsel_gpio; 37 int irq; 38 }; 39 40 enum { 41 PF9453_BUCK1 = 0, 42 PF9453_BUCK2, 43 PF9453_BUCK3, 44 PF9453_BUCK4, 45 PF9453_LDO1, 46 PF9453_LDO2, 47 PF9453_LDOSNVS, 48 PF9453_REGULATOR_CNT 49 }; 50 51 enum { 52 PF9453_DVS_LEVEL_RUN = 0, 53 PF9453_DVS_LEVEL_STANDBY, 54 PF9453_DVS_LEVEL_DPSTANDBY, 55 PF9453_DVS_LEVEL_MAX 56 }; 57 58 #define PF9453_BUCK1_VOLTAGE_NUM 0x80 59 #define PF9453_BUCK2_VOLTAGE_NUM 0x80 60 #define PF9453_BUCK3_VOLTAGE_NUM 0x80 61 #define PF9453_BUCK4_VOLTAGE_NUM 0x80 62 63 #define PF9453_LDO1_VOLTAGE_NUM 0x65 64 #define PF9453_LDO2_VOLTAGE_NUM 0x3b 65 #define PF9453_LDOSNVS_VOLTAGE_NUM 0x59 66 67 enum { 68 PF9453_REG_DEV_ID = 0x00, 69 PF9453_REG_OTP_VER = 0x01, 70 PF9453_REG_INT1 = 0x02, 71 PF9453_REG_INT1_MASK = 0x03, 72 PF9453_REG_INT1_STATUS = 0x04, 73 PF9453_REG_VRFLT1_INT = 0x05, 74 PF9453_REG_VRFLT1_MASK = 0x06, 75 PF9453_REG_PWRON_STAT = 0x07, 76 PF9453_REG_RESET_CTRL = 0x08, 77 PF9453_REG_SW_RST = 0x09, 78 PF9453_REG_PWR_CTRL = 0x0a, 79 PF9453_REG_CONFIG1 = 0x0b, 80 PF9453_REG_CONFIG2 = 0x0c, 81 PF9453_REG_32K_CONFIG = 0x0d, 82 PF9453_REG_BUCK1CTRL = 0x10, 83 PF9453_REG_BUCK1OUT = 0x11, 84 PF9453_REG_BUCK2CTRL = 0x14, 85 PF9453_REG_BUCK2OUT = 0x15, 86 PF9453_REG_BUCK2OUT_STBY = 0x1d, 87 PF9453_REG_BUCK2OUT_MAX_LIMIT = 0x1f, 88 PF9453_REG_BUCK2OUT_MIN_LIMIT = 0x20, 89 PF9453_REG_BUCK3CTRL = 0x21, 90 PF9453_REG_BUCK3OUT = 0x22, 91 PF9453_REG_BUCK4CTRL = 0x2e, 92 PF9453_REG_BUCK4OUT = 0x2f, 93 PF9453_REG_LDO1OUT_L = 0x36, 94 PF9453_REG_LDO1CFG = 0x37, 95 PF9453_REG_LDO1OUT_H = 0x38, 96 PF9453_REG_LDOSNVS_CFG1 = 0x39, 97 PF9453_REG_LDOSNVS_CFG2 = 0x3a, 98 PF9453_REG_LDO2CFG = 0x3b, 99 PF9453_REG_LDO2OUT = 0x3c, 100 PF9453_REG_BUCK_POK = 0x3d, 101 PF9453_REG_LSW_CTRL1 = 0x40, 102 PF9453_REG_LSW_CTRL2 = 0x41, 103 PF9453_REG_LOCK = 0x4e, 104 PF9453_MAX_REG 105 }; 106 107 #define PF9453_UNLOCK_KEY 0x5c 108 #define PF9453_LOCK_KEY 0x0 109 110 /* PF9453 BUCK ENMODE bits */ 111 #define BUCK_ENMODE_OFF 0x00 112 #define BUCK_ENMODE_ONREQ 0x01 113 #define BUCK_ENMODE_ONREQ_STBY 0x02 114 #define BUCK_ENMODE_ONREQ_STBY_DPSTBY 0x03 115 116 /* PF9453 BUCK ENMODE bits */ 117 #define LDO_ENMODE_OFF 0x00 118 #define LDO_ENMODE_ONREQ 0x01 119 #define LDO_ENMODE_ONREQ_STBY 0x02 120 #define LDO_ENMODE_ONREQ_STBY_DPSTBY 0x03 121 122 /* PF9453_REG_BUCK1_CTRL bits */ 123 #define BUCK1_LPMODE 0x30 124 #define BUCK1_AD 0x08 125 #define BUCK1_FPWM 0x04 126 #define BUCK1_ENMODE_MASK GENMASK(1, 0) 127 128 /* PF9453_REG_BUCK2_CTRL bits */ 129 #define BUCK2_RAMP_MASK GENMASK(7, 6) 130 #define BUCK2_RAMP_25MV 0x0 131 #define BUCK2_RAMP_12P5MV 0x1 132 #define BUCK2_RAMP_6P25MV 0x2 133 #define BUCK2_RAMP_3P125MV 0x3 134 #define BUCK2_LPMODE 0x30 135 #define BUCK2_AD 0x08 136 #define BUCK2_FPWM 0x04 137 #define BUCK2_ENMODE_MASK GENMASK(1, 0) 138 139 /* PF9453_REG_BUCK3_CTRL bits */ 140 #define BUCK3_LPMODE 0x30 141 #define BUCK3_AD 0x08 142 #define BUCK3_FPWM 0x04 143 #define BUCK3_ENMODE_MASK GENMASK(1, 0) 144 145 /* PF9453_REG_BUCK4_CTRL bits */ 146 #define BUCK4_LPMODE 0x30 147 #define BUCK4_AD 0x08 148 #define BUCK4_FPWM 0x04 149 #define BUCK4_ENMODE_MASK GENMASK(1, 0) 150 151 /* PF9453_REG_BUCK123_PRESET_EN bit */ 152 #define BUCK123_PRESET_EN 0x80 153 154 /* PF9453_BUCK1OUT bits */ 155 #define BUCK1OUT_MASK GENMASK(6, 0) 156 157 /* PF9453_BUCK2OUT bits */ 158 #define BUCK2OUT_MASK GENMASK(6, 0) 159 #define BUCK2OUT_STBY_MASK GENMASK(6, 0) 160 161 /* PF9453_REG_BUCK3OUT bits */ 162 #define BUCK3OUT_MASK GENMASK(6, 0) 163 164 /* PF9453_REG_BUCK4OUT bits */ 165 #define BUCK4OUT_MASK GENMASK(6, 0) 166 167 /* PF9453_REG_LDO1_VOLT bits */ 168 #define LDO1_EN_MASK GENMASK(1, 0) 169 #define LDO1OUT_MASK GENMASK(6, 0) 170 171 /* PF9453_REG_LDO2_VOLT bits */ 172 #define LDO2_EN_MASK GENMASK(1, 0) 173 #define LDO2OUT_MASK GENMASK(6, 0) 174 175 /* PF9453_REG_LDOSNVS_VOLT bits */ 176 #define LDOSNVS_EN_MASK GENMASK(0, 0) 177 #define LDOSNVSCFG1_MASK GENMASK(6, 0) 178 179 /* PF9453_REG_IRQ bits */ 180 #define IRQ_RSVD 0x80 181 #define IRQ_RSTB 0x40 182 #define IRQ_ONKEY 0x20 183 #define IRQ_RESETKEY 0x10 184 #define IRQ_VR_FLT1 0x08 185 #define IRQ_LOWVSYS 0x04 186 #define IRQ_THERM_100 0x02 187 #define IRQ_THERM_80 0x01 188 189 /* PF9453_REG_RESET_CTRL bits */ 190 #define WDOG_B_CFG_MASK GENMASK(7, 6) 191 #define WDOG_B_CFG_NONE 0x00 192 #define WDOG_B_CFG_WARM 0x40 193 #define WDOG_B_CFG_COLD 0x80 194 195 /* PF9453_REG_CONFIG2 bits */ 196 #define I2C_LT_MASK GENMASK(1, 0) 197 #define I2C_LT_FORCE_DISABLE 0x00 198 #define I2C_LT_ON_STANDBY_RUN 0x01 199 #define I2C_LT_ON_RUN 0x02 200 #define I2C_LT_FORCE_ENABLE 0x03 201 202 static const struct regmap_range pf9453_status_range = { 203 .range_min = PF9453_REG_INT1, 204 .range_max = PF9453_REG_PWRON_STAT, 205 }; 206 207 static const struct regmap_access_table pf9453_volatile_regs = { 208 .yes_ranges = &pf9453_status_range, 209 .n_yes_ranges = 1, 210 }; 211 212 static const struct regmap_config pf9453_regmap_config = { 213 .reg_bits = 8, 214 .val_bits = 8, 215 .volatile_table = &pf9453_volatile_regs, 216 .max_register = PF9453_MAX_REG - 1, 217 .cache_type = REGCACHE_RBTREE, 218 }; 219 220 /* 221 * BUCK2 222 * BUCK2RAM[1:0] BUCK2 DVS ramp rate setting 223 * 00: 25mV/1usec 224 * 01: 25mV/2usec 225 * 10: 25mV/4usec 226 * 11: 25mV/8usec 227 */ 228 static const unsigned int pf9453_dvs_buck_ramp_table[] = { 229 25000, 12500, 6250, 3125 230 }; 231 232 static bool is_reg_protect(uint reg) 233 { 234 switch (reg) { 235 case PF9453_REG_BUCK1OUT: 236 case PF9453_REG_BUCK2OUT: 237 case PF9453_REG_BUCK3OUT: 238 case PF9453_REG_BUCK4OUT: 239 case PF9453_REG_LDO1OUT_L: 240 case PF9453_REG_LDO1OUT_H: 241 case PF9453_REG_LDO2OUT: 242 case PF9453_REG_LDOSNVS_CFG1: 243 case PF9453_REG_BUCK2OUT_MAX_LIMIT: 244 case PF9453_REG_BUCK2OUT_MIN_LIMIT: 245 return true; 246 default: 247 return false; 248 } 249 } 250 251 static int pf9453_pmic_write(struct pf9453 *pf9453, unsigned int reg, u8 mask, unsigned int val) 252 { 253 int ret = -EINVAL; 254 u8 data, key; 255 u32 rxBuf; 256 257 /* If not updating entire register, perform a read-mod-write */ 258 data = val; 259 key = PF9453_UNLOCK_KEY; 260 261 if (mask != 0xffU) { 262 /* Read data */ 263 ret = regmap_read(pf9453->regmap, reg, &rxBuf); 264 if (ret) { 265 dev_err(pf9453->dev, "Read reg=%0x error!\n", reg); 266 return ret; 267 } 268 data = (val & mask) | (rxBuf & (~mask)); 269 } 270 271 if (reg < PF9453_MAX_REG) { 272 if (is_reg_protect(reg)) { 273 ret = regmap_raw_write(pf9453->regmap, PF9453_REG_LOCK, &key, 1U); 274 if (ret) { 275 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 276 return ret; 277 } 278 279 ret = regmap_raw_write(pf9453->regmap, reg, &data, 1U); 280 if (ret) { 281 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 282 return ret; 283 } 284 285 key = PF9453_LOCK_KEY; 286 ret = regmap_raw_write(pf9453->regmap, PF9453_REG_LOCK, &key, 1U); 287 if (ret) { 288 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 289 return ret; 290 } 291 } else { 292 ret = regmap_raw_write(pf9453->regmap, reg, &data, 1U); 293 if (ret) { 294 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 295 return ret; 296 } 297 } 298 } 299 300 return ret; 301 } 302 303 /** 304 * pf9453_regulator_enable_regmap for regmap users 305 * 306 * @rdev: regulator to operate on 307 * 308 * Regulators that use regmap for their register I/O can set the 309 * enable_reg and enable_mask fields in their descriptor and then use 310 * this as their enable() operation, saving some code. 311 */ 312 static int pf9453_regulator_enable_regmap(struct regulator_dev *rdev) 313 { 314 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 315 unsigned int val; 316 317 if (rdev->desc->enable_is_inverted) { 318 val = rdev->desc->disable_val; 319 } else { 320 val = rdev->desc->enable_val; 321 if (!val) 322 val = rdev->desc->enable_mask; 323 } 324 325 return pf9453_pmic_write(pf9453, rdev->desc->enable_reg, rdev->desc->enable_mask, val); 326 } 327 328 /** 329 * pf9453_regulator_disable_regmap for regmap users 330 * 331 * @rdev: regulator to operate on 332 * 333 * Regulators that use regmap for their register I/O can set the 334 * enable_reg and enable_mask fields in their descriptor and then use 335 * this as their disable() operation, saving some code. 336 */ 337 static int pf9453_regulator_disable_regmap(struct regulator_dev *rdev) 338 { 339 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 340 unsigned int val; 341 342 if (rdev->desc->enable_is_inverted) { 343 val = rdev->desc->enable_val; 344 if (!val) 345 val = rdev->desc->enable_mask; 346 } else { 347 val = rdev->desc->disable_val; 348 } 349 350 return pf9453_pmic_write(pf9453, rdev->desc->enable_reg, rdev->desc->enable_mask, val); 351 } 352 353 /** 354 * pf9453_regulator_set_voltage_sel_regmap for regmap users 355 * 356 * @rdev: regulator to operate on 357 * @sel: Selector to set 358 * 359 * Regulators that use regmap for their register I/O can set the 360 * vsel_reg and vsel_mask fields in their descriptor and then use this 361 * as their set_voltage_vsel operation, saving some code. 362 */ 363 static int pf9453_regulator_set_voltage_sel_regmap(struct regulator_dev *rdev, unsigned int sel) 364 { 365 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 366 int ret; 367 368 sel <<= ffs(rdev->desc->vsel_mask) - 1; 369 ret = pf9453_pmic_write(pf9453, rdev->desc->vsel_reg, rdev->desc->vsel_mask, sel); 370 if (ret) 371 return ret; 372 373 if (rdev->desc->apply_bit) 374 ret = pf9453_pmic_write(pf9453, rdev->desc->apply_reg, 375 rdev->desc->apply_bit, rdev->desc->apply_bit); 376 return ret; 377 } 378 379 static int find_closest_bigger(unsigned int target, const unsigned int *table, 380 unsigned int num_sel, unsigned int *sel) 381 { 382 unsigned int s, tmp, max, maxsel = 0; 383 bool found = false; 384 385 max = table[0]; 386 387 for (s = 0; s < num_sel; s++) { 388 if (table[s] > max) { 389 max = table[s]; 390 maxsel = s; 391 } 392 if (table[s] >= target) { 393 if (!found || table[s] - target < tmp - target) { 394 tmp = table[s]; 395 *sel = s; 396 found = true; 397 if (tmp == target) 398 break; 399 } 400 } 401 } 402 403 if (!found) { 404 *sel = maxsel; 405 return -EINVAL; 406 } 407 408 return 0; 409 } 410 411 /** 412 * pf9453_regulator_set_ramp_delay_regmap 413 * 414 * @rdev: regulator to operate on 415 * 416 * Regulators that use regmap for their register I/O can set the ramp_reg 417 * and ramp_mask fields in their descriptor and then use this as their 418 * set_ramp_delay operation, saving some code. 419 */ 420 static int pf9453_regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay) 421 { 422 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 423 unsigned int sel; 424 int ret; 425 426 if (WARN_ON(!rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table)) 427 return -EINVAL; 428 429 ret = find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, 430 rdev->desc->n_ramp_values, &sel); 431 432 if (ret) { 433 dev_warn(rdev_get_dev(rdev), 434 "Can't set ramp-delay %u, setting %u\n", ramp_delay, 435 rdev->desc->ramp_delay_table[sel]); 436 } 437 438 sel <<= ffs(rdev->desc->ramp_mask) - 1; 439 440 return pf9453_pmic_write(pf9453, rdev->desc->ramp_reg, 441 rdev->desc->ramp_mask, sel); 442 } 443 444 static const struct regulator_ops pf9453_dvs_buck_regulator_ops = { 445 .enable = pf9453_regulator_enable_regmap, 446 .disable = pf9453_regulator_disable_regmap, 447 .is_enabled = regulator_is_enabled_regmap, 448 .list_voltage = regulator_list_voltage_linear_range, 449 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 450 .get_voltage_sel = regulator_get_voltage_sel_regmap, 451 .set_voltage_time_sel = regulator_set_voltage_time_sel, 452 .set_ramp_delay = pf9453_regulator_set_ramp_delay_regmap, 453 }; 454 455 static const struct regulator_ops pf9453_buck_regulator_ops = { 456 .enable = pf9453_regulator_enable_regmap, 457 .disable = pf9453_regulator_disable_regmap, 458 .is_enabled = regulator_is_enabled_regmap, 459 .list_voltage = regulator_list_voltage_linear_range, 460 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 461 .get_voltage_sel = regulator_get_voltage_sel_regmap, 462 .set_voltage_time_sel = regulator_set_voltage_time_sel, 463 }; 464 465 static const struct regulator_ops pf9453_ldo_regulator_ops = { 466 .enable = pf9453_regulator_enable_regmap, 467 .disable = pf9453_regulator_disable_regmap, 468 .is_enabled = regulator_is_enabled_regmap, 469 .list_voltage = regulator_list_voltage_linear_range, 470 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 471 .get_voltage_sel = regulator_get_voltage_sel_regmap, 472 }; 473 474 /* 475 * BUCK1/3/4 476 * 0.60 to 3.775V (25mV step) 477 */ 478 static const struct linear_range pf9453_buck134_volts[] = { 479 REGULATOR_LINEAR_RANGE(600000, 0x00, 0x7F, 25000), 480 }; 481 482 /* 483 * BUCK2 484 * 0.60 to 2.1875V (12.5mV step) 485 */ 486 static const struct linear_range pf9453_buck2_volts[] = { 487 REGULATOR_LINEAR_RANGE(600000, 0x00, 0x7F, 12500), 488 }; 489 490 /* 491 * LDO1 492 * 0.8 to 3.3V (25mV step) 493 */ 494 static const struct linear_range pf9453_ldo1_volts[] = { 495 REGULATOR_LINEAR_RANGE(800000, 0x00, 0x64, 25000), 496 }; 497 498 /* 499 * LDO2 500 * 0.5 to 1.95V (25mV step) 501 */ 502 static const struct linear_range pf9453_ldo2_volts[] = { 503 REGULATOR_LINEAR_RANGE(500000, 0x00, 0x3A, 25000), 504 }; 505 506 /* 507 * LDOSNVS 508 * 1.2 to 3.4V (25mV step) 509 */ 510 static const struct linear_range pf9453_ldosnvs_volts[] = { 511 REGULATOR_LINEAR_RANGE(1200000, 0x00, 0x58, 25000), 512 }; 513 514 static int buck_set_dvs(const struct regulator_desc *desc, 515 struct device_node *np, struct pf9453 *pf9453, 516 char *prop, unsigned int reg, unsigned int mask) 517 { 518 int ret, i; 519 u32 uv; 520 521 ret = of_property_read_u32(np, prop, &uv); 522 if (ret == -EINVAL) 523 return 0; 524 else if (ret) 525 return ret; 526 527 for (i = 0; i < desc->n_voltages; i++) { 528 ret = regulator_desc_list_voltage_linear_range(desc, i); 529 if (ret < 0) 530 continue; 531 if (ret == uv) { 532 i <<= ffs(desc->vsel_mask) - 1; 533 ret = pf9453_pmic_write(pf9453, reg, mask, i); 534 break; 535 } 536 } 537 538 if (ret == 0) { 539 struct pf9453_regulator_desc *regulator = container_of(desc, 540 struct pf9453_regulator_desc, desc); 541 542 /* Enable DVS control through PMIC_STBY_REQ for this BUCK */ 543 ret = pf9453_pmic_write(pf9453, regulator->desc.enable_reg, 544 BUCK2_LPMODE, BUCK2_LPMODE); 545 } 546 return ret; 547 } 548 549 static int pf9453_set_dvs_levels(struct device_node *np, const struct regulator_desc *desc, 550 struct regulator_config *cfg) 551 { 552 struct pf9453_regulator_desc *data = container_of(desc, struct pf9453_regulator_desc, desc); 553 struct pf9453 *pf9453 = dev_get_drvdata(cfg->dev); 554 const struct pf9453_dvs_config *dvs = &data->dvs; 555 unsigned int reg, mask; 556 int i, ret = 0; 557 char *prop; 558 559 for (i = 0; i < PF9453_DVS_LEVEL_MAX; i++) { 560 switch (i) { 561 case PF9453_DVS_LEVEL_RUN: 562 prop = "nxp,dvs-run-voltage"; 563 reg = dvs->run_reg; 564 mask = dvs->run_mask; 565 break; 566 case PF9453_DVS_LEVEL_DPSTANDBY: 567 case PF9453_DVS_LEVEL_STANDBY: 568 prop = "nxp,dvs-standby-voltage"; 569 reg = dvs->standby_reg; 570 mask = dvs->standby_mask; 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 ret = buck_set_dvs(desc, np, pf9453, prop, reg, mask); 577 if (ret) 578 break; 579 } 580 581 return ret; 582 } 583 584 static const struct pf9453_regulator_desc pf9453_regulators[] = { 585 { 586 .desc = { 587 .name = "buck1", 588 .of_match = of_match_ptr("BUCK1"), 589 .regulators_node = of_match_ptr("regulators"), 590 .id = PF9453_BUCK1, 591 .ops = &pf9453_buck_regulator_ops, 592 .type = REGULATOR_VOLTAGE, 593 .n_voltages = PF9453_BUCK1_VOLTAGE_NUM, 594 .linear_ranges = pf9453_buck134_volts, 595 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 596 .vsel_reg = PF9453_REG_BUCK1OUT, 597 .vsel_mask = BUCK1OUT_MASK, 598 .enable_reg = PF9453_REG_BUCK1CTRL, 599 .enable_mask = BUCK1_ENMODE_MASK, 600 .enable_val = BUCK_ENMODE_ONREQ, 601 .owner = THIS_MODULE, 602 }, 603 }, 604 { 605 .desc = { 606 .name = "buck2", 607 .of_match = of_match_ptr("BUCK2"), 608 .regulators_node = of_match_ptr("regulators"), 609 .id = PF9453_BUCK2, 610 .ops = &pf9453_dvs_buck_regulator_ops, 611 .type = REGULATOR_VOLTAGE, 612 .n_voltages = PF9453_BUCK2_VOLTAGE_NUM, 613 .linear_ranges = pf9453_buck2_volts, 614 .n_linear_ranges = ARRAY_SIZE(pf9453_buck2_volts), 615 .vsel_reg = PF9453_REG_BUCK2OUT, 616 .vsel_mask = BUCK2OUT_MASK, 617 .enable_reg = PF9453_REG_BUCK2CTRL, 618 .enable_mask = BUCK2_ENMODE_MASK, 619 .enable_val = BUCK_ENMODE_ONREQ, 620 .ramp_reg = PF9453_REG_BUCK2CTRL, 621 .ramp_mask = BUCK2_RAMP_MASK, 622 .ramp_delay_table = pf9453_dvs_buck_ramp_table, 623 .n_ramp_values = ARRAY_SIZE(pf9453_dvs_buck_ramp_table), 624 .owner = THIS_MODULE, 625 .of_parse_cb = pf9453_set_dvs_levels, 626 }, 627 .dvs = { 628 .run_reg = PF9453_REG_BUCK2OUT, 629 .run_mask = BUCK2OUT_MASK, 630 .standby_reg = PF9453_REG_BUCK2OUT_STBY, 631 .standby_mask = BUCK2OUT_STBY_MASK, 632 }, 633 }, 634 { 635 .desc = { 636 .name = "buck3", 637 .of_match = of_match_ptr("BUCK3"), 638 .regulators_node = of_match_ptr("regulators"), 639 .id = PF9453_BUCK3, 640 .ops = &pf9453_buck_regulator_ops, 641 .type = REGULATOR_VOLTAGE, 642 .n_voltages = PF9453_BUCK3_VOLTAGE_NUM, 643 .linear_ranges = pf9453_buck134_volts, 644 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 645 .vsel_reg = PF9453_REG_BUCK3OUT, 646 .vsel_mask = BUCK3OUT_MASK, 647 .enable_reg = PF9453_REG_BUCK3CTRL, 648 .enable_mask = BUCK3_ENMODE_MASK, 649 .enable_val = BUCK_ENMODE_ONREQ, 650 .owner = THIS_MODULE, 651 }, 652 }, 653 { 654 .desc = { 655 .name = "buck4", 656 .of_match = of_match_ptr("BUCK4"), 657 .regulators_node = of_match_ptr("regulators"), 658 .id = PF9453_BUCK4, 659 .ops = &pf9453_buck_regulator_ops, 660 .type = REGULATOR_VOLTAGE, 661 .n_voltages = PF9453_BUCK4_VOLTAGE_NUM, 662 .linear_ranges = pf9453_buck134_volts, 663 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 664 .vsel_reg = PF9453_REG_BUCK4OUT, 665 .vsel_mask = BUCK4OUT_MASK, 666 .enable_reg = PF9453_REG_BUCK4CTRL, 667 .enable_mask = BUCK4_ENMODE_MASK, 668 .enable_val = BUCK_ENMODE_ONREQ, 669 .owner = THIS_MODULE, 670 }, 671 }, 672 { 673 .desc = { 674 .name = "ldo1", 675 .of_match = of_match_ptr("LDO1"), 676 .regulators_node = of_match_ptr("regulators"), 677 .id = PF9453_LDO1, 678 .ops = &pf9453_ldo_regulator_ops, 679 .type = REGULATOR_VOLTAGE, 680 .n_voltages = PF9453_LDO1_VOLTAGE_NUM, 681 .linear_ranges = pf9453_ldo1_volts, 682 .n_linear_ranges = ARRAY_SIZE(pf9453_ldo1_volts), 683 .vsel_reg = PF9453_REG_LDO1OUT_H, 684 .vsel_mask = LDO1OUT_MASK, 685 .enable_reg = PF9453_REG_LDO1CFG, 686 .enable_mask = LDO1_EN_MASK, 687 .enable_val = LDO_ENMODE_ONREQ, 688 .owner = THIS_MODULE, 689 }, 690 }, 691 { 692 .desc = { 693 .name = "ldo2", 694 .of_match = of_match_ptr("LDO2"), 695 .regulators_node = of_match_ptr("regulators"), 696 .id = PF9453_LDO2, 697 .ops = &pf9453_ldo_regulator_ops, 698 .type = REGULATOR_VOLTAGE, 699 .n_voltages = PF9453_LDO2_VOLTAGE_NUM, 700 .linear_ranges = pf9453_ldo2_volts, 701 .n_linear_ranges = ARRAY_SIZE(pf9453_ldo2_volts), 702 .vsel_reg = PF9453_REG_LDO2OUT, 703 .vsel_mask = LDO2OUT_MASK, 704 .enable_reg = PF9453_REG_LDO2CFG, 705 .enable_mask = LDO2_EN_MASK, 706 .enable_val = LDO_ENMODE_ONREQ, 707 .owner = THIS_MODULE, 708 }, 709 }, 710 { 711 .desc = { 712 .name = "ldosnvs", 713 .of_match = of_match_ptr("LDO-SNVS"), 714 .regulators_node = of_match_ptr("regulators"), 715 .id = PF9453_LDOSNVS, 716 .ops = &pf9453_ldo_regulator_ops, 717 .type = REGULATOR_VOLTAGE, 718 .n_voltages = PF9453_LDOSNVS_VOLTAGE_NUM, 719 .linear_ranges = pf9453_ldosnvs_volts, 720 .n_linear_ranges = ARRAY_SIZE(pf9453_ldosnvs_volts), 721 .vsel_reg = PF9453_REG_LDOSNVS_CFG1, 722 .vsel_mask = LDOSNVSCFG1_MASK, 723 .enable_reg = PF9453_REG_LDOSNVS_CFG2, 724 .enable_mask = LDOSNVS_EN_MASK, 725 .owner = THIS_MODULE, 726 }, 727 }, 728 { } 729 }; 730 731 static irqreturn_t pf9453_irq_handler(int irq, void *data) 732 { 733 struct pf9453 *pf9453 = data; 734 struct regmap *regmap = pf9453->regmap; 735 unsigned int status; 736 int ret; 737 738 ret = regmap_read(regmap, PF9453_REG_INT1, &status); 739 if (ret < 0) { 740 dev_err(pf9453->dev, "Failed to read INT1(%d)\n", ret); 741 return IRQ_NONE; 742 } 743 744 if (status & IRQ_RSTB) 745 dev_warn(pf9453->dev, "IRQ_RSTB interrupt.\n"); 746 747 if (status & IRQ_ONKEY) 748 dev_warn(pf9453->dev, "IRQ_ONKEY interrupt.\n"); 749 750 if (status & IRQ_VR_FLT1) 751 dev_warn(pf9453->dev, "VRFLT1 interrupt.\n"); 752 753 if (status & IRQ_RESETKEY) 754 dev_warn(pf9453->dev, "IRQ_RESETKEY interrupt.\n"); 755 756 if (status & IRQ_LOWVSYS) 757 dev_warn(pf9453->dev, "LOWVSYS interrupt.\n"); 758 759 if (status & IRQ_THERM_100) 760 dev_warn(pf9453->dev, "IRQ_THERM_100 interrupt.\n"); 761 762 if (status & IRQ_THERM_80) 763 dev_warn(pf9453->dev, "IRQ_THERM_80 interrupt.\n"); 764 765 return IRQ_HANDLED; 766 } 767 768 static int pf9453_i2c_probe(struct i2c_client *i2c) 769 { 770 const struct pf9453_regulator_desc *regulator_desc = of_device_get_match_data(&i2c->dev); 771 struct regulator_config config = { }; 772 unsigned int reset_ctrl; 773 unsigned int device_id; 774 struct pf9453 *pf9453; 775 int ret; 776 777 if (!i2c->irq) 778 return dev_err_probe(&i2c->dev, -EINVAL, "No IRQ configured?\n"); 779 780 pf9453 = devm_kzalloc(&i2c->dev, sizeof(struct pf9453), GFP_KERNEL); 781 if (!pf9453) 782 return -ENOMEM; 783 784 pf9453->regmap = devm_regmap_init_i2c(i2c, &pf9453_regmap_config); 785 if (IS_ERR(pf9453->regmap)) 786 return dev_err_probe(&i2c->dev, PTR_ERR(pf9453->regmap), 787 "regmap initialization failed\n"); 788 789 pf9453->irq = i2c->irq; 790 pf9453->dev = &i2c->dev; 791 792 dev_set_drvdata(&i2c->dev, pf9453); 793 794 ret = regmap_read(pf9453->regmap, PF9453_REG_DEV_ID, &device_id); 795 if (ret) 796 return dev_err_probe(&i2c->dev, ret, "Read device id error\n"); 797 798 /* Check your board and dts for match the right pmic */ 799 if ((device_id >> 4) != 0xb) 800 return dev_err_probe(&i2c->dev, -EINVAL, "Device id(%x) mismatched\n", 801 device_id >> 4); 802 803 while (regulator_desc->desc.name) { 804 const struct regulator_desc *desc; 805 struct regulator_dev *rdev; 806 807 desc = ®ulator_desc->desc; 808 809 config.regmap = pf9453->regmap; 810 config.dev = pf9453->dev; 811 812 rdev = devm_regulator_register(pf9453->dev, desc, &config); 813 if (IS_ERR(rdev)) 814 return dev_err_probe(pf9453->dev, PTR_ERR(rdev), 815 "Failed to register regulator(%s)\n", desc->name); 816 817 regulator_desc++; 818 } 819 820 ret = devm_request_threaded_irq(pf9453->dev, pf9453->irq, NULL, pf9453_irq_handler, 821 (IRQF_TRIGGER_FALLING | IRQF_ONESHOT), 822 "pf9453-irq", pf9453); 823 if (ret) 824 return dev_err_probe(pf9453->dev, ret, "Failed to request IRQ: %d\n", pf9453->irq); 825 826 /* Unmask all interrupt except PWRON/WDOG/RSVD */ 827 ret = pf9453_pmic_write(pf9453, PF9453_REG_INT1_MASK, 828 IRQ_ONKEY | IRQ_RESETKEY | IRQ_RSTB | IRQ_VR_FLT1 829 | IRQ_LOWVSYS | IRQ_THERM_100 | IRQ_THERM_80, IRQ_RSVD); 830 if (ret) 831 return dev_err_probe(&i2c->dev, ret, "Unmask irq error\n"); 832 833 if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset")) 834 reset_ctrl = WDOG_B_CFG_WARM; 835 else 836 reset_ctrl = WDOG_B_CFG_COLD; 837 838 /* Set reset behavior on assertion of WDOG_B signal */ 839 ret = pf9453_pmic_write(pf9453, PF9453_REG_RESET_CTRL, WDOG_B_CFG_MASK, reset_ctrl); 840 if (ret) 841 return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n"); 842 843 /* 844 * The driver uses the LDO1OUT_H register to control the LDO1 regulator. 845 * This is only valid if the SD_VSEL input of the PMIC is high. Let's 846 * check if the pin is available as GPIO and set it to high. 847 */ 848 pf9453->sd_vsel_gpio = gpiod_get_optional(pf9453->dev, "sd-vsel", GPIOD_OUT_HIGH); 849 850 if (IS_ERR(pf9453->sd_vsel_gpio)) 851 return dev_err_probe(&i2c->dev, PTR_ERR(pf9453->sd_vsel_gpio), 852 "Failed to get SD_VSEL GPIO\n"); 853 854 return 0; 855 } 856 857 static const struct of_device_id pf9453_of_match[] = { 858 { 859 .compatible = "nxp,pf9453", 860 .data = pf9453_regulators, 861 }, 862 { } 863 }; 864 MODULE_DEVICE_TABLE(of, pf9453_of_match); 865 866 static struct i2c_driver pf9453_i2c_driver = { 867 .driver = { 868 .name = "nxp-pf9453", 869 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 870 .of_match_table = pf9453_of_match, 871 }, 872 .probe = pf9453_i2c_probe, 873 }; 874 875 module_i2c_driver(pf9453_i2c_driver); 876 877 MODULE_AUTHOR("Joy Zou <joy.zou@nxp.com>"); 878 MODULE_DESCRIPTION("NXP PF9453 Power Management IC driver"); 879 MODULE_LICENSE("GPL"); 880