xref: /linux/drivers/pmdomain/mediatek/mt8189-pm-domains.h (revision e41a25c53f96abe40edc5db1626d37a518852d84) 
1*6734a5e8SIrving-CH Lin /* SPDX-License-Identifier: GPL-2.0-only */
2*6734a5e8SIrving-CH Lin /*
3*6734a5e8SIrving-CH Lin  * Copyright (c) 2025 MediaTek Inc.
4*6734a5e8SIrving-CH Lin  * Author: Qiqi Wang <qiqi.wang@mediatek.com>
5*6734a5e8SIrving-CH Lin  */
6*6734a5e8SIrving-CH Lin 
7*6734a5e8SIrving-CH Lin #ifndef __SOC_MEDIATEK_MT8189_PM_DOMAINS_H
8*6734a5e8SIrving-CH Lin #define __SOC_MEDIATEK_MT8189_PM_DOMAINS_H
9*6734a5e8SIrving-CH Lin 
10*6734a5e8SIrving-CH Lin #include "mtk-pm-domains.h"
11*6734a5e8SIrving-CH Lin #include <dt-bindings/power/mediatek,mt8189-power.h>
12*6734a5e8SIrving-CH Lin 
13*6734a5e8SIrving-CH Lin /*
14*6734a5e8SIrving-CH Lin  * MT8189 power domain support
15*6734a5e8SIrving-CH Lin  */
16*6734a5e8SIrving-CH Lin 
17*6734a5e8SIrving-CH Lin #define MT8189_SPM_PWR_STATUS				0x0f40
18*6734a5e8SIrving-CH Lin #define MT8189_SPM_PWR_STATUS_2ND			0x0f44
19*6734a5e8SIrving-CH Lin #define MT8189_SPM_PWR_STATUS_MSB			0x0f48
20*6734a5e8SIrving-CH Lin #define MT8189_SPM_PWR_STATUS_MSB_2ND			0x0f4c
21*6734a5e8SIrving-CH Lin #define MT8189_SPM_XPU_PWR_STATUS			0x0f50
22*6734a5e8SIrving-CH Lin #define MT8189_SPM_XPU_PWR_STATUS_2ND			0x0f54
23*6734a5e8SIrving-CH Lin 
24*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_EMICFG_GALS_SLP_SET		0x0084
25*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_EMICFG_GALS_SLP_CLR		0x0088
26*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_EMICFG_GALS_SLP_RDY		0x008c
27*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_SET			0x0c14
28*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_CLR			0x0c18
29*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_RDY			0x0c1c
30*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_SET			0x0c24
31*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_CLR			0x0c28
32*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_RDY			0x0c2c
33*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_0_SET		0x0c44
34*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_0_CLR		0x0c48
35*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_0_RDY		0x0c4c
36*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_1_SET		0x0c54
37*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_1_CLR		0x0c58
38*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_1_RDY		0x0c5c
39*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_PERISYS_STA_0_SET		0x0c84
40*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_PERISYS_STA_0_CLR		0x0c88
41*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_PERISYS_STA_0_RDY		0x0c8c
42*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MCU_STA_0_SET			0x0c94
43*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MCU_STA_0_CLR			0x0c98
44*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MCU_STA_0_RDY			0x0c9c
45*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MD_STA_0_SET			0x0ca4
46*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MD_STA_0_CLR			0x0ca8
47*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MD_STA_0_RDY			0x0cac
48*6734a5e8SIrving-CH Lin 
49*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_EMISYS_STA_0_MM_INFRA		(GENMASK(21, 20))
50*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_0_CONN		(BIT(8))
51*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_1_CONN		(BIT(12))
52*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_0_MM_INFRA		(BIT(16))
53*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_1_MM_INFRA		(BIT(11))
54*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_INFRASYS_STA_1_MFG1		(BIT(20))
55*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MCU_STA_0_CONN			(BIT(1))
56*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MCU_STA_0_CONN_2ND		(BIT(0))
57*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MD_STA_0_MFG1			(BIT(0) | BIT(2))
58*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MD_STA_0_MFG1_2ND		(BIT(4))
59*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MM_INFRA_IGN			(BIT(1))
60*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MM_INFRA_2_IGN			(BIT(0))
61*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN		(GENMASK(31, 30))
62*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN		(GENMASK(10, 9))
63*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_DISP			(GENMASK(1, 0))
64*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1		(BIT(3))
65*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1		(BIT(7))
66*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE		(BIT(2))
67*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE		(BIT(8))
68*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_MDP0			(BIT(18))
69*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA		(GENMASK(3, 2))
70*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND		(GENMASK(15, 7))
71*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_VDE0			(BIT(20))
72*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_VDE0			(BIT(13))
73*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_0_VEN0			(BIT(12))
74*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_MMSYS_STA_1_VEN0			(BIT(12))
75*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_PERISYS_STA_0_AUDIO		(BIT(6))
76*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_PERISYS_STA_0_SSUSB		(BIT(7))
77*6734a5e8SIrving-CH Lin #define MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1		(GENMASK(5, 4))
78*6734a5e8SIrving-CH Lin 
79*6734a5e8SIrving-CH Lin static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8189[] = {
80*6734a5e8SIrving-CH Lin 	BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI
81*6734a5e8SIrving-CH Lin };
82*6734a5e8SIrving-CH Lin 
83*6734a5e8SIrving-CH Lin static const struct scpsys_domain_data scpsys_domain_data_mt8189[] = {
84*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_CONN] = {
85*6734a5e8SIrving-CH Lin 		.name = "conn",
86*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(1),
87*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe04,
88*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
89*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
90*6734a5e8SIrving-CH Lin 		.bp_cfg = {
91*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
92*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_CONN,
93*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_SET,
94*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_CLR,
95*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_RDY),
96*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
97*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_CONN,
98*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_SET,
99*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_CLR,
100*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_RDY),
101*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
102*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_CONN_2ND,
103*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_SET,
104*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_CLR,
105*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MCU_STA_0_RDY),
106*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
107*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_0_CONN,
108*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_0_SET,
109*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_0_CLR,
110*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_0_RDY),
111*6734a5e8SIrving-CH Lin 		},
112*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
113*6734a5e8SIrving-CH Lin 	},
114*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_AUDIO] = {
115*6734a5e8SIrving-CH Lin 		.name = "audio",
116*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(6),
117*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe18,
118*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
119*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
120*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
121*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
122*6734a5e8SIrving-CH Lin 		.bp_cfg = {
123*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
124*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_AUDIO,
125*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_SET,
126*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_CLR,
127*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_RDY),
128*6734a5e8SIrving-CH Lin 		},
129*6734a5e8SIrving-CH Lin 	},
130*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT] = {
131*6734a5e8SIrving-CH Lin 		.name = "adsp-top-dormant",
132*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(7),
133*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe1c,
134*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
135*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
136*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(9),
137*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(13),
138*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED |
139*6734a5e8SIrving-CH Lin 			MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
140*6734a5e8SIrving-CH Lin 	},
141*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_ADSP_INFRA] = {
142*6734a5e8SIrving-CH Lin 		.name = "adsp-infra",
143*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(8),
144*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
145*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
146*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe20,
147*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
148*6734a5e8SIrving-CH Lin 	},
149*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_ADSP_AO] = {
150*6734a5e8SIrving-CH Lin 		.name = "adsp-ao",
151*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(9),
152*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe24,
153*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
154*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
155*6734a5e8SIrving-CH Lin 	},
156*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_ISP_IMG1] = {
157*6734a5e8SIrving-CH Lin 		.name = "isp-img1",
158*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(10),
159*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe28,
160*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
161*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
162*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
163*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
164*6734a5e8SIrving-CH Lin 		.bp_cfg = {
165*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
166*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1,
167*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_SET,
168*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CLR,
169*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_RDY),
170*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
171*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1,
172*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_SET,
173*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CLR,
174*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_RDY),
175*6734a5e8SIrving-CH Lin 		},
176*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
177*6734a5e8SIrving-CH Lin 	},
178*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_ISP_IMG2] = {
179*6734a5e8SIrving-CH Lin 		.name = "isp-img2",
180*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(11),
181*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe2c,
182*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
183*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
184*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
185*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
186*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
187*6734a5e8SIrving-CH Lin 	},
188*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_ISP_IPE] = {
189*6734a5e8SIrving-CH Lin 		.name = "isp-ipe",
190*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(12),
191*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe30,
192*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
193*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
194*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
195*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
196*6734a5e8SIrving-CH Lin 		.bp_cfg = {
197*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
198*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE,
199*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_SET,
200*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CLR,
201*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_RDY),
202*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
203*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE,
204*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_SET,
205*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CLR,
206*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_RDY),
207*6734a5e8SIrving-CH Lin 		},
208*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
209*6734a5e8SIrving-CH Lin 	},
210*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_VDE0] = {
211*6734a5e8SIrving-CH Lin 		.name = "vde0",
212*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(14),
213*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe38,
214*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
215*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
216*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
217*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
218*6734a5e8SIrving-CH Lin 		.bp_cfg = {
219*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
220*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_VDE0,
221*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_SET,
222*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CLR,
223*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_RDY),
224*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
225*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_VDE0,
226*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_SET,
227*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CLR,
228*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_RDY),
229*6734a5e8SIrving-CH Lin 		},
230*6734a5e8SIrving-CH Lin 	},
231*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_VEN0] = {
232*6734a5e8SIrving-CH Lin 		.name = "ven0",
233*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(16),
234*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe40,
235*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
236*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
237*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
238*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
239*6734a5e8SIrving-CH Lin 		.bp_cfg = {
240*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
241*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_VEN0,
242*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_SET,
243*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CLR,
244*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_RDY),
245*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
246*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_VEN0,
247*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_SET,
248*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CLR,
249*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_RDY),
250*6734a5e8SIrving-CH Lin 		},
251*6734a5e8SIrving-CH Lin 	},
252*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_CAM_MAIN] = {
253*6734a5e8SIrving-CH Lin 		.name = "cam-main",
254*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(18),
255*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe48,
256*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
257*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
258*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
259*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
260*6734a5e8SIrving-CH Lin 		.bp_cfg = {
261*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
262*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN,
263*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_SET,
264*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CLR,
265*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_RDY),
266*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
267*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN,
268*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_SET,
269*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CLR,
270*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_RDY),
271*6734a5e8SIrving-CH Lin 		},
272*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
273*6734a5e8SIrving-CH Lin 	},
274*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_CAM_SUBA] = {
275*6734a5e8SIrving-CH Lin 		.name = "cam-suba",
276*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(20),
277*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe50,
278*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
279*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
280*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
281*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
282*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
283*6734a5e8SIrving-CH Lin 	},
284*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_CAM_SUBB] = {
285*6734a5e8SIrving-CH Lin 		.name = "cam-subb",
286*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(21),
287*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe54,
288*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
289*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
290*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
291*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
292*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
293*6734a5e8SIrving-CH Lin 	},
294*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_MDP0] = {
295*6734a5e8SIrving-CH Lin 		.name = "mdp0",
296*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(26),
297*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe68,
298*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
299*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
300*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
301*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
302*6734a5e8SIrving-CH Lin 		.bp_cfg = {
303*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
304*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_MDP0,
305*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_SET,
306*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CLR,
307*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_RDY),
308*6734a5e8SIrving-CH Lin 		},
309*6734a5e8SIrving-CH Lin 	},
310*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_DISP] = {
311*6734a5e8SIrving-CH Lin 		.name = "disp",
312*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(28),
313*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe70,
314*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
315*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
316*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
317*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
318*6734a5e8SIrving-CH Lin 		.bp_cfg = {
319*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
320*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_DISP,
321*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_SET,
322*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_CLR,
323*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_0_RDY),
324*6734a5e8SIrving-CH Lin 		},
325*6734a5e8SIrving-CH Lin 	},
326*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_MM_INFRA] = {
327*6734a5e8SIrving-CH Lin 		.name = "mm-infra",
328*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(30),
329*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe78,
330*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
331*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
332*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
333*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
334*6734a5e8SIrving-CH Lin 		.bp_cfg = {
335*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
336*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA,
337*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_SET,
338*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CLR,
339*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_RDY),
340*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
341*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND,
342*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_SET,
343*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_CLR,
344*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MMSYS_STA_1_RDY),
345*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN_SUBCLK(INFRA,
346*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MM_INFRA_IGN,
347*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MMSYS_STA_1_SET,
348*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MMSYS_STA_1_CLR,
349*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MMSYS_STA_1_RDY),
350*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN_SUBCLK(INFRA,
351*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MM_INFRA_2_IGN,
352*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MMSYS_STA_1_SET,
353*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MMSYS_STA_1_CLR,
354*6734a5e8SIrving-CH Lin 					       MT8189_PROT_EN_MMSYS_STA_1_RDY),
355*6734a5e8SIrving-CH Lin 		},
356*6734a5e8SIrving-CH Lin 	},
357*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_DP_TX] = {
358*6734a5e8SIrving-CH Lin 		.name = "dp-tx",
359*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(0),
360*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe80,
361*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
362*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
363*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
364*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
365*6734a5e8SIrving-CH Lin 	},
366*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_CSI_RX] = {
367*6734a5e8SIrving-CH Lin 		.name = "csi-rx",
368*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(7),
369*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xe9c,
370*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
371*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
372*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
373*6734a5e8SIrving-CH Lin 	},
374*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_SSUSB] = {
375*6734a5e8SIrving-CH Lin 		.name = "ssusb",
376*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(10),
377*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xea8,
378*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
379*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
380*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
381*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
382*6734a5e8SIrving-CH Lin 		.bp_cfg = {
383*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
384*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_SSUSB,
385*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_SET,
386*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_CLR,
387*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_PERISYS_STA_0_RDY),
388*6734a5e8SIrving-CH Lin 		},
389*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_ACTIVE_WAKEUP,
390*6734a5e8SIrving-CH Lin 	},
391*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_MFG0] = {
392*6734a5e8SIrving-CH Lin 		.name = "mfg0",
393*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(1),
394*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xeb4,
395*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
396*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
397*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_DOMAIN_SUPPLY,
398*6734a5e8SIrving-CH Lin 	},
399*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_MFG1] = {
400*6734a5e8SIrving-CH Lin 		.name = "mfg1",
401*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(2),
402*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xeb8,
403*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
404*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
405*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
406*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
407*6734a5e8SIrving-CH Lin 		.bp_cfg = {
408*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
409*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_MFG1,
410*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_SET,
411*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_CLR,
412*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_INFRASYS_STA_1_RDY),
413*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
414*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_MFG1,
415*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_SET,
416*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_CLR,
417*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_RDY),
418*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(INFRA,
419*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_MFG1_2ND,
420*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_SET,
421*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_CLR,
422*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_MD_STA_0_RDY),
423*6734a5e8SIrving-CH Lin 			BUS_PROT_WR_IGN(SMI,
424*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1,
425*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_EMICFG_GALS_SLP_SET,
426*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_EMICFG_GALS_SLP_CLR,
427*6734a5e8SIrving-CH Lin 					MT8189_PROT_EN_EMICFG_GALS_SLP_RDY),
428*6734a5e8SIrving-CH Lin 		},
429*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_DOMAIN_SUPPLY,
430*6734a5e8SIrving-CH Lin 	},
431*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_MFG2] = {
432*6734a5e8SIrving-CH Lin 		.name = "mfg2",
433*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(3),
434*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xebc,
435*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
436*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
437*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
438*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
439*6734a5e8SIrving-CH Lin 	},
440*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_MFG3] = {
441*6734a5e8SIrving-CH Lin 		.name = "mfg3",
442*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(4),
443*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xec0,
444*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
445*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
446*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
447*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
448*6734a5e8SIrving-CH Lin 	},
449*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_EDP_TX_DORMANT] = {
450*6734a5e8SIrving-CH Lin 		.name = "edp-tx-dormant",
451*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(12),
452*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xf70,
453*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
454*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
455*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(9),
456*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = 0,
457*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED,
458*6734a5e8SIrving-CH Lin 	},
459*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_PCIE] = {
460*6734a5e8SIrving-CH Lin 		.name = "pcie",
461*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(13),
462*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xf74,
463*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
464*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
465*6734a5e8SIrving-CH Lin 		.sram_pdn_bits = BIT(8),
466*6734a5e8SIrving-CH Lin 		.sram_pdn_ack_bits = BIT(12),
467*6734a5e8SIrving-CH Lin 		.caps = MTK_SCPD_ACTIVE_WAKEUP,
468*6734a5e8SIrving-CH Lin 	},
469*6734a5e8SIrving-CH Lin 	[MT8189_POWER_DOMAIN_PCIE_PHY] = {
470*6734a5e8SIrving-CH Lin 		.name = "pcie-phy",
471*6734a5e8SIrving-CH Lin 		.sta_mask = BIT(14),
472*6734a5e8SIrving-CH Lin 		.ctl_offs = 0xf78,
473*6734a5e8SIrving-CH Lin 		.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
474*6734a5e8SIrving-CH Lin 		.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
475*6734a5e8SIrving-CH Lin 	},
476*6734a5e8SIrving-CH Lin };
477*6734a5e8SIrving-CH Lin 
478*6734a5e8SIrving-CH Lin static const struct scpsys_soc_data mt8189_scpsys_data = {
479*6734a5e8SIrving-CH Lin 	.domains_data = scpsys_domain_data_mt8189,
480*6734a5e8SIrving-CH Lin 	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8189),
481*6734a5e8SIrving-CH Lin 	.bus_prot_blocks = scpsys_bus_prot_blocks_mt8189,
482*6734a5e8SIrving-CH Lin 	.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8189),
483*6734a5e8SIrving-CH Lin };
484*6734a5e8SIrving-CH Lin 
485*6734a5e8SIrving-CH Lin #endif /* __SOC_MEDIATEK_MT8189_PM_DOMAINS_H */
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