1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * Author: Qiqi Wang <qiqi.wang@mediatek.com> 5 */ 6 7 #ifndef __SOC_MEDIATEK_MT8189_PM_DOMAINS_H 8 #define __SOC_MEDIATEK_MT8189_PM_DOMAINS_H 9 10 #include "mtk-pm-domains.h" 11 #include <dt-bindings/power/mediatek,mt8189-power.h> 12 13 /* 14 * MT8189 power domain support 15 */ 16 17 #define MT8189_SPM_PWR_STATUS 0x0f40 18 #define MT8189_SPM_PWR_STATUS_2ND 0x0f44 19 #define MT8189_SPM_PWR_STATUS_MSB 0x0f48 20 #define MT8189_SPM_PWR_STATUS_MSB_2ND 0x0f4c 21 #define MT8189_SPM_XPU_PWR_STATUS 0x0f50 22 #define MT8189_SPM_XPU_PWR_STATUS_2ND 0x0f54 23 24 #define MT8189_PROT_EN_EMICFG_GALS_SLP_SET 0x0084 25 #define MT8189_PROT_EN_EMICFG_GALS_SLP_CLR 0x0088 26 #define MT8189_PROT_EN_EMICFG_GALS_SLP_RDY 0x008c 27 #define MT8189_PROT_EN_MMSYS_STA_0_SET 0x0c14 28 #define MT8189_PROT_EN_MMSYS_STA_0_CLR 0x0c18 29 #define MT8189_PROT_EN_MMSYS_STA_0_RDY 0x0c1c 30 #define MT8189_PROT_EN_MMSYS_STA_1_SET 0x0c24 31 #define MT8189_PROT_EN_MMSYS_STA_1_CLR 0x0c28 32 #define MT8189_PROT_EN_MMSYS_STA_1_RDY 0x0c2c 33 #define MT8189_PROT_EN_INFRASYS_STA_0_SET 0x0c44 34 #define MT8189_PROT_EN_INFRASYS_STA_0_CLR 0x0c48 35 #define MT8189_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c 36 #define MT8189_PROT_EN_INFRASYS_STA_1_SET 0x0c54 37 #define MT8189_PROT_EN_INFRASYS_STA_1_CLR 0x0c58 38 #define MT8189_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c 39 #define MT8189_PROT_EN_PERISYS_STA_0_SET 0x0c84 40 #define MT8189_PROT_EN_PERISYS_STA_0_CLR 0x0c88 41 #define MT8189_PROT_EN_PERISYS_STA_0_RDY 0x0c8c 42 #define MT8189_PROT_EN_MCU_STA_0_SET 0x0c94 43 #define MT8189_PROT_EN_MCU_STA_0_CLR 0x0c98 44 #define MT8189_PROT_EN_MCU_STA_0_RDY 0x0c9c 45 #define MT8189_PROT_EN_MD_STA_0_SET 0x0ca4 46 #define MT8189_PROT_EN_MD_STA_0_CLR 0x0ca8 47 #define MT8189_PROT_EN_MD_STA_0_RDY 0x0cac 48 49 #define MT8189_PROT_EN_EMISYS_STA_0_MM_INFRA (GENMASK(21, 20)) 50 #define MT8189_PROT_EN_INFRASYS_STA_0_CONN (BIT(8)) 51 #define MT8189_PROT_EN_INFRASYS_STA_1_CONN (BIT(12)) 52 #define MT8189_PROT_EN_INFRASYS_STA_0_MM_INFRA (BIT(16)) 53 #define MT8189_PROT_EN_INFRASYS_STA_1_MM_INFRA (BIT(11)) 54 #define MT8189_PROT_EN_INFRASYS_STA_1_MFG1 (BIT(20)) 55 #define MT8189_PROT_EN_MCU_STA_0_CONN (BIT(1)) 56 #define MT8189_PROT_EN_MCU_STA_0_CONN_2ND (BIT(0)) 57 #define MT8189_PROT_EN_MD_STA_0_MFG1 (BIT(0) | BIT(2)) 58 #define MT8189_PROT_EN_MD_STA_0_MFG1_2ND (BIT(4)) 59 #define MT8189_PROT_EN_MM_INFRA_IGN (BIT(1)) 60 #define MT8189_PROT_EN_MM_INFRA_2_IGN (BIT(0)) 61 #define MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN (GENMASK(31, 30)) 62 #define MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN (GENMASK(10, 9)) 63 #define MT8189_PROT_EN_MMSYS_STA_0_DISP (GENMASK(1, 0)) 64 #define MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1 (BIT(3)) 65 #define MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1 (BIT(7)) 66 #define MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE (BIT(2)) 67 #define MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE (BIT(8)) 68 #define MT8189_PROT_EN_MMSYS_STA_0_MDP0 (BIT(18)) 69 #define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 2)) 70 #define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (GENMASK(15, 7)) 71 #define MT8189_PROT_EN_MMSYS_STA_0_VDE0 (BIT(20)) 72 #define MT8189_PROT_EN_MMSYS_STA_1_VDE0 (BIT(13)) 73 #define MT8189_PROT_EN_MMSYS_STA_0_VEN0 (BIT(12)) 74 #define MT8189_PROT_EN_MMSYS_STA_1_VEN0 (BIT(12)) 75 #define MT8189_PROT_EN_PERISYS_STA_0_AUDIO (BIT(6)) 76 #define MT8189_PROT_EN_PERISYS_STA_0_SSUSB (BIT(7)) 77 #define MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1 (GENMASK(5, 4)) 78 79 static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8189[] = { 80 BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI 81 }; 82 83 static const struct scpsys_domain_data scpsys_domain_data_mt8189[] = { 84 [MT8189_POWER_DOMAIN_CONN] = { 85 .name = "conn", 86 .sta_mask = BIT(1), 87 .ctl_offs = 0xe04, 88 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 89 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 90 .bp_cfg = { 91 BUS_PROT_WR_IGN(INFRA, 92 MT8189_PROT_EN_MCU_STA_0_CONN, 93 MT8189_PROT_EN_MCU_STA_0_SET, 94 MT8189_PROT_EN_MCU_STA_0_CLR, 95 MT8189_PROT_EN_MCU_STA_0_RDY), 96 BUS_PROT_WR_IGN(INFRA, 97 MT8189_PROT_EN_INFRASYS_STA_1_CONN, 98 MT8189_PROT_EN_INFRASYS_STA_1_SET, 99 MT8189_PROT_EN_INFRASYS_STA_1_CLR, 100 MT8189_PROT_EN_INFRASYS_STA_1_RDY), 101 BUS_PROT_WR_IGN(INFRA, 102 MT8189_PROT_EN_MCU_STA_0_CONN_2ND, 103 MT8189_PROT_EN_MCU_STA_0_SET, 104 MT8189_PROT_EN_MCU_STA_0_CLR, 105 MT8189_PROT_EN_MCU_STA_0_RDY), 106 BUS_PROT_WR_IGN(INFRA, 107 MT8189_PROT_EN_INFRASYS_STA_0_CONN, 108 MT8189_PROT_EN_INFRASYS_STA_0_SET, 109 MT8189_PROT_EN_INFRASYS_STA_0_CLR, 110 MT8189_PROT_EN_INFRASYS_STA_0_RDY), 111 }, 112 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 113 }, 114 [MT8189_POWER_DOMAIN_AUDIO] = { 115 .name = "audio", 116 .sta_mask = BIT(6), 117 .ctl_offs = 0xe18, 118 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 119 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 120 .sram_pdn_bits = BIT(8), 121 .sram_pdn_ack_bits = BIT(12), 122 .bp_cfg = { 123 BUS_PROT_WR_IGN(INFRA, 124 MT8189_PROT_EN_PERISYS_STA_0_AUDIO, 125 MT8189_PROT_EN_PERISYS_STA_0_SET, 126 MT8189_PROT_EN_PERISYS_STA_0_CLR, 127 MT8189_PROT_EN_PERISYS_STA_0_RDY), 128 }, 129 }, 130 [MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT] = { 131 .name = "adsp-top-dormant", 132 .sta_mask = BIT(7), 133 .ctl_offs = 0xe1c, 134 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 135 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 136 .sram_pdn_bits = BIT(9), 137 .sram_pdn_ack_bits = BIT(13), 138 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED | 139 MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, 140 }, 141 [MT8189_POWER_DOMAIN_ADSP_INFRA] = { 142 .name = "adsp-infra", 143 .sta_mask = BIT(8), 144 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 145 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 146 .ctl_offs = 0xe20, 147 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 148 }, 149 [MT8189_POWER_DOMAIN_ADSP_AO] = { 150 .name = "adsp-ao", 151 .sta_mask = BIT(9), 152 .ctl_offs = 0xe24, 153 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 154 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 155 }, 156 [MT8189_POWER_DOMAIN_ISP_IMG1] = { 157 .name = "isp-img1", 158 .sta_mask = BIT(10), 159 .ctl_offs = 0xe28, 160 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 161 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 162 .sram_pdn_bits = BIT(8), 163 .sram_pdn_ack_bits = BIT(12), 164 .bp_cfg = { 165 BUS_PROT_WR_IGN(INFRA, 166 MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1, 167 MT8189_PROT_EN_MMSYS_STA_0_SET, 168 MT8189_PROT_EN_MMSYS_STA_0_CLR, 169 MT8189_PROT_EN_MMSYS_STA_0_RDY), 170 BUS_PROT_WR_IGN(INFRA, 171 MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1, 172 MT8189_PROT_EN_MMSYS_STA_1_SET, 173 MT8189_PROT_EN_MMSYS_STA_1_CLR, 174 MT8189_PROT_EN_MMSYS_STA_1_RDY), 175 }, 176 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 177 }, 178 [MT8189_POWER_DOMAIN_ISP_IMG2] = { 179 .name = "isp-img2", 180 .sta_mask = BIT(11), 181 .ctl_offs = 0xe2c, 182 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 183 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 184 .sram_pdn_bits = BIT(8), 185 .sram_pdn_ack_bits = BIT(12), 186 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 187 }, 188 [MT8189_POWER_DOMAIN_ISP_IPE] = { 189 .name = "isp-ipe", 190 .sta_mask = BIT(12), 191 .ctl_offs = 0xe30, 192 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 193 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 194 .sram_pdn_bits = BIT(8), 195 .sram_pdn_ack_bits = BIT(12), 196 .bp_cfg = { 197 BUS_PROT_WR_IGN(INFRA, 198 MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE, 199 MT8189_PROT_EN_MMSYS_STA_0_SET, 200 MT8189_PROT_EN_MMSYS_STA_0_CLR, 201 MT8189_PROT_EN_MMSYS_STA_0_RDY), 202 BUS_PROT_WR_IGN(INFRA, 203 MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE, 204 MT8189_PROT_EN_MMSYS_STA_1_SET, 205 MT8189_PROT_EN_MMSYS_STA_1_CLR, 206 MT8189_PROT_EN_MMSYS_STA_1_RDY), 207 }, 208 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 209 }, 210 [MT8189_POWER_DOMAIN_VDE0] = { 211 .name = "vde0", 212 .sta_mask = BIT(14), 213 .ctl_offs = 0xe38, 214 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 215 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 216 .sram_pdn_bits = BIT(8), 217 .sram_pdn_ack_bits = BIT(12), 218 .bp_cfg = { 219 BUS_PROT_WR_IGN(INFRA, 220 MT8189_PROT_EN_MMSYS_STA_0_VDE0, 221 MT8189_PROT_EN_MMSYS_STA_0_SET, 222 MT8189_PROT_EN_MMSYS_STA_0_CLR, 223 MT8189_PROT_EN_MMSYS_STA_0_RDY), 224 BUS_PROT_WR_IGN(INFRA, 225 MT8189_PROT_EN_MMSYS_STA_1_VDE0, 226 MT8189_PROT_EN_MMSYS_STA_1_SET, 227 MT8189_PROT_EN_MMSYS_STA_1_CLR, 228 MT8189_PROT_EN_MMSYS_STA_1_RDY), 229 }, 230 }, 231 [MT8189_POWER_DOMAIN_VEN0] = { 232 .name = "ven0", 233 .sta_mask = BIT(16), 234 .ctl_offs = 0xe40, 235 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 236 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 237 .sram_pdn_bits = BIT(8), 238 .sram_pdn_ack_bits = BIT(12), 239 .bp_cfg = { 240 BUS_PROT_WR_IGN(INFRA, 241 MT8189_PROT_EN_MMSYS_STA_0_VEN0, 242 MT8189_PROT_EN_MMSYS_STA_0_SET, 243 MT8189_PROT_EN_MMSYS_STA_0_CLR, 244 MT8189_PROT_EN_MMSYS_STA_0_RDY), 245 BUS_PROT_WR_IGN(INFRA, 246 MT8189_PROT_EN_MMSYS_STA_1_VEN0, 247 MT8189_PROT_EN_MMSYS_STA_1_SET, 248 MT8189_PROT_EN_MMSYS_STA_1_CLR, 249 MT8189_PROT_EN_MMSYS_STA_1_RDY), 250 }, 251 }, 252 [MT8189_POWER_DOMAIN_CAM_MAIN] = { 253 .name = "cam-main", 254 .sta_mask = BIT(18), 255 .ctl_offs = 0xe48, 256 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 257 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 258 .sram_pdn_bits = BIT(8), 259 .sram_pdn_ack_bits = BIT(12), 260 .bp_cfg = { 261 BUS_PROT_WR_IGN(INFRA, 262 MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN, 263 MT8189_PROT_EN_MMSYS_STA_0_SET, 264 MT8189_PROT_EN_MMSYS_STA_0_CLR, 265 MT8189_PROT_EN_MMSYS_STA_0_RDY), 266 BUS_PROT_WR_IGN(INFRA, 267 MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN, 268 MT8189_PROT_EN_MMSYS_STA_1_SET, 269 MT8189_PROT_EN_MMSYS_STA_1_CLR, 270 MT8189_PROT_EN_MMSYS_STA_1_RDY), 271 }, 272 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 273 }, 274 [MT8189_POWER_DOMAIN_CAM_SUBA] = { 275 .name = "cam-suba", 276 .sta_mask = BIT(20), 277 .ctl_offs = 0xe50, 278 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 279 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 280 .sram_pdn_bits = BIT(8), 281 .sram_pdn_ack_bits = BIT(12), 282 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 283 }, 284 [MT8189_POWER_DOMAIN_CAM_SUBB] = { 285 .name = "cam-subb", 286 .sta_mask = BIT(21), 287 .ctl_offs = 0xe54, 288 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 289 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 290 .sram_pdn_bits = BIT(8), 291 .sram_pdn_ack_bits = BIT(12), 292 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 293 }, 294 [MT8189_POWER_DOMAIN_MDP0] = { 295 .name = "mdp0", 296 .sta_mask = BIT(26), 297 .ctl_offs = 0xe68, 298 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 299 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 300 .sram_pdn_bits = BIT(8), 301 .sram_pdn_ack_bits = BIT(12), 302 .bp_cfg = { 303 BUS_PROT_WR_IGN(INFRA, 304 MT8189_PROT_EN_MMSYS_STA_0_MDP0, 305 MT8189_PROT_EN_MMSYS_STA_0_SET, 306 MT8189_PROT_EN_MMSYS_STA_0_CLR, 307 MT8189_PROT_EN_MMSYS_STA_0_RDY), 308 }, 309 }, 310 [MT8189_POWER_DOMAIN_DISP] = { 311 .name = "disp", 312 .sta_mask = BIT(28), 313 .ctl_offs = 0xe70, 314 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 315 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 316 .sram_pdn_bits = BIT(8), 317 .sram_pdn_ack_bits = BIT(12), 318 .bp_cfg = { 319 BUS_PROT_WR_IGN(INFRA, 320 MT8189_PROT_EN_MMSYS_STA_0_DISP, 321 MT8189_PROT_EN_MMSYS_STA_0_SET, 322 MT8189_PROT_EN_MMSYS_STA_0_CLR, 323 MT8189_PROT_EN_MMSYS_STA_0_RDY), 324 }, 325 }, 326 [MT8189_POWER_DOMAIN_MM_INFRA] = { 327 .name = "mm-infra", 328 .sta_mask = BIT(30), 329 .ctl_offs = 0xe78, 330 .pwr_sta_offs = MT8189_SPM_PWR_STATUS, 331 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, 332 .sram_pdn_bits = BIT(8), 333 .sram_pdn_ack_bits = BIT(12), 334 .bp_cfg = { 335 BUS_PROT_WR_IGN(INFRA, 336 MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA, 337 MT8189_PROT_EN_MMSYS_STA_1_SET, 338 MT8189_PROT_EN_MMSYS_STA_1_CLR, 339 MT8189_PROT_EN_MMSYS_STA_1_RDY), 340 BUS_PROT_WR_IGN(INFRA, 341 MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND, 342 MT8189_PROT_EN_MMSYS_STA_1_SET, 343 MT8189_PROT_EN_MMSYS_STA_1_CLR, 344 MT8189_PROT_EN_MMSYS_STA_1_RDY), 345 BUS_PROT_WR_IGN_SUBCLK(INFRA, 346 MT8189_PROT_EN_MM_INFRA_IGN, 347 MT8189_PROT_EN_MMSYS_STA_1_SET, 348 MT8189_PROT_EN_MMSYS_STA_1_CLR, 349 MT8189_PROT_EN_MMSYS_STA_1_RDY), 350 BUS_PROT_WR_IGN_SUBCLK(INFRA, 351 MT8189_PROT_EN_MM_INFRA_2_IGN, 352 MT8189_PROT_EN_MMSYS_STA_1_SET, 353 MT8189_PROT_EN_MMSYS_STA_1_CLR, 354 MT8189_PROT_EN_MMSYS_STA_1_RDY), 355 }, 356 }, 357 [MT8189_POWER_DOMAIN_DP_TX] = { 358 .name = "dp-tx", 359 .sta_mask = BIT(0), 360 .ctl_offs = 0xe80, 361 .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, 362 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, 363 .sram_pdn_bits = BIT(8), 364 .sram_pdn_ack_bits = BIT(12), 365 }, 366 [MT8189_POWER_DOMAIN_CSI_RX] = { 367 .name = "csi-rx", 368 .sta_mask = BIT(7), 369 .ctl_offs = 0xe9c, 370 .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, 371 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, 372 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 373 }, 374 [MT8189_POWER_DOMAIN_SSUSB] = { 375 .name = "ssusb", 376 .sta_mask = BIT(10), 377 .ctl_offs = 0xea8, 378 .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, 379 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, 380 .sram_pdn_bits = BIT(8), 381 .sram_pdn_ack_bits = BIT(12), 382 .bp_cfg = { 383 BUS_PROT_WR_IGN(INFRA, 384 MT8189_PROT_EN_PERISYS_STA_0_SSUSB, 385 MT8189_PROT_EN_PERISYS_STA_0_SET, 386 MT8189_PROT_EN_PERISYS_STA_0_CLR, 387 MT8189_PROT_EN_PERISYS_STA_0_RDY), 388 }, 389 .caps = MTK_SCPD_ACTIVE_WAKEUP, 390 }, 391 [MT8189_POWER_DOMAIN_MFG0] = { 392 .name = "mfg0", 393 .sta_mask = BIT(1), 394 .ctl_offs = 0xeb4, 395 .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, 396 .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, 397 .caps = MTK_SCPD_DOMAIN_SUPPLY, 398 }, 399 [MT8189_POWER_DOMAIN_MFG1] = { 400 .name = "mfg1", 401 .sta_mask = BIT(2), 402 .ctl_offs = 0xeb8, 403 .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, 404 .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, 405 .sram_pdn_bits = BIT(8), 406 .sram_pdn_ack_bits = BIT(12), 407 .bp_cfg = { 408 BUS_PROT_WR_IGN(INFRA, 409 MT8189_PROT_EN_INFRASYS_STA_1_MFG1, 410 MT8189_PROT_EN_INFRASYS_STA_1_SET, 411 MT8189_PROT_EN_INFRASYS_STA_1_CLR, 412 MT8189_PROT_EN_INFRASYS_STA_1_RDY), 413 BUS_PROT_WR_IGN(INFRA, 414 MT8189_PROT_EN_MD_STA_0_MFG1, 415 MT8189_PROT_EN_MD_STA_0_SET, 416 MT8189_PROT_EN_MD_STA_0_CLR, 417 MT8189_PROT_EN_MD_STA_0_RDY), 418 BUS_PROT_WR_IGN(INFRA, 419 MT8189_PROT_EN_MD_STA_0_MFG1_2ND, 420 MT8189_PROT_EN_MD_STA_0_SET, 421 MT8189_PROT_EN_MD_STA_0_CLR, 422 MT8189_PROT_EN_MD_STA_0_RDY), 423 BUS_PROT_WR_IGN(SMI, 424 MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1, 425 MT8189_PROT_EN_EMICFG_GALS_SLP_SET, 426 MT8189_PROT_EN_EMICFG_GALS_SLP_CLR, 427 MT8189_PROT_EN_EMICFG_GALS_SLP_RDY), 428 }, 429 .caps = MTK_SCPD_DOMAIN_SUPPLY, 430 }, 431 [MT8189_POWER_DOMAIN_MFG2] = { 432 .name = "mfg2", 433 .sta_mask = BIT(3), 434 .ctl_offs = 0xebc, 435 .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, 436 .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, 437 .sram_pdn_bits = BIT(8), 438 .sram_pdn_ack_bits = BIT(12), 439 }, 440 [MT8189_POWER_DOMAIN_MFG3] = { 441 .name = "mfg3", 442 .sta_mask = BIT(4), 443 .ctl_offs = 0xec0, 444 .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, 445 .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, 446 .sram_pdn_bits = BIT(8), 447 .sram_pdn_ack_bits = BIT(12), 448 }, 449 [MT8189_POWER_DOMAIN_EDP_TX_DORMANT] = { 450 .name = "edp-tx-dormant", 451 .sta_mask = BIT(12), 452 .ctl_offs = 0xf70, 453 .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, 454 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, 455 .sram_pdn_bits = BIT(9), 456 .sram_pdn_ack_bits = 0, 457 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED, 458 }, 459 [MT8189_POWER_DOMAIN_PCIE] = { 460 .name = "pcie", 461 .sta_mask = BIT(13), 462 .ctl_offs = 0xf74, 463 .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, 464 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, 465 .sram_pdn_bits = BIT(8), 466 .sram_pdn_ack_bits = BIT(12), 467 .caps = MTK_SCPD_ACTIVE_WAKEUP, 468 }, 469 [MT8189_POWER_DOMAIN_PCIE_PHY] = { 470 .name = "pcie-phy", 471 .sta_mask = BIT(14), 472 .ctl_offs = 0xf78, 473 .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, 474 .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, 475 }, 476 }; 477 478 static const struct scpsys_soc_data mt8189_scpsys_data = { 479 .domains_data = scpsys_domain_data_mt8189, 480 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8189), 481 .bus_prot_blocks = scpsys_bus_prot_blocks_mt8189, 482 .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8189), 483 }; 484 485 #endif /* __SOC_MEDIATEK_MT8189_PM_DOMAINS_H */ 486