1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * KY Liu <ky.liu@mediatek.com> 5 * Copyright (c) 2026 Jolla Mobile Ltd 6 * Nikolai Burov <nikolai.burov@jolla.com> 7 */ 8 9 #ifndef __SOC_MEDIATEK_MT6858_PM_DOMAINS_H 10 #define __SOC_MEDIATEK_MT6858_PM_DOMAINS_H 11 12 #include "mtk-pm-domains.h" 13 #include <dt-bindings/power/mediatek,mt6858-power.h> 14 15 /* TOP_AXI registers */ 16 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET 0x0c14 17 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR 0x0c18 18 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY 0x0c1c 19 20 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_DIS0 (BIT(0) | BIT(1) | BIT(18)) 21 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IPE BIT(2) 22 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IMG1 BIT(3) 23 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VEN0 BIT(12) 24 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VDE0 BIT(20) 25 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CAM_MAIN (BIT(30) | BIT(31)) 26 27 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET 0x0c24 28 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR 0x0c28 29 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY 0x0c2c 30 31 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IMG1 BIT(7) 32 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IPE BIT(8) 33 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CAM_MAIN (BIT(9) | BIT(10)) 34 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VEN0 BIT(12) 35 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VDE0 BIT(13) 36 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 1) | BIT(6)) 37 #define MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (BIT(0) | BIT(5) | GENMASK(15, 7)) 38 39 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET 0x0c44 40 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR 0x0c48 41 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c 42 43 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CONN BIT(8) 44 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_MM_INFRA BIT(16) 45 46 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET 0x0c54 47 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR 0x0c58 48 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c 49 50 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_MM_INFRA BIT(11) 51 #define MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CONN BIT(12) 52 53 #define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_SET 0x0c64 54 #define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_CLR 0x0c68 55 #define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_RDY 0x0c6c 56 57 #define MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_MM_INFRA (BIT(20) | BIT(21)) 58 59 #define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET 0x0c84 60 #define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR 0x0c88 61 #define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY 0x0c8c 62 63 #define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_AUDIO BIT(6) 64 #define MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SSUSB BIT(7) 65 66 #define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET 0x0c94 67 #define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR 0x0c98 68 #define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY 0x0c9c 69 70 #define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN BIT(1) 71 #define MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN_2ND BIT(0) 72 73 /* {IMG,IPE,CAM}_SUBx registers */ 74 #define MT6858_SUBx_PROT_EN_SET 0x03c4 75 #define MT6858_SUBx_PROT_EN_CLR 0x03c8 76 #define MT6858_SUBx_PROT_EN_STA 0x03cc 77 78 #define MT6858_IMG_SUB0_PROT_EN_SMI_ISP_IMG1 (BIT(0) | BIT(1)) 79 80 #define MT6858_IPE_SUB0_PROT_EN_SMI_ISP_IPE (BIT(0) | BIT(1)) 81 82 #define MT6858_CAM_SUB0_PROT_EN_SMI_CAM_MAIN BIT(0) 83 #define MT6858_CAM_SUB0_PROT_EN_SMI_CAM_SUBB BIT(1) 84 85 #define MT6858_CAM_SUB1_PROT_EN_SMI_CAM_MAIN BIT(0) 86 #define MT6858_CAM_SUB1_PROT_EN_SMI_CAM_SUBA BIT(1) 87 88 /* VLP_AXI registers */ 89 #define MT6858_VLP_AXI_PROT_EN_SET 0x0214 90 #define MT6858_VLP_AXI_PROT_EN_CLR 0x0218 91 #define MT6858_VLP_AXI_PROT_EN_STA 0x021c 92 93 #define MT6858_VLP_AXI_PROT_EN_MM_PROC BIT(8) 94 #define MT6858_VLP_AXI_PROT_EN_MM_PROC_2ND (BIT(9) | BIT(10)) 95 96 /* PWR_CON registers */ 97 #define MT6858_PWR_ACK BIT(30) 98 #define MT6858_PWR_ACK_2ND BIT(31) 99 100 static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt6858[] = { 101 BUS_PROT_BLOCK_INFRA, 102 BUS_PROT_BLOCK_IMG_SUB0, 103 BUS_PROT_BLOCK_CAM_SUB1, 104 BUS_PROT_BLOCK_CAM_SUB0, 105 BUS_PROT_BLOCK_IPE_SUB0, 106 BUS_PROT_BLOCK_VLP, 107 }; 108 109 static const struct scpsys_domain_data scpsys_domain_data_mt6858[] = { 110 [MT6858_POWER_DOMAIN_MD] = { 111 .name = "md", 112 /* 113 * Note: the PWR_ACK_2ND bit is not used for the modem domain. 114 * Skip it and fall back to checking the 1st bit twice. 115 */ 116 .sta_mask = MT6858_PWR_ACK, 117 .ctl_offs = 0xe00, 118 .pwr_sta_offs = 0xe00, 119 .pwr_sta2nd_offs = 0xe00, 120 .ext_buck_iso_offs = 0xf20, 121 .ext_buck_iso_mask = GENMASK(1, 0), 122 .caps = MTK_SCPD_MODEM_SECURE_PWRSEQ | MTK_SCPD_EXT_BUCK_ISO | 123 MTK_SCPD_KEEP_DEFAULT_OFF, 124 }, 125 [MT6858_POWER_DOMAIN_CONN] = { 126 .name = "conn", 127 .sta_mask = MT6858_PWR_ACK, 128 .sta2nd_mask = MT6858_PWR_ACK_2ND, 129 .ctl_offs = 0xe04, 130 .pwr_sta_offs = 0xe04, 131 .pwr_sta2nd_offs = 0xe04, 132 .bp_cfg = { 133 BUS_PROT_WR_IGN(INFRA, 134 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN, 135 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET, 136 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR, 137 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY), 138 BUS_PROT_WR_IGN(INFRA, 139 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CONN, 140 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET, 141 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR, 142 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY), 143 BUS_PROT_WR_IGN(INFRA, 144 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CONN_2ND, 145 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_SET, 146 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_CLR, 147 MT6858_TOP_AXI_PROT_EN_MCU_STA_0_RDY), 148 BUS_PROT_WR_IGN(INFRA, 149 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CONN, 150 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET, 151 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR, 152 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY), 153 }, 154 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 155 }, 156 [MT6858_POWER_DOMAIN_AUDIO] = { 157 .name = "audio", 158 .sta_mask = MT6858_PWR_ACK, 159 .sta2nd_mask = MT6858_PWR_ACK_2ND, 160 .ctl_offs = 0xe18, 161 .pwr_sta_offs = 0xe18, 162 .pwr_sta2nd_offs = 0xe18, 163 .sram_pdn_bits = BIT(8), 164 .sram_pdn_ack_bits = BIT(12), 165 .bp_cfg = { 166 BUS_PROT_WR_IGN(INFRA, 167 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_AUDIO, 168 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET, 169 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR, 170 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY), 171 }, 172 }, 173 [MT6858_POWER_DOMAIN_ISP_IMG1] = { 174 .name = "isp-img1", 175 .sta_mask = MT6858_PWR_ACK, 176 .sta2nd_mask = MT6858_PWR_ACK_2ND, 177 .ctl_offs = 0xe28, 178 .pwr_sta_offs = 0xe28, 179 .pwr_sta2nd_offs = 0xe28, 180 .sram_pdn_bits = BIT(8), 181 .sram_pdn_ack_bits = BIT(12), 182 .bp_cfg = { 183 BUS_PROT_WR_IGN(INFRA, 184 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IMG1, 185 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET, 186 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR, 187 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY), 188 BUS_PROT_WR_IGN(INFRA, 189 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IMG1, 190 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET, 191 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR, 192 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY), 193 BUS_PROT_WR_IGN(IMG_SUB0, 194 MT6858_IMG_SUB0_PROT_EN_SMI_ISP_IMG1, 195 MT6858_SUBx_PROT_EN_SET, 196 MT6858_SUBx_PROT_EN_CLR, 197 MT6858_SUBx_PROT_EN_STA), 198 }, 199 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 200 }, 201 [MT6858_POWER_DOMAIN_ISP_IMG2] = { 202 .name = "isp-img2", 203 .sta_mask = MT6858_PWR_ACK, 204 .sta2nd_mask = MT6858_PWR_ACK_2ND, 205 .ctl_offs = 0xe2c, 206 .pwr_sta_offs = 0xe2c, 207 .pwr_sta2nd_offs = 0xe2c, 208 .sram_pdn_bits = BIT(8), 209 .sram_pdn_ack_bits = BIT(12), 210 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 211 }, 212 [MT6858_POWER_DOMAIN_ISP_IPE] = { 213 .name = "isp-ipe", 214 .sta_mask = MT6858_PWR_ACK, 215 .sta2nd_mask = MT6858_PWR_ACK_2ND, 216 .ctl_offs = 0xe30, 217 .pwr_sta_offs = 0xe30, 218 .pwr_sta2nd_offs = 0xe30, 219 .sram_pdn_bits = BIT(8), 220 .sram_pdn_ack_bits = BIT(12), 221 .bp_cfg = { 222 BUS_PROT_WR_IGN(INFRA, 223 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_ISP_IPE, 224 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET, 225 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR, 226 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY), 227 BUS_PROT_WR_IGN(INFRA, 228 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_ISP_IPE, 229 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET, 230 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR, 231 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY), 232 BUS_PROT_WR_IGN(IPE_SUB0, 233 MT6858_IPE_SUB0_PROT_EN_SMI_ISP_IPE, 234 MT6858_SUBx_PROT_EN_SET, 235 MT6858_SUBx_PROT_EN_CLR, 236 MT6858_SUBx_PROT_EN_STA), 237 }, 238 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 239 }, 240 [MT6858_POWER_DOMAIN_VDE0] = { 241 .name = "vde0", 242 .sta_mask = MT6858_PWR_ACK, 243 .sta2nd_mask = MT6858_PWR_ACK_2ND, 244 .ctl_offs = 0xe34, 245 .pwr_sta_offs = 0xe34, 246 .pwr_sta2nd_offs = 0xe34, 247 .sram_pdn_bits = BIT(8), 248 .sram_pdn_ack_bits = BIT(12), 249 .bp_cfg = { 250 BUS_PROT_WR_IGN(INFRA, 251 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VDE0, 252 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET, 253 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR, 254 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY), 255 BUS_PROT_WR_IGN(INFRA, 256 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VDE0, 257 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET, 258 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR, 259 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY), 260 }, 261 }, 262 [MT6858_POWER_DOMAIN_VEN0] = { 263 .name = "ven0", 264 .sta_mask = MT6858_PWR_ACK, 265 .sta2nd_mask = MT6858_PWR_ACK_2ND, 266 .ctl_offs = 0xe3c, 267 .pwr_sta_offs = 0xe3c, 268 .pwr_sta2nd_offs = 0xe3c, 269 .sram_pdn_bits = BIT(8), 270 .sram_pdn_ack_bits = BIT(12), 271 .bp_cfg = { 272 BUS_PROT_WR_IGN(INFRA, 273 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_VEN0, 274 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET, 275 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR, 276 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY), 277 BUS_PROT_WR_IGN(INFRA, 278 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_VEN0, 279 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET, 280 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR, 281 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY), 282 }, 283 }, 284 [MT6858_POWER_DOMAIN_CAM_MAIN] = { 285 .name = "cam-main", 286 .sta_mask = MT6858_PWR_ACK, 287 .sta2nd_mask = MT6858_PWR_ACK_2ND, 288 .ctl_offs = 0xe44, 289 .pwr_sta_offs = 0xe44, 290 .pwr_sta2nd_offs = 0xe44, 291 .sram_pdn_bits = BIT(8), 292 .sram_pdn_ack_bits = BIT(12), 293 .bp_cfg = { 294 BUS_PROT_WR_IGN(INFRA, 295 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CAM_MAIN, 296 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET, 297 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR, 298 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY), 299 BUS_PROT_WR_IGN(INFRA, 300 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CAM_MAIN, 301 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET, 302 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR, 303 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY), 304 BUS_PROT_WR_IGN(CAM_SUB0, 305 MT6858_CAM_SUB0_PROT_EN_SMI_CAM_MAIN, 306 MT6858_SUBx_PROT_EN_SET, 307 MT6858_SUBx_PROT_EN_CLR, 308 MT6858_SUBx_PROT_EN_STA), 309 BUS_PROT_WR_IGN(CAM_SUB1, 310 MT6858_CAM_SUB1_PROT_EN_SMI_CAM_MAIN, 311 MT6858_SUBx_PROT_EN_SET, 312 MT6858_SUBx_PROT_EN_CLR, 313 MT6858_SUBx_PROT_EN_STA), 314 }, 315 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 316 }, 317 [MT6858_POWER_DOMAIN_CAM_SUBA] = { 318 .name = "cam-suba", 319 .sta_mask = MT6858_PWR_ACK, 320 .sta2nd_mask = MT6858_PWR_ACK_2ND, 321 .ctl_offs = 0xe4c, 322 .pwr_sta_offs = 0xe4c, 323 .pwr_sta2nd_offs = 0xe4c, 324 .sram_pdn_bits = BIT(8), 325 .sram_pdn_ack_bits = BIT(12), 326 .bp_cfg = { 327 BUS_PROT_WR_IGN(CAM_SUB1, 328 MT6858_CAM_SUB1_PROT_EN_SMI_CAM_SUBA, 329 MT6858_SUBx_PROT_EN_SET, 330 MT6858_SUBx_PROT_EN_CLR, 331 MT6858_SUBx_PROT_EN_STA), 332 }, 333 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 334 }, 335 [MT6858_POWER_DOMAIN_CAM_SUBB] = { 336 .name = "cam-subb", 337 .sta_mask = MT6858_PWR_ACK, 338 .sta2nd_mask = MT6858_PWR_ACK_2ND, 339 .ctl_offs = 0xe50, 340 .pwr_sta_offs = 0xe50, 341 .pwr_sta2nd_offs = 0xe50, 342 .sram_pdn_bits = BIT(8), 343 .sram_pdn_ack_bits = BIT(12), 344 .bp_cfg = { 345 BUS_PROT_WR_IGN(CAM_SUB0, 346 MT6858_CAM_SUB0_PROT_EN_SMI_CAM_SUBB, 347 MT6858_SUBx_PROT_EN_SET, 348 MT6858_SUBx_PROT_EN_CLR, 349 MT6858_SUBx_PROT_EN_STA), 350 }, 351 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 352 }, 353 [MT6858_POWER_DOMAIN_DIS0] = { 354 .name = "dis0", 355 .sta_mask = MT6858_PWR_ACK, 356 .sta2nd_mask = MT6858_PWR_ACK_2ND, 357 .ctl_offs = 0xe6c, 358 .pwr_sta_offs = 0xe6c, 359 .pwr_sta2nd_offs = 0xe6c, 360 .sram_pdn_bits = BIT(8), 361 .sram_pdn_ack_bits = BIT(12), 362 .bp_cfg = { 363 BUS_PROT_WR_IGN(INFRA, 364 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_DIS0, 365 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_SET, 366 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_CLR, 367 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_0_RDY), 368 }, 369 }, 370 [MT6858_POWER_DOMAIN_MM_INFRA] = { 371 .name = "mm-infra", 372 .sta_mask = MT6858_PWR_ACK, 373 .sta2nd_mask = MT6858_PWR_ACK_2ND, 374 .ctl_offs = 0xe74, 375 .pwr_sta_offs = 0xe74, 376 .pwr_sta2nd_offs = 0xe74, 377 .sram_pdn_bits = BIT(8), 378 .sram_pdn_ack_bits = BIT(12), 379 .bp_cfg = { 380 BUS_PROT_WR_IGN(INFRA, 381 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA, 382 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET, 383 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR, 384 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY), 385 BUS_PROT_WR_IGN(INFRA, 386 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_MM_INFRA, 387 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_SET, 388 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_CLR, 389 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_1_RDY), 390 BUS_PROT_WR_IGN(INFRA, 391 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND, 392 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_SET, 393 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_CLR, 394 MT6858_TOP_AXI_PROT_EN_MMSYS_STA_1_RDY), 395 BUS_PROT_WR_IGN(INFRA, 396 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_MM_INFRA, 397 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_SET, 398 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_CLR, 399 MT6858_TOP_AXI_PROT_EN_INFRASYS_STA_0_RDY), 400 BUS_PROT_WR_IGN(INFRA, 401 MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_MM_INFRA, 402 MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_SET, 403 MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_CLR, 404 MT6858_TOP_AXI_PROT_EN_EMISYS_STA_0_RDY), 405 }, 406 }, 407 [MT6858_POWER_DOMAIN_MM_PROC_DORMANT] = { 408 .name = "mm-proc-dormant", 409 .sta_mask = MT6858_PWR_ACK, 410 .sta2nd_mask = MT6858_PWR_ACK_2ND, 411 .ctl_offs = 0xe78, 412 .pwr_sta_offs = 0xe78, 413 .pwr_sta2nd_offs = 0xe78, 414 .sram_pdn_bits = BIT(9), 415 .sram_pdn_ack_bits = BIT(13), 416 .bp_cfg = { 417 BUS_PROT_WR_IGN(VLP, 418 MT6858_VLP_AXI_PROT_EN_MM_PROC, 419 MT6858_VLP_AXI_PROT_EN_SET, 420 MT6858_VLP_AXI_PROT_EN_CLR, 421 MT6858_VLP_AXI_PROT_EN_STA), 422 BUS_PROT_WR_IGN(VLP, 423 MT6858_VLP_AXI_PROT_EN_MM_PROC_2ND, 424 MT6858_VLP_AXI_PROT_EN_SET, 425 MT6858_VLP_AXI_PROT_EN_CLR, 426 MT6858_VLP_AXI_PROT_EN_STA), 427 }, 428 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED, 429 }, 430 [MT6858_POWER_DOMAIN_CSI_RX] = { 431 .name = "csi-rx", 432 .sta_mask = MT6858_PWR_ACK, 433 .sta2nd_mask = MT6858_PWR_ACK_2ND, 434 .ctl_offs = 0xe98, 435 .pwr_sta_offs = 0xe98, 436 .pwr_sta2nd_offs = 0xe98, 437 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 438 }, 439 [MT6858_POWER_DOMAIN_SSUSB] = { 440 .name = "ssusb", 441 .sta_mask = MT6858_PWR_ACK, 442 .sta2nd_mask = MT6858_PWR_ACK_2ND, 443 .ctl_offs = 0xea4, 444 .pwr_sta_offs = 0xea4, 445 .pwr_sta2nd_offs = 0xea4, 446 .sram_pdn_bits = BIT(8), 447 .sram_pdn_ack_bits = BIT(12), 448 .bp_cfg = { 449 BUS_PROT_WR_IGN(INFRA, 450 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SSUSB, 451 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_SET, 452 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_CLR, 453 MT6858_TOP_AXI_PROT_EN_PERISYS_STA_0_RDY), 454 }, 455 }, 456 }; 457 458 static const struct scpsys_soc_data mt6858_scpsys_data = { 459 .domains_data = scpsys_domain_data_mt6858, 460 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6858), 461 .bus_prot_blocks = scpsys_bus_prot_blocks_mt6858, 462 .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt6858), 463 .type = SCPSYS_MTCMOS_TYPE_DIRECT_CTL, 464 }; 465 466 #endif /* __SOC_MEDIATEK_MT6858_PM_DOMAINS_H */ 467