1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Nova Lake PCH. 5 * 6 * Copyright (c) 2026, Intel Corporation. 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/pci.h> 11 12 #include "core.h" 13 14 /* PMC SSRAM PMT Telemetry GUIDS */ 15 #define PCDH_LPM_REQ_GUID 0x01093101 16 #define PCHS_LPM_REQ_GUID 0x01092101 17 #define PCDS_LPM_REQ_GUID 0x01091102 18 19 /* 20 * Die Mapping to Product. 21 * Product PCDDie PCHDie 22 * NVL-H PCD-H None 23 * NVL-S PCD-S PCH-S 24 */ 25 26 static const struct pmc_bit_map nvl_pcdh_pfear_map[] = { 27 {"PMC_PGD0", BIT(0)}, 28 {"FUSE_OSSE_PGD0", BIT(1)}, 29 {"SPI_PGD0", BIT(2)}, 30 {"XHCI_PGD0", BIT(3)}, 31 {"SPA_PGD0", BIT(4)}, 32 {"SPB_PGD0", BIT(5)}, 33 {"MPFPW2_PGD0", BIT(6)}, 34 {"GBE_PGD0", BIT(7)}, 35 36 {"SBR16B20_PGD0", BIT(0)}, 37 {"DBG_SBR_PGD0", BIT(1)}, 38 {"SBR16B7_PGD0", BIT(2)}, 39 {"STRC_PGD0", BIT(3)}, 40 {"SBR16B8_PGD0", BIT(4)}, 41 {"D2D_DISP_PGD1", BIT(5)}, 42 {"LPSS_PGD0", BIT(6)}, 43 {"LPC_PGD0", BIT(7)}, 44 45 {"SMB_PGD0", BIT(0)}, 46 {"ISH_PGD0", BIT(1)}, 47 {"SBR16B2_PGD0", BIT(2)}, 48 {"NPK_PGD0", BIT(3)}, 49 {"D2D_NOC_PGD1", BIT(4)}, 50 {"DBG_SBR16B_PGD0", BIT(5)}, 51 {"FUSE_PGD0", BIT(6)}, 52 {"SBR16B0_PGD0", BIT(7)}, 53 54 {"P2SB0_PGD0", BIT(0)}, 55 {"OTG_PGD0", BIT(1)}, 56 {"EXI_PGD0", BIT(2)}, 57 {"CSE_PGD0", BIT(3)}, 58 {"CSME_KVM_PGD0", BIT(4)}, 59 {"CSME_PMT_PGD0", BIT(5)}, 60 {"CSME_CLINK_PGD0", BIT(6)}, 61 {"SBR16B21_PGD0", BIT(7)}, 62 63 {"CSME_USBR_PGD0", BIT(0)}, 64 {"SBR16B22_PGD0", BIT(1)}, 65 {"CSME_SMT1_PGD0", BIT(2)}, 66 {"MPFPW1_PGD0", BIT(3)}, 67 {"CSME_SMS2_PGD0", BIT(4)}, 68 {"CSME_SMS_PGD0", BIT(5)}, 69 {"CSME_RTC_PGD0", BIT(6)}, 70 {"CSMEPSF_PGD0", BIT(7)}, 71 72 {"D2D_NOC_PGD0", BIT(0)}, 73 {"ESE_PGD0", BIT(1)}, 74 {"SBR16B6_PGD0", BIT(2)}, 75 {"P2SB1_PGD0", BIT(3)}, 76 {"SBR16B3_PGD0", BIT(4)}, 77 {"OSSE_SMT1_PGD0", BIT(5)}, 78 {"D2D_DISP_PGD0", BIT(6)}, 79 {"SNPS_USB2_A_PGD0", BIT(7)}, 80 81 {"U3FPW1_PGD0", BIT(0)}, 82 {"FIA_X_PGD0", BIT(1)}, 83 {"PSF4_PGD0", BIT(2)}, 84 {"CNVI_PGD0", BIT(3)}, 85 {"UFSX2_PGD0", BIT(4)}, 86 {"ENDBG_PGD0", BIT(5)}, 87 {"DBC_PGD0", BIT(6)}, 88 {"FIA_PG_PGD0", BIT(7)}, 89 90 {"D2D_IPU_PGD0", BIT(0)}, 91 {"NPK_PGD1", BIT(1)}, 92 {"FIACPCB_X_PGD0", BIT(2)}, 93 {"SBR8B4_PGD0", BIT(3)}, 94 {"DBG_PSF_PGD0", BIT(4)}, 95 {"PSF6_PGD0", BIT(5)}, 96 {"UFSPW1_PGD0", BIT(6)}, 97 {"FIA_U_PGD0", BIT(7)}, 98 99 {"PSF8_PGD0", BIT(0)}, 100 {"SBR16B9_PGD0", BIT(1)}, 101 {"PSF0_PGD0", BIT(2)}, 102 {"FIACPCB_U_PGD0", BIT(3)}, 103 {"TAM_PGD0", BIT(4)}, 104 {"D2D_NOC_PGD2", BIT(5)}, 105 {"SBR8B2_PGD0", BIT(6)}, 106 {"THC0_PGD0", BIT(7)}, 107 108 {"THC1_PGD0", BIT(0)}, 109 {"PMC_PGD1", BIT(1)}, 110 {"DISP_PGA1_PGD0", BIT(2)}, 111 {"TCSS_PGD0", BIT(3)}, 112 {"DISP_PGA_PGD0", BIT(4)}, 113 {"SBR16B1_PGD0", BIT(5)}, 114 {"SBRG_PGD0", BIT(6)}, 115 {"PSF5_PGD0", BIT(7)}, 116 117 {"SBR8B3_PGD0", BIT(0)}, 118 {"ACE_PGD0", BIT(1)}, 119 {"ACE_PGD1", BIT(2)}, 120 {"ACE_PGD2", BIT(3)}, 121 {"ACE_PGD3", BIT(4)}, 122 {"ACE_PGD4", BIT(5)}, 123 {"ACE_PGD5", BIT(6)}, 124 {"ACE_PGD6", BIT(7)}, 125 126 {"ACE_PGD7", BIT(0)}, 127 {"ACE_PGD8", BIT(1)}, 128 {"ACE_PGD9", BIT(2)}, 129 {"ACE_PGD10", BIT(3)}, 130 {"FIACPCB_PG_PGD0", BIT(4)}, 131 {"SNPS_USB2_B_PGD0", BIT(5)}, 132 {"OSSE_PGD0", BIT(6)}, 133 {"SBR8B0_PGD0", BIT(7)}, 134 135 {"SBR16B4_PGD0", BIT(0)}, 136 {"CSME_PTIO_PGD0", BIT(1)}, 137 {} 138 }; 139 140 static const struct pmc_bit_map *ext_nvl_pcdh_pfear_map[] = { 141 nvl_pcdh_pfear_map, 142 NULL 143 }; 144 145 static const struct pmc_bit_map nvl_pcdh_clocksource_status_map[] = { 146 {"AON2_OFF_STS", BIT(0), 1}, 147 {"AON3_OFF_STS", BIT(1), 0}, 148 {"AON4_OFF_STS", BIT(2), 1}, 149 {"AON5_OFF_STS", BIT(3), 1}, 150 {"AON1_OFF_STS", BIT(4), 0}, 151 {"XTAL_LVM_OFF_STS", BIT(5), 0}, 152 {"MPFPW1_0_PLL_OFF_STS", BIT(6), 1}, 153 {"D2D_PLL_OFF_STS", BIT(7), 1}, 154 {"USB3_PLL_OFF_STS", BIT(8), 1}, 155 {"AON3_SPL_OFF_STS", BIT(9), 1}, 156 {"MPFPW2_0_PLL_OFF_STS", BIT(12), 1}, 157 {"XTAL_AGGR_OFF_STS", BIT(17), 1}, 158 {"USB2_PLL_OFF_STS", BIT(18), 0}, 159 {"DDI2_PLL_OFF_STS", BIT(19), 1}, 160 {"SE_TCSS_PLL_OFF_STS", BIT(20), 1}, 161 {"DDI_PLL_OFF_STS", BIT(21), 1}, 162 {"FILTER_PLL_OFF_STS", BIT(22), 1}, 163 {"ACE_PLL_OFF_STS", BIT(24), 0}, 164 {"FABRIC_PLL_OFF_STS", BIT(25), 1}, 165 {"SOC_PLL_OFF_STS", BIT(26), 1}, 166 {"REF_PLL_OFF_STS", BIT(28), 1}, 167 {"IMG_PLL_OFF_STS", BIT(29), 1}, 168 {"GENLOCK_FILTER_PLL_OFF_STS", BIT(30), 1}, 169 {"RTC_PLL_OFF_STS", BIT(31), 0}, 170 {} 171 }; 172 173 static const struct pmc_bit_map nvl_pcdh_power_gating_status_0_map[] = { 174 {"PMC_PGD0_PG_STS", BIT(0), 0}, 175 {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0}, 176 {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, 177 {"XHCI_PGD0_PG_STS", BIT(3), 1}, 178 {"SPA_PGD0_PG_STS", BIT(4), 1}, 179 {"SPB_PGD0_PG_STS", BIT(5), 1}, 180 {"MPFPW2_PGD0_PG_STS", BIT(6), 0}, 181 {"GBE_PGD0_PG_STS", BIT(7), 1}, 182 {"SBR16B20_PGD0_PG_STS", BIT(8), 0}, 183 {"DBG_PGD0_PG_STS", BIT(9), 0}, 184 {"SBR16B7_PGD0_PG_STS", BIT(10), 0}, 185 {"STRC_PGD0_PG_STS", BIT(11), 0}, 186 {"SBR16B8_PGD0_PG_STS", BIT(12), 0}, 187 {"D2D_DISP_PGD1_PG_STS", BIT(13), 1}, 188 {"LPSS_PGD0_PG_STS", BIT(14), 1}, 189 {"LPC_PGD0_PG_STS", BIT(15), 0}, 190 {"SMB_PGD0_PG_STS", BIT(16), 0}, 191 {"ISH_PGD0_PG_STS", BIT(17), 0}, 192 {"SBR16B2_PGD0_PG_STS", BIT(18), 0}, 193 {"NPK_PGD0_PG_STS", BIT(19), 0}, 194 {"D2D_NOC_PGD1_PG_STS", BIT(20), 1}, 195 {"DBG_SBR16B_PGD0_PG_STS", BIT(21), 0}, 196 {"FUSE_PGD0_PG_STS", BIT(22), 0}, 197 {"SBR16B0_PGD0_PG_STS", BIT(23), 0}, 198 {"P2SB0_PGD0_PG_STS", BIT(24), 1}, 199 {"XDCI_PGD0_PG_STS", BIT(25), 1}, 200 {"EXI_PGD0_PG_STS", BIT(26), 0}, 201 {"CSE_PGD0_PG_STS", BIT(27), 1}, 202 {"KVMCC_PGD0_PG_STS", BIT(28), 1}, 203 {"PMT_PGD0_PG_STS", BIT(29), 1}, 204 {"CLINK_PGD0_PG_STS", BIT(30), 1}, 205 {"SBR16B21_PGD0_PG_STS", BIT(31), 0}, 206 {} 207 }; 208 209 static const struct pmc_bit_map nvl_pcdh_power_gating_status_1_map[] = { 210 {"USBR0_PGD0_PG_STS", BIT(0), 1}, 211 {"SBR16B22_PGD0_PG_STS", BIT(1), 0}, 212 {"SMT1_PGD0_PG_STS", BIT(2), 1}, 213 {"MPFPW1_PGD0_PG_STS", BIT(3), 0}, 214 {"SMS2_PGD0_PG_STS", BIT(4), 1}, 215 {"SMS1_PGD0_PG_STS", BIT(5), 1}, 216 {"CSMERTC_PGD0_PG_STS", BIT(6), 0}, 217 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0}, 218 {"D2D_NOC_PGD0_PG_STS", BIT(8), 0}, 219 {"ESE_PGD0_PG_STS", BIT(9), 1}, 220 {"SBR16B6_PGD0_PG_STS", BIT(10), 0}, 221 {"P2SB1_PGD0_PG_STS", BIT(11), 1}, 222 {"SBR16B3_PGD0_PG_STS", BIT(12), 0}, 223 {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1}, 224 {"D2D_DISP_PGD0_PG_STS", BIT(14), 1}, 225 {"SNPA_USB2_A_PGD0_PG_STS", BIT(15), 0}, 226 {"U3FPW1_PGD0_PG_STS", BIT(16), 0}, 227 {"FIA_X_PGD0_PG_STS", BIT(17), 0}, 228 {"PSF4_PGD0_PG_STS", BIT(18), 0}, 229 {"CNVI_PGD0_PG_STS", BIT(19), 0}, 230 {"UFSX2_PGD0_PG_STS", BIT(20), 1}, 231 {"ENDBG_PGD0_PG_STS", BIT(21), 0}, 232 {"DBC_PGD0_PG_STS", BIT(22), 0}, 233 {"FIA_PG_PGD0_PG_STS", BIT(23), 0}, 234 {"D2D_IPU_PGD0_PG_STS", BIT(24), 1}, 235 {"NPK_PGD1_PG_STS", BIT(25), 0}, 236 {"FIACPCB_X_PGD0_PG_STS", BIT(26), 0}, 237 {"SBR8B4_PGD0_PG_STS", BIT(27), 0}, 238 {"DBG_PSF_PGD0_PG_STS", BIT(28), 0}, 239 {"PSF6_PGD0_PG_STS", BIT(29), 0}, 240 {"UFSPW1_PGD0_PG_STS", BIT(30), 0}, 241 {"FIA_U_PGD0_PG_STS", BIT(31), 0}, 242 {} 243 }; 244 245 static const struct pmc_bit_map nvl_pcdh_power_gating_status_2_map[] = { 246 {"PSF8_PGD0_PG_STS", BIT(0), 0}, 247 {"SBR16B9_PGD0_PG_STS", BIT(1), 0}, 248 {"PSF0_PGD0_PG_STS", BIT(2), 0}, 249 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0}, 250 {"TAM_PGD0_PG_STS", BIT(4), 1}, 251 {"D2D_NOC_PGD2_PG_STS", BIT(5), 1}, 252 {"SBR8B2_PGD0_PG_STS", BIT(6), 0}, 253 {"THC0_PGD0_PG_STS", BIT(7), 1}, 254 {"THC1_PGD0_PG_STS", BIT(8), 1}, 255 {"PMC_PGD1_PG_STS", BIT(9), 0}, 256 {"DISP_PGA1_PGD0_PG_STS", BIT(10), 0}, 257 {"TCSS_PGD0_PG_STS", BIT(11), 0}, 258 {"DISP_PGA_PGD0_PG_STS", BIT(12), 0}, 259 {"SBR16B1_PGD0_PG_STS", BIT(13), 0}, 260 {"SBRG_PGD0_PG_STS", BIT(14), 0}, 261 {"PSF5_PGD0_PG_STS", BIT(15), 0}, 262 {"SBR8B3_PGD0_PG_STS", BIT(16), 0}, 263 {"ACE_PGD0_PG_STS", BIT(17), 0}, 264 {"ACE_PGD1_PG_STS", BIT(18), 0}, 265 {"ACE_PGD2_PG_STS", BIT(19), 0}, 266 {"ACE_PGD3_PG_STS", BIT(20), 0}, 267 {"ACE_PGD4_PG_STS", BIT(21), 0}, 268 {"ACE_PGD5_PG_STS", BIT(22), 0}, 269 {"ACE_PGD6_PG_STS", BIT(23), 0}, 270 {"ACE_PGD7_PG_STS", BIT(24), 0}, 271 {"ACE_PGD8_PG_STS", BIT(25), 0}, 272 {"ACE_PGD9_PG_STS", BIT(26), 0}, 273 {"ACE_PGD10_PG_STS", BIT(27), 0}, 274 {"FIACPCB_PG_PGD0_PG_STS", BIT(28), 0}, 275 {"SNPS_USB2_B_PGD0_PG_STS", BIT(29), 0}, 276 {"OSSE_PGD0_PG_STS", BIT(30), 1}, 277 {"SBR8B0_PGD0_PG_STS", BIT(31), 0}, 278 {} 279 }; 280 281 static const struct pmc_bit_map nvl_pcdh_power_gating_status_3_map[] = { 282 {"SBR16B4_PGD0_PG_STS", BIT(0), 0}, 283 {"PTIO_PGD0_PG_STS", BIT(1), 1}, 284 {} 285 }; 286 287 static const struct pmc_bit_map nvl_pcdh_d3_status_0_map[] = { 288 {"LPSS_D3_STS", BIT(3), 1}, 289 {"XDCI_D3_STS", BIT(4), 1}, 290 {"XHCI_D3_STS", BIT(5), 1}, 291 {"OSSE_D3_STS", BIT(6), 0}, 292 {"SPA_D3_STS", BIT(12), 0}, 293 {"SPB_D3_STS", BIT(13), 0}, 294 {"ESPISPI_D3_STS", BIT(18), 0}, 295 {"PSTH_D3_STS", BIT(21), 0}, 296 {} 297 }; 298 299 static const struct pmc_bit_map nvl_pcdh_d3_status_1_map[] = { 300 {"OSSE_SMT1_D3_STS", BIT(0), 0}, 301 {"GBE_D3_STS", BIT(19), 0}, 302 {"ITSS_D3_STS", BIT(23), 0}, 303 {"CNVI_D3_STS", BIT(27), 0}, 304 {"UFSX2_D3_STS", BIT(28), 0}, 305 {"ESE_D3_STS", BIT(29), 0}, 306 {} 307 }; 308 309 static const struct pmc_bit_map nvl_pcdh_d3_status_2_map[] = { 310 {"CSMERTC_D3_STS", BIT(1), 0}, 311 {"CSE_D3_STS", BIT(4), 0}, 312 {"KVMCC_D3_STS", BIT(5), 0}, 313 {"USBR0_D3_STS", BIT(6), 0}, 314 {"ISH_D3_STS", BIT(7), 0}, 315 {"SMT1_D3_STS", BIT(8), 0}, 316 {"SMT2_D3_STS", BIT(9), 0}, 317 {"SMT3_D3_STS", BIT(10), 0}, 318 {"OSSE_SMT2_D3_STS", BIT(11), 0}, 319 {"CLINK_D3_STS", BIT(14), 0}, 320 {"PTIO_D3_STS", BIT(16), 0}, 321 {"PMT_D3_STS", BIT(17), 0}, 322 {"SMS1_D3_STS", BIT(18), 0}, 323 {"SMS2_D3_STS", BIT(19), 0}, 324 {} 325 }; 326 327 static const struct pmc_bit_map nvl_pcdh_d3_status_3_map[] = { 328 {"THC0_D3_STS", BIT(14), 1}, 329 {"THC1_D3_STS", BIT(15), 1}, 330 {"OSSE_SMT3_D3_STS", BIT(16), 0}, 331 {"ACE_D3_STS", BIT(23), 0}, 332 {} 333 }; 334 335 static const struct pmc_bit_map nvl_pcdh_vnn_req_status_0_map[] = { 336 {"LPSS_VNN_REQ_STS", BIT(3), 1}, 337 {"OSSE_VNN_REQ_STS", BIT(6), 1}, 338 {"ESPISPI_VNN_REQ_STS", BIT(18), 1}, 339 {} 340 }; 341 342 static const struct pmc_bit_map nvl_pcdh_vnn_req_status_1_map[] = { 343 {"OSSE_SMT1_VNN_REQ_STS", BIT(0), 1}, 344 {"NPK_VNN_REQ_STS", BIT(4), 1}, 345 {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, 346 {"EXI_VNN_REQ_STS", BIT(9), 1}, 347 {"P2D_VNN_REQ_STS", BIT(18), 1}, 348 {"GBE_VNN_REQ_STS", BIT(19), 1}, 349 {"SMB_VNN_REQ_STS", BIT(25), 1}, 350 {"LPC_VNN_REQ_STS", BIT(26), 0}, 351 {"ESE_VNN_REQ_STS", BIT(29), 1}, 352 {} 353 }; 354 355 static const struct pmc_bit_map nvl_pcdh_vnn_req_status_2_map[] = { 356 {"CSMERTC_VNN_REQ_STS", BIT(1), 1}, 357 {"CSE_VNN_REQ_STS", BIT(4), 1}, 358 {"ISH_VNN_REQ_STS", BIT(7), 1}, 359 {"SMT1_VNN_REQ_STS", BIT(8), 1}, 360 {"CLINK_VNN_REQ_STS", BIT(14), 1}, 361 {"SMS1_VNN_REQ_STS", BIT(18), 1}, 362 {"SMS2_VNN_REQ_STS", BIT(19), 1}, 363 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 1}, 364 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1}, 365 {"DISP_SHIM_VNN_REQ_STS", BIT(22), 1}, 366 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1}, 367 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1}, 368 {} 369 }; 370 371 static const struct pmc_bit_map nvl_pcdh_vnn_req_status_3_map[] = { 372 {"DTS0_VNN_REQ_STS", BIT(7), 0}, 373 {"GPIOCOM5_VNN_REQ_STS", BIT(11), 1}, 374 {} 375 }; 376 377 static const struct pmc_bit_map nvl_pcdh_vnn_misc_status_map[] = { 378 {"CPU_C10_REQ_STS", BIT(0), 0}, 379 {"TS_OFF_REQ_STS", BIT(1), 0}, 380 {"PNDE_MET_REQ_STS", BIT(2), 1}, 381 {"PG5_PMA0_REQ_STS", BIT(3), 1}, 382 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0}, 383 {"VNN_SOC_REQ_STS", BIT(6), 1}, 384 {"ISH_VNNAON_REQ_STS", BIT(7), 0}, 385 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1}, 386 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1}, 387 {"D2D_IPU_QACTIVE_REQ_STS", BIT(10), 1}, 388 {"PLT_GREATER_REQ_STS", BIT(11), 1}, 389 {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0}, 390 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0}, 391 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0}, 392 {"EA_REQ_STS", BIT(15), 0}, 393 {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0}, 394 {"BRK_EV_EN_REQ_STS", BIT(17), 0}, 395 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0}, 396 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1}, 397 {"ARC_IDLE_REQ_STS", BIT(21), 0}, 398 {"PG5_PMA1_REQ_STS", BIT(22), 1}, 399 {"FIA_DEEP_PM_REQ_STS", BIT(23), 0}, 400 {"XDCI_ATTACHED_REQ_STS", BIT(24), 1}, 401 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0}, 402 {"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1}, 403 {"PRE_WAKE0_REQ_STS", BIT(27), 1}, 404 {"PRE_WAKE1_REQ_STS", BIT(28), 1}, 405 {"PRE_WAKE2_REQ_STS", BIT(29), 1}, 406 {"PG5_PMA2_GVNN", BIT(30), 1}, 407 {"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31), 1}, 408 {} 409 }; 410 411 static const struct pmc_bit_map nvl_pcdh_rsc_status_map[] = { 412 {"CORE", 0, 1}, 413 {"Memory", 0, 1}, 414 {"PRIM_D2D", 0, 1}, 415 {"PSF0", 0, 1}, 416 {"PSF4", 0, 1}, 417 {"PSF6", 0, 1}, 418 {"PSF8", 0, 1}, 419 {"SB", 0, 1}, 420 {} 421 }; 422 423 static const struct pmc_bit_map *nvl_pcdh_lpm_maps[] = { 424 nvl_pcdh_clocksource_status_map, 425 nvl_pcdh_power_gating_status_0_map, 426 nvl_pcdh_power_gating_status_1_map, 427 nvl_pcdh_power_gating_status_2_map, 428 nvl_pcdh_power_gating_status_3_map, 429 nvl_pcdh_d3_status_0_map, 430 nvl_pcdh_d3_status_1_map, 431 nvl_pcdh_d3_status_2_map, 432 nvl_pcdh_d3_status_3_map, 433 nvl_pcdh_vnn_req_status_0_map, 434 nvl_pcdh_vnn_req_status_1_map, 435 nvl_pcdh_vnn_req_status_2_map, 436 nvl_pcdh_vnn_req_status_3_map, 437 nvl_pcdh_vnn_misc_status_map, 438 ptl_pcdp_signal_status_map, 439 NULL 440 }; 441 442 static const struct pmc_bit_map *nvl_pcdh_blk_maps[] = { 443 nvl_pcdh_power_gating_status_0_map, 444 nvl_pcdh_power_gating_status_1_map, 445 nvl_pcdh_power_gating_status_2_map, 446 nvl_pcdh_power_gating_status_3_map, 447 nvl_pcdh_rsc_status_map, 448 nvl_pcdh_vnn_req_status_0_map, 449 nvl_pcdh_vnn_req_status_1_map, 450 nvl_pcdh_vnn_req_status_2_map, 451 nvl_pcdh_vnn_req_status_3_map, 452 nvl_pcdh_d3_status_0_map, 453 nvl_pcdh_d3_status_1_map, 454 nvl_pcdh_d3_status_2_map, 455 nvl_pcdh_d3_status_3_map, 456 nvl_pcdh_clocksource_status_map, 457 nvl_pcdh_vnn_misc_status_map, 458 ptl_pcdp_signal_status_map, 459 NULL 460 }; 461 462 static const struct pmc_bit_map nvl_pcds_pfear_map[] = { 463 {"PMC_PGD0", BIT(0)}, 464 {"FUSE_OSSE_PGD0", BIT(1)}, 465 {"SPI_PGD0", BIT(2)}, 466 {"XHCI_PGD0", BIT(3)}, 467 {"SPA_PGD0", BIT(4)}, 468 {"SPB_PGD0", BIT(5)}, 469 {"RSVD6", BIT(6)}, 470 {"GBE_PGD0", BIT(7)}, 471 472 {"RSVD8", BIT(0)}, 473 {"RSVD9", BIT(1)}, 474 {"SBR16B7_PGD0", BIT(2)}, 475 {"SBR16B21_PGD0", BIT(3)}, 476 {"RSVD12", BIT(4)}, 477 {"D2D_DISP_PGD1", BIT(5)}, 478 {"LPSS_PGD0", BIT(6)}, 479 {"LPC_PGD0", BIT(7)}, 480 481 {"SMB_PGD0", BIT(0)}, 482 {"ISH_PGD0", BIT(1)}, 483 {"SBR16B1_PGD0", BIT(2)}, 484 {"NPK_PGD0", BIT(3)}, 485 {"D2D_NOC_PGD1", BIT(4)}, 486 {"DBG_SBR16B_PGD0", BIT(5)}, 487 {"FUSE_PGD0", BIT(6)}, 488 {"RSVD23", BIT(7)}, 489 490 {"P2SB0_PGD0", BIT(0)}, 491 {"OTG_PGD0", BIT(1)}, 492 {"EXI_PGD0", BIT(2)}, 493 {"CSE_PGD0", BIT(3)}, 494 {"CSME_KVM_PGD0", BIT(4)}, 495 {"CSME_PMT_PGD0", BIT(5)}, 496 {"CSME_CLINK_PGD0", BIT(6)}, 497 {"CSME_PTIO_PGD0", BIT(7)}, 498 499 {"CSME_USBR_PGD0", BIT(0)}, 500 {"SBR16B22_PGD0", BIT(1)}, 501 {"CSME_SMT1_PGD0", BIT(2)}, 502 {"P2SB1_PGD0", BIT(3)}, 503 {"CSME_SMS2_PGD0", BIT(4)}, 504 {"CSME_SMS_PGD0", BIT(5)}, 505 {"CSME_RTC_PGD0", BIT(6)}, 506 {"CSMEPSF_PGD0", BIT(7)}, 507 508 {"D2D_NOC_PGD0", BIT(0)}, 509 {"RSVD41", BIT(1)}, 510 {"RSVD42", BIT(2)}, 511 {"RSVD43", BIT(3)}, 512 {"SBR16B2_PGD0", BIT(4)}, 513 {"OSSE_SMT1_PGD0", BIT(5)}, 514 {"D2D_DISP_PGD0", BIT(6)}, 515 {"RSVD47_PGD0", BIT(7)}, 516 517 {"RSVD48", BIT(0)}, 518 {"DBG_PSF_PGD0", BIT(1)}, 519 {"RSVD50", BIT(2)}, 520 {"CNVI_PGD0", BIT(3)}, 521 {"UFSX2_PGD0", BIT(4)}, 522 {"ENDBG_PGD0", BIT(5)}, 523 {"DBC_PGD0", BIT(6)}, 524 {"SBR16B4_PGD0", BIT(7)}, 525 526 {"RSVD56", BIT(0)}, 527 {"NPK_PGD1", BIT(1)}, 528 {"RSVD58", BIT(2)}, 529 {"SBR16B20_PGD0", BIT(3)}, 530 {"RSVD60", BIT(4)}, 531 {"SBR8B20_PGD0", BIT(5)}, 532 {"RSVD62", BIT(6)}, 533 {"FIA_U_PGD0", BIT(7)}, 534 535 {"PSF8_PGD0", BIT(0)}, 536 {"RSVD65", BIT(1)}, 537 {"RSVD66", BIT(2)}, 538 {"FIACPCB_U_PGD0", BIT(3)}, 539 {"TAM_PGD0", BIT(4)}, 540 {"D2D_NOC_PGD2", BIT(5)}, 541 {"SBR8B2_PGD0", BIT(6)}, 542 {"THC0_PGD0", BIT(7)}, 543 544 {"THC1_PGD0", BIT(0)}, 545 {"PMC_PGD1", BIT(1)}, 546 {"SBR16B3_PGD0", BIT(2)}, 547 {"TCSS_PGD0", BIT(3)}, 548 {"DISP_PGA_PGD0", BIT(4)}, 549 {"RSVD77", BIT(5)}, 550 {"RSVD78", BIT(6)}, 551 {"RSVD79", BIT(7)}, 552 553 {"SBRG_PGD0", BIT(0)}, 554 {"RSVD81", BIT(1)}, 555 {"SBR16B0_PGD0", BIT(2)}, 556 {"SBR8B0_PGD0", BIT(3)}, 557 {"PSF7_PGD0", BIT(4)}, 558 {"RSVD85", BIT(5)}, 559 {"RSVD86", BIT(6)}, 560 {"RSVD87", BIT(7)}, 561 562 {"SBR16B6_PGD0", BIT(0)}, 563 {"PSD0_PGD0", BIT(1)}, 564 {"STRC_PGD0", BIT(2)}, 565 {"RSVD91", BIT(3)}, 566 {"DBG_SBR_PGD0", BIT(4)}, 567 {"RSVD93", BIT(5)}, 568 {"OSSE_PGD0", BIT(6)}, 569 {"DISP_PGA1_PGD0", BIT(7)}, 570 {} 571 }; 572 573 static const struct pmc_bit_map *ext_nvl_pcds_pfear_map[] = { 574 nvl_pcds_pfear_map, 575 NULL 576 }; 577 578 static const struct pmc_bit_map nvl_pcds_ltr_show_map[] = { 579 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 580 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 581 {"SATA", CNP_PMC_LTR_SATA}, 582 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 583 {"XHCI", CNP_PMC_LTR_XHCI}, 584 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 585 {"ME", CNP_PMC_LTR_ME}, 586 {"SATA1", CNP_PMC_LTR_EVA}, 587 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 588 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 589 {"CNV", CNP_PMC_LTR_CNV}, 590 {"LPSS", CNP_PMC_LTR_LPSS}, 591 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 592 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 593 {"SATA2", PTL_PMC_LTR_SATA2}, 594 {"ESPI", CNP_PMC_LTR_ESPI}, 595 {"SCC", CNP_PMC_LTR_SCC}, 596 {"ISH", CNP_PMC_LTR_ISH}, 597 {"UFSX2", CNP_PMC_LTR_UFSX2}, 598 {"EMMC", CNP_PMC_LTR_EMMC}, 599 {"WIGIG", ICL_PMC_LTR_WIGIG}, 600 {"THC0", TGL_PMC_LTR_THC0}, 601 {"THC1", TGL_PMC_LTR_THC1}, 602 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 603 {"RSVD", NVL_PCDS_PMC_LTR_RESERVED}, 604 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 605 {"DMI3", ARL_PMC_LTR_DMI3}, 606 {"OSSE", LNL_PMC_LTR_OSSE}, 607 608 /* Below two cannot be used for LTR_IGNORE */ 609 {"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT}, 610 {"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT}, 611 {} 612 }; 613 614 static const struct pmc_bit_map nvl_pcds_clocksource_status_map[] = { 615 {"AON2_OFF_STS", BIT(0), 1}, 616 {"AON3_OFF_STS", BIT(1), 0}, 617 {"AON4_OFF_STS", BIT(2), 1}, 618 {"AON5_OFF_STS", BIT(3), 1}, 619 {"AON1_OFF_STS", BIT(4), 0}, 620 {"XTAL_LVM_OFF_STS", BIT(5), 0}, 621 {"D2D_OFF_STS", BIT(8), 1}, 622 {"AON3_SPL_OFF_STS", BIT(9), 1}, 623 {"XTAL_AGGR_OFF_STS", BIT(17), 1}, 624 {"BCLK_EXT_INJ_OFF_STS", BIT(18), 1}, 625 {"DDI2_PLL_OFF_STS", BIT(19), 1}, 626 {"SE_TCSS_PLL_OFF_STS", BIT(20), 1}, 627 {"DDI_PLL_OFF_STS", BIT(21), 1}, 628 {"FILTER_PLL_OFF_STS", BIT(22), 1}, 629 {"PHY_OC_EXT_INJ_OFF_STS", BIT(23), 1}, 630 {"ACE_PLL_OFF_STS", BIT(24), 0}, 631 {"FABRIC_PLL_OFF_STS", BIT(25), 1}, 632 {"SOC_PLL_OFF_STS", BIT(26), 1}, 633 {"REF_PLL_OFF_STS", BIT(28), 1}, 634 {"GENLOCK_FILTER_PLL_OFF_STS", BIT(30), 1}, 635 {"RTC_PLL_OFF_STS", BIT(31), 0}, 636 {} 637 }; 638 639 static const struct pmc_bit_map nvl_pcds_power_gating_status_0_map[] = { 640 {"PMC_PGD0_PG_STS", BIT(0), 0}, 641 {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0}, 642 {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, 643 {"XHCI_PGD0_PG_STS", BIT(3), 0}, 644 {"SPA_PGD0_PG_STS", BIT(4), 0}, 645 {"SPB_PGD0_PG_STS", BIT(5), 0}, 646 {"RSVD_6", BIT(6), 0}, 647 {"GBE_PGD0_PG_STS", BIT(7), 0}, 648 {"RSVD_8", BIT(8), 0}, 649 {"RSVD_9", BIT(9), 0}, 650 {"SBR16B7_PGD0_PG_STS", BIT(10), 0}, 651 {"SBR16B21_PGD0_PG_STS", BIT(11), 0}, 652 {"RSVD_12", BIT(12), 0}, 653 {"D2D_DISP_PGD1_PG_STS", BIT(13), 1}, 654 {"LPSS_PGD0_PG_STS", BIT(14), 0}, 655 {"LPC_PGD0_PG_STS", BIT(15), 0}, 656 {"SMB_PGD0_PG_STS", BIT(16), 0}, 657 {"ISH_PGD0_PG_STS", BIT(17), 0}, 658 {"SBR16B1_PGD0_PG_STS", BIT(18), 0}, 659 {"NPK_PGD0_PG_STS", BIT(19), 0}, 660 {"D2D_NOC_PGD1_PG_STS", BIT(20), 1}, 661 {"DBG_SBR16B_PGD0_PG_STS", BIT(21), 0}, 662 {"FUSE_PGD0_PG_STS", BIT(22), 0}, 663 {"RSVD_23", BIT(23), 0}, 664 {"P2SB0_PGD0_PG_STS", BIT(24), 1}, 665 {"XDCI_PGD0_PG_STS", BIT(25), 0}, 666 {"EXI_PGD0_PG_STS", BIT(26), 0}, 667 {"CSE_PGD0_PG_STS", BIT(27), 1}, 668 {"KVMCC_PGD0_PG_STS", BIT(28), 0}, 669 {"PMT_PGD0_PG_STS", BIT(29), 0}, 670 {"CLINK_PGD0_PG_STS", BIT(30), 0}, 671 {"PTIO_PGD0_PG_STS", BIT(31), 0}, 672 {} 673 }; 674 675 static const struct pmc_bit_map nvl_pcds_power_gating_status_1_map[] = { 676 {"USBR0_PGD0_PG_STS", BIT(0), 0}, 677 {"SBR16B22_PGD0_PG_STS", BIT(1), 0}, 678 {"SMT1_PGD0_PG_STS", BIT(2), 0}, 679 {"P2SB1_PGD0_PG_STS", BIT(3), 1}, 680 {"SMS2_PGD0_PG_STS", BIT(4), 0}, 681 {"SMS1_PGD0_PG_STS", BIT(5), 0}, 682 {"CSMERTC_PGD0_PG_STS", BIT(6), 0}, 683 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0}, 684 {"D2D_NOC_PGD0_PG_STS", BIT(8), 0}, 685 {"RSVD_9", BIT(9), 0}, 686 {"RSVD_10", BIT(10), 0}, 687 {"RSVD_11", BIT(11), 0}, 688 {"SBR16B2_PGD0_PG_STS", BIT(12), 0}, 689 {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1}, 690 {"D2D_DISP_PGD0_PG_STS", BIT(14), 1}, 691 {"RSVD_15", BIT(15), 0}, 692 {"RSVD_16", BIT(16), 0}, 693 {"DBG_PSF_PGD0_PG_STS", BIT(17), 0}, 694 {"RSVD_18", BIT(18), 0}, 695 {"CNVI_PGD0_PG_STS", BIT(19), 0}, 696 {"UFSX2_PGD0_PG_STS", BIT(20), 0}, 697 {"ENDBG_PGD0_PG_STS", BIT(21), 0}, 698 {"DBC_PGD0_PG_STS", BIT(22), 0}, 699 {"SBR16B4_PGD0_PG_STS", BIT(23), 0}, 700 {"RSVD_24", BIT(24), 0}, 701 {"NPK_PGD1_PG_STS", BIT(25), 0}, 702 {"RSVD_26", BIT(26), 0}, 703 {"SBR16B20_PGD0_PG_STS", BIT(27), 0}, 704 {"RSVD_28", BIT(28), 0}, 705 {"SBR8B20_PGD0_PG_STS", BIT(29), 0}, 706 {"RSVD_30", BIT(30), 0}, 707 {"FIA_U_PGD0_PG_STS", BIT(31), 0}, 708 {} 709 }; 710 711 static const struct pmc_bit_map nvl_pcds_power_gating_status_2_map[] = { 712 {"PSF8_PGD0_PG_STS", BIT(0), 0}, 713 {"RSVD_1", BIT(1), 0}, 714 {"RSVD_2", BIT(2), 0}, 715 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0}, 716 {"TAM_PGD0_PG_STS", BIT(4), 1}, 717 {"D2D_NOC_PGD2_PG_STS", BIT(5), 1}, 718 {"SBR8B2_PGD0_PG_STS", BIT(6), 0}, 719 {"THC0_PGD0_PG_STS", BIT(7), 0}, 720 {"THC1_PGD0_PG_STS", BIT(8), 0}, 721 {"PMC_PGD1_PG_STS", BIT(9), 0}, 722 {"SBR16B3_PGD0_PG_STS", BIT(10), 0}, 723 {"TCSS_PGD0_PG_STS", BIT(11), 0}, 724 {"DISP_PGA_PGD0_PG_STS", BIT(12), 0}, 725 {"RSVD_13", BIT(13), 0}, 726 {"RSVD_14", BIT(14), 0}, 727 {"RSVD_15", BIT(15), 0}, 728 {"SBRG_PGD0_PG_STS", BIT(16), 0}, 729 {"RSVD_17", BIT(17), 0}, 730 {"SBR16B0_PGD0_PG_STS", BIT(18), 0}, 731 {"SBR8B0_PGD0_PG_STS", BIT(19), 0}, 732 {"PSF7_PGD0_PG_STS", BIT(20), 0}, 733 {"RSVD_21", BIT(21), 0}, 734 {"RSVD_22", BIT(22), 0}, 735 {"RSVD_23", BIT(23), 0}, 736 {"SBR16B6_PGD0_PG_STS", BIT(24), 0}, 737 {"PSF0_PGD0_PG_STS", BIT(25), 0}, 738 {"STRC_PGD0_PG_STS", BIT(26), 0}, 739 {"RSVD_27", BIT(27), 0}, 740 {"DBG_SBR_PGD0_PG_STS", BIT(28), 0}, 741 {"RSVD_29", BIT(29), 0}, 742 {"OSSE_PGD0_PG_STS", BIT(30), 1}, 743 {"DISP_PGA1_PGD0_PG_STS", BIT(31), 0}, 744 {} 745 }; 746 747 static const struct pmc_bit_map nvl_pcds_d3_status_0_map[] = { 748 {"LPSS_D3_STS", BIT(3), 1}, 749 {"XDCI_D3_STS", BIT(4), 1}, 750 {"XHCI_D3_STS", BIT(5), 1}, 751 {"SPA_D3_STS", BIT(12), 0}, 752 {"SPB_D3_STS", BIT(13), 0}, 753 {"ESPISPI_D3_STS", BIT(18), 0}, 754 {"PSTH_D3_STS", BIT(21), 0}, 755 {} 756 }; 757 758 static const struct pmc_bit_map nvl_pcds_d3_status_1_map[] = { 759 {"OSSE_D3_STS", BIT(14), 0}, 760 {"GBE_D3_STS", BIT(19), 0}, 761 {"ITSS_D3_STS", BIT(23), 0}, 762 {"CNVI_D3_STS", BIT(27), 0}, 763 {"UFSX2_D3_STS", BIT(28), 0}, 764 {} 765 }; 766 767 static const struct pmc_bit_map nvl_pcds_d3_status_2_map[] = { 768 {"CSMERTC_D3_STS", BIT(1), 0}, 769 {"CSE_D3_STS", BIT(4), 0}, 770 {"KVMCC_D3_STS", BIT(5), 0}, 771 {"USBR0_D3_STS", BIT(6), 0}, 772 {"ISH_D3_STS", BIT(7), 0}, 773 {"SMT1_D3_STS", BIT(8), 0}, 774 {"SMT2_D3_STS", BIT(9), 0}, 775 {"SMT3_D3_STS", BIT(10), 0}, 776 {"OSSE_SMT1_D3_STS", BIT(12), 0}, 777 {"CLINK_D3_STS", BIT(14), 0}, 778 {"PTIO_D3_STS", BIT(16), 0}, 779 {"PMT_D3_STS", BIT(17), 0}, 780 {"SMS1_D3_STS", BIT(18), 0}, 781 {"SMS2_D3_STS", BIT(19), 0}, 782 {} 783 }; 784 785 static const struct pmc_bit_map nvl_pcds_d3_status_3_map[] = { 786 {"OSSE_SMT2_D3_STS", BIT(0), 0}, 787 {"THC0_D3_STS", BIT(14), 1}, 788 {"THC1_D3_STS", BIT(15), 1}, 789 {"OSSE_SMT3_D3_STS", BIT(19), 0}, 790 {} 791 }; 792 793 static const struct pmc_bit_map nvl_pcds_vnn_req_status_0_map[] = { 794 {"LPSS_VNN_REQ_STS", BIT(3), 0}, 795 {"ESPISPI_VNN_REQ_STS", BIT(18), 1}, 796 {} 797 }; 798 799 static const struct pmc_bit_map nvl_pcds_vnn_req_status_1_map[] = { 800 {"NPK_VNN_REQ_STS", BIT(4), 1}, 801 {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, 802 {"EXI_VNN_REQ_STS", BIT(9), 1}, 803 {"OSSE_VNN_REQ_STS", BIT(14), 1}, 804 {"P2D_VNN_REQ_STS", BIT(18), 1}, 805 {"GBE_VNN_REQ_STS", BIT(19), 0}, 806 {"SMB_VNN_REQ_STS", BIT(25), 1}, 807 {"LPC_VNN_REQ_STS", BIT(26), 0}, 808 {} 809 }; 810 811 static const struct pmc_bit_map nvl_pcds_vnn_req_status_2_map[] = { 812 {"CSMERTC_VNN_REQ_STS", BIT(1), 0}, 813 {"CSE_VNN_REQ_STS", BIT(4), 1}, 814 {"ISH_VNN_REQ_STS", BIT(7), 0}, 815 {"SMT1_VNN_REQ_STS", BIT(8), 0}, 816 {"OSSE_SMT1_VNN_REQ_STS", BIT(12), 1}, 817 {"CLINK_VNN_REQ_STS", BIT(14), 0}, 818 {"SMS1_VNN_REQ_STS", BIT(18), 0}, 819 {"SMS2_VNN_REQ_STS", BIT(19), 0}, 820 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 0}, 821 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1}, 822 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1}, 823 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1}, 824 {} 825 }; 826 827 static const struct pmc_bit_map nvl_pcds_vnn_req_status_3_map[] = { 828 {"DISP_SHIM_VNN_REQ_STS", BIT(4), 1}, 829 {"DTS0_VNN_REQ_STS", BIT(7), 0}, 830 {"GPIOCOM5_VNN_REQ_STS", BIT(11), 0}, 831 {} 832 }; 833 834 static const struct pmc_bit_map nvl_pcds_vnn_misc_status_map[] = { 835 {"CPU_C10_REQ_STS", BIT(0), 0}, 836 {"TS_OFF_REQ_STS", BIT(1), 0}, 837 {"PNDE_MET_REQ_STS", BIT(2), 1}, 838 {"PG5_PMA0_REQ_STS", BIT(3), 1}, 839 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0}, 840 {"VNN_SOC_REQ_STS", BIT(6), 1}, 841 {"ISH_VNNAON_REQ_STS", BIT(7), 0}, 842 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1}, 843 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1}, 844 {"PLT_GREATER_REQ_STS", BIT(11), 1}, 845 {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0}, 846 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0}, 847 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0}, 848 {"EA_REQ_STS", BIT(15), 0}, 849 {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0}, 850 {"BRK_EV_EN_REQ_STS", BIT(17), 0}, 851 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0}, 852 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1}, 853 {"ARC_IDLE_REQ_STS", BIT(21), 0}, 854 {"PG5_PMA1_REQ_STS", BIT(22), 1}, 855 {"DG5_PMA0_REQ_STS", BIT(23), 1}, 856 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0}, 857 {"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1}, 858 {"PRE_WAKE0_REQ_STS", BIT(27), 1}, 859 {"PRE_WAKE1_REQ_STS", BIT(28), 1}, 860 {"PRE_WAKE2_REQ_STS", BIT(29), 1}, 861 {"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31), 1}, 862 {} 863 }; 864 865 static const struct pmc_bit_map nvl_pcds_rsc_status_map[] = { 866 {"CORE", 0, 1}, 867 {"Memory", 0, 1}, 868 {"PRIM_D2D", 0, 1}, 869 {"PSF0", 0, 1}, 870 {"SB", 0, 1}, 871 {} 872 }; 873 874 static const struct pmc_bit_map nvl_pcds_signal_status_map[] = { 875 {"LSX_Wake0_STS", BIT(0), 0}, 876 {"LSX_Wake1_STS", BIT(1), 0}, 877 {"LSX_Wake2_STS", BIT(2), 0}, 878 {"LSX_Wake3_STS", BIT(3), 0}, 879 {"LSX_Wake4_STS", BIT(4), 0}, 880 {"LSX_Wake5_STS", BIT(5), 0}, 881 {"LSX_Wake6_STS", BIT(6), 0}, 882 {"LSX_Wake7_STS", BIT(7), 0}, 883 {"LPSS_Wake0_STS", BIT(8), 1}, 884 {"LPSS_Wake1_STS", BIT(9), 1}, 885 {"Int_Timer_SS_Wake0_STS", BIT(10), 1}, 886 {"Int_Timer_SS_Wake1_STS", BIT(11), 1}, 887 {"Int_Timer_SS_Wake2_STS", BIT(12), 1}, 888 {"Int_Timer_SS_Wake3_STS", BIT(13), 1}, 889 {"Int_Timer_SS_Wake4_STS", BIT(14), 1}, 890 {"Int_Timer_SS_Wake5_STS", BIT(15), 1}, 891 {} 892 }; 893 894 static const struct pmc_bit_map *nvl_pcds_lpm_maps[] = { 895 nvl_pcds_clocksource_status_map, 896 nvl_pcds_power_gating_status_0_map, 897 nvl_pcds_power_gating_status_1_map, 898 nvl_pcds_power_gating_status_2_map, 899 nvl_pcds_d3_status_0_map, 900 nvl_pcds_d3_status_1_map, 901 nvl_pcds_d3_status_2_map, 902 nvl_pcds_d3_status_3_map, 903 nvl_pcds_vnn_req_status_0_map, 904 nvl_pcds_vnn_req_status_1_map, 905 nvl_pcds_vnn_req_status_2_map, 906 nvl_pcds_vnn_req_status_3_map, 907 nvl_pcds_vnn_misc_status_map, 908 nvl_pcds_signal_status_map, 909 NULL 910 }; 911 912 static const struct pmc_bit_map *nvl_pcds_blk_maps[] = { 913 nvl_pcds_power_gating_status_0_map, 914 nvl_pcds_power_gating_status_1_map, 915 nvl_pcds_power_gating_status_2_map, 916 nvl_pcds_rsc_status_map, 917 nvl_pcds_vnn_req_status_0_map, 918 nvl_pcds_vnn_req_status_1_map, 919 nvl_pcds_vnn_req_status_2_map, 920 nvl_pcds_vnn_req_status_3_map, 921 nvl_pcds_d3_status_0_map, 922 nvl_pcds_d3_status_1_map, 923 nvl_pcds_d3_status_2_map, 924 nvl_pcds_d3_status_3_map, 925 nvl_pcds_clocksource_status_map, 926 nvl_pcds_vnn_misc_status_map, 927 nvl_pcds_signal_status_map, 928 NULL 929 }; 930 931 static const struct pmc_bit_map nvl_pchs_pfear_map[] = { 932 {"PMC_PGD0", BIT(0)}, 933 {"FIA_D_PGD0", BIT(1)}, 934 {"SPI_PGD0", BIT(2)}, 935 {"XHCI_PGD0", BIT(3)}, 936 {"SPA_PGD0", BIT(4)}, 937 {"SPB_PGD0", BIT(5)}, 938 {"MPFPW2_PGD0", BIT(6)}, 939 {"GBE_PGD0", BIT(7)}, 940 941 {"RSVD8", BIT(0)}, 942 {"PSF3_PGD0", BIT(1)}, 943 {"SBR5_PGD0", BIT(2)}, 944 {"SBR0_PGD0", BIT(3)}, 945 {"RSVD12", BIT(4)}, 946 {"D2D_DISP_PGD1", BIT(5)}, 947 {"LPSS_PGD0", BIT(6)}, 948 {"LPC_PGD0", BIT(7)}, 949 950 {"SMB_PGD0", BIT(0)}, 951 {"ISH_PGD0", BIT(1)}, 952 {"P2SB_PGD0", BIT(2)}, 953 {"NPK_PGD0", BIT(3)}, 954 {"D2D_NOC_PGD1", BIT(4)}, 955 {"EAH_PGD0", BIT(5)}, 956 {"FUSE_PGD0", BIT(6)}, 957 {"SBR8_PGD0", BIT(7)}, 958 959 {"PSF7_PGD0", BIT(0)}, 960 {"OTG_PGD0", BIT(1)}, 961 {"EXI_PGD0", BIT(2)}, 962 {"CSE_PGD0", BIT(3)}, 963 {"CSME_KVM_PGD0", BIT(4)}, 964 {"CSME_PMT_PGD0", BIT(5)}, 965 {"CSME_CLINK_PGD0", BIT(6)}, 966 {"CSME_PTIO_PGD0", BIT(7)}, 967 968 {"CSME_USBR_PGD0", BIT(0)}, 969 {"SBR1_PGD0", BIT(1)}, 970 {"CSME_SMT1_PGD0", BIT(2)}, 971 {"MPFPW1_PGD0", BIT(3)}, 972 {"CSME_SMS2_PGD0", BIT(4)}, 973 {"CSME_SMS_PGD0", BIT(5)}, 974 {"CSME_RTC_PGD0", BIT(6)}, 975 {"CSMEPSF_PGD0", BIT(7)}, 976 977 {"D2D_NOC_PGD0", BIT(0)}, 978 {"ESE_PGD0", BIT(1)}, 979 {"SBR2_PGD0", BIT(2)}, 980 {"SBR3_PGD0", BIT(3)}, 981 {"SBR4_PGD0", BIT(4)}, 982 {"RSVD45", BIT(5)}, 983 {"D2D_DISP_PGD0", BIT(6)}, 984 {"PSF1_PGD0", BIT(7)}, 985 986 {"U3FPW1_PGD0", BIT(0)}, 987 {"DMI3FPW_PGD0", BIT(1)}, 988 {"PSF4_PGD0", BIT(2)}, 989 {"CNVI_PGD0", BIT(3)}, 990 {"RSVD52", BIT(4)}, 991 {"ENDBG_PGD0", BIT(5)}, 992 {"DBC_PGD0", BIT(6)}, 993 {"SMT4_PGD0", BIT(7)}, 994 995 {"RSVD56", BIT(0)}, 996 {"NPK_PGD1", BIT(1)}, 997 {"RSVD58", BIT(2)}, 998 {"DMI3_PGD0", BIT(3)}, 999 {"RSVD60", BIT(4)}, 1000 {"FIACPCB_D_PGD0", BIT(5)}, 1001 {"RSVD62", BIT(6)}, 1002 {"FIA_U_PGD0", BIT(7)}, 1003 1004 {"FIACPCB_PGS_PGD0", BIT(0)}, 1005 {"FIA_PGS_PGD0", BIT(1)}, 1006 {"RSVD66", BIT(2)}, 1007 {"FIACPCB_U_PGD0", BIT(3)}, 1008 {"TAM_PGD0", BIT(4)}, 1009 {"D2D_NOC_PGD2", BIT(5)}, 1010 {"PSF2_PGD0", BIT(6)}, 1011 {"THC0_PGD0", BIT(7)}, 1012 1013 {"THC1_PGD0", BIT(0)}, 1014 {"PMC_PGD1", BIT(1)}, 1015 {"SBR9_PGD0", BIT(2)}, 1016 {"U3FPW2_PGD0", BIT(3)}, 1017 {"RSVD76", BIT(4)}, 1018 {"DBG_PSF_PGD0", BIT(5)}, 1019 {"DBG_SBR_PGD0", BIT(6)}, 1020 {"SBR6_PGD0", BIT(7)}, 1021 1022 {"SPC_PGD0", BIT(0)}, 1023 {"ACE_PGD0", BIT(1)}, 1024 {"ACE_PGD1", BIT(2)}, 1025 {"ACE_PGD2", BIT(3)}, 1026 {"ACE_PGD3", BIT(4)}, 1027 {"ACE_PGD4", BIT(5)}, 1028 {"ACE_PGD5", BIT(6)}, 1029 {"ACE_PGD6", BIT(7)}, 1030 1031 {"ACE_PGD7", BIT(0)}, 1032 {"ACE_PGD8", BIT(1)}, 1033 {"ACE_PGD9", BIT(2)}, 1034 {"ACE_PGD10", BIT(3)}, 1035 {"U3FPW3_PGD0", BIT(4)}, 1036 {"SBR7_PGD0", BIT(5)}, 1037 {"OSSE_PGD0", BIT(6)}, 1038 {"ST_PGD0", BIT(7)}, 1039 {} 1040 }; 1041 1042 static const struct pmc_bit_map *ext_nvl_pchs_pfear_map[] = { 1043 nvl_pchs_pfear_map, 1044 NULL 1045 }; 1046 1047 static const struct pmc_bit_map nvl_pchs_clocksource_status_map[] = { 1048 {"AON2_OFF_STS", BIT(0), 1}, 1049 {"AON3_OFF_STS", BIT(1), 0}, 1050 {"AON4_OFF_STS", BIT(2), 0}, 1051 {"AON2_SPL_OFF_STS", BIT(3), 0}, 1052 {"AONL_OFF_STS", BIT(4), 0}, 1053 {"XTAL_LVM_OFF_STS", BIT(5), 0}, 1054 {"AON5_OFF_STS", BIT(6), 0}, 1055 {"USB3_PLL_OFF_STS", BIT(8), 1}, 1056 {"MAIN_CRO_OFF_STS", BIT(11), 0}, 1057 {"MAIN_DIVIDER_OFF_STS", BIT(12), 1}, 1058 {"REF_PLL_NON_OC_OFF_STS", BIT(13), 1}, 1059 {"DMI_PLL_OFF_STS", BIT(14), 1}, 1060 {"PHY_EXT_INJ_OFF_STS", BIT(15), 1}, 1061 {"AON6_MCRO_OFF_STS", BIT(16), 0}, 1062 {"XTAL_AGGR_OFF_STS", BIT(17), 0}, 1063 {"USB2_PLL_OFF_STS", BIT(18), 1}, 1064 {"GBE_PLL_OFF_STS", BIT(21), 1}, 1065 {"SATA_PLL_OFF_STS", BIT(22), 1}, 1066 {"PCIE0_PLL_OFF_STS", BIT(23), 1}, 1067 {"PCIE1_PLL_OFF_STS", BIT(24), 1}, 1068 {"FABRIC_PLL_OFF_STS", BIT(25), 1}, 1069 {"PCIE2_PLL_OFF_STS", BIT(26), 1}, 1070 {"REF_PLL_OFF_STS", BIT(28), 1}, 1071 {"REF38P4_PLL_OFF_STS", BIT(31), 1}, 1072 {} 1073 }; 1074 1075 static const struct pmc_bit_map nvl_pchs_power_gating_status_0_map[] = { 1076 {"PMC_PGD0_PG_STS", BIT(0), 0}, 1077 {"FIA_D_PGD0_PG_STS", BIT(1), 0}, 1078 {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, 1079 {"XHCI_PGD0_PG_STS", BIT(3), 0}, 1080 {"SPA_PGD0_PG_STS", BIT(4), 1}, 1081 {"SPB_PGD0_PG_STS", BIT(5), 1}, 1082 {"MPFPW2_PGD0_PG_STS", BIT(6), 0}, 1083 {"GBE_PGD0_PG_STS", BIT(7), 1}, 1084 {"RSVD_8", BIT(8), 0}, 1085 {"PSF3_PGD0_PG_STS", BIT(9), 0}, 1086 {"SBR5_PGD0_PG_STS", BIT(10), 0}, 1087 {"SBR0_PGD0_PG_STS", BIT(11), 0}, 1088 {"RSVD_12", BIT(12), 0}, 1089 {"D2D_DISP_PGD1_PG_STS", BIT(13), 0}, 1090 {"LPSS_PGD0_PG_STS", BIT(14), 1}, 1091 {"LPC_PGD0_PG_STS", BIT(15), 0}, 1092 {"SMB_PGD0_PG_STS", BIT(16), 0}, 1093 {"ISH_PGD0_PG_STS", BIT(17), 0}, 1094 {"P2S_PGD0_PG_STS", BIT(18), 0}, 1095 {"NPK_PGD0_PG_STS", BIT(19), 0}, 1096 {"D2D_NOC_PGD1_PG_STS", BIT(20), 0}, 1097 {"EAH_PGD0_PG_STS", BIT(21), 0}, 1098 {"FUSE_PGD0_PG_STS", BIT(22), 0}, 1099 {"SBR8_PGD0_PG_STS", BIT(23), 0}, 1100 {"PSF7_PGD0_PG_STS", BIT(24), 0}, 1101 {"XDCI_PGD0_PG_STS", BIT(25), 1}, 1102 {"EXI_PGD0_PG_STS", BIT(26), 0}, 1103 {"CSE_PGD0_PG_STS", BIT(27), 1}, 1104 {"KVMCC_PGD0_PG_STS", BIT(28), 1}, 1105 {"PMT_PGD0_PG_STS", BIT(29), 1}, 1106 {"CLINK_PGD0_PG_STS", BIT(30), 1}, 1107 {"PTIO_PGD0_PG_STS", BIT(31), 1}, 1108 {} 1109 }; 1110 1111 static const struct pmc_bit_map nvl_pchs_power_gating_status_1_map[] = { 1112 {"USBR0_PGD0_PG_STS", BIT(0), 1}, 1113 {"SBR1_PGD0_PG_STS", BIT(1), 0}, 1114 {"SMT1_PGD0_PG_STS", BIT(2), 1}, 1115 {"MPFPW1_PGD0_PG_STS", BIT(3), 0}, 1116 {"SMS2_PGD0_PG_STS", BIT(4), 1}, 1117 {"SMS1_PGD0_PG_STS", BIT(5), 1}, 1118 {"CSMERTC_PGD0_PG_STS", BIT(6), 0}, 1119 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0}, 1120 {"D2D_NOC_PGD0_PG_STS", BIT(8), 0}, 1121 {"ESE_PGD0_PG_STS", BIT(9), 1}, 1122 {"SBR2_PGD0_PG_STS", BIT(10), 0}, 1123 {"SBR3_PGD0_PG_STS", BIT(11), 0}, 1124 {"SBR4_PGD0_PG_STS", BIT(12), 0}, 1125 {"RSVD_13", BIT(13), 0}, 1126 {"D2D_DISP_PGD0_PG_STS", BIT(14), 0}, 1127 {"PSF1_PGD0_PG_STS", BIT(15), 0}, 1128 {"U3FPW1_PGD0_PG_STS", BIT(16), 0}, 1129 {"DMI3FPW_PGD0_PG_STS", BIT(17), 0}, 1130 {"PSF4_PGD0_PG_STS", BIT(18), 0}, 1131 {"CNVI_PGD0_PG_STS", BIT(19), 0}, 1132 {"RSVD_20", BIT(20), 0}, 1133 {"ENDBG_PGD0_PG_STS", BIT(21), 0}, 1134 {"DBC_PGD0_PG_STS", BIT(22), 0}, 1135 {"SMT4_PGD0_PG_STS", BIT(23), 1}, 1136 {"RSVD_24", BIT(24), 0}, 1137 {"NPK_PGD1_PG_STS", BIT(25), 0}, 1138 {"RSVD_26", BIT(26), 0}, 1139 {"DMI3_PGD0_PG_STS", BIT(27), 1}, 1140 {"RSVD_28", BIT(28), 0}, 1141 {"FIACPCB_D_PGD0_PG_STS", BIT(29), 0}, 1142 {"RSVD_30", BIT(30), 0}, 1143 {"FIA_U_PGD0_PG_STS", BIT(31), 0}, 1144 {} 1145 }; 1146 1147 static const struct pmc_bit_map nvl_pchs_power_gating_status_2_map[] = { 1148 {"FIACPCB_PGS_PGD0_PG_STS", BIT(0), 0}, 1149 {"FIA_PGS_PGD0_PG_STS", BIT(1), 0}, 1150 {"RSVD_2", BIT(2), 0}, 1151 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0}, 1152 {"TAM_PGD0_PG_STS", BIT(4), 0}, 1153 {"D2D_NOC_PGD2_PG_STS", BIT(5), 0}, 1154 {"PSF2_PGD0_PG_STS", BIT(6), 0}, 1155 {"THC0_PGD0_PG_STS", BIT(7), 1}, 1156 {"THC1_PGD0_PG_STS", BIT(8), 1}, 1157 {"PMC_PGD1_PG_STS", BIT(9), 0}, 1158 {"SBR9_PGA0_PGD0_PG_STS", BIT(10), 0}, 1159 {"U3FPW2_PGD0_PG_STS", BIT(11), 0}, 1160 {"RSVD_12", BIT(12), 0}, 1161 {"DBG_PSF_PGD0_PG_STS", BIT(13), 0}, 1162 {"DBG_SBR_PGD0_PG_STS", BIT(14), 0}, 1163 {"SBR6_PGD0_PG_STS", BIT(15), 0}, 1164 {"SPC_PGD0_PG_STS", BIT(16), 1}, 1165 {"ACE_PGD0_PG_STS", BIT(17), 0}, 1166 {"ACE_PGD1_PG_STS", BIT(18), 0}, 1167 {"ACE_PGD2_PG_STS", BIT(19), 0}, 1168 {"ACE_PGD3_PG_STS", BIT(20), 0}, 1169 {"ACE_PGD4_PG_STS", BIT(21), 0}, 1170 {"ACE_PGD5_PG_STS", BIT(22), 0}, 1171 {"ACE_PGD6_PG_STS", BIT(23), 0}, 1172 {"ACE_PGD7_PG_STS", BIT(24), 0}, 1173 {"ACE_PGD8_PG_STS", BIT(25), 0}, 1174 {"ACE_PGD9_PG_STS", BIT(26), 0}, 1175 {"ACE_PGD10_PG_STS", BIT(27), 0}, 1176 {"U3FPW3_PGD0_PG_STS", BIT(28), 0}, 1177 {"SBR7_PGD0_PG_STS", BIT(29), 0}, 1178 {"OSSE_PGD0_PG_STS", BIT(30), 0}, 1179 {"SATA_PGD0_PG_STS", BIT(31), 1}, 1180 {} 1181 }; 1182 1183 static const struct pmc_bit_map nvl_pchs_d3_status_0_map[] = { 1184 {"LPSS_D3_STS", BIT(3), 1}, 1185 {"XDCI_D3_STS", BIT(4), 1}, 1186 {"XHCI_D3_STS", BIT(5), 0}, 1187 {"SPA_D3_STS", BIT(12), 0}, 1188 {"SPB_D3_STS", BIT(13), 0}, 1189 {"SPC_D3_STS", BIT(14), 0}, 1190 {"ESPISPI_D3_STS", BIT(18), 0}, 1191 {"SATA_D3_STS", BIT(20), 1}, 1192 {} 1193 }; 1194 1195 static const struct pmc_bit_map nvl_pchs_d3_status_1_map[] = { 1196 {"OSSE_D3_STS", BIT(6), 0}, 1197 {"GBE_D3_STS", BIT(19), 0}, 1198 {"ITSS_D3_STS", BIT(23), 0}, 1199 {"P2S_D3_STS", BIT(24), 0}, 1200 {"CNVI_D3_STS", BIT(27), 0}, 1201 {} 1202 }; 1203 1204 static const struct pmc_bit_map nvl_pchs_d3_status_2_map[] = { 1205 {"CSMERTC_D3_STS", BIT(1), 0}, 1206 {"CSE_D3_STS", BIT(4), 0}, 1207 {"KVMCC_D3_STS", BIT(5), 0}, 1208 {"USBR0_D3_STS", BIT(6), 0}, 1209 {"ISH_D3_STS", BIT(7), 0}, 1210 {"SMT1_D3_STS", BIT(8), 0}, 1211 {"SMT2_D3_STS", BIT(9), 0}, 1212 {"SMT3_D3_STS", BIT(10), 0}, 1213 {"SMT4_D3_STS", BIT(11), 0}, 1214 {"SMT5_D3_STS", BIT(12), 0}, 1215 {"SMT6_D3_STS", BIT(13), 0}, 1216 {"CLINK_D3_STS", BIT(14), 0}, 1217 {"PTIO_D3_STS", BIT(16), 0}, 1218 {"PMT_D3_STS", BIT(17), 0}, 1219 {"SMS1_D3_STS", BIT(18), 0}, 1220 {"SMS2_D3_STS", BIT(19), 0}, 1221 {} 1222 }; 1223 1224 static const struct pmc_bit_map nvl_pchs_d3_status_3_map[] = { 1225 {"THC0_D3_STS", BIT(14), 0}, 1226 {"THC1_D3_STS", BIT(15), 0}, 1227 {"ACE_D3_STS", BIT(23), 0}, 1228 {} 1229 }; 1230 1231 static const struct pmc_bit_map nvl_pchs_vnn_req_status_1_map[] = { 1232 {"NPK_VNN_REQ_STS", BIT(4), 0}, 1233 {"OSSE_VNN_REQ_STS", BIT(6), 0}, 1234 {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, 1235 {"EXI_VNN_REQ_STS", BIT(9), 0}, 1236 {"GBE_VNN_REQ_STS", BIT(19), 0}, 1237 {"SMB_VNN_REQ_STS", BIT(25), 0}, 1238 {"LPC_VNN_REQ_STS", BIT(26), 0}, 1239 {} 1240 }; 1241 1242 static const struct pmc_bit_map nvl_pchs_vnn_req_status_2_map[] = { 1243 {"CSMERTC_VNN_REQ_STS", BIT(1), 0}, 1244 {"CSE_VNN_REQ_STS", BIT(4), 0}, 1245 {"ISH_VNN_REQ_STS", BIT(7), 0}, 1246 {"SMT1_VNN_REQ_STS", BIT(8), 0}, 1247 {"SMT4_VNN_REQ_STS", BIT(11), 0}, 1248 {"CLINK_VNN_REQ_STS", BIT(14), 0}, 1249 {"SMS1_VNN_REQ_STS", BIT(18), 0}, 1250 {"SMS2_VNN_REQ_STS", BIT(19), 0}, 1251 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 0}, 1252 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 0}, 1253 {"GPIOCOM2_VNN_REQ_STS", BIT(22), 0}, 1254 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 0}, 1255 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 0}, 1256 {} 1257 }; 1258 1259 static const struct pmc_bit_map nvl_pchs_vnn_misc_status_map[] = { 1260 {"CPU_C10_REQ_STS", BIT(0), 0}, 1261 {"TS_OFF_REQ_STS", BIT(1), 0}, 1262 {"PNDE_MET_REQ_STS", BIT(2), 1}, 1263 {"PG5_PMA0_GVNN_REQ_STS", BIT(3), 1}, 1264 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0}, 1265 {"DMI_IN_L1_REQ_STS", BIT(6), 0}, 1266 {"ISH_VNNAON_REQ_STS", BIT(7), 0}, 1267 {"PLT_GREATER_REQ_STS", BIT(11), 1}, 1268 {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0}, 1269 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0}, 1270 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0}, 1271 {"EA_REQ_STS", BIT(15), 0}, 1272 {"DMI_CLKREQ_B_REQ_STS", BIT(16), 0}, 1273 {"BRK_EV_EN_REQ_STS", BIT(17), 0}, 1274 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0}, 1275 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1}, 1276 {"ARC_IDLE_REQ_STS", BIT(21), 0}, 1277 {"PG5_PMA1_GVNN_REQ_STS", BIT(22), 1}, 1278 {"FIA_DEEP_PM_REQ_STS", BIT(23), 0}, 1279 {"XDCI_ATTACHED_REQ_STS", BIT(24), 0}, 1280 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0}, 1281 {"PRE_WAKE0_REQ_STS", BIT(27), 1}, 1282 {"PRE_WAKE1_REQ_STS", BIT(28), 1}, 1283 {"PRE_WAKE2_EN_REQ_STS", BIT(29), 0}, 1284 {"PG5_PMA2_GVNN_REQ_STS", BIT(30), 1}, 1285 {} 1286 }; 1287 1288 static const struct pmc_bit_map nvl_pchs_rsc_status_map[] = { 1289 {"Memory", 0, 1}, 1290 {"Memory_NS", 0, 1}, 1291 {"PSF1", 0, 1}, 1292 {"PSF2", 0, 1}, 1293 {"PSF3", 0, 1}, 1294 {"REF_PLL", 0, 1}, 1295 {"SB", 0, 1}, 1296 {} 1297 }; 1298 1299 static const struct pmc_bit_map *nvl_pchs_lpm_maps[] = { 1300 nvl_pchs_clocksource_status_map, 1301 nvl_pchs_power_gating_status_0_map, 1302 nvl_pchs_power_gating_status_1_map, 1303 nvl_pchs_power_gating_status_2_map, 1304 nvl_pchs_d3_status_0_map, 1305 nvl_pchs_d3_status_1_map, 1306 nvl_pchs_d3_status_2_map, 1307 nvl_pchs_d3_status_3_map, 1308 nvl_pcds_vnn_req_status_0_map, 1309 nvl_pchs_vnn_req_status_1_map, 1310 nvl_pchs_vnn_req_status_2_map, 1311 nvl_pcdh_vnn_req_status_3_map, 1312 nvl_pchs_vnn_misc_status_map, 1313 ptl_pcdp_signal_status_map, 1314 NULL 1315 }; 1316 1317 static const struct pmc_bit_map *nvl_pchs_blk_maps[] = { 1318 nvl_pchs_power_gating_status_0_map, 1319 nvl_pchs_power_gating_status_1_map, 1320 nvl_pchs_power_gating_status_2_map, 1321 nvl_pchs_rsc_status_map, 1322 nvl_pchs_d3_status_0_map, 1323 nvl_pchs_clocksource_status_map, 1324 nvl_pchs_vnn_misc_status_map, 1325 NULL 1326 }; 1327 1328 static const struct pmc_reg_map nvl_pcdh_reg_map = { 1329 .pfear_sts = ext_nvl_pcdh_pfear_map, 1330 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 1331 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 1332 .ltr_show_sts = ptl_pcdp_ltr_show_map, 1333 .msr_sts = msr_map, 1334 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 1335 .regmap_length = NVL_PCDH_PMC_MMIO_REG_LEN, 1336 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 1337 .ppfear_buckets = NVL_PCDH_PPFEAR_NUM_ENTRIES, 1338 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 1339 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 1340 .lpm_num_maps = NVL_LPM_NUM_MAPS, 1341 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 1342 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 1343 .etr3_offset = ETR3_OFFSET, 1344 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 1345 .lpm_priority_offset = NVL_LPM_PRI_OFFSET, 1346 .lpm_en_offset = NVL_LPM_EN_OFFSET, 1347 .lpm_residency_offset = NVL_LPM_RESIDENCY_OFFSET, 1348 .lpm_sts = nvl_pcdh_lpm_maps, 1349 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 1350 .lpm_live_status_offset = NVL_LPM_LIVE_STATUS_OFFSET, 1351 .s0ix_blocker_maps = nvl_pcdh_blk_maps, 1352 .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, 1353 .num_s0ix_blocker = NVL_PCDH_NUM_S0IX_BLOCKER, 1354 .blocker_req_offset = NVL_PCDH_BLK_REQ_OFFSET, 1355 .lpm_req_guid = PCDH_LPM_REQ_GUID, 1356 }; 1357 1358 static const struct pmc_reg_map nvl_pcds_reg_map = { 1359 .pfear_sts = ext_nvl_pcds_pfear_map, 1360 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 1361 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 1362 .ltr_show_sts = nvl_pcds_ltr_show_map, 1363 .msr_sts = msr_map, 1364 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 1365 .regmap_length = NVL_PCDS_PMC_MMIO_REG_LEN, 1366 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 1367 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, 1368 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 1369 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 1370 .lpm_num_maps = PTL_LPM_NUM_MAPS, 1371 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 1372 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 1373 .etr3_offset = ETR3_OFFSET, 1374 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 1375 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 1376 .lpm_en_offset = MTL_LPM_EN_OFFSET, 1377 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 1378 .lpm_sts = nvl_pcds_lpm_maps, 1379 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 1380 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 1381 .s0ix_blocker_maps = nvl_pcds_blk_maps, 1382 .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, 1383 .num_s0ix_blocker = NVL_PCDS_NUM_S0IX_BLOCKER, 1384 .lpm_req_guid = PCDS_LPM_REQ_GUID, 1385 .blocker_req_offset = NVL_PCDS_BLK_REQ_OFFSET, 1386 }; 1387 1388 static const struct pmc_reg_map nvl_pchs_reg_map = { 1389 .pfear_sts = ext_nvl_pchs_pfear_map, 1390 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 1391 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 1392 .ltr_show_sts = ptl_pcdp_ltr_show_map, 1393 .msr_sts = msr_map, 1394 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 1395 .regmap_length = NVL_PCHS_PMC_MMIO_REG_LEN, 1396 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 1397 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, 1398 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 1399 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 1400 .lpm_num_maps = PTL_LPM_NUM_MAPS, 1401 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 1402 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 1403 .etr3_offset = ETR3_OFFSET, 1404 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 1405 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 1406 .lpm_en_offset = MTL_LPM_EN_OFFSET, 1407 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 1408 .lpm_sts = nvl_pchs_lpm_maps, 1409 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 1410 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 1411 .s0ix_blocker_maps = nvl_pchs_blk_maps, 1412 .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, 1413 .num_s0ix_blocker = NVL_PCHS_NUM_S0IX_BLOCKER, 1414 .blocker_req_offset = NVL_PCHS_BLK_REQ_OFFSET, 1415 .lpm_req_guid = PCHS_LPM_REQ_GUID, 1416 }; 1417 1418 static struct pmc_info nvl_pmc_info_list[] = { 1419 { 1420 .devid = PMC_DEVID_NVL_PCDH, 1421 .map = &nvl_pcdh_reg_map, 1422 }, 1423 { 1424 .devid = PMC_DEVID_NVL_PCDS, 1425 .map = &nvl_pcds_reg_map, 1426 }, 1427 { 1428 .devid = PMC_DEVID_NVL_PCHS, 1429 .map = &nvl_pchs_reg_map, 1430 }, 1431 {} 1432 }; 1433 1434 static const char *nvl_ltr_block_counter_arr[] = { 1435 "PKGC_PREVENT_LTR_IADOMAIN", 1436 "PKGC_PREVENT_LTR_GDIE", 1437 "PKGC_PREVENT_LTR_PCH", 1438 "PKGC_PREVENT_LTR_DISPLAY", 1439 "PKGC_PREVENT_LTR_IPU", 1440 NULL 1441 }; 1442 1443 static const char *nvl_pkgc_blocker_residency[] = { 1444 "PKGC_BLOCK_RESIDENCY_INVALID", 1445 "PKGC_BLOCK_RESIDENCY_MISC", 1446 "PKGC_BLOCK_RESIDENCY_CDIE_MISC", 1447 "PKGC_BLOCK_RESIDENCY_MEDIA_MISC", 1448 "PKGC_BLOCK_RESIDENCY_GT_MISC", 1449 "PKGC_BLOCK_RESIDENCY_HUBATOM_MISC", 1450 "PKGC_BLOCK_RESIDENCY_IPU_BUSY", 1451 "PKGC_BLOCK_RESIDENCY_IPU_LTR", 1452 "PKGC_BLOCK_RESIDENCY_IPU_TIMER", 1453 "PKGC_BLOCK_RESIDENCY_DISP_BUSY", 1454 "PKGC_BLOCK_RESIDENCY_DISP_LTR", 1455 "PKGC_BLOCK_RESIDENCY_DISP_TIMER", 1456 "PKGC_BLOCK_RESIDENCY_VPU_BUSY", 1457 "PKGC_BLOCK_RESIDENCY_VPU_TIMER", 1458 "PKGC_BLOCK_RESIDENCY_PMC_BUSY", 1459 "PKGC_BLOCK_RESIDENCY_PMC_LTR", 1460 "PKGC_BLOCK_RESIDENCY_PMC_TIMER", 1461 "PKGC_BLOCK_RESIDENCY_HUBATOM_ARAT", 1462 "PKGC_BLOCK_RESIDENCY_CDIE0_ARAT", 1463 "PKGC_BLOCK_RESIDENCY_CDIE1_ARAT", 1464 "PKGC_BLOCK_RESIDENCY_GT_ARAT", 1465 "PKGC_BLOCK_RESIDENCY_MEDIA_ARAT", 1466 "PKGC_BLOCK_RESIDENCY_DEMOTION", 1467 "PKGC_BLOCK_RESIDENCY_THERMALS", 1468 "PKGC_BLOCK_RESIDENCY_SNCU", 1469 "PKGC_BLOCK_RESIDENCY_SVTU", 1470 "PKGC_BLOCK_RESIDENCY_IAA", 1471 "PKGC_BLOCK_RESIDENCY_IOC", 1472 NULL, 1473 }; 1474 1475 static const u8 nvl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_PCH}; 1476 1477 #define NVL_NPU_PCI_DEV 0xd71d 1478 1479 /* 1480 * Set power state of select devices that do not have drivers to D3 1481 * so that they do not block Package C entry. 1482 */ 1483 static void nvl_d3_fixup(void) 1484 { 1485 pmc_core_set_device_d3(NVL_NPU_PCI_DEV); 1486 } 1487 1488 static int nvl_resume(struct pmc_dev *pmcdev) 1489 { 1490 nvl_d3_fixup(); 1491 return cnl_resume(pmcdev); 1492 } 1493 1494 static int nvl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) 1495 { 1496 nvl_d3_fixup(); 1497 return generic_core_init(pmcdev, pmc_dev_info); 1498 } 1499 1500 static u32 nvl_pmt_dmu_guids[] = {NVL_PMT_DMU_GUID, 0x0}; 1501 struct pmc_dev_info nvl_s_pmc_dev = { 1502 .num_pmcs = ARRAY_SIZE(nvl_pmc_list), 1503 .pmc_list = nvl_pmc_list, 1504 .regmap_list = nvl_pmc_info_list, 1505 .map = &nvl_pcds_reg_map, 1506 .sub_req_show = &pmc_core_substate_blk_req_fops, 1507 .suspend = cnl_suspend, 1508 .resume = nvl_resume, 1509 .init = nvl_core_init, 1510 .sub_req = pmc_core_pmt_get_blk_sub_req, 1511 .dmu_guids = nvl_pmt_dmu_guids, 1512 .pc_guid = NVL_PMT_PC_GUID, 1513 .pkgc_ltr_blocker_offset = NVL_LTR_BLK_OFFSET, 1514 .pkgc_ltr_blocker_counters = nvl_ltr_block_counter_arr, 1515 .pkgc_blocker_offset = NVL_PKGC_BLK_OFFSET, 1516 .pkgc_blocker_counters = nvl_pkgc_blocker_residency, 1517 .ssram_hidden = false, 1518 .die_c6_offset = NVL_PMT_DMU_DIE_C6_OFFSET, 1519 }; 1520 1521 struct pmc_dev_info nvl_h_pmc_dev = { 1522 .num_pmcs = ARRAY_SIZE(nvl_pmc_list), 1523 .pmc_list = nvl_pmc_list, 1524 .regmap_list = nvl_pmc_info_list, 1525 .map = &nvl_pcdh_reg_map, 1526 .sub_req_show = &pmc_core_substate_blk_req_fops, 1527 .suspend = cnl_suspend, 1528 .resume = nvl_resume, 1529 .init = nvl_core_init, 1530 .sub_req = pmc_core_pmt_get_blk_sub_req, 1531 .dmu_guids = nvl_pmt_dmu_guids, 1532 .pc_guid = NVL_PMT_PC_GUID, 1533 .pkgc_ltr_blocker_offset = NVL_LTR_BLK_OFFSET, 1534 .pkgc_ltr_blocker_counters = nvl_ltr_block_counter_arr, 1535 .pkgc_blocker_offset = NVL_PKGC_BLK_OFFSET, 1536 .pkgc_blocker_counters = nvl_pkgc_blocker_residency, 1537 .ssram_hidden = false, 1538 .die_c6_offset = NVL_PMT_DMU_DIE_C6_OFFSET, 1539 }; 1540