1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. 4 * 5 * Author: Jia Wang <wangjia@ultrarisc.com> 6 */ 7 8 #ifndef __PINCTRL_ULTRARISC_H__ 9 #define __PINCTRL_ULTRARISC_H__ 10 11 #include <linux/io.h> 12 #include <linux/pinctrl/pinctrl.h> 13 #include <linux/spinlock.h> 14 15 struct platform_device; 16 17 #define UR_FUNC_DEFAULT 0U 18 #define UR_FUNC_0 1U 19 #define UR_FUNC_1 0x10000U 20 21 #define UR_MAX_PINS_PER_PORT 16 22 23 #define UR_BIAS_MASK 0x0000000F 24 #define UR_PULL_MASK 0x0C 25 #define UR_PULL_DIS 0 26 #define UR_PULL_UP 1 27 #define UR_PULL_DOWN 2 28 #define UR_DRIVE_MASK 0x03 29 30 struct ur_port_desc { 31 u32 pin_base; 32 u32 npins; 33 u32 func_offset; 34 u32 conf_offset; 35 u32 supported_modes; 36 bool supports_gpio; 37 }; 38 39 struct ur_func_route { 40 const char *function; 41 u32 mode; 42 u64 valid_pins; 43 }; 44 45 struct ur_pinctrl_data { 46 const struct pinctrl_pin_desc *pins; 47 u32 npins; 48 const struct ur_func_route *routes; 49 u32 num_routes; 50 }; 51 52 struct ur_pinctrl { 53 struct device *dev; 54 struct pinctrl_dev *pctl_dev; 55 const struct ur_pinctrl_data *data; 56 void __iomem *base; 57 raw_spinlock_t lock; /* Protects mux and conf registers */ 58 }; 59 60 int ur_pinctrl_probe(struct platform_device *pdev, 61 const struct ur_pinctrl_data *data); 62 63 #endif 64