1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. 4 * 5 * Author: Jia Wang <wangjia@ultrarisc.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/pinctrl/pinconf.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 #include <linux/pinctrl/pinmux.h> 14 #include <linux/platform_device.h> 15 #include <linux/seq_file.h> 16 #include <linux/slab.h> 17 18 #include "../core.h" 19 #include "../devicetree.h" 20 #include "../pinconf.h" 21 #include "../pinmux.h" 22 23 #include "pinctrl-ultrarisc.h" 24 25 #define UR_CONF_BIT_PER_PIN 4 26 #define UR_CONF_PIN_PER_REG (32 / UR_CONF_BIT_PER_PIN) 27 static const u32 ur_drive_strengths[] = { 20, 27, 33, 40 }; 28 29 static const struct ur_port_desc *ur_get_pin_port(struct pinctrl_dev *pctldev, 30 unsigned int pin) 31 { 32 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 33 34 if (!desc || !desc->drv_data) 35 return NULL; 36 37 return desc->drv_data; 38 } 39 40 static u32 ur_get_pin_conf_offset(const struct ur_port_desc *port_desc, u32 pin) 41 { 42 return port_desc->conf_offset + 43 (pin / UR_CONF_PIN_PER_REG) * sizeof(u32); 44 } 45 46 static int ur_read_pin_conf(struct ur_pinctrl *pctrl, unsigned int pin, u32 *conf) 47 { 48 const struct ur_port_desc *port_desc; 49 u32 pin_offset; 50 u32 reg_offset; 51 u32 shift; 52 u32 mask; 53 54 port_desc = ur_get_pin_port(pctrl->pctl_dev, pin); 55 if (!port_desc) 56 return -EINVAL; 57 58 pin_offset = pin - port_desc->pin_base; 59 reg_offset = ur_get_pin_conf_offset(port_desc, pin_offset); 60 shift = (pin_offset % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; 61 mask = GENMASK(UR_CONF_BIT_PER_PIN - 1, 0) << shift; 62 *conf = field_get(mask, readl_relaxed(pctrl->base + reg_offset)); 63 64 return 0; 65 } 66 67 static int ur_write_pin_conf(struct ur_pinctrl *pctrl, unsigned int pin, u32 conf) 68 { 69 const struct ur_port_desc *port_desc; 70 void __iomem *reg; 71 u32 pin_offset; 72 u32 reg_offset; 73 u32 shift; 74 u32 mask; 75 u32 val; 76 77 port_desc = ur_get_pin_port(pctrl->pctl_dev, pin); 78 if (!port_desc) 79 return -EINVAL; 80 81 pin_offset = pin - port_desc->pin_base; 82 reg_offset = ur_get_pin_conf_offset(port_desc, pin_offset); 83 reg = pctrl->base + reg_offset; 84 shift = (pin_offset % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; 85 mask = GENMASK(UR_CONF_BIT_PER_PIN - 1, 0) << shift; 86 87 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { 88 val = readl_relaxed(reg); 89 val = (val & ~mask) | field_prep(mask, conf); 90 writel_relaxed(val, reg); 91 } 92 93 return 0; 94 } 95 96 static int ur_set_pin_mux(struct ur_pinctrl *pctrl, 97 const struct ur_port_desc *port_desc, 98 u32 pin_offset, u32 mode) 99 { 100 void __iomem *reg = pctrl->base + port_desc->func_offset; 101 u32 val; 102 103 if (WARN_ON(pin_offset >= UR_MAX_PINS_PER_PORT)) 104 return -EINVAL; 105 106 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { 107 val = readl_relaxed(reg); 108 val &= ~((UR_FUNC_0 | UR_FUNC_1) << pin_offset); 109 val |= mode << pin_offset; 110 writel_relaxed(val, reg); 111 } 112 113 return 0; 114 } 115 116 static int ur_set_pin_mux_by_num(struct ur_pinctrl *pctrl, unsigned int pin, u32 mode) 117 { 118 const struct ur_port_desc *port_desc = ur_get_pin_port(pctrl->pctl_dev, pin); 119 u32 pin_offset; 120 121 if (!port_desc) 122 return -EINVAL; 123 124 if (mode != UR_FUNC_DEFAULT && !(port_desc->supported_modes & mode)) 125 return -EINVAL; 126 127 pin_offset = pin - port_desc->pin_base; 128 129 return ur_set_pin_mux(pctrl, port_desc, pin_offset, mode); 130 } 131 132 static int ur_hw_to_config(unsigned long *config, u32 conf) 133 { 134 enum pin_config_param param = pinconf_to_config_param(*config); 135 u32 drive = FIELD_GET(UR_DRIVE_MASK, conf); 136 u32 pull = FIELD_GET(UR_PULL_MASK, conf); 137 138 switch (param) { 139 case PIN_CONFIG_BIAS_DISABLE: 140 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 141 if (pull != UR_PULL_DIS) 142 return -EINVAL; 143 *config = pinconf_to_config_packed(param, 1); 144 return 0; 145 case PIN_CONFIG_BIAS_PULL_UP: 146 if (pull != UR_PULL_UP) 147 return -EINVAL; 148 *config = pinconf_to_config_packed(param, 1); 149 return 0; 150 case PIN_CONFIG_BIAS_PULL_DOWN: 151 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 152 if (pull != UR_PULL_DOWN) 153 return -EINVAL; 154 *config = pinconf_to_config_packed(param, 1); 155 return 0; 156 case PIN_CONFIG_DRIVE_STRENGTH: 157 if (drive >= ARRAY_SIZE(ur_drive_strengths)) 158 return -EINVAL; 159 *config = pinconf_to_config_packed(param, ur_drive_strengths[drive]); 160 return 0; 161 default: 162 return -EINVAL; 163 } 164 } 165 166 static int ur_config_to_hw(unsigned long config, u32 *conf) 167 { 168 enum pin_config_param param = pinconf_to_config_param(config); 169 u32 arg = pinconf_to_config_argument(config); 170 171 switch (param) { 172 case PIN_CONFIG_BIAS_DISABLE: 173 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 174 FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_DIS); 175 return 0; 176 case PIN_CONFIG_BIAS_PULL_UP: 177 FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_UP); 178 return 0; 179 case PIN_CONFIG_BIAS_PULL_DOWN: 180 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 181 FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_DOWN); 182 return 0; 183 case PIN_CONFIG_DRIVE_STRENGTH: 184 for (u32 i = 0; i < ARRAY_SIZE(ur_drive_strengths); i++) { 185 if (ur_drive_strengths[i] != arg) 186 continue; 187 FIELD_MODIFY(UR_DRIVE_MASK, conf, i); 188 return 0; 189 } 190 return -EINVAL; 191 case PIN_CONFIG_PERSIST_STATE: 192 /* 193 * For PIN_CONFIG_PERSIST_STATE, gpiolib only treats 194 * -ENOTSUPP as an optional unsupported result. 195 * Do not use -EOPNOTSUPP here. 196 */ 197 return -ENOTSUPP; 198 default: 199 return -EOPNOTSUPP; 200 } 201 } 202 203 /** 204 * ur_find_group_route() - Find the route matching a function and pin set 205 * @pctrl: pin controller instance 206 * @function: mux function name 207 * @group_mask: bitmap of pins in the selected group 208 * @route_out: returned route entry on success 209 * 210 * A mux function may be associated with multiple hardware routing options, 211 * each valid for a specific set of pins. This helper finds the unique route 212 * whose valid_pins mask covers all pins in @group_mask. 213 * 214 * The routing table must guarantee that a given function plus pin set 215 * resolves to exactly one route. If multiple routes match, the routing 216 * description is considered ambiguous and the lookup fails. 217 * 218 * Return: 0 on success, or -EINVAL if no matching route exists or if the 219 * routing table contains ambiguous entries. 220 */ 221 static int ur_find_group_route(struct ur_pinctrl *pctrl, 222 const char *function, 223 u64 group_mask, 224 const struct ur_func_route **route_out) 225 { 226 const struct ur_func_route *match = NULL; 227 228 for (u32 i = 0; i < pctrl->data->num_routes; i++) { 229 const struct ur_func_route *route = &pctrl->data->routes[i]; 230 231 if (strcmp(route->function, function)) 232 continue; 233 234 if ((route->valid_pins & group_mask) != group_mask) 235 continue; 236 237 if (match) { 238 dev_err(pctrl->dev, 239 "ambiguous route for function %s group_mask=%#llx\n", 240 function, (unsigned long long)group_mask); 241 return -EINVAL; 242 } 243 244 match = route; 245 } 246 247 if (match) { 248 *route_out = match; 249 return 0; 250 } 251 252 return -EINVAL; 253 } 254 255 static const char *ur_get_group_function(struct pinctrl_dev *pctldev, 256 unsigned int group_selector, 257 unsigned int pin_index) 258 { 259 const struct group_desc *group; 260 const char * const *functions; 261 262 group = pinctrl_generic_get_group(pctldev, group_selector); 263 if (!group || pin_index >= group->grp.npins || !group->data) 264 return NULL; 265 266 functions = group->data; 267 268 return functions[pin_index]; 269 } 270 271 static int ur_resolve_group_mux(struct pinctrl_dev *pctldev, 272 struct ur_pinctrl *pctrl, 273 unsigned int group_selector, 274 const unsigned int *pins, 275 unsigned int npins, 276 const struct ur_func_route **route_out) 277 { 278 const char *function; 279 u64 group_mask = 0; 280 281 if (!npins) 282 return -EINVAL; 283 284 function = ur_get_group_function(pctldev, group_selector, 0); 285 if (!function) 286 return -EINVAL; 287 288 for (u32 i = 0; i < npins; i++) 289 group_mask |= BIT_ULL(pins[i]); 290 291 return ur_find_group_route(pctrl, function, group_mask, route_out); 292 } 293 294 static bool ur_function_is_gpio(struct pinctrl_dev *pctldev, 295 unsigned int selector) 296 { 297 const struct function_desc *function; 298 299 function = pinmux_generic_get_function(pctldev, selector); 300 if (!function) 301 return false; 302 303 for (u32 i = 0; i < function->func->ngroups; i++) { 304 const char *func_name; 305 int group_selector; 306 307 group_selector = pinctrl_get_group_selector(pctldev, 308 function->func->groups[i]); 309 if (group_selector < 0) 310 return false; 311 312 func_name = ur_get_group_function(pctldev, group_selector, 0); 313 if (!func_name || strcmp(func_name, "gpio")) 314 return false; 315 } 316 317 return true; 318 } 319 320 static const struct pinctrl_ops ur_pinctrl_ops = { 321 .get_groups_count = pinctrl_generic_get_group_count, 322 .get_group_name = pinctrl_generic_get_group_name, 323 .get_group_pins = pinctrl_generic_get_group_pins, 324 .dt_node_to_map = pinctrl_generic_pins_function_dt_node_to_map, 325 .dt_free_map = pinconf_generic_dt_free_map, 326 }; 327 328 static int ur_gpio_request_enable(struct pinctrl_dev *pctldev, 329 struct pinctrl_gpio_range *range, 330 unsigned int offset) 331 { 332 struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 333 const struct ur_port_desc *port_desc; 334 const struct ur_func_route *route; 335 int ret; 336 337 (void)range; 338 339 port_desc = ur_get_pin_port(pctldev, offset); 340 if (!port_desc || !port_desc->supports_gpio) 341 return -EINVAL; 342 343 ret = ur_find_group_route(pctrl, "gpio", BIT_ULL(offset), &route); 344 if (ret) 345 return ret; 346 347 return ur_set_pin_mux_by_num(pctrl, offset, route->mode); 348 } 349 350 static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 351 unsigned int group_selector) 352 { 353 struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 354 const struct ur_func_route *route; 355 const unsigned int *pins; 356 unsigned int npins; 357 int ret; 358 359 (void)func_selector; 360 361 ret = pinctrl_generic_get_group_pins(pctldev, group_selector, &pins, &npins); 362 if (ret) 363 return ret; 364 365 ret = ur_resolve_group_mux(pctldev, pctrl, group_selector, pins, npins, 366 &route); 367 if (ret) 368 return ret; 369 370 for (u32 i = 0; i < npins; i++) { 371 ret = ur_set_pin_mux_by_num(pctrl, pins[i], route->mode); 372 if (ret) 373 return ret; 374 } 375 376 return 0; 377 } 378 379 static const struct pinmux_ops ur_pinmux_ops = { 380 .get_functions_count = pinmux_generic_get_function_count, 381 .get_function_name = pinmux_generic_get_function_name, 382 .get_function_groups = pinmux_generic_get_function_groups, 383 .function_is_gpio = ur_function_is_gpio, 384 .set_mux = ur_set_mux, 385 .gpio_request_enable = ur_gpio_request_enable, 386 .strict = true, 387 }; 388 389 static int ur_pin_config_get(struct pinctrl_dev *pctldev, 390 unsigned int pin, 391 unsigned long *config) 392 { 393 struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 394 u32 conf; 395 int ret; 396 397 ret = ur_read_pin_conf(pctrl, pin, &conf); 398 if (ret) 399 return ret; 400 401 return ur_hw_to_config(config, conf); 402 } 403 404 static int ur_pin_config_set(struct pinctrl_dev *pctldev, 405 unsigned int pin, 406 unsigned long *configs, 407 unsigned int num_configs) 408 { 409 struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 410 u32 conf; 411 int ret; 412 413 ret = ur_read_pin_conf(pctrl, pin, &conf); 414 if (ret) 415 return ret; 416 417 for (u32 i = 0; i < num_configs; i++) { 418 ret = ur_config_to_hw(configs[i], &conf); 419 if (ret) 420 return ret; 421 } 422 423 return ur_write_pin_conf(pctrl, pin, conf); 424 } 425 426 static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, 427 unsigned int selector, 428 unsigned long *config) 429 { 430 const unsigned int *pins; 431 unsigned int npins; 432 int ret; 433 434 ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); 435 if (ret || !npins) 436 return ret ?: -EINVAL; 437 438 return ur_pin_config_get(pctldev, pins[0], config); 439 } 440 441 static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, 442 unsigned int selector, 443 unsigned long *configs, 444 unsigned int num_configs) 445 { 446 const unsigned int *pins; 447 unsigned int npins; 448 int ret; 449 450 ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); 451 if (ret) 452 return ret; 453 454 for (u32 i = 0; i < npins; i++) { 455 ret = ur_pin_config_set(pctldev, pins[i], configs, num_configs); 456 if (ret) 457 return ret; 458 } 459 460 return 0; 461 } 462 463 static const struct pinconf_ops ur_pinconf_ops = { 464 .pin_config_get = ur_pin_config_get, 465 .pin_config_set = ur_pin_config_set, 466 .pin_config_group_get = ur_pin_config_group_get, 467 .pin_config_group_set = ur_pin_config_group_set, 468 .is_generic = true, 469 .pin_config_config_dbg_show = pinconf_generic_dump_config, 470 }; 471 472 int ur_pinctrl_probe(struct platform_device *pdev, 473 const struct ur_pinctrl_data *data) 474 { 475 struct pinctrl_desc *desc; 476 struct ur_pinctrl *pctrl; 477 int ret; 478 479 if (!data) 480 return -ENODEV; 481 482 desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL); 483 if (!desc) 484 return -ENOMEM; 485 486 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 487 if (!pctrl) 488 return -ENOMEM; 489 490 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 491 if (IS_ERR(pctrl->base)) 492 return PTR_ERR(pctrl->base); 493 pctrl->dev = &pdev->dev; 494 pctrl->data = data; 495 496 raw_spin_lock_init(&pctrl->lock); 497 498 desc->name = dev_name(&pdev->dev); 499 desc->owner = THIS_MODULE; 500 desc->pins = data->pins; 501 desc->npins = data->npins; 502 desc->pctlops = &ur_pinctrl_ops; 503 desc->pmxops = &ur_pinmux_ops; 504 desc->confops = &ur_pinconf_ops; 505 506 ret = devm_pinctrl_register_and_init(&pdev->dev, desc, pctrl, &pctrl->pctl_dev); 507 if (ret) 508 return dev_err_probe(&pdev->dev, ret, "failed to register pinctrl\n"); 509 510 platform_set_drvdata(pdev, pctrl); 511 512 return pinctrl_enable(pctrl->pctl_dev); 513 } 514 EXPORT_SYMBOL_GPL(ur_pinctrl_probe); 515 516 MODULE_DESCRIPTION("UltraRISC pinctrl core driver"); 517 MODULE_LICENSE("GPL"); 518