1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. 4 * 5 * Author: Jia Wang <wangjia@ultrarisc.com> 6 */ 7 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 12 #include "pinctrl-ultrarisc.h" 13 14 /* Port indices. */ 15 #define UR_DP1000_PORT_A_IDX 0 16 #define UR_DP1000_PORT_B_IDX 1 17 #define UR_DP1000_PORT_C_IDX 2 18 #define UR_DP1000_PORT_D_IDX 3 19 #define UR_DP1000_PORT_LPC_IDX 4 20 21 /* Port mux register offsets. */ 22 #define UR_DP1000_PORTA_FUNC_OFFSET 0x2c0 23 #define UR_DP1000_PORTB_FUNC_OFFSET 0x2c4 24 #define UR_DP1000_PORTC_FUNC_OFFSET 0x2c8 25 #define UR_DP1000_PORTD_FUNC_OFFSET 0x2cc 26 #define UR_DP1000_PORTLPC_FUNC_OFFSET 0x2d0 27 28 /* Port pinconf register offsets. */ 29 #define UR_DP1000_PORTA_CONF_OFFSET 0x310 30 #define UR_DP1000_PORTB_CONF_OFFSET 0x318 31 #define UR_DP1000_PORTC_CONF_OFFSET 0x31c 32 #define UR_DP1000_PORTD_CONF_OFFSET 0x320 33 #define UR_DP1000_PORTLPC_CONF_OFFSET 0x324 34 35 /* Pin ranges for function descriptors. */ 36 #define UR_DP1000_PINS_ABCD GENMASK_ULL(39, 0) 37 #define UR_DP1000_PINS_LPC GENMASK_ULL(52, 40) 38 39 /* Static table entry helpers. */ 40 #define UR_DP1000_PORT(_base, _npins, _func, _conf, _modes, _gpio) \ 41 { .pin_base = (_base), .npins = (_npins), .func_offset = (_func), \ 42 .conf_offset = (_conf), .supported_modes = (_modes), \ 43 .supports_gpio = (_gpio) } 44 45 #define UR_DP1000_PIN(_nr, _name, _port) \ 46 { .number = (_nr), .name = (_name), .drv_data = (void *)&ur_dp1000_ports[_port] } 47 48 static const struct ur_func_route ur_dp1000_routes[] = { 49 { "gpio", UR_FUNC_DEFAULT, UR_DP1000_PINS_ABCD }, 50 { "i2c", UR_FUNC_0, GENMASK_ULL(13, 12) }, 51 { "i2c", UR_FUNC_0, GENMASK_ULL(23, 22) }, 52 { "i2c", UR_FUNC_0, GENMASK_ULL(25, 24) }, 53 { "i2c", UR_FUNC_0, GENMASK_ULL(27, 26) }, 54 { "pwm", UR_FUNC_0, GENMASK_ULL(19, 16) }, 55 { "spi", UR_FUNC_1, GENMASK_ULL(39, 32) }, 56 { "spi", UR_FUNC_0, GENMASK_ULL(6, 0) }, 57 { "uart", UR_FUNC_1, GENMASK_ULL(9, 8) }, 58 { "uart", UR_FUNC_0, GENMASK_ULL(21, 20) }, 59 { "uart", UR_FUNC_0, GENMASK_ULL(29, 28) }, 60 { "uart", UR_FUNC_0, GENMASK_ULL(31, 30) }, 61 { "lpc", UR_FUNC_DEFAULT, UR_DP1000_PINS_LPC }, 62 { "espi", UR_FUNC_0, UR_DP1000_PINS_LPC }, 63 }; 64 65 static const struct ur_port_desc ur_dp1000_ports[] = { 66 UR_DP1000_PORT(0, 16, UR_DP1000_PORTA_FUNC_OFFSET, 67 UR_DP1000_PORTA_CONF_OFFSET, 68 UR_FUNC_0 | UR_FUNC_1, true), 69 UR_DP1000_PORT(16, 8, UR_DP1000_PORTB_FUNC_OFFSET, 70 UR_DP1000_PORTB_CONF_OFFSET, 71 UR_FUNC_0 | UR_FUNC_1, true), 72 UR_DP1000_PORT(24, 8, UR_DP1000_PORTC_FUNC_OFFSET, 73 UR_DP1000_PORTC_CONF_OFFSET, 74 UR_FUNC_0 | UR_FUNC_1, true), 75 UR_DP1000_PORT(32, 8, UR_DP1000_PORTD_FUNC_OFFSET, 76 UR_DP1000_PORTD_CONF_OFFSET, 77 UR_FUNC_0 | UR_FUNC_1, true), 78 UR_DP1000_PORT(40, 13, UR_DP1000_PORTLPC_FUNC_OFFSET, 79 UR_DP1000_PORTLPC_CONF_OFFSET, 80 UR_FUNC_0, false), 81 }; 82 83 static const struct pinctrl_pin_desc ur_dp1000_pins[] = { 84 UR_DP1000_PIN(0, "PA0", UR_DP1000_PORT_A_IDX), 85 UR_DP1000_PIN(1, "PA1", UR_DP1000_PORT_A_IDX), 86 UR_DP1000_PIN(2, "PA2", UR_DP1000_PORT_A_IDX), 87 UR_DP1000_PIN(3, "PA3", UR_DP1000_PORT_A_IDX), 88 UR_DP1000_PIN(4, "PA4", UR_DP1000_PORT_A_IDX), 89 UR_DP1000_PIN(5, "PA5", UR_DP1000_PORT_A_IDX), 90 UR_DP1000_PIN(6, "PA6", UR_DP1000_PORT_A_IDX), 91 UR_DP1000_PIN(7, "PA7", UR_DP1000_PORT_A_IDX), 92 UR_DP1000_PIN(8, "PA8", UR_DP1000_PORT_A_IDX), 93 UR_DP1000_PIN(9, "PA9", UR_DP1000_PORT_A_IDX), 94 UR_DP1000_PIN(10, "PA10", UR_DP1000_PORT_A_IDX), 95 UR_DP1000_PIN(11, "PA11", UR_DP1000_PORT_A_IDX), 96 UR_DP1000_PIN(12, "PA12", UR_DP1000_PORT_A_IDX), 97 UR_DP1000_PIN(13, "PA13", UR_DP1000_PORT_A_IDX), 98 UR_DP1000_PIN(14, "PA14", UR_DP1000_PORT_A_IDX), 99 UR_DP1000_PIN(15, "PA15", UR_DP1000_PORT_A_IDX), 100 UR_DP1000_PIN(16, "PB0", UR_DP1000_PORT_B_IDX), 101 UR_DP1000_PIN(17, "PB1", UR_DP1000_PORT_B_IDX), 102 UR_DP1000_PIN(18, "PB2", UR_DP1000_PORT_B_IDX), 103 UR_DP1000_PIN(19, "PB3", UR_DP1000_PORT_B_IDX), 104 UR_DP1000_PIN(20, "PB4", UR_DP1000_PORT_B_IDX), 105 UR_DP1000_PIN(21, "PB5", UR_DP1000_PORT_B_IDX), 106 UR_DP1000_PIN(22, "PB6", UR_DP1000_PORT_B_IDX), 107 UR_DP1000_PIN(23, "PB7", UR_DP1000_PORT_B_IDX), 108 UR_DP1000_PIN(24, "PC0", UR_DP1000_PORT_C_IDX), 109 UR_DP1000_PIN(25, "PC1", UR_DP1000_PORT_C_IDX), 110 UR_DP1000_PIN(26, "PC2", UR_DP1000_PORT_C_IDX), 111 UR_DP1000_PIN(27, "PC3", UR_DP1000_PORT_C_IDX), 112 UR_DP1000_PIN(28, "PC4", UR_DP1000_PORT_C_IDX), 113 UR_DP1000_PIN(29, "PC5", UR_DP1000_PORT_C_IDX), 114 UR_DP1000_PIN(30, "PC6", UR_DP1000_PORT_C_IDX), 115 UR_DP1000_PIN(31, "PC7", UR_DP1000_PORT_C_IDX), 116 UR_DP1000_PIN(32, "PD0", UR_DP1000_PORT_D_IDX), 117 UR_DP1000_PIN(33, "PD1", UR_DP1000_PORT_D_IDX), 118 UR_DP1000_PIN(34, "PD2", UR_DP1000_PORT_D_IDX), 119 UR_DP1000_PIN(35, "PD3", UR_DP1000_PORT_D_IDX), 120 UR_DP1000_PIN(36, "PD4", UR_DP1000_PORT_D_IDX), 121 UR_DP1000_PIN(37, "PD5", UR_DP1000_PORT_D_IDX), 122 UR_DP1000_PIN(38, "PD6", UR_DP1000_PORT_D_IDX), 123 UR_DP1000_PIN(39, "PD7", UR_DP1000_PORT_D_IDX), 124 UR_DP1000_PIN(40, "LPC0", UR_DP1000_PORT_LPC_IDX), 125 UR_DP1000_PIN(41, "LPC1", UR_DP1000_PORT_LPC_IDX), 126 UR_DP1000_PIN(42, "LPC2", UR_DP1000_PORT_LPC_IDX), 127 UR_DP1000_PIN(43, "LPC3", UR_DP1000_PORT_LPC_IDX), 128 UR_DP1000_PIN(44, "LPC4", UR_DP1000_PORT_LPC_IDX), 129 UR_DP1000_PIN(45, "LPC5", UR_DP1000_PORT_LPC_IDX), 130 UR_DP1000_PIN(46, "LPC6", UR_DP1000_PORT_LPC_IDX), 131 UR_DP1000_PIN(47, "LPC7", UR_DP1000_PORT_LPC_IDX), 132 UR_DP1000_PIN(48, "LPC8", UR_DP1000_PORT_LPC_IDX), 133 UR_DP1000_PIN(49, "LPC9", UR_DP1000_PORT_LPC_IDX), 134 UR_DP1000_PIN(50, "LPC10", UR_DP1000_PORT_LPC_IDX), 135 UR_DP1000_PIN(51, "LPC11", UR_DP1000_PORT_LPC_IDX), 136 UR_DP1000_PIN(52, "LPC12", UR_DP1000_PORT_LPC_IDX), 137 }; 138 139 static const struct ur_pinctrl_data ur_dp1000_pinctrl_data = { 140 .pins = ur_dp1000_pins, 141 .npins = ARRAY_SIZE(ur_dp1000_pins), 142 .routes = ur_dp1000_routes, 143 .num_routes = ARRAY_SIZE(ur_dp1000_routes), 144 }; 145 146 static const struct of_device_id ur_pinctrl_of_match[] = { 147 { .compatible = "ultrarisc,dp1000-pinctrl" }, 148 { } 149 }; 150 MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); 151 152 static int ur_dp1000_pinctrl_probe(struct platform_device *pdev) 153 { 154 return ur_pinctrl_probe(pdev, &ur_dp1000_pinctrl_data); 155 } 156 157 static struct platform_driver ur_pinctrl_driver = { 158 .driver = { 159 .name = "ultrarisc-pinctrl-dp1000", 160 .of_match_table = ur_pinctrl_of_match, 161 }, 162 .probe = ur_dp1000_pinctrl_probe, 163 }; 164 165 module_platform_driver(ur_pinctrl_driver); 166 167 MODULE_DESCRIPTION("UltraRISC DP1000 pinctrl driver"); 168 MODULE_LICENSE("GPL"); 169