1 /*
2 * Allwinner H3 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/pinctrl/pinctrl.h>
19
20 #include "pinctrl-sunxi.h"
21
22 static const struct sunxi_desc_pin sun8i_h3_pins[] = {
23 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
24 SUNXI_FUNCTION(0x0, "gpio_in"),
25 SUNXI_FUNCTION(0x1, "gpio_out"),
26 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
27 SUNXI_FUNCTION(0x3, "jtag"), /* MS */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
33 SUNXI_FUNCTION(0x3, "jtag"), /* CK */
34 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
35 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
36 SUNXI_FUNCTION(0x0, "gpio_in"),
37 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
39 SUNXI_FUNCTION(0x3, "jtag"), /* DO */
40 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
42 SUNXI_FUNCTION(0x0, "gpio_in"),
43 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
45 SUNXI_FUNCTION(0x3, "jtag"), /* DI */
46 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
51 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
56 SUNXI_FUNCTION(0x3, "pwm0"),
57 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
62 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "sim"), /* CLK */
67 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "sim"), /* DATA */
72 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "sim"), /* RST */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "sim"), /* DET */
82 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
87 SUNXI_FUNCTION(0x3, "di"), /* TX */
88 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
93 SUNXI_FUNCTION(0x3, "di"), /* RX */
94 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
99 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
100 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
105 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
106 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
111 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
112 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
117 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
118 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
119 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
120 SUNXI_FUNCTION(0x0, "gpio_in"),
121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
128 SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
129 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
130 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
131 SUNXI_FUNCTION(0x0, "gpio_in"),
132 SUNXI_FUNCTION(0x1, "gpio_out"),
133 SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
134 SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
135 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
140 SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */
141 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
142 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
143 SUNXI_FUNCTION(0x0, "gpio_in"),
144 SUNXI_FUNCTION(0x1, "gpio_out"),
145 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
146 SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */
147 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
148 /* Hole */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
153 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
158 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
163 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
168 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
169 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
170 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out"),
172 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
174 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
177 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
178 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
179 SUNXI_FUNCTION(0x0, "gpio_in"),
180 SUNXI_FUNCTION(0x1, "gpio_out"),
181 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
182 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
183 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
184 SUNXI_FUNCTION(0x0, "gpio_in"),
185 SUNXI_FUNCTION(0x1, "gpio_out"),
186 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out"),
190 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
191 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
192 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
193 SUNXI_FUNCTION(0x0, "gpio_in"),
194 SUNXI_FUNCTION(0x1, "gpio_out"),
195 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
196 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
197 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
198 SUNXI_FUNCTION(0x0, "gpio_in"),
199 SUNXI_FUNCTION(0x1, "gpio_out"),
200 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
201 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
206 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
211 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
216 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
221 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
226 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
231 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
232 /* Hole */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "emac")), /* RXD3 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "emac")), /* RXD2 */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "emac")), /* RXD1 */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "emac")), /* RXD0 */
249 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
250 SUNXI_FUNCTION(0x0, "gpio_in"),
251 SUNXI_FUNCTION(0x1, "gpio_out"),
252 SUNXI_FUNCTION(0x2, "emac")), /* RXCK */
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
254 SUNXI_FUNCTION(0x0, "gpio_in"),
255 SUNXI_FUNCTION(0x1, "gpio_out"),
256 SUNXI_FUNCTION(0x2, "emac")), /* RXCTL/RXDV */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "emac")), /* RXERR */
261 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
262 SUNXI_FUNCTION(0x0, "gpio_in"),
263 SUNXI_FUNCTION(0x1, "gpio_out"),
264 SUNXI_FUNCTION(0x2, "emac")), /* TXD3 */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "emac")), /* TXD2 */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
270 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out"),
272 SUNXI_FUNCTION(0x2, "emac")), /* TXD1 */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "emac")), /* TXD0 */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "emac")), /* CRS */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
282 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out"),
284 SUNXI_FUNCTION(0x2, "emac")), /* TXCK */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "emac")), /* TXCTL/TXEN */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "emac")), /* TXERR */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "emac")), /* CLKIN/COL */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "emac")), /* MDC */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "emac")), /* MDIO */
305 /* Hole */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
310 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out"),
314 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
315 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
316 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
317 SUNXI_FUNCTION(0x0, "gpio_in"),
318 SUNXI_FUNCTION(0x1, "gpio_out"),
319 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
320 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
321 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
322 SUNXI_FUNCTION(0x0, "gpio_in"),
323 SUNXI_FUNCTION(0x1, "gpio_out"),
324 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
325 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
330 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
335 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
337 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out"),
339 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
340 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
341 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
342 SUNXI_FUNCTION(0x0, "gpio_in"),
343 SUNXI_FUNCTION(0x1, "gpio_out"),
344 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
345 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
346 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
347 SUNXI_FUNCTION(0x0, "gpio_in"),
348 SUNXI_FUNCTION(0x1, "gpio_out"),
349 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
350 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
355 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
357 SUNXI_FUNCTION(0x0, "gpio_in"),
358 SUNXI_FUNCTION(0x1, "gpio_out"),
359 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
360 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
361 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
362 SUNXI_FUNCTION(0x0, "gpio_in"),
363 SUNXI_FUNCTION(0x1, "gpio_out"),
364 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
365 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
366 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
370 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
375 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
376 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
377 SUNXI_FUNCTION(0x0, "gpio_in"),
378 SUNXI_FUNCTION(0x1, "gpio_out")),
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out")),
382 /* Hole */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
387 SUNXI_FUNCTION(0x3, "jtag")), /* MS */
388 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
389 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out"),
391 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
392 SUNXI_FUNCTION(0x3, "jtag")), /* DI */
393 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
394 SUNXI_FUNCTION(0x0, "gpio_in"),
395 SUNXI_FUNCTION(0x1, "gpio_out"),
396 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
397 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
398 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
399 SUNXI_FUNCTION(0x0, "gpio_in"),
400 SUNXI_FUNCTION(0x1, "gpio_out"),
401 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
402 SUNXI_FUNCTION(0x3, "jtag")), /* DO */
403 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
404 SUNXI_FUNCTION(0x0, "gpio_in"),
405 SUNXI_FUNCTION(0x1, "gpio_out"),
406 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
407 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
408 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
409 SUNXI_FUNCTION(0x0, "gpio_in"),
410 SUNXI_FUNCTION(0x1, "gpio_out"),
411 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
412 SUNXI_FUNCTION(0x3, "jtag")), /* CK */
413 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
414 SUNXI_FUNCTION(0x0, "gpio_in"),
415 SUNXI_FUNCTION(0x1, "gpio_out")),
416 /* Hole */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
421 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
426 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
431 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
436 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
441 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
446 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
451 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
456 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
461 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
466 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
471 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
476 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
481 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out"),
485 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
486 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
487 };
488
489 static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = {
490 .pins = sun8i_h3_pins,
491 .npins = ARRAY_SIZE(sun8i_h3_pins),
492 .irq_banks = 2,
493 .irq_read_needs_mux = true,
494 .disable_strict_mode = true,
495 };
496
sun8i_h3_pinctrl_probe(struct platform_device * pdev)497 static int sun8i_h3_pinctrl_probe(struct platform_device *pdev)
498 {
499 return sunxi_pinctrl_init(pdev,
500 &sun8i_h3_pinctrl_data);
501 }
502
503 static const struct of_device_id sun8i_h3_pinctrl_match[] = {
504 { .compatible = "allwinner,sun8i-h3-pinctrl", },
505 {}
506 };
507
508 static struct platform_driver sun8i_h3_pinctrl_driver = {
509 .probe = sun8i_h3_pinctrl_probe,
510 .driver = {
511 .name = "sun8i-h3-pinctrl",
512 .of_match_table = sun8i_h3_pinctrl_match,
513 },
514 };
515 builtin_platform_driver(sun8i_h3_pinctrl_driver);
516