1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Sophgo SG2002 SoC pinctrl driver.
4 *
5 * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6 *
7 * This file is generated from vendor pinout definition.
8 */
9
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/of.h>
13
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16
17 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
18
19 #include "pinctrl-cv18xx.h"
20
21 enum SG2002_POWER_DOMAIN {
22 VDD18A_MIPI = 0,
23 VDD18A_USB_PLL_ETH = 1,
24 VDDIO_RTC = 2,
25 VDDIO_SD0_EMMC = 3,
26 VDDIO_SD1 = 4
27 };
28
29 static const char *const sg2002_power_domain_desc[] = {
30 [VDD18A_MIPI] = "VDD18A_MIPI",
31 [VDD18A_USB_PLL_ETH] = "VDD18A_USB_PLL_ETH",
32 [VDDIO_RTC] = "VDDIO_RTC",
33 [VDDIO_SD0_EMMC] = "VDDIO_SD0_EMMC",
34 [VDDIO_SD1] = "VDDIO_SD1",
35 };
36
sg2002_get_pull_up(struct cv1800_pin * pin,const u32 * psmap)37 static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
38 {
39 u32 pstate = psmap[pin->power_domain];
40 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
41
42 if (type == IO_TYPE_1V8_ONLY)
43 return 79000;
44
45 if (type == IO_TYPE_1V8_OR_3V3) {
46 if (pstate == PIN_POWER_STATE_1V8)
47 return 60000;
48 if (pstate == PIN_POWER_STATE_3V3)
49 return 60000;
50
51 return -EINVAL;
52 }
53
54 return -ENOTSUPP;
55 }
56
sg2002_get_pull_down(struct cv1800_pin * pin,const u32 * psmap)57 static int sg2002_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
58 {
59 u32 pstate = psmap[pin->power_domain];
60 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
61
62 if (type == IO_TYPE_1V8_ONLY)
63 return 87000;
64
65 if (type == IO_TYPE_1V8_OR_3V3) {
66 if (pstate == PIN_POWER_STATE_1V8)
67 return 61000;
68 if (pstate == PIN_POWER_STATE_3V3)
69 return 62000;
70
71 return -EINVAL;
72 }
73
74 return -ENOTSUPP;
75 }
76
77 static const u32 sg2002_1v8_oc_map[] = {
78 12800,
79 25300,
80 37400,
81 49000
82 };
83
84 static const u32 sg2002_18od33_1v8_oc_map[] = {
85 7800,
86 11700,
87 15500,
88 19200,
89 23000,
90 26600,
91 30200,
92 33700
93 };
94
95 static const u32 sg2002_18od33_3v3_oc_map[] = {
96 5500,
97 8200,
98 10800,
99 13400,
100 16100,
101 18700,
102 21200,
103 23700
104 };
105
106 static const u32 sg2002_eth_oc_map[] = {
107 15700,
108 17800
109 };
110
sg2002_get_oc_map(struct cv1800_pin * pin,const u32 * psmap,const u32 ** map)111 static int sg2002_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
112 const u32 **map)
113 {
114 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
115 u32 pstate = psmap[pin->power_domain];
116
117 if (type == IO_TYPE_1V8_ONLY) {
118 *map = sg2002_1v8_oc_map;
119 return ARRAY_SIZE(sg2002_1v8_oc_map);
120 }
121
122 if (type == IO_TYPE_1V8_OR_3V3) {
123 if (pstate == PIN_POWER_STATE_1V8) {
124 *map = sg2002_18od33_1v8_oc_map;
125 return ARRAY_SIZE(sg2002_18od33_1v8_oc_map);
126 } else if (pstate == PIN_POWER_STATE_3V3) {
127 *map = sg2002_18od33_3v3_oc_map;
128 return ARRAY_SIZE(sg2002_18od33_3v3_oc_map);
129 }
130 }
131
132 if (type == IO_TYPE_ETH) {
133 *map = sg2002_eth_oc_map;
134 return ARRAY_SIZE(sg2002_eth_oc_map);
135 }
136
137 return -ENOTSUPP;
138 }
139
140 static const u32 sg2002_1v8_schmitt_map[] = {
141 0,
142 970000,
143 1040000
144 };
145
146 static const u32 sg2002_18od33_1v8_schmitt_map[] = {
147 0,
148 1070000
149 };
150
151 static const u32 sg2002_18od33_3v3_schmitt_map[] = {
152 0,
153 1100000
154 };
155
sg2002_get_schmitt_map(struct cv1800_pin * pin,const u32 * psmap,const u32 ** map)156 static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
157 const u32 **map)
158 {
159 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
160 u32 pstate = psmap[pin->power_domain];
161
162 if (type == IO_TYPE_1V8_ONLY) {
163 *map = sg2002_1v8_schmitt_map;
164 return ARRAY_SIZE(sg2002_1v8_schmitt_map);
165 }
166
167 if (type == IO_TYPE_1V8_OR_3V3) {
168 if (pstate == PIN_POWER_STATE_1V8) {
169 *map = sg2002_18od33_1v8_schmitt_map;
170 return ARRAY_SIZE(sg2002_18od33_1v8_schmitt_map);
171 } else if (pstate == PIN_POWER_STATE_3V3) {
172 *map = sg2002_18od33_3v3_schmitt_map;
173 return ARRAY_SIZE(sg2002_18od33_3v3_schmitt_map);
174 }
175 }
176
177 return -ENOTSUPP;
178 }
179
180 static const struct cv1800_vddio_cfg_ops sg2002_vddio_cfg_ops = {
181 .get_pull_up = sg2002_get_pull_up,
182 .get_pull_down = sg2002_get_pull_down,
183 .get_oc_map = sg2002_get_oc_map,
184 .get_schmitt_map = sg2002_get_schmitt_map,
185 };
186
187 static const struct pinctrl_pin_desc sg2002_pins[] = {
188 PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
189 PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
190 PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
191 PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
192 PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
193 PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
194 PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
195 PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
196 PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
197 PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
198 PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
199 PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
200 PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
201 PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
202 PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
203 PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
204 PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
205 PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
206 PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
207 PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
208 PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
209 PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
210 PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
211 PINCTRL_PIN(PIN_AUX0, "AUX0"),
212 PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
213 PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
214 PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
215 PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
216 PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
217 PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
218 PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
219 PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
220 PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
221 PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
222 PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
223 PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
224 PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
225 PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
226 PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
227 PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
228 PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
229 PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
230 PINCTRL_PIN(PIN_ADC1, "ADC1"),
231 PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
232 PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
233 PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
234 PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
235 PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
236 PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
237 PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
238 PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
239 PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
240 PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
241 PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
242 PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
243 PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
244 PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
245 PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
246 PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
247 PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
248 PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
249 PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
250 PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
251 PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
252 PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
253 };
254
255 static const struct cv1800_pin sg2002_pin_data[ARRAY_SIZE(sg2002_pins)] = {
256 CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
257 IO_TYPE_AUDIO,
258 CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
259 CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
260 IO_TYPE_AUDIO,
261 CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
262 CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0_EMMC,
263 IO_TYPE_1V8_OR_3V3,
264 CV1800_PINCONF_AREA_SYS, 0x01c, 7,
265 CV1800_PINCONF_AREA_SYS, 0xa00),
266 CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0_EMMC,
267 IO_TYPE_1V8_OR_3V3,
268 CV1800_PINCONF_AREA_SYS, 0x020, 7,
269 CV1800_PINCONF_AREA_SYS, 0xa04),
270 CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0_EMMC,
271 IO_TYPE_1V8_OR_3V3,
272 CV1800_PINCONF_AREA_SYS, 0x024, 7,
273 CV1800_PINCONF_AREA_SYS, 0xa08),
274 CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0_EMMC,
275 IO_TYPE_1V8_OR_3V3,
276 CV1800_PINCONF_AREA_SYS, 0x028, 7,
277 CV1800_PINCONF_AREA_SYS, 0xa0c),
278 CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0_EMMC,
279 IO_TYPE_1V8_OR_3V3,
280 CV1800_PINCONF_AREA_SYS, 0x02c, 7,
281 CV1800_PINCONF_AREA_SYS, 0xa10),
282 CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0_EMMC,
283 IO_TYPE_1V8_OR_3V3,
284 CV1800_PINCONF_AREA_SYS, 0x030, 7,
285 CV1800_PINCONF_AREA_SYS, 0xa14),
286 CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_SD0_EMMC,
287 IO_TYPE_1V8_OR_3V3,
288 CV1800_PINCONF_AREA_SYS, 0x034, 3,
289 CV1800_PINCONF_AREA_SYS, 0x900),
290 CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_SD0_EMMC,
291 IO_TYPE_1V8_OR_3V3,
292 CV1800_PINCONF_AREA_SYS, 0x038, 3,
293 CV1800_PINCONF_AREA_SYS, 0x904),
294 CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_SD0_EMMC,
295 IO_TYPE_1V8_OR_3V3,
296 CV1800_PINCONF_AREA_SYS, 0x03c, 3,
297 CV1800_PINCONF_AREA_SYS, 0x908),
298 CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_SD0_EMMC,
299 IO_TYPE_1V8_OR_3V3,
300 CV1800_PINCONF_AREA_SYS, 0x040, 7,
301 CV1800_PINCONF_AREA_SYS, 0x90c),
302 CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_SD0_EMMC,
303 IO_TYPE_1V8_OR_3V3,
304 CV1800_PINCONF_AREA_SYS, 0x044, 7,
305 CV1800_PINCONF_AREA_SYS, 0x910),
306 CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_SD0_EMMC,
307 IO_TYPE_1V8_OR_3V3,
308 CV1800_PINCONF_AREA_SYS, 0x04c, 3,
309 CV1800_PINCONF_AREA_SYS, 0x918),
310 CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_SD0_EMMC,
311 IO_TYPE_1V8_OR_3V3,
312 CV1800_PINCONF_AREA_SYS, 0x050, 3,
313 CV1800_PINCONF_AREA_SYS, 0x91c),
314 CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_SD0_EMMC,
315 IO_TYPE_1V8_OR_3V3,
316 CV1800_PINCONF_AREA_SYS, 0x054, 3,
317 CV1800_PINCONF_AREA_SYS, 0x920),
318 CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_SD0_EMMC,
319 IO_TYPE_1V8_OR_3V3,
320 CV1800_PINCONF_AREA_SYS, 0x058, 3,
321 CV1800_PINCONF_AREA_SYS, 0x924),
322 CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_SD0_EMMC,
323 IO_TYPE_1V8_OR_3V3,
324 CV1800_PINCONF_AREA_SYS, 0x05c, 3,
325 CV1800_PINCONF_AREA_SYS, 0x928),
326 CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_SD0_EMMC,
327 IO_TYPE_1V8_OR_3V3,
328 CV1800_PINCONF_AREA_SYS, 0x060, 3,
329 CV1800_PINCONF_AREA_SYS, 0x92c),
330 CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_SD0_EMMC,
331 IO_TYPE_1V8_OR_3V3,
332 CV1800_PINCONF_AREA_SYS, 0x064, 7,
333 CV1800_PINCONF_AREA_SYS, 0x930),
334 CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_SD0_EMMC,
335 IO_TYPE_1V8_OR_3V3,
336 CV1800_PINCONF_AREA_SYS, 0x068, 7,
337 CV1800_PINCONF_AREA_SYS, 0x934),
338 CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_SD0_EMMC,
339 IO_TYPE_1V8_OR_3V3,
340 CV1800_PINCONF_AREA_SYS, 0x070, 7,
341 CV1800_PINCONF_AREA_SYS, 0x93c),
342 CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_SD0_EMMC,
343 IO_TYPE_1V8_OR_3V3,
344 CV1800_PINCONF_AREA_SYS, 0x074, 7,
345 CV1800_PINCONF_AREA_SYS, 0x940),
346 CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_SD0_EMMC,
347 IO_TYPE_1V8_OR_3V3,
348 CV1800_PINCONF_AREA_SYS, 0x078, 7,
349 CV1800_PINCONF_AREA_SYS, 0x944),
350 CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
351 IO_TYPE_1V8_ONLY,
352 CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
353 CV1800_PINCONF_AREA_RTC, 0x0e0),
354 CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
355 IO_TYPE_1V8_ONLY,
356 CV1800_PINCONF_AREA_SYS, 0x07c, 0,
357 CV1800_PINCONF_AREA_RTC, 0x000),
358 CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
359 IO_TYPE_1V8_ONLY,
360 CV1800_PINCONF_AREA_SYS, 0x080, 0,
361 CV1800_PINCONF_AREA_RTC, 0x004),
362 CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
363 IO_TYPE_1V8_ONLY,
364 CV1800_PINCONF_AREA_SYS, 0x084, 3,
365 CV1800_PINCONF_AREA_RTC, 0x008),
366 CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
367 IO_TYPE_1V8_ONLY,
368 CV1800_PINCONF_AREA_SYS, 0x088, 3,
369 CV1800_PINCONF_AREA_RTC, 0x00c),
370 CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
371 IO_TYPE_1V8_ONLY,
372 CV1800_PINCONF_AREA_SYS, 0x090, 7,
373 CV1800_PINCONF_AREA_RTC, 0x018),
374 CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
375 IO_TYPE_1V8_ONLY,
376 CV1800_PINCONF_AREA_SYS, 0x098, 7,
377 CV1800_PINCONF_AREA_RTC, 0x020),
378 CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
379 IO_TYPE_1V8_ONLY,
380 CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
381 CV1800_PINCONF_AREA_RTC, 0x028),
382 CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
383 IO_TYPE_1V8_ONLY,
384 CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
385 CV1800_PINCONF_AREA_RTC, 0x02c),
386 CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
387 IO_TYPE_1V8_ONLY,
388 CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
389 CV1800_PINCONF_AREA_RTC, 0x030),
390 CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
391 IO_TYPE_1V8_ONLY,
392 CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
393 CV1800_PINCONF_AREA_RTC, 0x034),
394 CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
395 IO_TYPE_1V8_OR_3V3,
396 CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
397 CV1800_PINCONF_AREA_RTC, 0x058),
398 CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
399 IO_TYPE_1V8_OR_3V3,
400 CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
401 CV1800_PINCONF_AREA_RTC, 0x05c),
402 CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
403 IO_TYPE_1V8_OR_3V3,
404 CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
405 CV1800_PINCONF_AREA_RTC, 0x060),
406 CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
407 IO_TYPE_1V8_OR_3V3,
408 CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
409 CV1800_PINCONF_AREA_RTC, 0x064),
410 CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
411 IO_TYPE_1V8_OR_3V3,
412 CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
413 CV1800_PINCONF_AREA_RTC, 0x068),
414 CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
415 IO_TYPE_1V8_OR_3V3,
416 CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
417 CV1800_PINCONF_AREA_RTC, 0x06c),
418 CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDD18A_USB_PLL_ETH,
419 IO_TYPE_1V8_ONLY,
420 CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
421 CV1800_PINCONF_AREA_SYS, 0x804),
422 CV1800_GENERAL_PIN(PIN_ADC1, VDD18A_USB_PLL_ETH,
423 IO_TYPE_1V8_ONLY,
424 CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
425 CV1800_PINCONF_AREA_SYS, 0x810),
426 CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDD18A_USB_PLL_ETH,
427 IO_TYPE_1V8_ONLY,
428 CV1800_PINCONF_AREA_SYS, 0x108, 5,
429 CV1800_PINCONF_AREA_SYS, 0x820),
430 CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_USB_PLL_ETH,
431 IO_TYPE_ETH,
432 CV1800_PINCONF_AREA_SYS, 0x124, 7),
433 CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_USB_PLL_ETH,
434 IO_TYPE_ETH,
435 CV1800_PINCONF_AREA_SYS, 0x128, 7),
436 CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_USB_PLL_ETH,
437 IO_TYPE_ETH,
438 CV1800_PINCONF_AREA_SYS, 0x12c, 7),
439 CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_USB_PLL_ETH,
440 IO_TYPE_ETH,
441 CV1800_PINCONF_AREA_SYS, 0x130, 7),
442 CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDD18A_USB_PLL_ETH,
443 IO_TYPE_1V8_ONLY,
444 CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
445 CV1800_PINCONF_AREA_SYS, 0xc8c),
446 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
447 IO_TYPE_1V8_ONLY,
448 CV1800_PINCONF_AREA_SYS, 0x16c, 7,
449 CV1800_PINCONF_AREA_SYS, 0x120, 7,
450 CV1800_PINCONF_AREA_SYS, 0xc38),
451 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
452 IO_TYPE_1V8_ONLY,
453 CV1800_PINCONF_AREA_SYS, 0x170, 7,
454 CV1800_PINCONF_AREA_SYS, 0x11c, 7,
455 CV1800_PINCONF_AREA_SYS, 0xc3c),
456 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
457 IO_TYPE_1V8_ONLY,
458 CV1800_PINCONF_AREA_SYS, 0x174, 7,
459 CV1800_PINCONF_AREA_SYS, 0x114, 7,
460 CV1800_PINCONF_AREA_SYS, 0xc40),
461 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
462 IO_TYPE_1V8_ONLY,
463 CV1800_PINCONF_AREA_SYS, 0x178, 7,
464 CV1800_PINCONF_AREA_SYS, 0x118, 7,
465 CV1800_PINCONF_AREA_SYS, 0xc44),
466 CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
467 IO_TYPE_1V8_ONLY,
468 CV1800_PINCONF_AREA_SYS, 0x17c, 7,
469 CV1800_PINCONF_AREA_SYS, 0xc48),
470 CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
471 IO_TYPE_1V8_ONLY,
472 CV1800_PINCONF_AREA_SYS, 0x180, 7,
473 CV1800_PINCONF_AREA_SYS, 0xc4c),
474 CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
475 IO_TYPE_1V8_ONLY,
476 CV1800_PINCONF_AREA_SYS, 0x184, 7,
477 CV1800_PINCONF_AREA_SYS, 0xc50),
478 CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
479 IO_TYPE_1V8_ONLY,
480 CV1800_PINCONF_AREA_SYS, 0x188, 7,
481 CV1800_PINCONF_AREA_SYS, 0xc54),
482 CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
483 IO_TYPE_1V8_ONLY,
484 CV1800_PINCONF_AREA_SYS, 0x18c, 7,
485 CV1800_PINCONF_AREA_SYS, 0xc58),
486 CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
487 IO_TYPE_1V8_ONLY,
488 CV1800_PINCONF_AREA_SYS, 0x190, 7,
489 CV1800_PINCONF_AREA_SYS, 0xc5c),
490 CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
491 IO_TYPE_1V8_ONLY,
492 CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
493 CV1800_PINCONF_AREA_SYS, 0xc70),
494 CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
495 IO_TYPE_1V8_ONLY,
496 CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
497 CV1800_PINCONF_AREA_SYS, 0xc74),
498 CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
499 IO_TYPE_1V8_ONLY,
500 CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
501 CV1800_PINCONF_AREA_SYS, 0xc78),
502 CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
503 IO_TYPE_1V8_ONLY,
504 CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
505 CV1800_PINCONF_AREA_SYS, 0xc7c),
506 CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
507 IO_TYPE_1V8_ONLY,
508 CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
509 CV1800_PINCONF_AREA_SYS, 0xc80),
510 CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
511 IO_TYPE_1V8_ONLY,
512 CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
513 CV1800_PINCONF_AREA_SYS, 0xc84),
514 };
515
516 static const struct cv1800_pinctrl_data sg2002_pindata = {
517 .pins = sg2002_pins,
518 .pindata = sg2002_pin_data,
519 .pdnames = sg2002_power_domain_desc,
520 .vddio_ops = &sg2002_vddio_cfg_ops,
521 .npins = ARRAY_SIZE(sg2002_pins),
522 .npd = ARRAY_SIZE(sg2002_power_domain_desc),
523 };
524
525 static const struct of_device_id sg2002_pinctrl_ids[] = {
526 { .compatible = "sophgo,sg2002-pinctrl", .data = &sg2002_pindata },
527 { }
528 };
529 MODULE_DEVICE_TABLE(of, sg2002_pinctrl_ids);
530
531 static struct platform_driver sg2002_pinctrl_driver = {
532 .probe = cv1800_pinctrl_probe,
533 .driver = {
534 .name = "sg2002-pinctrl",
535 .suppress_bind_attrs = true,
536 .of_match_table = sg2002_pinctrl_ids,
537 },
538 };
539 module_platform_driver(sg2002_pinctrl_driver);
540
541 MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC");
542 MODULE_LICENSE("GPL");
543