1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/T2H Pin Control and GPIO driver core 4 * 5 * Based on drivers/pinctrl/renesas/pinctrl-rzg2l.c 6 * 7 * Copyright (C) 2025 Renesas Electronics Corporation. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/bits.h> 13 #include <linux/cleanup.h> 14 #include <linux/clk.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/spinlock.h> 24 #include <linux/types.h> 25 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 32 #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 33 34 #include "../core.h" 35 #include "../pinconf.h" 36 #include "../pinmux.h" 37 38 #define DRV_NAME "pinctrl-rzt2h" 39 40 #define P(m) (0x001 * (m)) 41 #define PM(m) (0x200 + 2 * (m)) 42 #define PMC(m) (0x400 + (m)) 43 #define PFC(m) (0x600 + 8 * (m)) 44 #define PIN(m) (0x800 + (m)) 45 #define RSELP(m) (0xc00 + (m)) 46 47 #define PM_MASK GENMASK(1, 0) 48 #define PM_PIN_MASK(pin) (PM_MASK << ((pin) * 2)) 49 #define PM_INPUT BIT(0) 50 #define PM_OUTPUT BIT(1) 51 52 #define PFC_MASK GENMASK_ULL(5, 0) 53 #define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8)) 54 55 /* 56 * Use 16 lower bits [15:0] for pin identifier 57 * Use 8 higher bits [23:16] for pin mux function 58 */ 59 #define MUX_PIN_ID_MASK GENMASK(15, 0) 60 #define MUX_FUNC_MASK GENMASK(23, 16) 61 62 #define RZT2H_PIN_ID_TO_PORT(id) ((id) / RZT2H_PINS_PER_PORT) 63 #define RZT2H_PIN_ID_TO_PIN(id) ((id) % RZT2H_PINS_PER_PORT) 64 65 #define RZT2H_MAX_SAFETY_PORTS 12 66 67 struct rzt2h_pinctrl_data { 68 unsigned int n_port_pins; 69 const u8 *port_pin_configs; 70 unsigned int n_ports; 71 }; 72 73 struct rzt2h_pinctrl { 74 struct pinctrl_dev *pctl; 75 struct pinctrl_desc desc; 76 struct pinctrl_pin_desc *pins; 77 const struct rzt2h_pinctrl_data *data; 78 void __iomem *base0, *base1; 79 struct device *dev; 80 struct gpio_chip gpio_chip; 81 struct pinctrl_gpio_range gpio_range; 82 spinlock_t lock; /* lock read/write registers */ 83 struct mutex mutex; /* serialize adding groups and functions */ 84 bool safety_port_enabled; 85 }; 86 87 #define RZT2H_GET_BASE(pctrl, port) \ 88 ((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1) 89 90 #define RZT2H_PINCTRL_REG_ACCESS(size, type) \ 91 static inline void rzt2h_pinctrl_write##size(struct rzt2h_pinctrl *pctrl, u8 port, \ 92 type val, unsigned int offset) \ 93 { \ 94 write##size(val, RZT2H_GET_BASE(pctrl, port) + offset); \ 95 } \ 96 static inline type rzt2h_pinctrl_read##size(struct rzt2h_pinctrl *pctrl, u8 port, \ 97 unsigned int offset) \ 98 { \ 99 return read##size(RZT2H_GET_BASE(pctrl, port) + offset); \ 100 } 101 102 RZT2H_PINCTRL_REG_ACCESS(b, u8) 103 RZT2H_PINCTRL_REG_ACCESS(w, u16) 104 RZT2H_PINCTRL_REG_ACCESS(q, u64) 105 106 static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset) 107 { 108 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 109 u8 pin = RZT2H_PIN_ID_TO_PIN(offset); 110 u8 pincfg; 111 112 if (offset >= pctrl->data->n_port_pins || port >= pctrl->data->n_ports) 113 return -EINVAL; 114 115 if (!pctrl->safety_port_enabled && port <= RZT2H_MAX_SAFETY_PORTS) 116 return -EINVAL; 117 118 pincfg = pctrl->data->port_pin_configs[port]; 119 return (pincfg & BIT(pin)) ? 0 : -EINVAL; 120 } 121 122 static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, 123 u8 port, u8 pin, u8 func) 124 { 125 u64 reg64; 126 u16 reg16; 127 128 guard(spinlock_irqsave)(&pctrl->lock); 129 130 /* Set pin to 'Non-use (Hi-Z input protection)' */ 131 reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 132 reg16 &= ~PM_PIN_MASK(pin); 133 rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port)); 134 135 /* Temporarily switch to GPIO mode with PMC register */ 136 reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 137 rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port)); 138 139 /* Select Pin function mode with PFC register */ 140 reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); 141 reg64 &= ~PFC_PIN_MASK(pin); 142 rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port)); 143 144 /* Switch to Peripheral pin function with PMC register */ 145 reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 146 rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port)); 147 }; 148 149 static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev, 150 unsigned int func_selector, 151 unsigned int group_selector) 152 { 153 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 154 const struct function_desc *func; 155 struct group_desc *group; 156 const unsigned int *pins; 157 unsigned int i; 158 u8 *psel_val; 159 int ret; 160 161 func = pinmux_generic_get_function(pctldev, func_selector); 162 if (!func) 163 return -EINVAL; 164 165 group = pinctrl_generic_get_group(pctldev, group_selector); 166 if (!group) 167 return -EINVAL; 168 169 psel_val = func->data; 170 pins = group->grp.pins; 171 172 for (i = 0; i < group->grp.npins; i++) { 173 dev_dbg(pctrl->dev, "port:%u pin:%u PSEL:%u\n", 174 RZT2H_PIN_ID_TO_PORT(pins[i]), RZT2H_PIN_ID_TO_PIN(pins[i]), 175 psel_val[i]); 176 ret = rzt2h_validate_pin(pctrl, pins[i]); 177 if (ret) 178 return ret; 179 180 rzt2h_pinctrl_set_pfc_mode(pctrl, RZT2H_PIN_ID_TO_PORT(pins[i]), 181 RZT2H_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 182 } 183 184 return 0; 185 }; 186 187 static int rzt2h_map_add_config(struct pinctrl_map *map, 188 const char *group_or_pin, 189 enum pinctrl_map_type type, 190 unsigned long *configs, 191 unsigned int num_configs) 192 { 193 unsigned long *cfgs; 194 195 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 196 if (!cfgs) 197 return -ENOMEM; 198 199 map->type = type; 200 map->data.configs.group_or_pin = group_or_pin; 201 map->data.configs.configs = cfgs; 202 map->data.configs.num_configs = num_configs; 203 204 return 0; 205 } 206 207 static int rzt2h_dt_subnode_to_map(struct pinctrl_dev *pctldev, 208 struct device_node *np, 209 struct device_node *parent, 210 struct pinctrl_map **map, 211 unsigned int *num_maps, 212 unsigned int *index) 213 { 214 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 215 struct pinctrl_map *maps = *map; 216 unsigned int nmaps = *num_maps; 217 unsigned long *configs = NULL; 218 unsigned int num_pinmux = 0; 219 unsigned int idx = *index; 220 unsigned int num_pins, i; 221 unsigned int num_configs; 222 struct property *pinmux; 223 struct property *prop; 224 int ret, gsel, fsel; 225 const char **pin_fn; 226 unsigned int *pins; 227 const char *name; 228 const char *pin; 229 u8 *psel_val; 230 231 pinmux = of_find_property(np, "pinmux", NULL); 232 if (pinmux) 233 num_pinmux = pinmux->length / sizeof(u32); 234 235 ret = of_property_count_strings(np, "pins"); 236 if (ret == -EINVAL) { 237 num_pins = 0; 238 } else if (ret < 0) { 239 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 240 return ret; 241 } else { 242 num_pins = ret; 243 } 244 245 if (!num_pinmux && !num_pins) 246 return 0; 247 248 if (num_pinmux && num_pins) { 249 dev_err(pctrl->dev, 250 "DT node must contain either a pinmux or pins and not both\n"); 251 return -EINVAL; 252 } 253 254 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 255 if (ret < 0) 256 return ret; 257 258 if (num_pins && !num_configs) { 259 dev_err(pctrl->dev, "DT node must contain a config\n"); 260 ret = -ENODEV; 261 goto done; 262 } 263 264 if (num_pinmux) { 265 nmaps += 1; 266 if (num_configs) 267 nmaps += 1; 268 } 269 270 if (num_pins) 271 nmaps += num_pins; 272 273 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 274 if (!maps) { 275 ret = -ENOMEM; 276 goto done; 277 } 278 279 *map = maps; 280 *num_maps = nmaps; 281 if (num_pins) { 282 of_property_for_each_string(np, "pins", prop, pin) { 283 ret = rzt2h_map_add_config(&maps[idx], pin, 284 PIN_MAP_TYPE_CONFIGS_PIN, 285 configs, num_configs); 286 if (ret < 0) 287 goto done; 288 289 idx++; 290 } 291 ret = 0; 292 goto done; 293 } 294 295 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 296 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 297 GFP_KERNEL); 298 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 299 if (!pins || !psel_val || !pin_fn) { 300 ret = -ENOMEM; 301 goto done; 302 } 303 304 /* Collect pin locations and mux settings from DT properties */ 305 for (i = 0; i < num_pinmux; ++i) { 306 u32 value; 307 308 ret = of_property_read_u32_index(np, "pinmux", i, &value); 309 if (ret) 310 goto done; 311 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 312 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 313 } 314 315 if (parent) { 316 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 317 parent, np); 318 if (!name) { 319 ret = -ENOMEM; 320 goto done; 321 } 322 } else { 323 name = np->name; 324 } 325 326 if (num_configs) { 327 ret = rzt2h_map_add_config(&maps[idx], name, 328 PIN_MAP_TYPE_CONFIGS_GROUP, 329 configs, num_configs); 330 if (ret < 0) 331 goto done; 332 333 idx++; 334 } 335 336 scoped_guard(mutex, &pctrl->mutex) { 337 /* Register a single pin group listing all the pins we read from DT */ 338 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 339 if (gsel < 0) { 340 ret = gsel; 341 goto done; 342 } 343 344 /* 345 * Register a single group function where the 'data' is an array PSEL 346 * register values read from DT. 347 */ 348 pin_fn[0] = name; 349 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 350 if (fsel < 0) { 351 ret = fsel; 352 goto remove_group; 353 } 354 } 355 356 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 357 maps[idx].data.mux.group = name; 358 maps[idx].data.mux.function = name; 359 idx++; 360 361 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 362 ret = 0; 363 goto done; 364 365 remove_group: 366 pinctrl_generic_remove_group(pctldev, gsel); 367 done: 368 *index = idx; 369 kfree(configs); 370 return ret; 371 } 372 373 static void rzt2h_dt_free_map(struct pinctrl_dev *pctldev, 374 struct pinctrl_map *map, 375 unsigned int num_maps) 376 { 377 unsigned int i; 378 379 if (!map) 380 return; 381 382 for (i = 0; i < num_maps; ++i) { 383 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 384 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 385 kfree(map[i].data.configs.configs); 386 } 387 kfree(map); 388 } 389 390 static int rzt2h_dt_node_to_map(struct pinctrl_dev *pctldev, 391 struct device_node *np, 392 struct pinctrl_map **map, 393 unsigned int *num_maps) 394 { 395 struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 396 unsigned int index; 397 int ret; 398 399 *map = NULL; 400 *num_maps = 0; 401 index = 0; 402 403 for_each_child_of_node_scoped(np, child) { 404 ret = rzt2h_dt_subnode_to_map(pctldev, child, np, map, 405 num_maps, &index); 406 if (ret < 0) 407 goto done; 408 } 409 410 if (*num_maps == 0) { 411 ret = rzt2h_dt_subnode_to_map(pctldev, np, NULL, map, 412 num_maps, &index); 413 if (ret < 0) 414 goto done; 415 } 416 417 if (*num_maps) 418 return 0; 419 420 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 421 ret = -EINVAL; 422 423 done: 424 rzt2h_dt_free_map(pctldev, *map, *num_maps); 425 return ret; 426 } 427 428 static const struct pinctrl_ops rzt2h_pinctrl_pctlops = { 429 .get_groups_count = pinctrl_generic_get_group_count, 430 .get_group_name = pinctrl_generic_get_group_name, 431 .get_group_pins = pinctrl_generic_get_group_pins, 432 .dt_node_to_map = rzt2h_dt_node_to_map, 433 .dt_free_map = rzt2h_dt_free_map, 434 }; 435 436 static const struct pinmux_ops rzt2h_pinctrl_pmxops = { 437 .get_functions_count = pinmux_generic_get_function_count, 438 .get_function_name = pinmux_generic_get_function_name, 439 .get_function_groups = pinmux_generic_get_function_groups, 440 .set_mux = rzt2h_pinctrl_set_mux, 441 .strict = true, 442 }; 443 444 static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset) 445 { 446 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 447 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 448 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 449 int ret; 450 u8 reg; 451 452 ret = rzt2h_validate_pin(pctrl, offset); 453 if (ret) 454 return ret; 455 456 ret = pinctrl_gpio_request(chip, offset); 457 if (ret) 458 return ret; 459 460 guard(spinlock_irqsave)(&pctrl->lock); 461 462 /* Select GPIO mode in PMC Register */ 463 reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 464 reg &= ~BIT(bit); 465 rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port)); 466 467 return 0; 468 } 469 470 static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port, 471 u8 bit, bool output) 472 { 473 u16 reg; 474 475 guard(spinlock_irqsave)(&pctrl->lock); 476 477 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 478 reg &= ~PM_PIN_MASK(bit); 479 480 reg |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 481 rzt2h_pinctrl_writew(pctrl, port, reg, PM(port)); 482 } 483 484 static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 485 { 486 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 487 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 488 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 489 u16 reg; 490 int ret; 491 492 ret = rzt2h_validate_pin(pctrl, offset); 493 if (ret) 494 return ret; 495 496 if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) 497 return -EINVAL; 498 499 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 500 reg = (reg >> (bit * 2)) & PM_MASK; 501 if (reg & PM_OUTPUT) 502 return GPIO_LINE_DIRECTION_OUT; 503 if (reg & PM_INPUT) 504 return GPIO_LINE_DIRECTION_IN; 505 506 return -EINVAL; 507 } 508 509 static int rzt2h_gpio_set(struct gpio_chip *chip, unsigned int offset, 510 int value) 511 { 512 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 513 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 514 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 515 u8 reg; 516 517 guard(spinlock_irqsave)(&pctrl->lock); 518 519 reg = rzt2h_pinctrl_readb(pctrl, port, P(port)); 520 if (value) 521 rzt2h_pinctrl_writeb(pctrl, port, reg | BIT(bit), P(port)); 522 else 523 rzt2h_pinctrl_writeb(pctrl, port, reg & ~BIT(bit), P(port)); 524 525 return 0; 526 } 527 528 static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset) 529 { 530 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 531 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 532 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 533 u16 reg; 534 535 reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 536 reg = (reg >> (bit * 2)) & PM_MASK; 537 if (reg & PM_INPUT) 538 return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit)); 539 if (reg & PM_OUTPUT) 540 return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit)); 541 542 return -EINVAL; 543 } 544 545 static int rzt2h_gpio_direction_input(struct gpio_chip *chip, 546 unsigned int offset) 547 { 548 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 549 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 550 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 551 552 rzt2h_gpio_set_direction(pctrl, port, bit, false); 553 554 return 0; 555 } 556 557 static int rzt2h_gpio_direction_output(struct gpio_chip *chip, 558 unsigned int offset, int value) 559 { 560 struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 561 u8 port = RZT2H_PIN_ID_TO_PORT(offset); 562 u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 563 564 rzt2h_gpio_set(chip, offset, value); 565 rzt2h_gpio_set_direction(pctrl, port, bit, true); 566 567 return 0; 568 } 569 570 static void rzt2h_gpio_free(struct gpio_chip *chip, unsigned int offset) 571 { 572 pinctrl_gpio_free(chip, offset); 573 574 /* 575 * Set the GPIO as an input to ensure that the next GPIO request won't 576 * drive the GPIO pin as an output. 577 */ 578 rzt2h_gpio_direction_input(chip, offset); 579 } 580 581 static const char * const rzt2h_gpio_names[] = { 582 "P00_0", "P00_1", "P00_2", "P00_3", "P00_4", "P00_5", "P00_6", "P00_7", 583 "P01_0", "P01_1", "P01_2", "P01_3", "P01_4", "P01_5", "P01_6", "P01_7", 584 "P02_0", "P02_1", "P02_2", "P02_3", "P02_4", "P02_5", "P02_6", "P02_7", 585 "P03_0", "P03_1", "P03_2", "P03_3", "P03_4", "P03_5", "P03_6", "P03_7", 586 "P04_0", "P04_1", "P04_2", "P04_3", "P04_4", "P04_5", "P04_6", "P04_7", 587 "P05_0", "P05_1", "P05_2", "P05_3", "P05_4", "P05_5", "P05_6", "P05_7", 588 "P06_0", "P06_1", "P06_2", "P06_3", "P06_4", "P06_5", "P06_6", "P06_7", 589 "P07_0", "P07_1", "P07_2", "P07_3", "P07_4", "P07_5", "P07_6", "P07_7", 590 "P08_0", "P08_1", "P08_2", "P08_3", "P08_4", "P08_5", "P08_6", "P08_7", 591 "P09_0", "P09_1", "P09_2", "P09_3", "P09_4", "P09_5", "P09_6", "P09_7", 592 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 593 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 594 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 595 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 596 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 597 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 598 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 599 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 600 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 601 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 602 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 603 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 604 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 605 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 606 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 607 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 608 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 609 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 610 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 611 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 612 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 613 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 614 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 615 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 616 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 617 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 618 }; 619 620 static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) 621 { 622 struct pinctrl_gpio_range *range = &pctrl->gpio_range; 623 struct gpio_chip *chip = &pctrl->gpio_chip; 624 struct device *dev = pctrl->dev; 625 struct of_phandle_args of_args; 626 int ret; 627 628 ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args); 629 if (ret) 630 return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n"); 631 632 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 633 of_args.args[2] != pctrl->data->n_port_pins) 634 return dev_err_probe(dev, -EINVAL, 635 "gpio-ranges does not match selected SOC\n"); 636 637 chip->base = -1; 638 chip->parent = dev; 639 chip->owner = THIS_MODULE; 640 chip->ngpio = of_args.args[2]; 641 chip->names = rzt2h_gpio_names; 642 chip->request = rzt2h_gpio_request; 643 chip->free = rzt2h_gpio_free; 644 chip->get_direction = rzt2h_gpio_get_direction; 645 chip->direction_input = rzt2h_gpio_direction_input; 646 chip->direction_output = rzt2h_gpio_direction_output; 647 chip->get = rzt2h_gpio_get; 648 chip->set = rzt2h_gpio_set; 649 chip->label = dev_name(dev); 650 651 range->id = 0; 652 range->pin_base = 0; 653 range->base = 0; 654 range->npins = chip->ngpio; 655 range->name = chip->label; 656 range->gc = chip; 657 658 ret = devm_gpiochip_add_data(dev, chip, pctrl); 659 if (ret) 660 return dev_err_probe(dev, ret, "gpiochip registration failed\n"); 661 662 return ret; 663 } 664 665 static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) 666 { 667 struct pinctrl_desc *desc = &pctrl->desc; 668 struct device *dev = pctrl->dev; 669 struct pinctrl_pin_desc *pins; 670 unsigned int i, j; 671 int ret; 672 673 desc->name = DRV_NAME; 674 desc->npins = pctrl->data->n_port_pins; 675 desc->pctlops = &rzt2h_pinctrl_pctlops; 676 desc->pmxops = &rzt2h_pinctrl_pmxops; 677 desc->owner = THIS_MODULE; 678 679 pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL); 680 if (!pins) 681 return -ENOMEM; 682 683 pctrl->pins = pins; 684 desc->pins = pins; 685 686 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 687 pins[i].number = i; 688 pins[i].name = rzt2h_gpio_names[i]; 689 if (i && !(i % RZT2H_PINS_PER_PORT)) 690 j++; 691 } 692 693 ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl); 694 if (ret) 695 return dev_err_probe(dev, ret, "pinctrl registration failed\n"); 696 697 ret = pinctrl_enable(pctrl->pctl); 698 if (ret) 699 return dev_err_probe(dev, ret, "pinctrl enable failed\n"); 700 701 return rzt2h_gpio_register(pctrl); 702 } 703 704 static int rzt2h_pinctrl_cfg_regions(struct platform_device *pdev, 705 struct rzt2h_pinctrl *pctrl) 706 { 707 struct resource *res; 708 709 pctrl->base0 = devm_platform_ioremap_resource_byname(pdev, "nsr"); 710 if (IS_ERR(pctrl->base0)) 711 return PTR_ERR(pctrl->base0); 712 713 /* 714 * Open-coded instead of using devm_platform_ioremap_resource_byname() 715 * because the "srs" region is optional. 716 */ 717 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "srs"); 718 if (res) { 719 u8 port; 720 721 pctrl->base1 = devm_ioremap_resource(&pdev->dev, res); 722 if (IS_ERR(pctrl->base1)) 723 return PTR_ERR(pctrl->base1); 724 725 pctrl->safety_port_enabled = true; 726 727 /* Configure to select safety region 0x812c0xxx */ 728 for (port = 0; port <= RZT2H_MAX_SAFETY_PORTS; port++) 729 writeb(0x0, pctrl->base1 + RSELP(port)); 730 } 731 732 return 0; 733 } 734 735 static int rzt2h_pinctrl_probe(struct platform_device *pdev) 736 { 737 struct device *dev = &pdev->dev; 738 struct rzt2h_pinctrl *pctrl; 739 int ret; 740 741 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 742 if (!pctrl) 743 return -ENOMEM; 744 745 pctrl->dev = dev; 746 pctrl->data = of_device_get_match_data(dev); 747 748 ret = rzt2h_pinctrl_cfg_regions(pdev, pctrl); 749 if (ret) 750 return ret; 751 752 spin_lock_init(&pctrl->lock); 753 mutex_init(&pctrl->mutex); 754 platform_set_drvdata(pdev, pctrl); 755 756 return rzt2h_pinctrl_register(pctrl); 757 } 758 759 static const u8 r9a09g077_gpio_configs[] = { 760 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 761 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 762 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 763 }; 764 765 static const u8 r9a09g087_gpio_configs[] = { 766 0x1f, 0xff, 0xff, 0x1f, 0x00, 0xfe, 0xff, 0x00, 0x7e, 0xf0, 0xff, 0x01, 767 0xff, 0xff, 0xff, 0x00, 0xe0, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x01, 768 0xe0, 0xff, 0xff, 0x7f, 0x00, 0xfe, 0xff, 0x7f, 0x00, 0xfc, 0x7f, 769 }; 770 771 static struct rzt2h_pinctrl_data r9a09g077_data = { 772 .n_port_pins = ARRAY_SIZE(r9a09g077_gpio_configs) * RZT2H_PINS_PER_PORT, 773 .port_pin_configs = r9a09g077_gpio_configs, 774 .n_ports = ARRAY_SIZE(r9a09g077_gpio_configs), 775 }; 776 777 static struct rzt2h_pinctrl_data r9a09g087_data = { 778 .n_port_pins = ARRAY_SIZE(r9a09g087_gpio_configs) * RZT2H_PINS_PER_PORT, 779 .port_pin_configs = r9a09g087_gpio_configs, 780 .n_ports = ARRAY_SIZE(r9a09g087_gpio_configs), 781 }; 782 783 static const struct of_device_id rzt2h_pinctrl_of_table[] = { 784 { 785 .compatible = "renesas,r9a09g077-pinctrl", 786 .data = &r9a09g077_data, 787 }, 788 { 789 .compatible = "renesas,r9a09g087-pinctrl", 790 .data = &r9a09g087_data, 791 }, 792 { /* sentinel */ } 793 }; 794 795 static struct platform_driver rzt2h_pinctrl_driver = { 796 .driver = { 797 .name = DRV_NAME, 798 .of_match_table = of_match_ptr(rzt2h_pinctrl_of_table), 799 .suppress_bind_attrs = true, 800 }, 801 .probe = rzt2h_pinctrl_probe, 802 }; 803 804 static int __init rzt2h_pinctrl_init(void) 805 { 806 return platform_driver_register(&rzt2h_pinctrl_driver); 807 } 808 core_initcall(rzt2h_pinctrl_init); 809 810 MODULE_LICENSE("GPL"); 811 MODULE_AUTHOR("Thierry Bultel <thierry.bultel.yh@bp.renesas.com>"); 812 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 813 MODULE_DESCRIPTION("Pin and gpio controller driver for the RZ/T2H family"); 814