1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 10 #include "pinctrl-msm.h" 11 12 #define REG_SIZE 0x1000 13 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 14 { \ 15 .grp = PINCTRL_PINGROUP("gpio" #id, \ 16 gpio##id##_pins, \ 17 ARRAY_SIZE(gpio##id##_pins)), \ 18 .ctl_reg = REG_SIZE * id, \ 19 .io_reg = 0x4 + REG_SIZE * id, \ 20 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 21 .intr_status_reg = 0xc + REG_SIZE * id, \ 22 .mux_bit = 2, \ 23 .pull_bit = 0, \ 24 .drv_bit = 6, \ 25 .oe_bit = 9, \ 26 .in_bit = 0, \ 27 .out_bit = 1, \ 28 .intr_enable_bit = 0, \ 29 .intr_status_bit = 0, \ 30 .intr_target_bit = 5, \ 31 .intr_target_kpss_val = 3, \ 32 .intr_raw_status_bit = 4, \ 33 .intr_polarity_bit = 1, \ 34 .intr_detection_bit = 2, \ 35 .intr_detection_width = 2, \ 36 .funcs = (int[]){ \ 37 msm_mux_gpio, /* gpio mode */ \ 38 msm_mux_##f1, \ 39 msm_mux_##f2, \ 40 msm_mux_##f3, \ 41 msm_mux_##f4, \ 42 msm_mux_##f5, \ 43 msm_mux_##f6, \ 44 msm_mux_##f7, \ 45 msm_mux_##f8, \ 46 msm_mux_##f9, \ 47 }, \ 48 .nfuncs = 10, \ 49 } 50 51 static const struct pinctrl_pin_desc ipq5210_pins[] = { 52 PINCTRL_PIN(0, "GPIO_0"), 53 PINCTRL_PIN(1, "GPIO_1"), 54 PINCTRL_PIN(2, "GPIO_2"), 55 PINCTRL_PIN(3, "GPIO_3"), 56 PINCTRL_PIN(4, "GPIO_4"), 57 PINCTRL_PIN(5, "GPIO_5"), 58 PINCTRL_PIN(6, "GPIO_6"), 59 PINCTRL_PIN(7, "GPIO_7"), 60 PINCTRL_PIN(8, "GPIO_8"), 61 PINCTRL_PIN(9, "GPIO_9"), 62 PINCTRL_PIN(10, "GPIO_10"), 63 PINCTRL_PIN(11, "GPIO_11"), 64 PINCTRL_PIN(12, "GPIO_12"), 65 PINCTRL_PIN(13, "GPIO_13"), 66 PINCTRL_PIN(14, "GPIO_14"), 67 PINCTRL_PIN(15, "GPIO_15"), 68 PINCTRL_PIN(16, "GPIO_16"), 69 PINCTRL_PIN(17, "GPIO_17"), 70 PINCTRL_PIN(18, "GPIO_18"), 71 PINCTRL_PIN(19, "GPIO_19"), 72 PINCTRL_PIN(20, "GPIO_20"), 73 PINCTRL_PIN(21, "GPIO_21"), 74 PINCTRL_PIN(22, "GPIO_22"), 75 PINCTRL_PIN(23, "GPIO_23"), 76 PINCTRL_PIN(24, "GPIO_24"), 77 PINCTRL_PIN(25, "GPIO_25"), 78 PINCTRL_PIN(26, "GPIO_26"), 79 PINCTRL_PIN(27, "GPIO_27"), 80 PINCTRL_PIN(28, "GPIO_28"), 81 PINCTRL_PIN(29, "GPIO_29"), 82 PINCTRL_PIN(30, "GPIO_30"), 83 PINCTRL_PIN(31, "GPIO_31"), 84 PINCTRL_PIN(32, "GPIO_32"), 85 PINCTRL_PIN(33, "GPIO_33"), 86 PINCTRL_PIN(34, "GPIO_34"), 87 PINCTRL_PIN(35, "GPIO_35"), 88 PINCTRL_PIN(36, "GPIO_36"), 89 PINCTRL_PIN(37, "GPIO_37"), 90 PINCTRL_PIN(38, "GPIO_38"), 91 PINCTRL_PIN(39, "GPIO_39"), 92 PINCTRL_PIN(40, "GPIO_40"), 93 PINCTRL_PIN(41, "GPIO_41"), 94 PINCTRL_PIN(42, "GPIO_42"), 95 PINCTRL_PIN(43, "GPIO_43"), 96 PINCTRL_PIN(44, "GPIO_44"), 97 PINCTRL_PIN(45, "GPIO_45"), 98 PINCTRL_PIN(46, "GPIO_46"), 99 PINCTRL_PIN(47, "GPIO_47"), 100 PINCTRL_PIN(48, "GPIO_48"), 101 PINCTRL_PIN(49, "GPIO_49"), 102 PINCTRL_PIN(50, "GPIO_50"), 103 PINCTRL_PIN(51, "GPIO_51"), 104 PINCTRL_PIN(52, "GPIO_52"), 105 PINCTRL_PIN(53, "GPIO_53"), 106 }; 107 108 #define DECLARE_MSM_GPIO_PINS(pin) \ 109 static const unsigned int gpio##pin##_pins[] = { pin } 110 DECLARE_MSM_GPIO_PINS(0); 111 DECLARE_MSM_GPIO_PINS(1); 112 DECLARE_MSM_GPIO_PINS(2); 113 DECLARE_MSM_GPIO_PINS(3); 114 DECLARE_MSM_GPIO_PINS(4); 115 DECLARE_MSM_GPIO_PINS(5); 116 DECLARE_MSM_GPIO_PINS(6); 117 DECLARE_MSM_GPIO_PINS(7); 118 DECLARE_MSM_GPIO_PINS(8); 119 DECLARE_MSM_GPIO_PINS(9); 120 DECLARE_MSM_GPIO_PINS(10); 121 DECLARE_MSM_GPIO_PINS(11); 122 DECLARE_MSM_GPIO_PINS(12); 123 DECLARE_MSM_GPIO_PINS(13); 124 DECLARE_MSM_GPIO_PINS(14); 125 DECLARE_MSM_GPIO_PINS(15); 126 DECLARE_MSM_GPIO_PINS(16); 127 DECLARE_MSM_GPIO_PINS(17); 128 DECLARE_MSM_GPIO_PINS(18); 129 DECLARE_MSM_GPIO_PINS(19); 130 DECLARE_MSM_GPIO_PINS(20); 131 DECLARE_MSM_GPIO_PINS(21); 132 DECLARE_MSM_GPIO_PINS(22); 133 DECLARE_MSM_GPIO_PINS(23); 134 DECLARE_MSM_GPIO_PINS(24); 135 DECLARE_MSM_GPIO_PINS(25); 136 DECLARE_MSM_GPIO_PINS(26); 137 DECLARE_MSM_GPIO_PINS(27); 138 DECLARE_MSM_GPIO_PINS(28); 139 DECLARE_MSM_GPIO_PINS(29); 140 DECLARE_MSM_GPIO_PINS(30); 141 DECLARE_MSM_GPIO_PINS(31); 142 DECLARE_MSM_GPIO_PINS(32); 143 DECLARE_MSM_GPIO_PINS(33); 144 DECLARE_MSM_GPIO_PINS(34); 145 DECLARE_MSM_GPIO_PINS(35); 146 DECLARE_MSM_GPIO_PINS(36); 147 DECLARE_MSM_GPIO_PINS(37); 148 DECLARE_MSM_GPIO_PINS(38); 149 DECLARE_MSM_GPIO_PINS(39); 150 DECLARE_MSM_GPIO_PINS(40); 151 DECLARE_MSM_GPIO_PINS(41); 152 DECLARE_MSM_GPIO_PINS(42); 153 DECLARE_MSM_GPIO_PINS(43); 154 DECLARE_MSM_GPIO_PINS(44); 155 DECLARE_MSM_GPIO_PINS(45); 156 DECLARE_MSM_GPIO_PINS(46); 157 DECLARE_MSM_GPIO_PINS(47); 158 DECLARE_MSM_GPIO_PINS(48); 159 DECLARE_MSM_GPIO_PINS(49); 160 DECLARE_MSM_GPIO_PINS(50); 161 DECLARE_MSM_GPIO_PINS(51); 162 DECLARE_MSM_GPIO_PINS(52); 163 DECLARE_MSM_GPIO_PINS(53); 164 165 enum ipq5210_functions { 166 msm_mux_atest_char_start, 167 msm_mux_atest_char_status0, 168 msm_mux_atest_char_status1, 169 msm_mux_atest_char_status2, 170 msm_mux_atest_char_status3, 171 msm_mux_atest_tic_en, 172 msm_mux_audio_pri, 173 msm_mux_audio_pri_mclk_out0, 174 msm_mux_audio_pri_mclk_in0, 175 msm_mux_audio_pri_mclk_out1, 176 msm_mux_audio_pri_mclk_in1, 177 msm_mux_audio_pri_mclk_out2, 178 msm_mux_audio_pri_mclk_in2, 179 msm_mux_audio_pri_mclk_out3, 180 msm_mux_audio_pri_mclk_in3, 181 msm_mux_audio_sec, 182 msm_mux_audio_sec_mclk_out0, 183 msm_mux_audio_sec_mclk_in0, 184 msm_mux_audio_sec_mclk_out1, 185 msm_mux_audio_sec_mclk_in1, 186 msm_mux_audio_sec_mclk_out2, 187 msm_mux_audio_sec_mclk_in2, 188 msm_mux_audio_sec_mclk_out3, 189 msm_mux_audio_sec_mclk_in3, 190 msm_mux_core_voltage_0, 191 msm_mux_cri_trng0, 192 msm_mux_cri_trng1, 193 msm_mux_cri_trng2, 194 msm_mux_cri_trng3, 195 msm_mux_dbg_out_clk, 196 msm_mux_dg_out, 197 msm_mux_gcc_plltest_bypassnl, 198 msm_mux_gcc_plltest_resetn, 199 msm_mux_gcc_tlmm, 200 msm_mux_gpio, 201 msm_mux_led0, 202 msm_mux_led1, 203 msm_mux_led2, 204 msm_mux_mdc_mst, 205 msm_mux_mdc_slv0, 206 msm_mux_mdc_slv1, 207 msm_mux_mdc_slv2, 208 msm_mux_mdio_mst, 209 msm_mux_mdio_slv0, 210 msm_mux_mdio_slv1, 211 msm_mux_mdio_slv2, 212 msm_mux_mux_tod_out, 213 msm_mux_pcie0_clk_req_n, 214 msm_mux_pcie0_wake, 215 msm_mux_pcie1_clk_req_n, 216 msm_mux_pcie1_wake, 217 msm_mux_pll_test, 218 msm_mux_pon_active_led, 219 msm_mux_pon_mux_sel, 220 msm_mux_pon_rx, 221 msm_mux_pon_rx_los, 222 msm_mux_pon_tx, 223 msm_mux_pon_tx_burst, 224 msm_mux_pon_tx_dis, 225 msm_mux_pon_tx_fault, 226 msm_mux_pon_tx_sd, 227 msm_mux_gpn_rx_los, 228 msm_mux_gpn_tx_burst, 229 msm_mux_gpn_tx_dis, 230 msm_mux_gpn_tx_fault, 231 msm_mux_gpn_tx_sd, 232 msm_mux_pps, 233 msm_mux_pwm0, 234 msm_mux_pwm1, 235 msm_mux_pwm2, 236 msm_mux_pwm3, 237 msm_mux_qdss_cti_trig_in_a0, 238 msm_mux_qdss_cti_trig_in_a1, 239 msm_mux_qdss_cti_trig_in_b0, 240 msm_mux_qdss_cti_trig_in_b1, 241 msm_mux_qdss_cti_trig_out_a0, 242 msm_mux_qdss_cti_trig_out_a1, 243 msm_mux_qdss_cti_trig_out_b0, 244 msm_mux_qdss_cti_trig_out_b1, 245 msm_mux_qdss_traceclk_a, 246 msm_mux_qdss_tracectl_a, 247 msm_mux_qdss_tracedata_a, 248 msm_mux_qrng_rosc0, 249 msm_mux_qrng_rosc1, 250 msm_mux_qrng_rosc2, 251 msm_mux_qspi_data, 252 msm_mux_qspi_clk, 253 msm_mux_qspi_cs_n, 254 msm_mux_qup_se0, 255 msm_mux_qup_se1, 256 msm_mux_qup_se2, 257 msm_mux_qup_se3, 258 msm_mux_qup_se4, 259 msm_mux_qup_se5, 260 msm_mux_qup_se5_l1, 261 msm_mux_resout, 262 msm_mux_rx_los0, 263 msm_mux_rx_los1, 264 msm_mux_rx_los2, 265 msm_mux_sdc_clk, 266 msm_mux_sdc_cmd, 267 msm_mux_sdc_data, 268 msm_mux_tsens_max, 269 msm_mux__, 270 }; 271 272 static const char *const gpio_groups[] = { 273 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", 274 "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", 275 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", 276 "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", 277 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", 278 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 279 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", 280 "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", 281 }; 282 283 static const char *const atest_char_start_groups[] = { 284 "gpio46", 285 }; 286 287 static const char *const atest_char_status0_groups[] = { 288 "gpio34", 289 }; 290 291 static const char *const atest_char_status1_groups[] = { 292 "gpio35", 293 }; 294 295 static const char *const atest_char_status2_groups[] = { 296 "gpio36", 297 }; 298 299 static const char *const atest_char_status3_groups[] = { 300 "gpio37", 301 }; 302 303 static const char *const atest_tic_en_groups[] = { 304 "gpio42", 305 }; 306 307 static const char *const audio_pri_groups[] = { 308 "gpio34", "gpio35", "gpio36", "gpio37", 309 }; 310 311 static const char *const audio_pri_mclk_out0_groups[] = { 312 "gpio12", 313 }; 314 315 static const char *const audio_pri_mclk_in0_groups[] = { 316 "gpio12", 317 }; 318 319 static const char *const audio_pri_mclk_out1_groups[] = { 320 "gpio19", 321 }; 322 323 static const char *const audio_pri_mclk_in1_groups[] = { 324 "gpio19", 325 }; 326 327 static const char *const audio_pri_mclk_out2_groups[] = { 328 "gpio8", 329 }; 330 331 static const char *const audio_pri_mclk_in2_groups[] = { 332 "gpio8", 333 }; 334 335 static const char *const audio_pri_mclk_out3_groups[] = { 336 "gpio13", 337 }; 338 339 static const char *const audio_pri_mclk_in3_groups[] = { 340 "gpio13", 341 }; 342 343 static const char *const audio_sec_mclk_out0_groups[] = { 344 "gpio17", 345 }; 346 347 static const char *const audio_sec_mclk_in0_groups[] = { 348 "gpio17", 349 }; 350 351 static const char *const audio_sec_mclk_out1_groups[] = { 352 "gpio16", 353 }; 354 355 static const char *const audio_sec_mclk_in1_groups[] = { 356 "gpio16", 357 }; 358 359 static const char *const audio_sec_mclk_out2_groups[] = { 360 "gpio49", 361 }; 362 363 static const char *const audio_sec_mclk_in2_groups[] = { 364 "gpio49", 365 }; 366 367 static const char *const audio_sec_mclk_out3_groups[] = { 368 "gpio50", 369 }; 370 371 static const char *const audio_sec_mclk_in3_groups[] = { 372 "gpio50", 373 }; 374 375 static const char *const audio_sec_groups[] = { 376 "gpio40", "gpio41", "gpio42", "gpio43", 377 }; 378 379 static const char *const core_voltage_0_groups[] = { 380 "gpio22", 381 }; 382 383 static const char *const cri_trng0_groups[] = { 384 "gpio6", 385 }; 386 387 static const char *const cri_trng1_groups[] = { 388 "gpio7", 389 }; 390 391 static const char *const cri_trng2_groups[] = { 392 "gpio8", 393 }; 394 395 static const char *const cri_trng3_groups[] = { 396 "gpio9", 397 }; 398 399 static const char *const dbg_out_clk_groups[] = { 400 "gpio23", 401 }; 402 403 static const char *const dg_out_groups[] = { 404 "gpio46", 405 }; 406 407 static const char *const gcc_plltest_bypassnl_groups[] = { 408 "gpio38", 409 }; 410 411 static const char *const gcc_plltest_resetn_groups[] = { 412 "gpio40", 413 }; 414 415 static const char *const gcc_tlmm_groups[] = { 416 "gpio39", 417 }; 418 419 static const char *const led0_groups[] = { 420 "gpio6", "gpio23", "gpio39", 421 }; 422 423 static const char *const led1_groups[] = { 424 "gpio7", "gpio27", "gpio39", 425 }; 426 427 static const char *const led2_groups[] = { 428 "gpio9", "gpio26", "gpio38", 429 }; 430 431 static const char *const mdc_mst_groups[] = { 432 "gpio26", 433 }; 434 435 static const char *const mdc_slv0_groups[] = { 436 "gpio31", 437 }; 438 439 static const char *const mdc_slv1_groups[] = { 440 "gpio20", 441 }; 442 443 static const char *const mdc_slv2_groups[] = { 444 "gpio47", 445 }; 446 447 static const char *const mdio_mst_groups[] = { 448 "gpio27", 449 }; 450 451 static const char *const mdio_slv0_groups[] = { 452 "gpio33", 453 }; 454 455 static const char *const mdio_slv1_groups[] = { 456 "gpio21", 457 }; 458 459 static const char *const mdio_slv2_groups[] = { 460 "gpio49", 461 }; 462 463 static const char *const mux_tod_out_groups[] = { 464 "gpio19", 465 }; 466 467 static const char *const pcie0_clk_req_n_groups[] = { 468 "gpio31", 469 }; 470 471 static const char *const pcie0_wake_groups[] = { 472 "gpio33", 473 }; 474 475 static const char *const pcie1_clk_req_n_groups[] = { 476 "gpio28", 477 }; 478 479 static const char *const pcie1_wake_groups[] = { 480 "gpio30", 481 }; 482 483 static const char *const pll_test_groups[] = { 484 "gpio18", 485 }; 486 487 static const char *const pon_active_led_groups[] = { 488 "gpio11", 489 }; 490 491 static const char *const pon_mux_sel_groups[] = { 492 "gpio45", 493 }; 494 495 static const char *const pon_rx_groups[] = { 496 "gpio48", 497 }; 498 499 static const char *const pon_rx_los_groups[] = { 500 "gpio10", 501 }; 502 503 static const char *const pon_tx_groups[] = { 504 "gpio15", 505 }; 506 507 static const char *const pon_tx_burst_groups[] = { 508 "gpio14", 509 }; 510 511 static const char *const pon_tx_dis_groups[] = { 512 "gpio12", 513 }; 514 515 static const char *const pon_tx_fault_groups[] = { 516 "gpio17", 517 }; 518 519 static const char *const pon_tx_sd_groups[] = { 520 "gpio16", 521 }; 522 523 static const char *const gpn_rx_los_groups[] = { 524 "gpio47", 525 }; 526 527 static const char *const gpn_tx_burst_groups[] = { 528 "gpio51", 529 }; 530 531 static const char *const gpn_tx_dis_groups[] = { 532 "gpio13", 533 }; 534 535 static const char *const gpn_tx_fault_groups[] = { 536 "gpio49", 537 }; 538 539 static const char *const gpn_tx_sd_groups[] = { 540 "gpio50", 541 }; 542 543 static const char *const pps_groups[] = { 544 "gpio18", 545 }; 546 547 static const char *const pwm0_groups[] = { 548 "gpio10", "gpio11", "gpio12", "gpio13", 549 }; 550 551 static const char *const pwm1_groups[] = { 552 "gpio6", "gpio7", "gpio8", "gpio9", 553 }; 554 555 static const char *const pwm2_groups[] = { 556 "gpio0", "gpio1", "gpio2", "gpio3", 557 }; 558 559 static const char *const pwm3_groups[] = { 560 "gpio22", 561 }; 562 563 static const char *const qdss_cti_trig_in_a0_groups[] = { 564 "gpio30", 565 }; 566 567 static const char *const qdss_cti_trig_in_a1_groups[] = { 568 "gpio33", 569 }; 570 571 static const char *const qdss_cti_trig_in_b0_groups[] = { 572 "gpio34", 573 }; 574 575 static const char *const qdss_cti_trig_in_b1_groups[] = { 576 "gpio37", 577 }; 578 579 static const char *const qdss_cti_trig_out_a0_groups[] = { 580 "gpio28", 581 }; 582 583 static const char *const qdss_cti_trig_out_a1_groups[] = { 584 "gpio31", 585 }; 586 587 static const char *const qdss_cti_trig_out_b0_groups[] = { 588 "gpio16", 589 }; 590 591 static const char *const qdss_cti_trig_out_b1_groups[] = { 592 "gpio35", 593 }; 594 595 static const char *const qdss_traceclk_a_groups[] = { 596 "gpio23", 597 }; 598 599 static const char *const qdss_tracectl_a_groups[] = { 600 "gpio26", 601 }; 602 603 static const char *const qdss_tracedata_a_groups[] = { 604 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 605 "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", 606 "gpio38", "gpio39", "gpio40", "gpio41", 607 }; 608 609 static const char *const qrng_rosc0_groups[] = { 610 "gpio12", 611 }; 612 613 static const char *const qrng_rosc1_groups[] = { 614 "gpio13", 615 }; 616 617 static const char *const qrng_rosc2_groups[] = { 618 "gpio14", 619 }; 620 621 static const char *const qspi_data_groups[] = { 622 "gpio0", "gpio1", "gpio2", "gpio3", 623 }; 624 625 static const char *const qspi_clk_groups[] = { 626 "gpio5", 627 }; 628 629 static const char *const qspi_cs_n_groups[] = { 630 "gpio4", 631 }; 632 633 static const char *const qup_se0_groups[] = { 634 "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", "gpio15", 635 }; 636 637 static const char *const qup_se1_groups[] = { 638 "gpio28", "gpio30", "gpio38", "gpio39", 639 }; 640 641 static const char *const qup_se2_groups[] = { 642 "gpio12", "gpio13", "gpio20", "gpio21", "gpio52", "gpio53", 643 }; 644 645 static const char *const qup_se3_groups[] = { 646 "gpio10", "gpio11", "gpio22", "gpio23", 647 }; 648 649 static const char *const qup_se4_groups[] = { 650 "gpio40", "gpio41", "gpio42", "gpio43", "gpio52", "gpio53", 651 }; 652 653 static const char *const qup_se5_groups[] = { 654 "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", 655 }; 656 657 static const char *const qup_se5_l1_groups[] = { 658 "gpio52", "gpio53", 659 }; 660 661 static const char *const resout_groups[] = { 662 "gpio44", 663 }; 664 665 static const char *const rx_los0_groups[] = { 666 "gpio37", "gpio42", 667 }; 668 669 static const char *const rx_los1_groups[] = { 670 "gpio36", "gpio41", 671 }; 672 673 static const char *const rx_los2_groups[] = { 674 "gpio35", "gpio40", 675 }; 676 677 static const char *const sdc_clk_groups[] = { 678 "gpio5", 679 }; 680 681 static const char *const sdc_cmd_groups[] = { 682 "gpio4", 683 }; 684 685 static const char *const sdc_data_groups[] = { 686 "gpio0", "gpio1", "gpio2", "gpio3", 687 }; 688 689 static const char *const tsens_max_groups[] = { 690 "gpio20", 691 }; 692 693 static const struct pinfunction ipq5210_functions[] = { 694 MSM_PIN_FUNCTION(atest_char_start), 695 MSM_PIN_FUNCTION(atest_char_status0), 696 MSM_PIN_FUNCTION(atest_char_status1), 697 MSM_PIN_FUNCTION(atest_char_status2), 698 MSM_PIN_FUNCTION(atest_char_status3), 699 MSM_PIN_FUNCTION(atest_tic_en), 700 MSM_PIN_FUNCTION(audio_pri), 701 MSM_PIN_FUNCTION(audio_pri_mclk_out0), 702 MSM_PIN_FUNCTION(audio_pri_mclk_in0), 703 MSM_PIN_FUNCTION(audio_pri_mclk_out1), 704 MSM_PIN_FUNCTION(audio_pri_mclk_in1), 705 MSM_PIN_FUNCTION(audio_pri_mclk_out2), 706 MSM_PIN_FUNCTION(audio_pri_mclk_in2), 707 MSM_PIN_FUNCTION(audio_pri_mclk_out3), 708 MSM_PIN_FUNCTION(audio_pri_mclk_in3), 709 MSM_PIN_FUNCTION(audio_sec), 710 MSM_PIN_FUNCTION(audio_sec_mclk_out0), 711 MSM_PIN_FUNCTION(audio_sec_mclk_in0), 712 MSM_PIN_FUNCTION(audio_sec_mclk_out1), 713 MSM_PIN_FUNCTION(audio_sec_mclk_in1), 714 MSM_PIN_FUNCTION(audio_sec_mclk_out2), 715 MSM_PIN_FUNCTION(audio_sec_mclk_in2), 716 MSM_PIN_FUNCTION(audio_sec_mclk_out3), 717 MSM_PIN_FUNCTION(audio_sec_mclk_in3), 718 MSM_PIN_FUNCTION(core_voltage_0), 719 MSM_PIN_FUNCTION(cri_trng0), 720 MSM_PIN_FUNCTION(cri_trng1), 721 MSM_PIN_FUNCTION(cri_trng2), 722 MSM_PIN_FUNCTION(cri_trng3), 723 MSM_PIN_FUNCTION(dbg_out_clk), 724 MSM_PIN_FUNCTION(dg_out), 725 MSM_PIN_FUNCTION(gcc_plltest_bypassnl), 726 MSM_PIN_FUNCTION(gcc_plltest_resetn), 727 MSM_PIN_FUNCTION(gcc_tlmm), 728 MSM_GPIO_PIN_FUNCTION(gpio), 729 MSM_PIN_FUNCTION(led0), 730 MSM_PIN_FUNCTION(led1), 731 MSM_PIN_FUNCTION(led2), 732 MSM_PIN_FUNCTION(mdc_mst), 733 MSM_PIN_FUNCTION(mdc_slv0), 734 MSM_PIN_FUNCTION(mdc_slv1), 735 MSM_PIN_FUNCTION(mdc_slv2), 736 MSM_PIN_FUNCTION(mdio_mst), 737 MSM_PIN_FUNCTION(mdio_slv0), 738 MSM_PIN_FUNCTION(mdio_slv1), 739 MSM_PIN_FUNCTION(mdio_slv2), 740 MSM_PIN_FUNCTION(mux_tod_out), 741 MSM_PIN_FUNCTION(pcie0_clk_req_n), 742 MSM_PIN_FUNCTION(pcie0_wake), 743 MSM_PIN_FUNCTION(pcie1_clk_req_n), 744 MSM_PIN_FUNCTION(pcie1_wake), 745 MSM_PIN_FUNCTION(pll_test), 746 MSM_PIN_FUNCTION(pon_active_led), 747 MSM_PIN_FUNCTION(pon_mux_sel), 748 MSM_PIN_FUNCTION(pon_rx), 749 MSM_PIN_FUNCTION(pon_rx_los), 750 MSM_PIN_FUNCTION(pon_tx), 751 MSM_PIN_FUNCTION(pon_tx_burst), 752 MSM_PIN_FUNCTION(pon_tx_dis), 753 MSM_PIN_FUNCTION(pon_tx_fault), 754 MSM_PIN_FUNCTION(pon_tx_sd), 755 MSM_PIN_FUNCTION(gpn_rx_los), 756 MSM_PIN_FUNCTION(gpn_tx_burst), 757 MSM_PIN_FUNCTION(gpn_tx_dis), 758 MSM_PIN_FUNCTION(gpn_tx_fault), 759 MSM_PIN_FUNCTION(gpn_tx_sd), 760 MSM_PIN_FUNCTION(pps), 761 MSM_PIN_FUNCTION(pwm0), 762 MSM_PIN_FUNCTION(pwm1), 763 MSM_PIN_FUNCTION(pwm2), 764 MSM_PIN_FUNCTION(pwm3), 765 MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), 766 MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), 767 MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), 768 MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), 769 MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), 770 MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), 771 MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), 772 MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), 773 MSM_PIN_FUNCTION(qdss_traceclk_a), 774 MSM_PIN_FUNCTION(qdss_tracectl_a), 775 MSM_PIN_FUNCTION(qdss_tracedata_a), 776 MSM_PIN_FUNCTION(qrng_rosc0), 777 MSM_PIN_FUNCTION(qrng_rosc1), 778 MSM_PIN_FUNCTION(qrng_rosc2), 779 MSM_PIN_FUNCTION(qspi_data), 780 MSM_PIN_FUNCTION(qspi_clk), 781 MSM_PIN_FUNCTION(qspi_cs_n), 782 MSM_PIN_FUNCTION(qup_se0), 783 MSM_PIN_FUNCTION(qup_se1), 784 MSM_PIN_FUNCTION(qup_se2), 785 MSM_PIN_FUNCTION(qup_se3), 786 MSM_PIN_FUNCTION(qup_se4), 787 MSM_PIN_FUNCTION(qup_se5), 788 MSM_PIN_FUNCTION(qup_se5_l1), 789 MSM_PIN_FUNCTION(resout), 790 MSM_PIN_FUNCTION(rx_los0), 791 MSM_PIN_FUNCTION(rx_los1), 792 MSM_PIN_FUNCTION(rx_los2), 793 MSM_PIN_FUNCTION(sdc_clk), 794 MSM_PIN_FUNCTION(sdc_cmd), 795 MSM_PIN_FUNCTION(sdc_data), 796 MSM_PIN_FUNCTION(tsens_max), 797 }; 798 799 static const struct msm_pingroup ipq5210_groups[] = { 800 [0] = PINGROUP(0, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), 801 [1] = PINGROUP(1, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), 802 [2] = PINGROUP(2, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), 803 [3] = PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), 804 [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _), 805 [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), 806 [6] = PINGROUP(6, qup_se0, led0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _), 807 [7] = PINGROUP(7, qup_se0, led1, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _), 808 [8] = PINGROUP(8, qup_se0, pwm1, audio_pri_mclk_out2, audio_pri_mclk_in2, _, cri_trng2, qdss_tracedata_a, _, _), 809 [9] = PINGROUP(9, qup_se0, led2, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _), 810 [10] = PINGROUP(10, pon_rx_los, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _), 811 [11] = PINGROUP(11, pon_active_led, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _), 812 [12] = PINGROUP(12, pon_tx_dis, qup_se2, pwm0, audio_pri_mclk_out0, audio_pri_mclk_in0, _, qrng_rosc0, qdss_tracedata_a, _), 813 [13] = PINGROUP(13, gpn_tx_dis, qup_se2, pwm0, audio_pri_mclk_out3, audio_pri_mclk_in3, _, qrng_rosc1, qdss_tracedata_a, _), 814 [14] = PINGROUP(14, pon_tx_burst, qup_se0, _, qrng_rosc2, qdss_tracedata_a, _, _, _, _), 815 [15] = PINGROUP(15, pon_tx, qup_se0, _, qdss_tracedata_a, _, _, _, _, _), 816 [16] = PINGROUP(16, pon_tx_sd, audio_sec_mclk_out1, audio_sec_mclk_in1, qdss_cti_trig_out_b0, _, _, _, _, _), 817 [17] = PINGROUP(17, pon_tx_fault, audio_sec_mclk_out0, audio_sec_mclk_in0, _, _, _, _, _, _), 818 [18] = PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _), 819 [19] = PINGROUP(19, mux_tod_out, audio_pri_mclk_out1, audio_pri_mclk_in1, _, _, _, _, _, _), 820 [20] = PINGROUP(20, qup_se2, mdc_slv1, tsens_max, qdss_tracedata_a, _, _, _, _, _), 821 [21] = PINGROUP(21, qup_se2, mdio_slv1, qdss_tracedata_a, _, _, _, _, _, _), 822 [22] = PINGROUP(22, core_voltage_0, qup_se3, pwm3, _, _, _, _, _, _), 823 [23] = PINGROUP(23, led0, qup_se3, dbg_out_clk, qdss_traceclk_a, _, _, _, _, _), 824 [24] = PINGROUP(24, _, _, _, _, _, _, _, _, _), 825 [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _), 826 [26] = PINGROUP(26, mdc_mst, led2, _, qdss_tracectl_a, _, _, _, _, _), 827 [27] = PINGROUP(27, mdio_mst, led1, _, _, _, _, _, _, _), 828 [28] = PINGROUP(28, pcie1_clk_req_n, qup_se1, _, _, qdss_cti_trig_out_a0, _, _, _, _), 829 [29] = PINGROUP(29, _, _, _, _, _, _, _, _, _), 830 [30] = PINGROUP(30, pcie1_wake, qup_se1, _, _, qdss_cti_trig_in_a0, _, _, _, _), 831 [31] = PINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1, _, _, _, _, _), 832 [32] = PINGROUP(32, _, _, _, _, _, _, _, _, _), 833 [33] = PINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _, _, _, _), 834 [34] = PINGROUP(34, audio_pri, atest_char_status0, qdss_cti_trig_in_b0, _, _, _, _, _, _), 835 [35] = PINGROUP(35, audio_pri, rx_los2, atest_char_status1, qdss_cti_trig_out_b1, _, _, _, _, _), 836 [36] = PINGROUP(36, audio_pri, _, rx_los1, atest_char_status2, _, _, _, _, _), 837 [37] = PINGROUP(37, audio_pri, rx_los0, atest_char_status3, _, qdss_cti_trig_in_b1, _, _, _, _), 838 [38] = PINGROUP(38, qup_se1, led2, gcc_plltest_bypassnl, qdss_tracedata_a, _, _, _, _, _), 839 [39] = PINGROUP(39, qup_se1, led1, led0, gcc_tlmm, qdss_tracedata_a, _, _, _, _), 840 [40] = PINGROUP(40, qup_se4, rx_los2, audio_sec, gcc_plltest_resetn, qdss_tracedata_a, _, _, _, _), 841 [41] = PINGROUP(41, qup_se4, rx_los1, audio_sec, qdss_tracedata_a, _, _, _, _, _), 842 [42] = PINGROUP(42, qup_se4, rx_los0, audio_sec, atest_tic_en, _, _, _, _, _), 843 [43] = PINGROUP(43, qup_se4, audio_sec, _, _, _, _, _, _, _), 844 [44] = PINGROUP(44, resout, _, _, _, _, _, _, _, _), 845 [45] = PINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _), 846 [46] = PINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _), 847 [47] = PINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5, _, _, _, _, _, _), 848 [48] = PINGROUP(48, pon_rx, qup_se5, _, _, _, _, _, _, _), 849 [49] = PINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5, audio_sec_mclk_out2, audio_sec_mclk_in2, _, _, _, _), 850 [50] = PINGROUP(50, gpn_tx_sd, qup_se5, audio_sec_mclk_out3, audio_sec_mclk_in3, _, _, _, _, _), 851 [51] = PINGROUP(51, gpn_tx_burst, qup_se5, _, _, _, _, _, _, _), 852 [52] = PINGROUP(52, qup_se2, qup_se5, qup_se4, qup_se5_l1, _, _, _, _, _), 853 [53] = PINGROUP(53, qup_se2, qup_se4, qup_se5_l1, _, _, _, _, _, _), 854 }; 855 856 static const struct msm_pinctrl_soc_data ipq5210_tlmm = { 857 .pins = ipq5210_pins, 858 .npins = ARRAY_SIZE(ipq5210_pins), 859 .functions = ipq5210_functions, 860 .nfunctions = ARRAY_SIZE(ipq5210_functions), 861 .groups = ipq5210_groups, 862 .ngroups = ARRAY_SIZE(ipq5210_groups), 863 .ngpios = 54, 864 }; 865 866 static const struct of_device_id ipq5210_tlmm_of_match[] = { 867 { .compatible = "qcom,ipq5210-tlmm", }, 868 { }, 869 }; 870 871 static int ipq5210_tlmm_probe(struct platform_device *pdev) 872 { 873 return msm_pinctrl_probe(pdev, &ipq5210_tlmm); 874 } 875 876 static struct platform_driver ipq5210_tlmm_driver = { 877 .driver = { 878 .name = "ipq5210-tlmm", 879 .of_match_table = ipq5210_tlmm_of_match, 880 }, 881 .probe = ipq5210_tlmm_probe, 882 }; 883 884 static int __init ipq5210_tlmm_init(void) 885 { 886 return platform_driver_register(&ipq5210_tlmm_driver); 887 } 888 arch_initcall(ipq5210_tlmm_init); 889 890 static void __exit ipq5210_tlmm_exit(void) 891 { 892 platform_driver_unregister(&ipq5210_tlmm_driver); 893 } 894 module_exit(ipq5210_tlmm_exit); 895 896 MODULE_DESCRIPTION("QTI IPQ5210 TLMM driver"); 897 MODULE_LICENSE("GPL"); 898