1*657cbf9bSIvan T. Ivanov /* SPDX-License-Identifier: GPL-2.0+ */ 2*657cbf9bSIvan T. Ivanov /* 3*657cbf9bSIvan T. Ivanov * Header for Broadcom brcmstb GPIO based drivers 4*657cbf9bSIvan T. Ivanov * 5*657cbf9bSIvan T. Ivanov * Copyright (C) 2024-2025 Ivan T. Ivanov, Andrea della Porta 6*657cbf9bSIvan T. Ivanov * Copyright (C) 2021-3 Raspberry Pi Ltd. 7*657cbf9bSIvan T. Ivanov * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 8*657cbf9bSIvan T. Ivanov * 9*657cbf9bSIvan T. Ivanov * Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by: 10*657cbf9bSIvan T. Ivanov * pinctrl-nomadik.c, please see original file for copyright information 11*657cbf9bSIvan T. Ivanov * pinctrl-tegra.c, please see original file for copyright information 12*657cbf9bSIvan T. Ivanov */ 13*657cbf9bSIvan T. Ivanov 14*657cbf9bSIvan T. Ivanov #ifndef __PINCTRL_BRCMSTB_H__ 15*657cbf9bSIvan T. Ivanov #define __PINCTRL_BRCMSTB_H__ 16*657cbf9bSIvan T. Ivanov 17*657cbf9bSIvan T. Ivanov #include <linux/types.h> 18*657cbf9bSIvan T. Ivanov #include <linux/platform_device.h> 19*657cbf9bSIvan T. Ivanov 20*657cbf9bSIvan T. Ivanov #define BRCMSTB_FUNC(f) \ 21*657cbf9bSIvan T. Ivanov [func_##f] = #f 22*657cbf9bSIvan T. Ivanov 23*657cbf9bSIvan T. Ivanov #define MUX_BIT_VALID 0x8000 24*657cbf9bSIvan T. Ivanov #define PAD_BIT_INVALID 0xffff 25*657cbf9bSIvan T. Ivanov 26*657cbf9bSIvan T. Ivanov #define MUX_BIT(muxreg, muxshift) \ 27*657cbf9bSIvan T. Ivanov (MUX_BIT_VALID + ((muxreg) << 5) + ((muxshift) << 2)) 28*657cbf9bSIvan T. Ivanov #define PAD_BIT(padreg, padshift) \ 29*657cbf9bSIvan T. Ivanov (((padreg) << 5) + ((padshift) << 1)) 30*657cbf9bSIvan T. Ivanov 31*657cbf9bSIvan T. Ivanov #define GPIO_REGS(n, muxreg, muxshift, padreg, padshift) \ 32*657cbf9bSIvan T. Ivanov [n] = { MUX_BIT(muxreg, muxshift), PAD_BIT(padreg, padshift) } 33*657cbf9bSIvan T. Ivanov 34*657cbf9bSIvan T. Ivanov #define EMMC_REGS(n, padreg, padshift) \ 35*657cbf9bSIvan T. Ivanov [n] = { 0, PAD_BIT(padreg, padshift) } 36*657cbf9bSIvan T. Ivanov 37*657cbf9bSIvan T. Ivanov #define AON_GPIO_REGS(n, muxreg, muxshift, padreg, padshift) \ 38*657cbf9bSIvan T. Ivanov GPIO_REGS(n, muxreg, muxshift, padreg, padshift) 39*657cbf9bSIvan T. Ivanov 40*657cbf9bSIvan T. Ivanov #define AON_SGPIO_REGS(n, muxreg, muxshift) \ 41*657cbf9bSIvan T. Ivanov [(n) + 32] = { MUX_BIT(muxreg, muxshift), PAD_BIT_INVALID } 42*657cbf9bSIvan T. Ivanov 43*657cbf9bSIvan T. Ivanov #define GPIO_PIN(n) PINCTRL_PIN(n, "gpio" #n) 44*657cbf9bSIvan T. Ivanov /** 45*657cbf9bSIvan T. Ivanov * AON pins are in the Always-On power domain. SGPIOs are also 'Safe' 46*657cbf9bSIvan T. Ivanov * being 5V tolerant (necessary for the HDMI I2C pins), and can be driven 47*657cbf9bSIvan T. Ivanov * while the power is off. 48*657cbf9bSIvan T. Ivanov */ 49*657cbf9bSIvan T. Ivanov #define AON_GPIO_PIN(n) PINCTRL_PIN(n, "aon_gpio" #n) 50*657cbf9bSIvan T. Ivanov #define AON_SGPIO_PIN(n) PINCTRL_PIN((n) + 32, "aon_sgpio" #n) 51*657cbf9bSIvan T. Ivanov 52*657cbf9bSIvan T. Ivanov struct pin_regs { 53*657cbf9bSIvan T. Ivanov u16 mux_bit; 54*657cbf9bSIvan T. Ivanov u16 pad_bit; 55*657cbf9bSIvan T. Ivanov }; 56*657cbf9bSIvan T. Ivanov 57*657cbf9bSIvan T. Ivanov /** 58*657cbf9bSIvan T. Ivanov * struct brcmstb_pin_funcs - pins provide their primary/alternate 59*657cbf9bSIvan T. Ivanov * functions in this struct 60*657cbf9bSIvan T. Ivanov * @func_mask: mask representing valid bits of the function selector 61*657cbf9bSIvan T. Ivanov * in the registers 62*657cbf9bSIvan T. Ivanov * @funcs: array of function identifiers 63*657cbf9bSIvan T. Ivanov * @n_funcs: number of identifiers of the @funcs array above 64*657cbf9bSIvan T. Ivanov */ 65*657cbf9bSIvan T. Ivanov struct brcmstb_pin_funcs { 66*657cbf9bSIvan T. Ivanov const u32 func_mask; 67*657cbf9bSIvan T. Ivanov const u8 *funcs; 68*657cbf9bSIvan T. Ivanov const unsigned int n_funcs; 69*657cbf9bSIvan T. Ivanov }; 70*657cbf9bSIvan T. Ivanov 71*657cbf9bSIvan T. Ivanov /** 72*657cbf9bSIvan T. Ivanov * struct brcmstb_pdata - specific data for a pinctrl chip implementation 73*657cbf9bSIvan T. Ivanov * @pctl_desc: pin controller descriptor for this implementation 74*657cbf9bSIvan T. Ivanov * @gpio_range: range of GPIOs served by this controller 75*657cbf9bSIvan T. Ivanov * @pin_regs: array of register descriptors for each pin 76*657cbf9bSIvan T. Ivanov * @pin_funcs: array of all possible assignable function for each pin 77*657cbf9bSIvan T. Ivanov * @func_count: total number of functions 78*657cbf9bSIvan T. Ivanov * @func_gpio: which function number is GPIO (usually 0) 79*657cbf9bSIvan T. Ivanov * @func_names: an array listing all function names 80*657cbf9bSIvan T. Ivanov */ 81*657cbf9bSIvan T. Ivanov struct brcmstb_pdata { 82*657cbf9bSIvan T. Ivanov const struct pinctrl_desc *pctl_desc; 83*657cbf9bSIvan T. Ivanov const struct pinctrl_gpio_range *gpio_range; 84*657cbf9bSIvan T. Ivanov const struct pin_regs *pin_regs; 85*657cbf9bSIvan T. Ivanov const struct brcmstb_pin_funcs *pin_funcs; 86*657cbf9bSIvan T. Ivanov const unsigned int func_count; 87*657cbf9bSIvan T. Ivanov const unsigned int func_gpio; 88*657cbf9bSIvan T. Ivanov const char * const *func_names; 89*657cbf9bSIvan T. Ivanov }; 90*657cbf9bSIvan T. Ivanov 91*657cbf9bSIvan T. Ivanov int brcmstb_pinctrl_probe(struct platform_device *pdev); 92*657cbf9bSIvan T. Ivanov 93*657cbf9bSIvan T. Ivanov #endif 94