1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Aspeed G7 SoC1 4 * 5 * Copyright (C) 2026 Aspeed Technology Inc. 6 */ 7 8 #include <linux/errno.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 #include <linux/pinctrl/pinconf.h> 14 #include <linux/pinctrl/pinctrl.h> 15 #include <linux/pinctrl/pinmux.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 20 #include "../core.h" 21 #include "../pinconf.h" 22 #include "../pinctrl-utils.h" 23 #include "../pinmux.h" 24 25 #define ASPEED_G7_SOC1_NR_PINS 220 26 #define ASPEED_G7_SOC1_REG_WIDTH 32 27 #define ASPEED_G7_SOC1_REG_STRIDE 4 28 29 #define ASPEED_G7_SOC1_MUX_BASE 0x400 30 #define ASPEED_G7_SOC1_BIAS_BASE 0x480 31 #define ASPEED_G7_SOC1_DRV_BASE 0x4C0 32 #define ASPEED_G7_SOC1_PCIE_REG 0x908 33 #define ASPEED_G7_SOC1_USB_MODE_REG 0x3B0 34 #define ASPEED_G7_SOC1_SGMII_REG 0x47C 35 36 /* 37 * Each pin occupies a 4-bit slot in the MUX registers (MUX_BITS_PER_PIN), 38 * but only bits [2:0] select the mux function; bit 3 is reserved read-only 39 * and must not be written. MUX_FUNC_MASK therefore covers 3 bits, not 4. 40 */ 41 #define ASPEED_G7_SOC1_MUX_FUNC_MASK 0x7 42 #define ASPEED_G7_SOC1_MUX_BITS_PER_PIN 4 43 #define ASPEED_G7_SOC1_MUX_PINS_PER_REG \ 44 (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_MUX_BITS_PER_PIN) 45 46 #define ASPEED_G7_SOC1_BIAS_FUNC_MASK 0x1 47 #define ASPEED_G7_SOC1_BIAS_BITS_PER_PIN 1 48 #define ASPEED_G7_SOC1_BIAS_PINS_PER_REG \ 49 (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_BIAS_BITS_PER_PIN) 50 51 #define ASPEED_G7_SOC1_DRV_FUNC_MASK 0x3 52 #define ASPEED_G7_SOC1_DRV_BITS_PER_PIN 2 53 #define ASPEED_G7_SOC1_DRV_PINS_PER_REG \ 54 (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_DRV_BITS_PER_PIN) 55 56 #define ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA 4 57 #define ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE 1 58 #define ASPEED_G7_SOC1_DRV_STRENGTH_MIN_MA \ 59 (ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE * ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) 60 #define ASPEED_G7_SOC1_DRV_STRENGTH_MAX_MA \ 61 ((ASPEED_G7_SOC1_DRV_FUNC_MASK + ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE) * \ 62 ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) 63 64 /* 65 * NOTE: The numeric values of these enum entries are significant. 66 * They must match the SoC GPIO numbering / ball-to-GPIO ID mapping. 67 * Do not reorder alphabetically. 68 */ 69 enum { 70 C16, 71 C14, 72 C11, 73 D9, 74 F14, 75 D10, 76 C12, 77 C13, 78 AC26, 79 AA25, 80 AB23, 81 U22, 82 V21, 83 N26, 84 P25, 85 N25, 86 V23, 87 W22, 88 AB26, 89 AD26, 90 P26, 91 AE26, 92 AF26, 93 AF25, 94 AE25, 95 AD25, 96 AF23, 97 AF20, 98 AF21, 99 AE21, 100 AE23, 101 AD22, 102 AF17, 103 AA16, 104 Y16, 105 V17, 106 J13, 107 AB16, 108 AC16, 109 AF16, 110 AA15, 111 AB15, 112 AC15, 113 AD15, 114 Y15, 115 AA14, 116 W16, 117 V16, 118 AB18, 119 AC18, 120 K13, 121 AA17, 122 AB17, 123 AD16, 124 AC17, 125 AD17, 126 AE16, 127 AE17, 128 AB24, 129 W26, 130 HOLE0, 131 HOLE1, 132 HOLE2, 133 HOLE3, 134 W25, 135 Y23, 136 Y24, 137 W21, 138 AA23, 139 AC22, 140 AB22, 141 Y21, 142 AE20, 143 AF19, 144 Y22, 145 AA20, 146 AA22, 147 AB20, 148 AF18, 149 AE19, 150 AD20, 151 AC20, 152 AA21, 153 AB21, 154 AC19, 155 AE18, 156 AD19, 157 AD18, 158 U25, 159 U26, 160 Y26, 161 AA24, 162 R25, 163 AA26, 164 R26, 165 Y25, 166 B16, 167 D14, 168 B15, 169 B14, 170 C17, 171 B13, 172 E14, 173 C15, 174 D24, 175 B23, 176 B22, 177 C23, 178 B18, 179 B21, 180 M15, 181 B19, 182 B26, 183 A25, 184 A24, 185 B24, 186 E26, 187 A21, 188 A19, 189 A18, 190 D26, 191 C26, 192 A23, 193 A22, 194 B25, 195 F26, 196 A26, 197 A14, 198 E10, 199 E13, 200 D12, 201 F10, 202 E11, 203 F11, 204 F13, 205 N15, 206 C20, 207 C19, 208 A8, 209 R14, 210 A7, 211 P14, 212 D20, 213 A6, 214 B6, 215 N14, 216 B7, 217 B8, 218 B9, 219 M14, 220 J11, 221 E7, 222 D19, 223 B11, 224 D15, 225 B12, 226 B10, 227 P13, 228 C18, 229 C6, 230 C7, 231 D7, 232 N13, 233 C8, 234 C9, 235 C10, 236 M16, 237 A15, 238 G11, 239 H7, 240 H8, 241 H9, 242 H10, 243 H11, 244 J9, 245 J10, 246 E9, 247 F9, 248 F8, 249 M13, 250 F7, 251 D8, 252 E8, 253 L12, 254 F12, 255 E12, 256 J12, 257 G7, 258 G8, 259 G9, 260 G10, 261 K12, 262 W17, 263 V18, 264 W18, 265 Y17, 266 AA18, 267 AA13, 268 Y18, 269 AA12, 270 W20, 271 V20, 272 Y11, 273 V14, 274 V19, 275 W14, 276 Y20, 277 AB19, 278 U21, 279 T24, 280 V24, 281 V22, 282 T23, 283 AC25, 284 AB25, 285 AC24, 286 PCIERC2_PERST, 287 PORTC_MODE, 288 PORTD_MODE, 289 SGMII0, 290 }; 291 292 struct aspeed_g7_soc1_pinctrl { 293 struct device *dev; 294 struct regmap *regmap; 295 struct pinctrl_dev *pctl; 296 }; 297 298 struct aspeed_g7_field { 299 unsigned int reg; 300 unsigned int shift; 301 unsigned int mask; 302 }; 303 304 static struct aspeed_g7_field 305 aspeed_g7_soc1_pinmux_field_from_pin(unsigned int pin) 306 { 307 return (struct aspeed_g7_field){ 308 .reg = ASPEED_G7_SOC1_MUX_BASE + 309 (pin / ASPEED_G7_SOC1_MUX_PINS_PER_REG) * 310 ASPEED_G7_SOC1_REG_STRIDE, 311 .shift = (pin % ASPEED_G7_SOC1_MUX_PINS_PER_REG) * 312 ASPEED_G7_SOC1_MUX_BITS_PER_PIN, 313 .mask = ASPEED_G7_SOC1_MUX_FUNC_MASK, 314 }; 315 } 316 317 static struct aspeed_g7_field 318 aspeed_g7_soc1_bias_field_from_pin(unsigned int pin) 319 { 320 return (struct aspeed_g7_field){ 321 .reg = ASPEED_G7_SOC1_BIAS_BASE + 322 (pin / ASPEED_G7_SOC1_BIAS_PINS_PER_REG) * 323 ASPEED_G7_SOC1_REG_STRIDE, 324 .shift = pin % ASPEED_G7_SOC1_BIAS_PINS_PER_REG, 325 .mask = ASPEED_G7_SOC1_BIAS_FUNC_MASK, 326 }; 327 } 328 329 static struct aspeed_g7_field 330 aspeed_g7_soc1_drv_field_from_idx(unsigned int idx) 331 { 332 return (struct aspeed_g7_field){ 333 .reg = ASPEED_G7_SOC1_DRV_BASE + 334 (idx / ASPEED_G7_SOC1_DRV_PINS_PER_REG) * 335 ASPEED_G7_SOC1_REG_STRIDE, 336 .shift = (idx % ASPEED_G7_SOC1_DRV_PINS_PER_REG) * 337 ASPEED_G7_SOC1_DRV_BITS_PER_PIN, 338 .mask = ASPEED_G7_SOC1_DRV_FUNC_MASK, 339 }; 340 } 341 342 #define PIN(n) PINCTRL_PIN(n, #n) 343 344 static const struct pinctrl_pin_desc aspeed_g7_soc1_pins[] = { 345 PIN(C16), 346 PIN(C14), 347 PIN(C11), 348 PIN(D9), 349 PIN(F14), 350 PIN(D10), 351 PIN(C12), 352 PIN(C13), 353 PIN(AC26), 354 PIN(AA25), 355 PIN(AB23), 356 PIN(U22), 357 PIN(V21), 358 PIN(N26), 359 PIN(P25), 360 PIN(N25), 361 PIN(V23), 362 PIN(W22), 363 PIN(AB26), 364 PIN(AD26), 365 PIN(P26), 366 PIN(AE26), 367 PIN(AF26), 368 PIN(AF25), 369 PIN(AE25), 370 PIN(AD25), 371 PIN(AF23), 372 PIN(AF20), 373 PIN(AF21), 374 PIN(AE21), 375 PIN(AE23), 376 PIN(AD22), 377 PIN(AF17), 378 PIN(AA16), 379 PIN(Y16), 380 PIN(V17), 381 PIN(J13), 382 PIN(AB16), 383 PIN(AC16), 384 PIN(AF16), 385 PIN(AA15), 386 PIN(AB15), 387 PIN(AC15), 388 PIN(AD15), 389 PIN(Y15), 390 PIN(AA14), 391 PIN(W16), 392 PIN(V16), 393 PIN(AB18), 394 PIN(AC18), 395 PIN(K13), 396 PIN(AA17), 397 PIN(AB17), 398 PIN(AD16), 399 PIN(AC17), 400 PIN(AD17), 401 PIN(AE16), 402 PIN(AE17), 403 PIN(AB24), 404 PIN(W26), 405 PIN(HOLE0), 406 PIN(HOLE1), 407 PIN(HOLE2), 408 PIN(HOLE3), 409 PIN(W25), 410 PIN(Y23), 411 PIN(Y24), 412 PIN(W21), 413 PIN(AA23), 414 PIN(AC22), 415 PIN(AB22), 416 PIN(Y21), 417 PIN(AE20), 418 PIN(AF19), 419 PIN(Y22), 420 PIN(AA20), 421 PIN(AA22), 422 PIN(AB20), 423 PIN(AF18), 424 PIN(AE19), 425 PIN(AD20), 426 PIN(AC20), 427 PIN(AA21), 428 PIN(AB21), 429 PIN(AC19), 430 PIN(AE18), 431 PIN(AD19), 432 PIN(AD18), 433 PIN(U25), 434 PIN(U26), 435 PIN(Y26), 436 PIN(AA24), 437 PIN(R25), 438 PIN(AA26), 439 PIN(R26), 440 PIN(Y25), 441 PIN(B16), 442 PIN(D14), 443 PIN(B15), 444 PIN(B14), 445 PIN(C17), 446 PIN(B13), 447 PIN(E14), 448 PIN(C15), 449 PIN(D24), 450 PIN(B23), 451 PIN(B22), 452 PIN(C23), 453 PIN(B18), 454 PIN(B21), 455 PIN(M15), 456 PIN(B19), 457 PIN(B26), 458 PIN(A25), 459 PIN(A24), 460 PIN(B24), 461 PIN(E26), 462 PIN(A21), 463 PIN(A19), 464 PIN(A18), 465 PIN(D26), 466 PIN(C26), 467 PIN(A23), 468 PIN(A22), 469 PIN(B25), 470 PIN(F26), 471 PIN(A26), 472 PIN(A14), 473 PIN(E10), 474 PIN(E13), 475 PIN(D12), 476 PIN(F10), 477 PIN(E11), 478 PIN(F11), 479 PIN(F13), 480 PIN(N15), 481 PIN(C20), 482 PIN(C19), 483 PIN(A8), 484 PIN(R14), 485 PIN(A7), 486 PIN(P14), 487 PIN(D20), 488 PIN(A6), 489 PIN(B6), 490 PIN(N14), 491 PIN(B7), 492 PIN(B8), 493 PIN(B9), 494 PIN(M14), 495 PIN(J11), 496 PIN(E7), 497 PIN(D19), 498 PIN(B11), 499 PIN(D15), 500 PIN(B12), 501 PIN(B10), 502 PIN(P13), 503 PIN(C18), 504 PIN(C6), 505 PIN(C7), 506 PIN(D7), 507 PIN(N13), 508 PIN(C8), 509 PIN(C9), 510 PIN(C10), 511 PIN(M16), 512 PIN(A15), 513 PIN(G11), 514 PIN(H7), 515 PIN(H8), 516 PIN(H9), 517 PIN(H10), 518 PIN(H11), 519 PIN(J9), 520 PIN(J10), 521 PIN(E9), 522 PIN(F9), 523 PIN(F8), 524 PIN(M13), 525 PIN(F7), 526 PIN(D8), 527 PIN(E8), 528 PIN(L12), 529 PIN(F12), 530 PIN(E12), 531 PIN(J12), 532 PIN(G7), 533 PIN(G8), 534 PIN(G9), 535 PIN(G10), 536 PIN(K12), 537 PIN(W17), 538 PIN(V18), 539 PIN(W18), 540 PIN(Y17), 541 PIN(AA18), 542 PIN(AA13), 543 PIN(Y18), 544 PIN(AA12), 545 PIN(W20), 546 PIN(V20), 547 PIN(Y11), 548 PIN(V14), 549 PIN(V19), 550 PIN(W14), 551 PIN(Y20), 552 PIN(AB19), 553 PIN(U21), 554 PIN(T24), 555 PIN(V24), 556 PIN(V22), 557 PIN(T23), 558 PIN(AC25), 559 PIN(AB25), 560 PIN(AC24), 561 PIN(PCIERC2_PERST), 562 PIN(PORTC_MODE), 563 PIN(PORTD_MODE), 564 PIN(SGMII0), 565 }; 566 567 static const struct pinctrl_ops aspeed_g7_soc1_pctl_ops = { 568 .get_groups_count = pinctrl_generic_get_group_count, 569 .get_group_name = pinctrl_generic_get_group_name, 570 .get_group_pins = pinctrl_generic_get_group_pins, 571 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 572 .dt_free_map = pinctrl_utils_free_map, 573 }; 574 575 struct aspeed_g7_soc1_function { 576 struct pinfunction pinfunction; 577 const u8 *muxvals; 578 }; 579 580 static int aspeed_g7_soc1_drive_strength_to_hw(u32 strength, 581 unsigned int *val) 582 { 583 if (strength < ASPEED_G7_SOC1_DRV_STRENGTH_MIN_MA || 584 strength > ASPEED_G7_SOC1_DRV_STRENGTH_MAX_MA || 585 strength % ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) 586 return -EINVAL; 587 588 *val = (strength / ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) - 589 ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE; 590 591 return 0; 592 } 593 594 static int aspeed_g7_soc1_set_mux(struct pinctrl_dev *pctldev, 595 unsigned int fselector, unsigned int group) 596 { 597 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 598 const struct aspeed_g7_soc1_function *soc1_func; 599 const struct function_desc *fd; 600 const struct pinfunction *func; 601 const struct pingroup *grp; 602 struct group_desc *gd; 603 const char *gname; 604 int i, g_idx = -1, ret; 605 606 gd = pinctrl_generic_get_group(pctldev, group); 607 if (!gd) 608 return -EINVAL; 609 610 grp = &gd->grp; 611 612 fd = pinmux_generic_get_function(pctldev, fselector); 613 if (!fd) 614 return -EINVAL; 615 616 soc1_func = fd->data; 617 if (!soc1_func) 618 return -EINVAL; 619 620 func = &soc1_func->pinfunction; 621 gname = grp->name; 622 623 for (i = 0; i < func->ngroups; i++) { 624 if (!strcmp(gname, func->groups[i])) { 625 g_idx = i; 626 break; 627 } 628 } 629 630 if (g_idx < 0) 631 return -EINVAL; 632 633 for (i = 0; i < grp->npins; i++) { 634 unsigned int val = soc1_func->muxvals[g_idx]; 635 unsigned int pin = grp->pins[i]; 636 struct aspeed_g7_field field; 637 638 if (pin == PCIERC2_PERST) { 639 /* 640 * PCIERC2_PERST is a special case: it is managed by a 641 * dedicated control register (0x908) instead of the 642 * standard 4-bit multi-function field. 643 */ 644 field.reg = ASPEED_G7_SOC1_PCIE_REG; 645 field.shift = 0; 646 field.mask = 0x1; 647 val = 1; 648 } else if (pin == PORTC_MODE || pin == PORTD_MODE) { 649 /* 650 * PORTC_MODE and PORTD_MODE are virtual "pins" that 651 * control the USB 2.0 controller mode settings. 652 * These reside in a specific control register (0x3B0) 653 * with non-standard bit widths. 654 */ 655 field.reg = ASPEED_G7_SOC1_USB_MODE_REG; 656 field.mask = 0x3; 657 field.shift = pin == PORTC_MODE ? 0 : 2; 658 } else if (pin == SGMII0) { 659 /* 660 * SGMII0 is a virtual pin whose mux control resides at 661 * SCU47C bit 0, outside the contiguous pin-indexed MUX 662 * register range starting at MUX_BASE. The field is 663 * 1 bit wide; use a 1-bit mask to avoid clobbering 664 * adjacent bits in SCU47C. 665 */ 666 field.reg = ASPEED_G7_SOC1_SGMII_REG; 667 field.shift = 0; 668 field.mask = 0x1; 669 } else { 670 /* Standard 4-bit-per-pin multi-function configuration */ 671 field = aspeed_g7_soc1_pinmux_field_from_pin(pin); 672 } 673 674 dev_dbg(pctl->dev, 675 "Setting pin %u reg 0x%x shift %u to function %s (muxval=0x%x)\n", 676 pin, field.reg, field.shift, func->name, val); 677 678 ret = regmap_update_bits(pctl->regmap, field.reg, 679 field.mask << field.shift, 680 val << field.shift); 681 if (ret) 682 return ret; 683 } 684 685 return 0; 686 } 687 688 static int aspeed_g7_soc1_gpio_request_enable(struct pinctrl_dev *pctldev, 689 struct pinctrl_gpio_range *range, 690 unsigned int pin) 691 { 692 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 693 struct aspeed_g7_field field; 694 unsigned int val = 0; 695 int ret = -ENOTSUPP; 696 697 if (pin <= AC24) { 698 /* 699 * Balls W17 through AB19 are the ADC-capable pins: mux 700 * function 0 selects the ADC input and function 1 selects 701 * GPIO, unlike all other pins where function 0 is GPIO. 702 */ 703 if (pin >= W17 && pin <= AB19) 704 val = 1; 705 field = aspeed_g7_soc1_pinmux_field_from_pin(pin); 706 ret = regmap_update_bits(pctl->regmap, field.reg, 707 field.mask << field.shift, 708 val << field.shift); 709 } 710 711 return ret; 712 } 713 714 static const struct pinmux_ops aspeed_g7_soc1_pmx_ops = { 715 .get_functions_count = pinmux_generic_get_function_count, 716 .get_function_name = pinmux_generic_get_function_name, 717 .get_function_groups = pinmux_generic_get_function_groups, 718 .set_mux = aspeed_g7_soc1_set_mux, 719 .gpio_request_enable = aspeed_g7_soc1_gpio_request_enable, 720 .strict = true, 721 }; 722 723 /* 724 * aspeed_g7_soc1_drv_map - Mapping table for pin drive strength control. 725 * 726 * In AST2700 SOC1, drive strength configuration is architecturally decoupled 727 * from the main pin mux registers (0x400 range). It is managed by a separate 728 * set of registers starting at 0x4C0. 729 * 730 * This table is required because: 731 * 1. The mapping between physical pin IDs and drive strength control slots 732 * is non-linear and sparse. 733 * For example, W25 maps to field index 8 (stored as 9), 734 * meaning it occupies bits [17:16] of the first 0x4C0 register. 735 * 2. Only a subset of physical pins supports drive strength configuration. 736 * 737 * The table stores (drive strength field index + 1). 738 * The field index refers to the 2-bit drive strength field position within the 739 * 0x4C0 register range. A value of 0 indicates that the pin does not support 740 * drive strength configuration (returning -ENOTSUPP). 741 * This +1 offset allows us to rely on C's default zero-initialization for 742 * unsupported pins while avoiding compiler warnings regarding overridden 743 * initializers. 744 */ 745 static const int aspeed_g7_soc1_drv_map[ASPEED_G7_SOC1_NR_PINS] = { 746 [C16] = 1, [C14] = 2, [C11] = 3, [D9] = 4, [F14] = 5, [D10] = 6, [C12] = 7, 747 [C13] = 8, [W25] = 9, [Y23] = 10, [Y24] = 11, [W21] = 12, [AA23] = 13, [AC22] = 14, 748 [AB22] = 15, [Y21] = 16, [AE20] = 17, [AF19] = 18, [Y22] = 19, [AA20] = 20, [AA22] = 21, 749 [AB20] = 22, [AF18] = 23, [AE19] = 24, [AD20] = 25, [AC20] = 26, [AA21] = 27, [AB21] = 28, 750 [AC19] = 29, [AE18] = 30, [AD19] = 31, [AD18] = 32, [U25] = 33, [U26] = 34, [Y26] = 35, 751 [AA24] = 36, [R25] = 37, [AA26] = 38, [R26] = 39, [Y25] = 40, [B16] = 41, [D14] = 42, 752 [B15] = 43, [B14] = 44, [C17] = 45, [B13] = 46, [E14] = 47, [C15] = 48, [D24] = 49, 753 [B23] = 50, [B22] = 51, [C23] = 52, [B18] = 53, [B21] = 54, [M15] = 55, [B19] = 56, 754 [B26] = 57, [A25] = 58, [A24] = 59, [B24] = 60, [E26] = 61, [A21] = 62, [A19] = 63, 755 [A18] = 64, [D26] = 65, [C26] = 66, [A23] = 67, [A22] = 68, [B25] = 69, [F26] = 70, 756 [A26] = 71, [A14] = 72, [E10] = 73, [E13] = 74, [D12] = 75, [F10] = 76, [E11] = 77, 757 [F11] = 78, [F13] = 79, [N15] = 80, [C20] = 81, [C19] = 82, [A8] = 83, [R14] = 84, 758 [A7] = 85, [P14] = 86, [D20] = 87, [A6] = 88, [B6] = 89, [N14] = 90, [B7] = 91, 759 [B8] = 92, [B9] = 93, [M14] = 94, [J11] = 95, [E7] = 96, [D19] = 97, [B11] = 98, 760 [D15] = 99, [B12] = 100, [B10] = 101, [P13] = 102, [C18] = 103, [C6] = 104, [C7] = 105, 761 [D7] = 106, [N13] = 107, [C8] = 108, [C9] = 109, [C10] = 110, [M16] = 111, [A15] = 112, 762 [E9] = 113, [F9] = 114, [F8] = 115, [M13] = 116, [F7] = 117, [D8] = 118, [E8] = 119, 763 [L12] = 120, 764 }; 765 766 static int aspeed_g7_soc1_pin_config_get(struct pinctrl_dev *pctldev, 767 unsigned int pin, 768 unsigned long *config) 769 { 770 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 771 enum pin_config_param param = pinconf_to_config_param(*config); 772 struct aspeed_g7_field field; 773 unsigned int val, val_raw; 774 int ret, ds_idx; 775 776 if (pin > AC24) 777 return -EINVAL; 778 779 switch (param) { 780 case PIN_CONFIG_BIAS_DISABLE: 781 field = aspeed_g7_soc1_bias_field_from_pin(pin); 782 break; 783 case PIN_CONFIG_BIAS_PULL_DOWN: 784 case PIN_CONFIG_BIAS_PULL_UP: 785 /* 786 * The hardware has a single 1-bit enable/disable field per 787 * pin; pull direction is fixed in silicon and cannot be read 788 * back from the register. Reject readback requests for a 789 * specific pull direction. 790 */ 791 return -ENOTSUPP; 792 case PIN_CONFIG_DRIVE_STRENGTH: 793 ds_idx = aspeed_g7_soc1_drv_map[pin]; 794 if (!ds_idx) 795 return -ENOTSUPP; 796 ds_idx--; /* Adjust back to 0-based hardware index */ 797 field = aspeed_g7_soc1_drv_field_from_idx(ds_idx); 798 break; 799 default: 800 return -ENOTSUPP; 801 } 802 803 ret = regmap_read(pctl->regmap, field.reg, &val_raw); 804 if (ret) 805 return ret; 806 807 val = (val_raw & (field.mask << field.shift)) >> field.shift; 808 if (param == PIN_CONFIG_DRIVE_STRENGTH) 809 val = (val + ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE) * 810 ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA; 811 812 if (!val) 813 return -EINVAL; 814 815 *config = pinconf_to_config_packed(param, val); 816 817 return 0; 818 } 819 820 static int aspeed_g7_soc1_pin_config_set(struct pinctrl_dev *pctldev, 821 unsigned int pin, 822 unsigned long *configs, 823 unsigned int num_configs) 824 { 825 struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 826 struct aspeed_g7_field field; 827 enum pin_config_param param; 828 int i, ret, ds_idx; 829 unsigned int val; 830 u32 arg; 831 832 if (pin > AC24) 833 return -EINVAL; 834 835 for (i = 0; i < num_configs; i++) { 836 param = pinconf_to_config_param(configs[i]); 837 arg = pinconf_to_config_argument(configs[i]); 838 839 switch (param) { 840 case PIN_CONFIG_BIAS_PULL_DOWN: 841 case PIN_CONFIG_BIAS_PULL_UP: 842 /* 843 * The hardware has one enable/disable bit per pin; 844 * pull direction is fixed in silicon. Both PULL_UP 845 * and PULL_DOWN map to "enable bias"; the caller must 846 * request the direction that the hardware provides. 847 */ 848 case PIN_CONFIG_BIAS_DISABLE: 849 field = aspeed_g7_soc1_bias_field_from_pin(pin); 850 val = (param == PIN_CONFIG_BIAS_DISABLE) ? 1 : 0; 851 break; 852 case PIN_CONFIG_DRIVE_STRENGTH: 853 ds_idx = aspeed_g7_soc1_drv_map[pin]; 854 if (!ds_idx) 855 return -ENOTSUPP; 856 ds_idx--; /* Adjust back to 0-based hardware index */ 857 field = aspeed_g7_soc1_drv_field_from_idx(ds_idx); 858 ret = aspeed_g7_soc1_drive_strength_to_hw(arg, &val); 859 if (ret) 860 return ret; 861 break; 862 default: 863 return -ENOTSUPP; 864 } 865 866 dev_dbg(pctl->dev, 867 "Configuring pin %u reg 0x%x shift %u param %d arg %u val 0x%x\n", 868 pin, field.reg, field.shift, param, arg, val); 869 870 ret = regmap_update_bits(pctl->regmap, field.reg, 871 field.mask << field.shift, 872 val << field.shift); 873 874 if (ret) 875 return ret; 876 } 877 878 return 0; 879 } 880 881 static int aspeed_g7_soc1_pin_config_group_get(struct pinctrl_dev *pctldev, 882 unsigned int selector, 883 unsigned long *config) 884 { 885 const unsigned int *pins; 886 unsigned int npins; 887 int ret; 888 889 ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); 890 if (ret) 891 return ret; 892 if (!npins) 893 return -ENODEV; 894 895 return aspeed_g7_soc1_pin_config_get(pctldev, pins[0], config); 896 } 897 898 static int aspeed_g7_soc1_pin_config_group_set(struct pinctrl_dev *pctldev, 899 unsigned int selector, 900 unsigned long *configs, 901 unsigned int num_configs) 902 { 903 const unsigned int *pins; 904 unsigned int npins; 905 int ret; 906 int i; 907 908 ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); 909 if (ret) 910 return ret; 911 912 for (i = 0; i < npins; i++) { 913 ret = aspeed_g7_soc1_pin_config_set(pctldev, pins[i], configs, 914 num_configs); 915 if (ret) 916 return ret; 917 } 918 919 return 0; 920 } 921 922 static const struct pinconf_ops aspeed_g7_soc1_conf_ops = { 923 .is_generic = true, 924 .pin_config_get = aspeed_g7_soc1_pin_config_get, 925 .pin_config_set = aspeed_g7_soc1_pin_config_set, 926 .pin_config_group_get = aspeed_g7_soc1_pin_config_group_get, 927 .pin_config_group_set = aspeed_g7_soc1_pin_config_group_set, 928 .pin_config_config_dbg_show = pinconf_generic_dump_config, 929 }; 930 931 static const struct pinctrl_desc aspeed_g7_soc1_desc = { 932 .name = "aspeed-g7-soc1-pinctrl", 933 .pins = aspeed_g7_soc1_pins, 934 .npins = ARRAY_SIZE(aspeed_g7_soc1_pins), 935 .pctlops = &aspeed_g7_soc1_pctl_ops, 936 .pmxops = &aspeed_g7_soc1_pmx_ops, 937 .confops = &aspeed_g7_soc1_conf_ops, 938 .owner = THIS_MODULE, 939 }; 940 941 #define PIN_GROUP(name, ...) static const unsigned int name ## _pins[] = { __VA_ARGS__ } 942 943 /* Pin Groups and Functions */ 944 PIN_GROUP(ADC0, W17); 945 PIN_GROUP(ADC1, V18); 946 PIN_GROUP(ADC10, Y11); 947 PIN_GROUP(ADC11, V14); 948 PIN_GROUP(ADC12, V19); 949 PIN_GROUP(ADC13, W14); 950 PIN_GROUP(ADC14, Y20); 951 PIN_GROUP(ADC15, AB19); 952 PIN_GROUP(ADC2, W18); 953 PIN_GROUP(ADC3, Y17); 954 PIN_GROUP(ADC4, AA18); 955 PIN_GROUP(ADC5, AA13); 956 PIN_GROUP(ADC6, Y18); 957 PIN_GROUP(ADC7, AA12); 958 PIN_GROUP(ADC8, W20); 959 PIN_GROUP(ADC9, V20); 960 PIN_GROUP(AUXPWRGOOD0, W14); 961 PIN_GROUP(AUXPWRGOOD1, Y20); 962 PIN_GROUP(CANBUS, G7, G8, G9); 963 PIN_GROUP(DI2C0, C16, D9); 964 PIN_GROUP(DI2C1, C14, F14); 965 PIN_GROUP(DI2C10, R25, AA26); 966 PIN_GROUP(DI2C11, R26, Y25); 967 PIN_GROUP(DI2C12, W25, Y23); 968 PIN_GROUP(DI2C13, Y24, W21); 969 PIN_GROUP(DI2C14, AA23, AC22); 970 PIN_GROUP(DI2C15, AB22, Y21); 971 PIN_GROUP(DI2C2, D10, C12); 972 PIN_GROUP(DI2C3, C11, C13); 973 PIN_GROUP(DI2C8, U25, U26); 974 PIN_GROUP(DI2C9, Y26, AA24); 975 PIN_GROUP(DSGPM0, D19, B10, C7, D7); 976 PIN_GROUP(ESPI0, B16, D14, B15, B14, C17, B13, E14, C15); 977 PIN_GROUP(ESPI1, C16, C14, C11, D9, F14, D10, C12, C13); 978 PIN_GROUP(FSI0, AD20, AC20); 979 PIN_GROUP(FSI1, AA21, AB21); 980 PIN_GROUP(FSI2, AC19, AE18); 981 PIN_GROUP(FSI3, AD19, AD18); 982 PIN_GROUP(FWQSPI, M16, A15); 983 PIN_GROUP(FWSPIABR, A14); 984 PIN_GROUP(FWWPN, N15); 985 PIN_GROUP(HBLED, V24); 986 PIN_GROUP(HVI3C0, U25, U26); 987 PIN_GROUP(HVI3C1, Y26, AA24); 988 PIN_GROUP(HVI3C12, W25, Y23); 989 PIN_GROUP(HVI3C13, Y24, W21); 990 PIN_GROUP(HVI3C14, AA23, AC22); 991 PIN_GROUP(HVI3C15, AB22, Y21); 992 PIN_GROUP(HVI3C2, R25, AA26); 993 PIN_GROUP(HVI3C3, R26, Y25); 994 PIN_GROUP(I2C0, G11, H7); 995 PIN_GROUP(I2C1, H8, H9); 996 PIN_GROUP(I2C10, G8, G9); 997 PIN_GROUP(I2C11, G10, K12); 998 PIN_GROUP(I2C12, AC18, AA17); 999 PIN_GROUP(I2C13, AB17, AD16); 1000 PIN_GROUP(I2C14, AC17, AD17); 1001 PIN_GROUP(I2C15, AE16, AE17); 1002 PIN_GROUP(I2C2, H10, H11); 1003 PIN_GROUP(I2C3, J9, J10); 1004 PIN_GROUP(I2C4, E9, F9); 1005 PIN_GROUP(I2C5, F8, M13); 1006 PIN_GROUP(I2C6, F7, D8); 1007 PIN_GROUP(I2C7, E8, L12); 1008 PIN_GROUP(I2C8, F12, E12); 1009 PIN_GROUP(I2C9, J12, G7); 1010 PIN_GROUP(I2CF0, F12, E12, J12, G7); 1011 PIN_GROUP(I2CF1, E9, F9, F8, M13); 1012 PIN_GROUP(I2CF2, F7, D8, E8, L12); 1013 PIN_GROUP(I3C10, AC19, AE18); 1014 PIN_GROUP(I3C11, AD19, AD18); 1015 PIN_GROUP(I3C4, AE20, AF19); 1016 PIN_GROUP(I3C5, Y22, AA20); 1017 PIN_GROUP(I3C6, AA22, AB20); 1018 PIN_GROUP(I3C7, AF18, AE19); 1019 PIN_GROUP(I3C8, AD20, AC20); 1020 PIN_GROUP(I3C9, AA21, AB21); 1021 PIN_GROUP(JTAGM1, D12, F10, E11, F11, F13); 1022 PIN_GROUP(LPC0, AF26, AF25, B16, D14, B15, B14, C17, B13, E14, C15); 1023 PIN_GROUP(LPC1, C16, C14, C11, D9, F14, D10, C12, C13, AE16, AE17); 1024 PIN_GROUP(LTPI, U25, U26, Y26, AA24); 1025 PIN_GROUP(LTPI_PS_I2C0, G11, H7); 1026 PIN_GROUP(LTPI_PS_I2C1, H8, H9); 1027 PIN_GROUP(LTPI_PS_I2C2, H10, H11); 1028 PIN_GROUP(LTPI_PS_I2C3, J9, J10); 1029 PIN_GROUP(MACLINK0, U21); 1030 PIN_GROUP(MACLINK1, AC24); 1031 PIN_GROUP(MACLINK2, T24); 1032 PIN_GROUP(MDIO0, B9, M14); 1033 PIN_GROUP(MDIO1, C9, C10); 1034 PIN_GROUP(MDIO2, E10, E13); 1035 PIN_GROUP(NCTS0, AF17); 1036 PIN_GROUP(NCTS1, AA15); 1037 PIN_GROUP(NCTS5, V21); 1038 PIN_GROUP(NCTS6, AB26); 1039 PIN_GROUP(NDCD0, AA16); 1040 PIN_GROUP(NDCD1, AB15); 1041 PIN_GROUP(NDCD5, N26); 1042 PIN_GROUP(NDCD6, AD26); 1043 PIN_GROUP(NDSR0, Y16); 1044 PIN_GROUP(NDSR1, AC15); 1045 PIN_GROUP(NDSR5, P25); 1046 PIN_GROUP(NDSR6, P26); 1047 PIN_GROUP(NDTR0, J13); 1048 PIN_GROUP(NDTR1, Y15); 1049 PIN_GROUP(NDTR5, V23); 1050 PIN_GROUP(NDTR6, AF26); 1051 PIN_GROUP(NRI0, V17); 1052 PIN_GROUP(NRI1, AD15); 1053 PIN_GROUP(NRI5, N25); 1054 PIN_GROUP(NRI6, AE26); 1055 PIN_GROUP(NRTS0, AB16); 1056 PIN_GROUP(NRTS1, AA14); 1057 PIN_GROUP(NRTS5, W22); 1058 PIN_GROUP(NRTS6, AF25); 1059 PIN_GROUP(OSCCLK, C17); 1060 PIN_GROUP(PE2SGRSTN, E10, PCIERC2_PERST); 1061 PIN_GROUP(PWM0, AE25); 1062 PIN_GROUP(PWM1, AD25); 1063 PIN_GROUP(PWM10, AB17); 1064 PIN_GROUP(PWM11, AD16); 1065 PIN_GROUP(PWM12, AC17); 1066 PIN_GROUP(PWM13, AD17); 1067 PIN_GROUP(PWM14, AE16); 1068 PIN_GROUP(PWM15, AE17); 1069 PIN_GROUP(PWM2, AF23); 1070 PIN_GROUP(PWM3, AF20); 1071 PIN_GROUP(PWM4, AF21); 1072 PIN_GROUP(PWM5, AE21); 1073 PIN_GROUP(PWM6, AE23); 1074 PIN_GROUP(PWM7, AD22); 1075 PIN_GROUP(PWM8, K13); 1076 PIN_GROUP(PWM9, AA17); 1077 PIN_GROUP(QSPI0, C23, B18); 1078 PIN_GROUP(QSPI1, B24, E26); 1079 PIN_GROUP(QSPI2, B25, F26); 1080 PIN_GROUP(RGMII0, C20, C19, A8, R14, A7, P14, D20, A6, B6, N14, B7, B8); 1081 PIN_GROUP(RGMII1, D19, B11, D15, B12, B10, P13, C18, C6, C7, D7, N13, C8); 1082 PIN_GROUP(RMII0, C20, A8, R14, A7, P14, A6, B6, N14); 1083 PIN_GROUP(RMII0RCLKO, D20); 1084 PIN_GROUP(RMII1, D19, D15, B12, B10, P13, C6, C7, D7); 1085 PIN_GROUP(RMII1RCLKO, C18); 1086 PIN_GROUP(SALT0, AC17); 1087 PIN_GROUP(SALT1, AD17); 1088 PIN_GROUP(SALT10, Y18); 1089 PIN_GROUP(SALT11, AA12); 1090 PIN_GROUP(SALT12, AB26); 1091 PIN_GROUP(SALT13, AD26); 1092 PIN_GROUP(SALT14, P26); 1093 PIN_GROUP(SALT15, AE26); 1094 PIN_GROUP(SALT2, AC15); 1095 PIN_GROUP(SALT3, AD15); 1096 PIN_GROUP(SALT4, W17); 1097 PIN_GROUP(SALT5, V18); 1098 PIN_GROUP(SALT6, W18); 1099 PIN_GROUP(SALT7, Y17); 1100 PIN_GROUP(SALT8, AA18); 1101 PIN_GROUP(SALT9, AA13); 1102 PIN_GROUP(SD, C16, C14, C11, D9, F14, D10, C12, C13); 1103 PIN_GROUP(SGMII, SGMII0); 1104 PIN_GROUP(SGPM0, U21, T24, V22, T23); 1105 PIN_GROUP(SGPM1, AC25, AB25, AB24, W26); 1106 PIN_GROUP(SGPS, B11, C18, N13, C8); 1107 PIN_GROUP(SIOONCTRLN0, AE23); 1108 PIN_GROUP(SIOONCTRLN1, AA15); 1109 PIN_GROUP(SIOPBIN0, AD25); 1110 PIN_GROUP(SIOPBIN1, AA16); 1111 PIN_GROUP(SIOPBON0, AE25); 1112 PIN_GROUP(SIOPBON1, AF17); 1113 PIN_GROUP(SIOPWREQN0, AE21); 1114 PIN_GROUP(SIOPWREQN1, AB16); 1115 PIN_GROUP(SIOPWRGD1, AB15); 1116 PIN_GROUP(SIOS3N0, AF20); 1117 PIN_GROUP(SIOS3N1, V17); 1118 PIN_GROUP(SIOS5N0, AF21); 1119 PIN_GROUP(SIOS5N1, J13); 1120 PIN_GROUP(SIOSCIN0, AF23); 1121 PIN_GROUP(SIOSCIN1, Y16); 1122 PIN_GROUP(SMON0, U21, T24, V22, T23); 1123 PIN_GROUP(SMON1, W26, AC25, AB25); 1124 PIN_GROUP(SPI0, D24, B23, B22); 1125 PIN_GROUP(SPI0ABR, M15); 1126 PIN_GROUP(SPI0CS1, B21); 1127 PIN_GROUP(SPI0WPN, B19); 1128 PIN_GROUP(SPI1, B26, A25, A24); 1129 PIN_GROUP(SPI1ABR, A19); 1130 PIN_GROUP(SPI1CS1, A21); 1131 PIN_GROUP(SPI1WPN, A18); 1132 PIN_GROUP(SPI2, D26, C26, A23, A22); 1133 PIN_GROUP(SPI2CS1, A26); 1134 PIN_GROUP(TACH0, AC26); 1135 PIN_GROUP(TACH1, AA25); 1136 PIN_GROUP(TACH10, AB26); 1137 PIN_GROUP(TACH11, AD26); 1138 PIN_GROUP(TACH12, P26); 1139 PIN_GROUP(TACH13, AE26); 1140 PIN_GROUP(TACH14, AF26); 1141 PIN_GROUP(TACH15, AF25); 1142 PIN_GROUP(TACH2, AB23); 1143 PIN_GROUP(TACH3, U22); 1144 PIN_GROUP(TACH4, V21); 1145 PIN_GROUP(TACH5, N26); 1146 PIN_GROUP(TACH6, P25); 1147 PIN_GROUP(TACH7, N25); 1148 PIN_GROUP(TACH8, V23); 1149 PIN_GROUP(TACH9, W22); 1150 PIN_GROUP(THRU0, AC26, AA25); 1151 PIN_GROUP(THRU1, AB23, U22); 1152 PIN_GROUP(THRU2, A19, A18); 1153 PIN_GROUP(THRU3, B25, F26); 1154 PIN_GROUP(UART0, AC16, AF16); 1155 PIN_GROUP(UART1, W16, V16); 1156 PIN_GROUP(UART2, AB18, AC18); 1157 PIN_GROUP(UART3, K13, AA17); 1158 PIN_GROUP(UART5, AB17, AD16); 1159 PIN_GROUP(UART6, AC17, AD17); 1160 PIN_GROUP(UART7, AE16, AE17); 1161 PIN_GROUP(UART8, M15, B19); 1162 PIN_GROUP(UART9, B26, A25); 1163 PIN_GROUP(UART10, A24, B24); 1164 PIN_GROUP(UART11, E26, A21); 1165 PIN_GROUP(USB2CD, PORTC_MODE); 1166 PIN_GROUP(USB2CH, PORTC_MODE); 1167 PIN_GROUP(USB2CU, PORTC_MODE); 1168 PIN_GROUP(USB2CUD, PORTC_MODE); 1169 PIN_GROUP(USB2DD, PORTD_MODE); 1170 PIN_GROUP(USB2DH, PORTD_MODE); 1171 PIN_GROUP(USBUART, G10, K12); 1172 PIN_GROUP(VGA, J11, E7); 1173 PIN_GROUP(VPI, C16, C14, C11, D9, F14, D10, AC26, AA25, AB23, U22, V21, N26, 1174 P25, N25, V23, W22, AB26, AD26, P26, AE26, AF26, AF25, AE25, AD25, 1175 AF23, AF20, AF21, AE21); 1176 PIN_GROUP(WDTRST0N, K13); 1177 PIN_GROUP(WDTRST1N, AA17); 1178 PIN_GROUP(WDTRST2N, AB17); 1179 PIN_GROUP(WDTRST3N, AD16); 1180 PIN_GROUP(WDTRST4N, AC25); 1181 PIN_GROUP(WDTRST5N, AB25); 1182 PIN_GROUP(WDTRST6N, AC24); 1183 PIN_GROUP(WDTRST7N, AB24); 1184 1185 #define GROUP(n) PINCTRL_PINGROUP(#n, n##_pins, ARRAY_SIZE(n##_pins)) 1186 1187 static const struct pingroup aspeed_g7_soc1_groups[] = { 1188 GROUP(ADC0), 1189 GROUP(ADC1), 1190 GROUP(ADC10), 1191 GROUP(ADC11), 1192 GROUP(ADC12), 1193 GROUP(ADC13), 1194 GROUP(ADC14), 1195 GROUP(ADC15), 1196 GROUP(ADC2), 1197 GROUP(ADC3), 1198 GROUP(ADC4), 1199 GROUP(ADC5), 1200 GROUP(ADC6), 1201 GROUP(ADC7), 1202 GROUP(ADC8), 1203 GROUP(ADC9), 1204 GROUP(AUXPWRGOOD0), 1205 GROUP(AUXPWRGOOD1), 1206 GROUP(CANBUS), 1207 GROUP(DI2C0), 1208 GROUP(DI2C1), 1209 GROUP(DI2C10), 1210 GROUP(DI2C11), 1211 GROUP(DI2C12), 1212 GROUP(DI2C13), 1213 GROUP(DI2C14), 1214 GROUP(DI2C15), 1215 GROUP(DI2C2), 1216 GROUP(DI2C3), 1217 GROUP(DI2C8), 1218 GROUP(DI2C9), 1219 GROUP(DSGPM0), 1220 GROUP(ESPI0), 1221 GROUP(ESPI1), 1222 GROUP(FSI0), 1223 GROUP(FSI1), 1224 GROUP(FSI2), 1225 GROUP(FSI3), 1226 GROUP(FWQSPI), 1227 GROUP(FWSPIABR), 1228 GROUP(FWWPN), 1229 GROUP(HBLED), 1230 GROUP(HVI3C0), 1231 GROUP(HVI3C1), 1232 GROUP(HVI3C12), 1233 GROUP(HVI3C13), 1234 GROUP(HVI3C14), 1235 GROUP(HVI3C15), 1236 GROUP(HVI3C2), 1237 GROUP(HVI3C3), 1238 GROUP(I2C0), 1239 GROUP(I2C1), 1240 GROUP(I2C10), 1241 GROUP(I2C11), 1242 GROUP(I2C12), 1243 GROUP(I2C13), 1244 GROUP(I2C14), 1245 GROUP(I2C15), 1246 GROUP(I2C2), 1247 GROUP(I2C3), 1248 GROUP(I2C4), 1249 GROUP(I2C5), 1250 GROUP(I2C6), 1251 GROUP(I2C7), 1252 GROUP(I2C8), 1253 GROUP(I2C9), 1254 GROUP(I2CF0), 1255 GROUP(I2CF1), 1256 GROUP(I2CF2), 1257 GROUP(I3C10), 1258 GROUP(I3C11), 1259 GROUP(I3C4), 1260 GROUP(I3C5), 1261 GROUP(I3C6), 1262 GROUP(I3C7), 1263 GROUP(I3C8), 1264 GROUP(I3C9), 1265 GROUP(JTAGM1), 1266 GROUP(LPC0), 1267 GROUP(LPC1), 1268 GROUP(LTPI), 1269 GROUP(LTPI_PS_I2C0), 1270 GROUP(LTPI_PS_I2C1), 1271 GROUP(LTPI_PS_I2C2), 1272 GROUP(LTPI_PS_I2C3), 1273 GROUP(MACLINK0), 1274 GROUP(MACLINK1), 1275 GROUP(MACLINK2), 1276 GROUP(MDIO0), 1277 GROUP(MDIO1), 1278 GROUP(MDIO2), 1279 GROUP(NCTS0), 1280 GROUP(NCTS1), 1281 GROUP(NCTS5), 1282 GROUP(NCTS6), 1283 GROUP(NDCD0), 1284 GROUP(NDCD1), 1285 GROUP(NDCD5), 1286 GROUP(NDCD6), 1287 GROUP(NDSR0), 1288 GROUP(NDSR1), 1289 GROUP(NDSR5), 1290 GROUP(NDSR6), 1291 GROUP(NDTR0), 1292 GROUP(NDTR1), 1293 GROUP(NDTR5), 1294 GROUP(NDTR6), 1295 GROUP(NRI0), 1296 GROUP(NRI1), 1297 GROUP(NRI5), 1298 GROUP(NRI6), 1299 GROUP(NRTS0), 1300 GROUP(NRTS1), 1301 GROUP(NRTS5), 1302 GROUP(NRTS6), 1303 GROUP(OSCCLK), 1304 GROUP(PE2SGRSTN), 1305 GROUP(PWM0), 1306 GROUP(PWM1), 1307 GROUP(PWM10), 1308 GROUP(PWM11), 1309 GROUP(PWM12), 1310 GROUP(PWM13), 1311 GROUP(PWM14), 1312 GROUP(PWM15), 1313 GROUP(PWM2), 1314 GROUP(PWM3), 1315 GROUP(PWM4), 1316 GROUP(PWM5), 1317 GROUP(PWM6), 1318 GROUP(PWM7), 1319 GROUP(PWM8), 1320 GROUP(PWM9), 1321 GROUP(QSPI0), 1322 GROUP(QSPI1), 1323 GROUP(QSPI2), 1324 GROUP(RGMII0), 1325 GROUP(RGMII1), 1326 GROUP(RMII0), 1327 GROUP(RMII0RCLKO), 1328 GROUP(RMII1), 1329 GROUP(RMII1RCLKO), 1330 GROUP(SALT0), 1331 GROUP(SALT1), 1332 GROUP(SALT10), 1333 GROUP(SALT11), 1334 GROUP(SALT12), 1335 GROUP(SALT13), 1336 GROUP(SALT14), 1337 GROUP(SALT15), 1338 GROUP(SALT2), 1339 GROUP(SALT3), 1340 GROUP(SALT4), 1341 GROUP(SALT5), 1342 GROUP(SALT6), 1343 GROUP(SALT7), 1344 GROUP(SALT8), 1345 GROUP(SALT9), 1346 GROUP(SD), 1347 GROUP(SGMII), 1348 GROUP(SGPM0), 1349 GROUP(SGPM1), 1350 GROUP(SGPS), 1351 GROUP(SIOONCTRLN0), 1352 GROUP(SIOONCTRLN1), 1353 GROUP(SIOPBIN0), 1354 GROUP(SIOPBIN1), 1355 GROUP(SIOPBON0), 1356 GROUP(SIOPBON1), 1357 GROUP(SIOPWREQN0), 1358 GROUP(SIOPWREQN1), 1359 GROUP(SIOPWRGD1), 1360 GROUP(SIOS3N0), 1361 GROUP(SIOS3N1), 1362 GROUP(SIOS5N0), 1363 GROUP(SIOS5N1), 1364 GROUP(SIOSCIN0), 1365 GROUP(SIOSCIN1), 1366 GROUP(SMON0), 1367 GROUP(SMON1), 1368 GROUP(SPI0), 1369 GROUP(SPI0ABR), 1370 GROUP(SPI0CS1), 1371 GROUP(SPI0WPN), 1372 GROUP(SPI1), 1373 GROUP(SPI1ABR), 1374 GROUP(SPI1CS1), 1375 GROUP(SPI1WPN), 1376 GROUP(SPI2), 1377 GROUP(SPI2CS1), 1378 GROUP(TACH0), 1379 GROUP(TACH1), 1380 GROUP(TACH10), 1381 GROUP(TACH11), 1382 GROUP(TACH12), 1383 GROUP(TACH13), 1384 GROUP(TACH14), 1385 GROUP(TACH15), 1386 GROUP(TACH2), 1387 GROUP(TACH3), 1388 GROUP(TACH4), 1389 GROUP(TACH5), 1390 GROUP(TACH6), 1391 GROUP(TACH7), 1392 GROUP(TACH8), 1393 GROUP(TACH9), 1394 GROUP(THRU0), 1395 GROUP(THRU1), 1396 GROUP(THRU2), 1397 GROUP(THRU3), 1398 GROUP(UART0), 1399 GROUP(UART1), 1400 GROUP(UART10), 1401 GROUP(UART11), 1402 GROUP(UART2), 1403 GROUP(UART3), 1404 GROUP(UART5), 1405 GROUP(UART6), 1406 GROUP(UART7), 1407 GROUP(UART8), 1408 GROUP(UART9), 1409 GROUP(USB2CD), 1410 GROUP(USB2CH), 1411 GROUP(USB2CU), 1412 GROUP(USB2CUD), 1413 GROUP(USB2DD), 1414 GROUP(USB2DH), 1415 GROUP(USBUART), 1416 GROUP(VGA), 1417 GROUP(VPI), 1418 GROUP(WDTRST0N), 1419 GROUP(WDTRST1N), 1420 GROUP(WDTRST2N), 1421 GROUP(WDTRST3N), 1422 GROUP(WDTRST4N), 1423 GROUP(WDTRST5N), 1424 GROUP(WDTRST6N), 1425 GROUP(WDTRST7N), 1426 }; 1427 1428 /** 1429 * VM() - Helper macro to unwrap a parenthesized list of arguments. 1430 * @...: The parenthesized list to be unwrapped. 1431 * 1432 * Since the C preprocessor treats commas inside braces {} as argument 1433 * separators for macros, we wrap lists (like mux values) in parentheses () 1434 * to protect them during macro expansion. This macro strips those 1435 * parentheses when the values are needed for array initialization. 1436 */ 1437 #define VM(...) __VA_ARGS__ 1438 1439 /** 1440 * FUNC() - Macro to initialize an aspeed_g7_soc1_function entry. 1441 * @n: Name of the pin function. 1442 * @m: Parenthesized list of mux values, mapped 1:1 to the groups list. 1443 * @...: Variable list of pin group names associated with this function. 1444 * 1445 * This macro solves complex static initialization by: 1446 * 1. Creating anonymous arrays for both group names and mux values 1447 * using C99 Compound Literals. 1448 * 2. Using VM(m) to unwrap mux values into the array initializer. 1449 * 3. Calculating the number of groups via sizeof() division, which 1450 * bypasses the __must_be_array() check performed by ARRAY_SIZE() 1451 * that often fails on compound literals in the kernel environment. 1452 * 1453 * Example: FUNC(i2c0, (1, 4), "i2c0", "di2c0") 1454 * Maps "i2c0" group to mux value 1 and "di2c0" group to mux value 4. 1455 */ 1456 #define FUNC(n, m, ...) \ 1457 { \ 1458 .pinfunction = { \ 1459 .name = #n, \ 1460 .groups = (const char *const[]){ __VA_ARGS__ }, \ 1461 .ngroups = sizeof((const char *const[]){ __VA_ARGS__ }) / sizeof(char *), \ 1462 }, \ 1463 .muxvals = (const u8[]){ VM m } \ 1464 } 1465 1466 static const struct aspeed_g7_soc1_function aspeed_g7_soc1_functions[] = { 1467 FUNC(ADC0, (0), "ADC0"), 1468 FUNC(ADC1, (0), "ADC1"), 1469 FUNC(ADC10, (0), "ADC10"), 1470 FUNC(ADC11, (0), "ADC11"), 1471 FUNC(ADC12, (0), "ADC12"), 1472 FUNC(ADC13, (0), "ADC13"), 1473 FUNC(ADC14, (0), "ADC14"), 1474 FUNC(ADC15, (0), "ADC15"), 1475 FUNC(ADC2, (0), "ADC2"), 1476 FUNC(ADC3, (0), "ADC3"), 1477 FUNC(ADC4, (0), "ADC4"), 1478 FUNC(ADC5, (0), "ADC5"), 1479 FUNC(ADC6, (0), "ADC6"), 1480 FUNC(ADC7, (0), "ADC7"), 1481 FUNC(ADC8, (0), "ADC8"), 1482 FUNC(ADC9, (0), "ADC9"), 1483 FUNC(AUXPWRGOOD0, (2), "AUXPWRGOOD0"), 1484 FUNC(AUXPWRGOOD1, (2), "AUXPWRGOOD1"), 1485 FUNC(CANBUS, (2), "CANBUS"), 1486 FUNC(ESPI0, (1), "ESPI0"), 1487 FUNC(ESPI1, (1), "ESPI1"), 1488 FUNC(FSI0, (2), "FSI0"), 1489 FUNC(FSI1, (2), "FSI1"), 1490 FUNC(FSI2, (2), "FSI2"), 1491 FUNC(FSI3, (2), "FSI3"), 1492 FUNC(FWQSPI, (1), "FWQSPI"), 1493 FUNC(FWSPIABR, (1), "FWSPIABR"), 1494 FUNC(FWWPN, (1), "FWWPN"), 1495 FUNC(HBLED, (2), "HBLED"), 1496 FUNC(I2C0, (1, 2, 4), "I2C0", "LTPI_PS_I2C0", "DI2C0"), 1497 FUNC(I2C1, (1, 2, 4), "I2C1", "LTPI_PS_I2C1", "DI2C1"), 1498 FUNC(I2C10, (1, 2), "I2C10", "DI2C10"), 1499 FUNC(I2C11, (1, 2), "I2C11", "DI2C11"), 1500 FUNC(I2C12, (4, 2), "I2C12", "DI2C12"), 1501 FUNC(I2C13, (4, 2), "I2C13", "DI2C13"), 1502 FUNC(I2C14, (4, 2), "I2C14", "DI2C14"), 1503 FUNC(I2C15, (2, 2), "I2C15", "DI2C15"), 1504 FUNC(I2C2, (1, 2, 4), "I2C2", "LTPI_PS_I2C2", "DI2C2"), 1505 FUNC(I2C3, (1, 2, 4), "I2C3", "LTPI_PS_I2C3", "DI2C3"), 1506 FUNC(I2C4, (1), "I2C4"), 1507 FUNC(I2C5, (1), "I2C5"), 1508 FUNC(I2C6, (1), "I2C6"), 1509 FUNC(I2C7, (1), "I2C7"), 1510 FUNC(I2C8, (1, 2), "I2C8", "DI2C8"), 1511 FUNC(I2C9, (1, 2), "I2C9", "DI2C9"), 1512 FUNC(I2CF0, (5), "I2CF0"), 1513 FUNC(I2CF1, (5), "I2CF1"), 1514 FUNC(I2CF2, (5), "I2CF2"), 1515 FUNC(I3C0, (1), "HVI3C0"), 1516 FUNC(I3C1, (1), "HVI3C1"), 1517 FUNC(I3C10, (1), "I3C10"), 1518 FUNC(I3C11, (1), "I3C11"), 1519 FUNC(I3C12, (1), "HVI3C12"), 1520 FUNC(I3C13, (1), "HVI3C13"), 1521 FUNC(I3C14, (1), "HVI3C14"), 1522 FUNC(I3C15, (1), "HVI3C15"), 1523 FUNC(I3C2, (1), "HVI3C2"), 1524 FUNC(I3C3, (1), "HVI3C3"), 1525 FUNC(I3C4, (1), "I3C4"), 1526 FUNC(I3C5, (1), "I3C5"), 1527 FUNC(I3C6, (1), "I3C6"), 1528 FUNC(I3C7, (1), "I3C7"), 1529 FUNC(I3C8, (1), "I3C8"), 1530 FUNC(I3C9, (1), "I3C9"), 1531 FUNC(JTAGM1, (1), "JTAGM1"), 1532 FUNC(LPC0, (2), "LPC0"), 1533 FUNC(LPC1, (2), "LPC1"), 1534 FUNC(LTPI, (2), "LTPI"), 1535 FUNC(MACLINK0, (4), "MACLINK0"), 1536 FUNC(MACLINK1, (3), "MACLINK1"), 1537 FUNC(MACLINK2, (4), "MACLINK2"), 1538 FUNC(MDIO0, (1), "MDIO0"), 1539 FUNC(MDIO1, (1), "MDIO1"), 1540 FUNC(MDIO2, (1), "MDIO2"), 1541 FUNC(NCTS0, (1), "NCTS0"), 1542 FUNC(NCTS1, (1), "NCTS1"), 1543 FUNC(NCTS5, (4), "NCTS5"), 1544 FUNC(NCTS6, (4), "NCTS6"), 1545 FUNC(NDCD0, (1), "NDCD0"), 1546 FUNC(NDCD1, (1), "NDCD1"), 1547 FUNC(NDCD5, (4), "NDCD5"), 1548 FUNC(NDCD6, (4), "NDCD6"), 1549 FUNC(NDSR0, (1), "NDSR0"), 1550 FUNC(NDSR1, (1), "NDSR1"), 1551 FUNC(NDSR5, (4), "NDSR5"), 1552 FUNC(NDSR6, (4), "NDSR6"), 1553 FUNC(NDTR0, (1), "NDTR0"), 1554 FUNC(NDTR1, (1), "NDTR1"), 1555 FUNC(NDTR5, (4), "NDTR5"), 1556 FUNC(NDTR6, (4), "NDTR6"), 1557 FUNC(NRI0, (1), "NRI0"), 1558 FUNC(NRI1, (1), "NRI1"), 1559 FUNC(NRI5, (4), "NRI5"), 1560 FUNC(NRI6, (4), "NRI6"), 1561 FUNC(NRTS0, (1), "NRTS0"), 1562 FUNC(NRTS1, (1), "NRTS1"), 1563 FUNC(NRTS5, (4), "NRTS5"), 1564 FUNC(NRTS6, (4), "NRTS6"), 1565 FUNC(OSCCLK, (3), "OSCCLK"), 1566 FUNC(PCIERC, (2), "PE2SGRSTN"), 1567 FUNC(PWM0, (1), "PWM0"), 1568 FUNC(PWM1, (1), "PWM1"), 1569 FUNC(PWM10, (3), "PWM10"), 1570 FUNC(PWM11, (3), "PWM11"), 1571 FUNC(PWM12, (3), "PWM12"), 1572 FUNC(PWM13, (3), "PWM13"), 1573 FUNC(PWM14, (3), "PWM14"), 1574 FUNC(PWM15, (3), "PWM15"), 1575 FUNC(PWM2, (1), "PWM2"), 1576 FUNC(PWM3, (1), "PWM3"), 1577 FUNC(PWM4, (1), "PWM4"), 1578 FUNC(PWM5, (1), "PWM5"), 1579 FUNC(PWM6, (1), "PWM6"), 1580 FUNC(PWM7, (1), "PWM7"), 1581 FUNC(PWM8, (3), "PWM8"), 1582 FUNC(PWM9, (3), "PWM9"), 1583 FUNC(QSPI0, (1), "QSPI0"), 1584 FUNC(QSPI1, (1), "QSPI1"), 1585 FUNC(QSPI2, (1), "QSPI2"), 1586 FUNC(RGMII0, (1), "RGMII0"), 1587 FUNC(RGMII1, (1), "RGMII1"), 1588 FUNC(RMII0, (2), "RMII0"), 1589 FUNC(RMII0RCLKO, (2), "RMII0RCLKO"), 1590 FUNC(RMII1, (2), "RMII1"), 1591 FUNC(RMII1RCLKO, (2), "RMII1RCLKO"), 1592 FUNC(SALT0, (2), "SALT0"), 1593 FUNC(SALT1, (2), "SALT1"), 1594 FUNC(SALT10, (2), "SALT10"), 1595 FUNC(SALT11, (2), "SALT11"), 1596 FUNC(SALT12, (2), "SALT12"), 1597 FUNC(SALT13, (2), "SALT13"), 1598 FUNC(SALT14, (2), "SALT14"), 1599 FUNC(SALT15, (2), "SALT15"), 1600 FUNC(SALT2, (2), "SALT2"), 1601 FUNC(SALT3, (2), "SALT3"), 1602 FUNC(SALT4, (2), "SALT4"), 1603 FUNC(SALT5, (2), "SALT5"), 1604 FUNC(SALT6, (2), "SALT6"), 1605 FUNC(SALT7, (2), "SALT7"), 1606 FUNC(SALT8, (2), "SALT8"), 1607 FUNC(SALT9, (2), "SALT9"), 1608 FUNC(SD, (3), "SD"), 1609 FUNC(SGMII, (1), "SGMII"), 1610 FUNC(SGPM0, (1, 4), "SGPM0", "DSGPM0"), 1611 FUNC(SGPM1, (1), "SGPM1"), 1612 FUNC(SGPS, (5), "SGPS"), 1613 FUNC(SIOONCTRLN0, (2), "SIOONCTRLN0"), 1614 FUNC(SIOONCTRLN1, (2), "SIOONCTRLN1"), 1615 FUNC(SIOPBIN0, (2), "SIOPBIN0"), 1616 FUNC(SIOPBIN1, (2), "SIOPBIN1"), 1617 FUNC(SIOPBON0, (2), "SIOPBON0"), 1618 FUNC(SIOPBON1, (2), "SIOPBON1"), 1619 FUNC(SIOPWREQN0, (2), "SIOPWREQN0"), 1620 FUNC(SIOPWREQN1, (2), "SIOPWREQN1"), 1621 FUNC(SIOPWRGD1, (2), "SIOPWRGD1"), 1622 FUNC(SIOS3N0, (2), "SIOS3N0"), 1623 FUNC(SIOS3N1, (2), "SIOS3N1"), 1624 FUNC(SIOS5N0, (2), "SIOS5N0"), 1625 FUNC(SIOS5N1, (2), "SIOS5N1"), 1626 FUNC(SIOSCIN0, (2), "SIOSCIN0"), 1627 FUNC(SIOSCIN1, (2), "SIOSCIN1"), 1628 FUNC(SMON0, (2), "SMON0"), 1629 FUNC(SMON1, (4), "SMON1"), 1630 FUNC(SPI0, (1), "SPI0"), 1631 FUNC(SPI0ABR, (1), "SPI0ABR"), 1632 FUNC(SPI0CS1, (1), "SPI0CS1"), 1633 FUNC(SPI0WPN, (1), "SPI0WPN"), 1634 FUNC(SPI1, (1), "SPI1"), 1635 FUNC(SPI1ABR, (1), "SPI1ABR"), 1636 FUNC(SPI1CS1, (1), "SPI1CS1"), 1637 FUNC(SPI1WPN, (1), "SPI1WPN"), 1638 FUNC(SPI2, (1), "SPI2"), 1639 FUNC(SPI2CS1, (1), "SPI2CS1"), 1640 FUNC(TACH0, (1), "TACH0"), 1641 FUNC(TACH1, (1), "TACH1"), 1642 FUNC(TACH10, (1), "TACH10"), 1643 FUNC(TACH11, (1), "TACH11"), 1644 FUNC(TACH12, (1), "TACH12"), 1645 FUNC(TACH13, (1), "TACH13"), 1646 FUNC(TACH14, (1), "TACH14"), 1647 FUNC(TACH15, (1), "TACH15"), 1648 FUNC(TACH2, (1), "TACH2"), 1649 FUNC(TACH3, (1), "TACH3"), 1650 FUNC(TACH4, (1), "TACH4"), 1651 FUNC(TACH5, (1), "TACH5"), 1652 FUNC(TACH6, (1), "TACH6"), 1653 FUNC(TACH7, (1), "TACH7"), 1654 FUNC(TACH8, (1), "TACH8"), 1655 FUNC(TACH9, (1), "TACH9"), 1656 FUNC(THRU0, (2), "THRU0"), 1657 FUNC(THRU1, (2), "THRU1"), 1658 FUNC(THRU2, (4), "THRU2"), 1659 FUNC(THRU3, (4), "THRU3"), 1660 FUNC(UART0, (1), "UART0"), 1661 FUNC(UART1, (1), "UART1"), 1662 FUNC(UART10, (3), "UART10"), 1663 FUNC(UART11, (3), "UART11"), 1664 FUNC(UART2, (1), "UART2"), 1665 FUNC(UART3, (1), "UART3"), 1666 FUNC(UART5, (4), "UART5"), 1667 FUNC(UART6, (4), "UART6"), 1668 FUNC(UART7, (1), "UART7"), 1669 FUNC(UART8, (3), "UART8"), 1670 FUNC(UART9, (3), "UART9"), 1671 FUNC(USB2C, (0, 1, 2, 3), "USB2CUD", "USB2CD", "USB2CH", "USB2CU"), 1672 FUNC(USB2D, (1, 2), "USB2DD", "USB2DH"), 1673 FUNC(USBUART, (2), "USBUART"), 1674 FUNC(VGA, (1), "VGA"), 1675 FUNC(VPI, (5), "VPI"), 1676 FUNC(WDTRST0N, (2), "WDTRST0N"), 1677 FUNC(WDTRST1N, (2), "WDTRST1N"), 1678 FUNC(WDTRST2N, (2), "WDTRST2N"), 1679 FUNC(WDTRST3N, (2), "WDTRST3N"), 1680 FUNC(WDTRST4N, (2), "WDTRST4N"), 1681 FUNC(WDTRST5N, (2), "WDTRST5N"), 1682 FUNC(WDTRST6N, (2), "WDTRST6N"), 1683 FUNC(WDTRST7N, (2), "WDTRST7N"), 1684 }; 1685 1686 static int aspeed_g7_soc1_pinctrl_probe(struct platform_device *pdev) 1687 { 1688 struct aspeed_g7_soc1_pinctrl *pctl; 1689 struct device *dev = &pdev->dev; 1690 int i, ret; 1691 1692 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1693 if (!pctl) 1694 return -ENOMEM; 1695 1696 pctl->dev = dev; 1697 pctl->regmap = syscon_node_to_regmap(dev->parent->of_node); 1698 if (IS_ERR(pctl->regmap)) { 1699 dev_err(dev, "Failed to get regmap from parent\n"); 1700 return PTR_ERR(pctl->regmap); 1701 } 1702 1703 ret = devm_pinctrl_register_and_init(dev, &aspeed_g7_soc1_desc, pctl, 1704 &pctl->pctl); 1705 if (ret) { 1706 dev_err(dev, "Failed to register pinctrl\n"); 1707 return ret; 1708 } 1709 1710 for (i = 0; i < ARRAY_SIZE(aspeed_g7_soc1_groups); i++) { 1711 const struct pingroup *grp = &aspeed_g7_soc1_groups[i]; 1712 1713 ret = pinctrl_generic_add_group(pctl->pctl, grp->name, 1714 (const unsigned int *)grp->pins, 1715 grp->npins, pctl); 1716 if (ret < 0) { 1717 dev_err(dev, "Failed to add group %s\n", grp->name); 1718 return ret; 1719 } 1720 } 1721 1722 for (i = 0; i < ARRAY_SIZE(aspeed_g7_soc1_functions); i++) { 1723 const struct aspeed_g7_soc1_function *func = &aspeed_g7_soc1_functions[i]; 1724 1725 ret = pinmux_generic_add_function(pctl->pctl, func->pinfunction.name, 1726 func->pinfunction.groups, 1727 func->pinfunction.ngroups, (void *)func); 1728 if (ret < 0) { 1729 dev_err(dev, "Failed to add function %s\n", func->pinfunction.name); 1730 return ret; 1731 } 1732 } 1733 1734 return pinctrl_enable(pctl->pctl); 1735 } 1736 1737 static const struct of_device_id aspeed_g7_soc1_pinctrl_match[] = { 1738 { .compatible = "aspeed,ast2700-soc1-pinctrl" }, 1739 {} 1740 }; 1741 MODULE_DEVICE_TABLE(of, aspeed_g7_soc1_pinctrl_match); 1742 1743 static struct platform_driver aspeed_g7_soc1_pinctrl_driver = { 1744 .probe = aspeed_g7_soc1_pinctrl_probe, 1745 .driver = { 1746 .name = "aspeed-g7-soc1-pinctrl", 1747 .of_match_table = aspeed_g7_soc1_pinctrl_match, 1748 .suppress_bind_attrs = true, 1749 }, 1750 }; 1751 1752 static int __init aspeed_g7_soc1_pinctrl_init(void) 1753 { 1754 return platform_driver_register(&aspeed_g7_soc1_pinctrl_driver); 1755 } 1756 arch_initcall(aspeed_g7_soc1_pinctrl_init); 1757