1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/bitops.h> 4 #include <linux/bits.h> 5 #include <linux/mfd/syscon.h> 6 #include <linux/of.h> 7 #include <linux/pinctrl/pinconf-generic.h> 8 #include <linux/pinctrl/pinconf.h> 9 #include <linux/pinctrl/pinctrl.h> 10 #include <linux/pinctrl/pinmux.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 14 #include "pinctrl-aspeed.h" 15 #include "pinmux-aspeed.h" 16 #include "../pinctrl-utils.h" 17 18 #define SCU200 0x200 /* System Reset Control #1 */ 19 20 #define SCU010 0x010 /* Hardware Strap Register */ 21 #define SCU400 0x400 /* Multi-function Pin Control #1 */ 22 #define SCU404 0x404 /* Multi-function Pin Control #2 */ 23 #define SCU408 0x408 /* Multi-function Pin Control #3 */ 24 #define SCU40C 0x40C /* Multi-function Pin Control #3 */ 25 #define SCU410 0x410 /* USB Multi-function Control Register */ 26 #define SCU414 0x414 /* VGA Function Control Register */ 27 28 #define SCU480 0x480 /* GPIO18A0 IO Control Register */ 29 #define SCU484 0x484 /* GPIO18A1 IO Control Register */ 30 #define SCU488 0x488 /* GPIO18A2 IO Control Register */ 31 #define SCU48C 0x48c /* GPIO18A3 IO Control Register */ 32 #define SCU490 0x490 /* GPIO18A4 IO Control Register */ 33 #define SCU494 0x494 /* GPIO18A5 IO Control Register */ 34 #define SCU498 0x498 /* GPIO18A6 IO Control Register */ 35 #define SCU49C 0x49c /* GPIO18A7 IO Control Register */ 36 #define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */ 37 #define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */ 38 #define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */ 39 #define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */ 40 41 enum { 42 AC14, 43 AE15, 44 AD14, 45 AE14, 46 AF14, 47 AB13, 48 AB14, 49 AF15, 50 AF13, 51 AC13, 52 AD13, 53 AE13, 54 JTAG_PORT, 55 PCIERC0_PERST, 56 PCIERC1_PERST, 57 PORTA_MODE, 58 PORTA_U2, 59 PORTB_MODE, 60 PORTB_U2, 61 PORTA_U2_PHY, 62 PORTB_U2_PHY, 63 PORTA_U3, 64 PORTB_U3, 65 PORTA_U3_PHY, 66 PORTB_U3_PHY, 67 }; 68 69 SIG_EXPR_LIST_DECL_SEMG(AC14, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 0)); 70 SIG_EXPR_LIST_DECL_SEMG(AC14, VB1CS, VB1, VB, SIG_DESC_SET(SCU404, 0)); 71 PIN_DECL_2(AC14, GPIO18A0, EMMCCLK, VB1CS); 72 73 SIG_EXPR_LIST_DECL_SEMG(AE15, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 1)); 74 SIG_EXPR_LIST_DECL_SEMG(AE15, VB1CK, VB1, VB, SIG_DESC_SET(SCU404, 1)); 75 PIN_DECL_2(AE15, GPIO18A1, EMMCCMD, VB1CK); 76 77 SIG_EXPR_LIST_DECL_SEMG(AD14, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 2)); 78 SIG_EXPR_LIST_DECL_SEMG(AD14, VB1MOSI, VB1, VB, SIG_DESC_SET(SCU404, 2)); 79 PIN_DECL_2(AD14, GPIO18A2, EMMCDAT0, VB1MOSI); 80 81 SIG_EXPR_LIST_DECL_SEMG(AE14, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 3)); 82 SIG_EXPR_LIST_DECL_SEMG(AE14, VB1MISO, VB1, VB, SIG_DESC_SET(SCU404, 3)); 83 PIN_DECL_2(AE14, GPIO18A3, EMMCDAT1, VB1MISO); 84 85 SIG_EXPR_LIST_DECL_SEMG(AF14, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 4)); 86 PIN_DECL_1(AF14, GPIO18A4, EMMCDAT2); 87 88 SIG_EXPR_LIST_DECL_SEMG(AB13, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 5)); 89 PIN_DECL_1(AB13, GPIO18A5, EMMCDAT3); 90 91 SIG_EXPR_LIST_DECL_SEMG(AB14, EMMCCDN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 6)); 92 SIG_EXPR_LIST_DECL_SEMG(AB14, VB0CS, VB0, VB, SIG_DESC_SET(SCU010, 17)); 93 PIN_DECL_2(AB14, GPIO18A6, EMMCCDN, VB0CS); 94 95 SIG_EXPR_LIST_DECL_SEMG(AF15, EMMCWPN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 7)); 96 SIG_EXPR_LIST_DECL_SEMG(AF15, VB0CK, VB0, VB, SIG_DESC_SET(SCU010, 17)); 97 PIN_DECL_2(AF15, GPIO18A7, EMMCWPN, VB0CK); 98 99 SIG_EXPR_LIST_DECL_SESG(AF13, TSPRSTN, TSPRSTN, SIG_DESC_SET(SCU010, 9)); 100 SIG_EXPR_LIST_DECL_SEMG(AF13, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 8)); 101 SIG_EXPR_LIST_DECL_SEMG(AF13, VB0MOSI, VB0, VB, SIG_DESC_SET(SCU010, 17)); 102 PIN_DECL_3(AF13, GPIO18B0, TSPRSTN, EMMCDAT4, VB0MOSI); 103 104 SIG_EXPR_LIST_DECL_SESG(AC13, UFSCLKI, UFSCLKI, SIG_DESC_SET(SCU010, 19)); 105 SIG_EXPR_LIST_DECL_SEMG(AC13, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 9)); 106 SIG_EXPR_LIST_DECL_SEMG(AC13, VB0MISO, VB0, VB, SIG_DESC_SET(SCU010, 17)); 107 PIN_DECL_3(AC13, GPIO18B1, UFSCLKI, EMMCDAT5, VB0MISO); 108 109 SIG_EXPR_LIST_DECL_SEMG(AD13, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 10)); 110 SIG_EXPR_LIST_DECL_SESG(AD13, DDCCLK, VGADDC, SIG_DESC_SET(SCU404, 10)); 111 PIN_DECL_2(AD13, GPIO18B2, EMMCDAT6, DDCCLK); 112 113 SIG_EXPR_LIST_DECL_SEMG(AE13, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 11)); 114 SIG_EXPR_LIST_DECL_SESG(AE13, DDCDAT, VGADDC, SIG_DESC_SET(SCU404, 11)); 115 PIN_DECL_2(AE13, GPIO18B3, EMMCDAT7, DDCDAT); 116 117 GROUP_DECL(EMMCG1, AC14, AE15, AD14); 118 GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13); 119 GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, AE13); 120 GROUP_DECL(EMMCWPN, AF15); 121 GROUP_DECL(EMMCCDN, AB14); 122 FUNC_DECL_(EMMC, "EMMCG1", "EMMCG4", "EMMCG8", "EMMCWPN", "EMMCCDN"); 123 124 GROUP_DECL(VB1, AC14, AE15, AD14, AE14); 125 GROUP_DECL(VB0, AF15, AB14, AF13, AC13); 126 FUNC_DECL_2(VB, VB1, VB0); 127 128 FUNC_GROUP_DECL(TSPRSTN, AF13); 129 130 FUNC_GROUP_DECL(UFSCLKI, AC13); 131 132 FUNC_GROUP_DECL(VGADDC, AD13, AE13); 133 134 /* JTAG Port Selection */ 135 #define JTAG_PORT_PSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x0, 0 } 136 #define JTAG_PORT_SSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x41, 0 } 137 #define JTAG_PORT_TSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x42, 0 } 138 #define JTAG_PORT_DDR_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x43, 0 } 139 #define JTAG_PORT_USB3A_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x44, 0 } 140 #define JTAG_PORT_USB3B_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x45, 0 } 141 #define JTAG_PORT_PCIEA_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x46, 0 } 142 #define JTAG_PORT_PCIEB_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x47, 0 } 143 #define JTAG_PORT_JTAGM0_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x8, 0 } 144 145 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPSP, JTAG0, JTAGPSP, JTAG_PORT_PSP_DESC); 146 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGSSP, JTAG0, JTAGSSP, JTAG_PORT_SSP_DESC); 147 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGTSP, JTAG0, JTAGTSP, JTAG_PORT_TSP_DESC); 148 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGDDR, JTAG0, JTAGDDR, JTAG_PORT_DDR_DESC); 149 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3A, JTAG0, JTAGUSB3A, JTAG_PORT_USB3A_DESC); 150 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3B, JTAG0, JTAGUSB3B, JTAG_PORT_USB3B_DESC); 151 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEA, JTAG0, JTAGPCIEA, JTAG_PORT_PCIEA_DESC); 152 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEB, JTAG0, JTAGPCIEB, JTAG_PORT_PCIEB_DESC); 153 SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGM0, JTAG0, JTAGM0, JTAG_PORT_JTAGM0_DESC); 154 PIN_DECL_(JTAG_PORT, SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGSSP), 155 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGTSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGDDR), 156 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3A), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3B), 157 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEA), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEB), 158 SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGM0)); 159 160 GROUP_DECL(JTAG0, JTAG_PORT); 161 162 FUNC_DECL_1(JTAGPSP, JTAG0); 163 FUNC_DECL_1(JTAGSSP, JTAG0); 164 FUNC_DECL_1(JTAGTSP, JTAG0); 165 FUNC_DECL_1(JTAGDDR, JTAG0); 166 FUNC_DECL_1(JTAGUSB3A, JTAG0); 167 FUNC_DECL_1(JTAGUSB3B, JTAG0); 168 FUNC_DECL_1(JTAGPCIEA, JTAG0); 169 FUNC_DECL_1(JTAGPCIEB, JTAG0); 170 FUNC_DECL_1(JTAGM0, JTAG0); 171 172 /* PCIe Reset Control */ 173 SIG_EXPR_LIST_DECL_SESG(PCIERC0_PERST, PCIERC0PERST, PCIERC0PERST, SIG_DESC_SET(SCU200, 21)); 174 PIN_DECL_(PCIERC0_PERST, SIG_EXPR_LIST_PTR(PCIERC0_PERST, PCIERC0PERST)); 175 FUNC_GROUP_DECL(PCIERC0PERST, PCIERC0_PERST); 176 177 SIG_EXPR_LIST_DECL_SESG(PCIERC1_PERST, PCIERC1PERST, PCIERC1PERST, SIG_DESC_SET(SCU200, 19)); 178 PIN_DECL_(PCIERC1_PERST, SIG_EXPR_LIST_PTR(PCIERC1_PERST, PCIERC1PERST)); 179 FUNC_GROUP_DECL(PCIERC1PERST, PCIERC1_PERST); 180 181 #define PORTA_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 0, 0 } 182 #define PORTA_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 1, 0 } 183 #define PORTA_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 2, 0 } 184 #define PORTA_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 3, 0 } 185 186 SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHPD0, USB2AH, USB2AHPD0, PORTA_MODE_HPD0_DESC); 187 SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AH, USB2AHAP, USB2AH, PORTA_MODE_H_DESC); 188 SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHP, USB2AHAP, USB2AHP, PORTA_MODE_HP_DESC); 189 SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AD0, USB2AHAP, USB2AD0, PORTA_MODE_D0_DESC); 190 PIN_DECL_(PORTA_MODE, SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHPD0), 191 SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AH), SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHP), 192 SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AD0)); 193 194 #define PORTA_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 0, 0 } 195 #define PORTA_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 1, 0 } 196 #define PORTA_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 2, 0 } 197 #define PORTA_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 3, 0 } 198 199 SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHD1, USB2A, USB2AXHD1, PORTA_U2_XHD_DESC, 200 SIG_DESC_SET(SCU410, 9)); 201 SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHPD1, USB2A, USB2AXHPD1, PORTA_U2_XHD_DESC, 202 SIG_DESC_CLEAR(SCU410, 9)); 203 SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH, USB2AAP, USB2AXH, PORTA_U2_XH_DESC, 204 SIG_DESC_SET(SCU410, 9)); 205 SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP, USB2AAP, USB2AXHP, PORTA_U2_XH_DESC, 206 SIG_DESC_CLEAR(SCU410, 9)); 207 SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH2B, USB2ABP, USB2AXH2B, PORTA_U2_XH2E_DESC, 208 SIG_DESC_SET(SCU410, 9)); 209 SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP2B, USB2ABP, USB2AXHP2B, PORTA_U2_XH2E_DESC, 210 SIG_DESC_CLEAR(SCU410, 9)); 211 SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AD1, USB2ADAP, USB2AD1, PORTA_U2_D1_DESC); 212 PIN_DECL_(PORTA_U2, SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHD1), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHPD1), 213 SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP), 214 SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH2B), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP2B), 215 SIG_EXPR_LIST_PTR(PORTA_U2, USB2AD1)); 216 217 #define PORTB_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 0, 0 } 218 #define PORTB_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 1, 0 } 219 #define PORTB_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 2, 0 } 220 #define PORTB_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 3, 0 } 221 222 SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHPD0, USB2BH, USB2BHPD0, PORTB_MODE_HPD0_DESC); 223 SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BH, USB2BHBP, USB2BH, PORTB_MODE_H_DESC); 224 SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHP, USB2BHBP, USB2BHP, PORTB_MODE_HP_DESC); 225 SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BD0, USB2BHBP, USB2BD0, PORTB_MODE_D0_DESC); 226 PIN_DECL_(PORTB_MODE, SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHPD0), 227 SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BH), SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHP), 228 SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BD0)); 229 230 #define PORTB_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 0, 0 } 231 #define PORTB_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 1, 0 } 232 #define PORTB_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 2, 0 } 233 #define PORTB_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 3, 0 } 234 235 SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHD1, USB2B, USB2BXHD1, PORTB_U2_XHD_DESC, 236 SIG_DESC_SET(SCU410, 10)); 237 SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHPD1, USB2B, USB2BXHPD1, PORTB_U2_XHD_DESC, 238 SIG_DESC_CLEAR(SCU410, 10)); 239 SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH, USB2BBP, USB2BXH, PORTB_U2_XH_DESC, 240 SIG_DESC_SET(SCU410, 10)); 241 SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP, USB2BBP, USB2BXHP, PORTB_U2_XH_DESC, 242 SIG_DESC_CLEAR(SCU410, 10)); 243 SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH2A, USB2BAP, USB2BXH2A, PORTB_U2_XH2E_DESC, 244 SIG_DESC_SET(SCU410, 10)); 245 SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP2A, USB2BAP, USB2BXHP2A, PORTB_U2_XH2E_DESC, 246 SIG_DESC_CLEAR(SCU410, 10)); 247 SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BD1, USB2BDBP, USB2BD1, PORTB_U2_D1_DESC); 248 PIN_DECL_(PORTB_U2, SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHD1), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHPD1), 249 SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP), 250 SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH2A), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP2A), 251 SIG_EXPR_LIST_PTR(PORTB_U2, USB2BD1)); 252 /* 253 * USB2 virtual PHY pins. 254 * 255 * PORTA_U2_PHY and PORTB_U2_PHY are logical endpoints, not package pins. 256 * They alias existing USB2 expressions so pin groups can model direct and 257 * cross-coupled routing for host and mode paths. 258 * 259 * - USB2AAP/USB2ADAP/USB2AHAP: use PORTA_U2_PHY 260 * - USB2ABP : use PORTB_U2_PHY 261 * - USB2BBP/USB2BDBP/USB2BHBP: use PORTB_U2_PHY 262 * - USB2BAP : use PORTA_U2_PHY 263 * 264 * They do not have any registers to configure this behaviour; the goal is 265 * simply for the driver to prevent conflicting selections. For example, 266 * selecting group USB2ABP and USB2BBP at the same time should not be 267 * allowed. 268 */ 269 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXH, USB2AAP); 270 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXHP, USB2AAP); 271 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXH2A, USB2BAP); 272 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXHP2A, USB2BAP); 273 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD1, USB2ADAP); 274 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AH, USB2AHAP); 275 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AHP, USB2AHAP); 276 SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD0, USB2AHAP); 277 PIN_DECL_(PORTA_U2_PHY, SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXH), 278 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXHP), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXH2A), 279 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXHP2A), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD1), 280 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AH), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AHP), 281 SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD0)); 282 283 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXH2B, USB2ABP); 284 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXHP2B, USB2ABP); 285 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXH, USB2BBP); 286 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXHP, USB2BBP); 287 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD1, USB2BDBP); 288 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BH, USB2BHBP); 289 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BHP, USB2BHBP); 290 SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD0, USB2BHBP); 291 PIN_DECL_(PORTB_U2_PHY, SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXH2B), 292 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXH), 293 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXHP), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD1), 294 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BH), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BHP), 295 SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD0)); 296 297 GROUP_DECL(USB2A, PORTA_U2); 298 GROUP_DECL(USB2AAP, PORTA_U2, PORTA_U2_PHY); 299 GROUP_DECL(USB2ABP, PORTA_U2, PORTB_U2_PHY); 300 GROUP_DECL(USB2ADAP, PORTA_U2, PORTA_U2_PHY); 301 GROUP_DECL(USB2AH, PORTA_MODE); 302 GROUP_DECL(USB2AHAP, PORTA_MODE, PORTA_U2_PHY); 303 304 FUNC_DECL_1(USB2AXHD1, USB2A); 305 FUNC_DECL_1(USB2AXHPD1, USB2A); 306 FUNC_DECL_1(USB2AXH, USB2AAP); 307 FUNC_DECL_1(USB2AXHP, USB2AAP); 308 FUNC_DECL_1(USB2AXH2B, USB2ABP); 309 FUNC_DECL_1(USB2AXHP2B, USB2ABP); 310 FUNC_DECL_1(USB2AD1, USB2ADAP); 311 FUNC_DECL_1(USB2AHPD0, USB2AH); 312 FUNC_DECL_1(USB2AH, USB2AHAP); 313 FUNC_DECL_1(USB2AHP, USB2AHAP); 314 FUNC_DECL_1(USB2AD0, USB2AHAP); 315 316 GROUP_DECL(USB2B, PORTB_U2); 317 GROUP_DECL(USB2BBP, PORTB_U2, PORTB_U2_PHY); 318 GROUP_DECL(USB2BAP, PORTB_U2, PORTA_U2_PHY); 319 GROUP_DECL(USB2BDBP, PORTB_U2, PORTB_U2_PHY); 320 GROUP_DECL(USB2BH, PORTB_MODE); 321 GROUP_DECL(USB2BHBP, PORTB_MODE, PORTB_U2_PHY); 322 323 FUNC_DECL_1(USB2BXHD1, USB2B); 324 FUNC_DECL_1(USB2BXHPD1, USB2B); 325 FUNC_DECL_1(USB2BXH, USB2BBP); 326 FUNC_DECL_1(USB2BXHP, USB2BBP); 327 FUNC_DECL_1(USB2BXH2A, USB2BAP); 328 FUNC_DECL_1(USB2BXHP2A, USB2BAP); 329 FUNC_DECL_1(USB2BD1, USB2BDBP); 330 FUNC_DECL_1(USB2BHPD0, USB2BH); 331 FUNC_DECL_1(USB2BH, USB2BHBP); 332 FUNC_DECL_1(USB2BHP, USB2BHBP); 333 FUNC_DECL_1(USB2BD0, USB2BHBP); 334 335 #define PORTA_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 0, 0 } 336 #define PORTA_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 2, 0 } 337 #define PORTA_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 3, 0 } 338 339 SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHD, USB3A, USB3AXHD, PORTA_U3_XHD_DESC, 340 SIG_DESC_SET(SCU410, 9)); 341 SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHPD, USB3A, USB3AXHPD, PORTA_U3_XHD_DESC, 342 SIG_DESC_CLEAR(SCU410, 9)); 343 SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH, USB3AAP, USB3AXH, PORTA_U3_XH_DESC, 344 SIG_DESC_SET(SCU410, 9)); 345 SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP, USB3AAP, USB3AXHP, PORTA_U3_XH_DESC, 346 SIG_DESC_CLEAR(SCU410, 9)); 347 SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH2B, USB3ABP, USB3AXH2B, PORTA_U3_XH2E_DESC, 348 SIG_DESC_SET(SCU410, 9)); 349 SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP2B, USB3ABP, USB3AXHP2B, PORTA_U3_XH2E_DESC, 350 SIG_DESC_CLEAR(SCU410, 9)); 351 PIN_DECL_(PORTA_U3, SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHD), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHPD), 352 SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP), 353 SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH2B), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP2B)); 354 355 #define PORTB_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 0, 0 } 356 #define PORTB_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 2, 0 } 357 #define PORTB_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 3, 0 } 358 359 SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHD, USB3B, USB3BXHD, PORTB_U3_XHD_DESC, 360 SIG_DESC_SET(SCU410, 10)); 361 SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHPD, USB3B, USB3BXHPD, PORTB_U3_XHD_DESC, 362 SIG_DESC_CLEAR(SCU410, 10)); 363 SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH, USB3BBP, USB3BXH, PORTB_U3_XH_DESC, 364 SIG_DESC_SET(SCU410, 10)); 365 SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP, USB3BBP, USB3BXHP, PORTB_U3_XH_DESC, 366 SIG_DESC_CLEAR(SCU410, 10)); 367 SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH2A, USB3BAP, USB3BXH2A, PORTB_U3_XH2E_DESC, 368 SIG_DESC_SET(SCU410, 10)); 369 SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP2A, USB3BAP, USB3BXHP2A, PORTB_U3_XH2E_DESC, 370 SIG_DESC_CLEAR(SCU410, 10)); 371 PIN_DECL_(PORTB_U3, SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHD), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHPD), 372 SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP), 373 SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH2A), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP2A)); 374 375 /* 376 * USB3 virtual PHY pins. 377 * 378 * PORTA_U3_PHY and PORTB_U3_PHY are logical endpoints, not package pins. 379 * They alias existing USB3 expressions so pin groups can model both direct and 380 * cross-coupled routing to PHY A/B. 381 * 382 * - USB3AAP: PORTA_U3 + PORTA_U3_PHY (A -> PHY A) 383 * - USB3ABP: PORTA_U3 + PORTB_U3_PHY (A -> PHY B) 384 * - USB3BBP: PORTB_U3 + PORTB_U3_PHY (B -> PHY B) 385 * - USB3BAP: PORTB_U3 + PORTA_U3_PHY (B -> PHY A) 386 * 387 * They do not have any registers to configure this behavior; the goal is 388 * simply for the driver to prevent conflicting selections. For example, 389 * selecting group USB3ABP and USB3BBP at the same time should not be 390 * allowed. 391 */ 392 SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXH, USB3AAP); 393 SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXHP, USB3AAP); 394 SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXH2A, USB3BAP); 395 SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXHP2A, USB3BAP); 396 PIN_DECL_(PORTA_U3_PHY, SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXH), 397 SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXHP), SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXH2A), 398 SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXHP2A)); 399 400 SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXH2B, USB3ABP); 401 SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXHP2B, USB3ABP); 402 SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXH, USB3BBP); 403 SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXHP, USB3BBP); 404 PIN_DECL_(PORTB_U3_PHY, SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXH2B), 405 SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXH), 406 SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXHP)); 407 408 /* USB3A xHCI to vHUB */ 409 GROUP_DECL(USB3A, PORTA_U3); 410 /* USB3A xHCI to USB3A PHY */ 411 GROUP_DECL(USB3AAP, PORTA_U3, PORTA_U3_PHY); 412 /* USB3A xHCI to USB3B PHY */ 413 GROUP_DECL(USB3ABP, PORTA_U3, PORTB_U3_PHY); 414 415 FUNC_DECL_1(USB3AXHD, USB3A); 416 FUNC_DECL_1(USB3AXHPD, USB3A); 417 FUNC_DECL_1(USB3AXH, USB3AAP); 418 FUNC_DECL_1(USB3AXHP, USB3AAP); 419 FUNC_DECL_1(USB3AXH2B, USB3ABP); 420 FUNC_DECL_1(USB3AXHP2B, USB3ABP); 421 422 /* USB3B xHCI to vHUB */ 423 GROUP_DECL(USB3B, PORTB_U3); 424 /* USB3B xHCI to USB3A PHY */ 425 GROUP_DECL(USB3BAP, PORTB_U3, PORTA_U3_PHY); 426 /* USB3B xHCI to USB3B PHY */ 427 GROUP_DECL(USB3BBP, PORTB_U3, PORTB_U3_PHY); 428 429 FUNC_DECL_1(USB3BXHD, USB3B); 430 FUNC_DECL_1(USB3BXHPD, USB3B); 431 FUNC_DECL_1(USB3BXH, USB3BBP); 432 FUNC_DECL_1(USB3BXHP, USB3BBP); 433 FUNC_DECL_1(USB3BXH2A, USB3BAP); 434 FUNC_DECL_1(USB3BXHP2A, USB3BAP); 435 436 static const struct pinctrl_pin_desc aspeed_g7_soc0_pins[] = { 437 ASPEED_PINCTRL_PIN(AC14), 438 ASPEED_PINCTRL_PIN(AE15), 439 ASPEED_PINCTRL_PIN(AD14), 440 ASPEED_PINCTRL_PIN(AE14), 441 ASPEED_PINCTRL_PIN(AF14), 442 ASPEED_PINCTRL_PIN(AB13), 443 ASPEED_PINCTRL_PIN(AB14), 444 ASPEED_PINCTRL_PIN(AF15), 445 ASPEED_PINCTRL_PIN(AF13), 446 ASPEED_PINCTRL_PIN(AC13), 447 ASPEED_PINCTRL_PIN(AD13), 448 ASPEED_PINCTRL_PIN(AE13), 449 ASPEED_PINCTRL_PIN(JTAG_PORT), 450 ASPEED_PINCTRL_PIN(PCIERC0_PERST), 451 ASPEED_PINCTRL_PIN(PCIERC1_PERST), 452 ASPEED_PINCTRL_PIN(PORTA_MODE), 453 ASPEED_PINCTRL_PIN(PORTA_U2), 454 ASPEED_PINCTRL_PIN(PORTA_U3), 455 ASPEED_PINCTRL_PIN(PORTA_U2_PHY), 456 ASPEED_PINCTRL_PIN(PORTA_U3_PHY), 457 ASPEED_PINCTRL_PIN(PORTB_MODE), 458 ASPEED_PINCTRL_PIN(PORTB_U2), 459 ASPEED_PINCTRL_PIN(PORTB_U3), 460 ASPEED_PINCTRL_PIN(PORTB_U2_PHY), 461 ASPEED_PINCTRL_PIN(PORTB_U3_PHY), 462 }; 463 464 static const struct aspeed_pin_group aspeed_g7_soc0_groups[] = { 465 ASPEED_PINCTRL_GROUP(EMMCCDN), 466 ASPEED_PINCTRL_GROUP(EMMCG1), 467 ASPEED_PINCTRL_GROUP(EMMCG4), 468 ASPEED_PINCTRL_GROUP(EMMCG8), 469 ASPEED_PINCTRL_GROUP(EMMCWPN), 470 ASPEED_PINCTRL_GROUP(TSPRSTN), 471 ASPEED_PINCTRL_GROUP(UFSCLKI), 472 ASPEED_PINCTRL_GROUP(VB0), 473 ASPEED_PINCTRL_GROUP(VB1), 474 ASPEED_PINCTRL_GROUP(VGADDC), 475 /* JTAG groups */ 476 ASPEED_PINCTRL_GROUP(JTAG0), 477 /* PCIE RC groups */ 478 ASPEED_PINCTRL_GROUP(PCIERC0PERST), 479 ASPEED_PINCTRL_GROUP(PCIERC1PERST), 480 /* USB3A groups */ 481 ASPEED_PINCTRL_GROUP(USB3A), 482 ASPEED_PINCTRL_GROUP(USB3AAP), 483 ASPEED_PINCTRL_GROUP(USB3ABP), 484 /* USB3B groups */ 485 ASPEED_PINCTRL_GROUP(USB3B), 486 ASPEED_PINCTRL_GROUP(USB3BAP), 487 ASPEED_PINCTRL_GROUP(USB3BBP), 488 /* USB2A groups */ 489 ASPEED_PINCTRL_GROUP(USB2A), 490 ASPEED_PINCTRL_GROUP(USB2AAP), 491 ASPEED_PINCTRL_GROUP(USB2ABP), 492 ASPEED_PINCTRL_GROUP(USB2ADAP), 493 ASPEED_PINCTRL_GROUP(USB2AH), 494 ASPEED_PINCTRL_GROUP(USB2AHAP), 495 /* USB2B groups */ 496 ASPEED_PINCTRL_GROUP(USB2B), 497 ASPEED_PINCTRL_GROUP(USB2BAP), 498 ASPEED_PINCTRL_GROUP(USB2BBP), 499 ASPEED_PINCTRL_GROUP(USB2BDBP), 500 ASPEED_PINCTRL_GROUP(USB2BH), 501 ASPEED_PINCTRL_GROUP(USB2BHBP), 502 }; 503 504 static const struct aspeed_pin_function aspeed_g7_soc0_functions[] = { 505 ASPEED_PINCTRL_FUNC(EMMC), 506 ASPEED_PINCTRL_FUNC(TSPRSTN), 507 ASPEED_PINCTRL_FUNC(UFSCLKI), 508 ASPEED_PINCTRL_FUNC(VB), 509 ASPEED_PINCTRL_FUNC(VGADDC), 510 /* JTAG functions */ 511 ASPEED_PINCTRL_FUNC(JTAGDDR), 512 ASPEED_PINCTRL_FUNC(JTAGM0), 513 ASPEED_PINCTRL_FUNC(JTAGPCIEA), 514 ASPEED_PINCTRL_FUNC(JTAGPCIEB), 515 ASPEED_PINCTRL_FUNC(JTAGPSP), 516 ASPEED_PINCTRL_FUNC(JTAGSSP), 517 ASPEED_PINCTRL_FUNC(JTAGTSP), 518 ASPEED_PINCTRL_FUNC(JTAGUSB3A), 519 ASPEED_PINCTRL_FUNC(JTAGUSB3B), 520 /* PCIE RC functions */ 521 ASPEED_PINCTRL_FUNC(PCIERC0PERST), 522 ASPEED_PINCTRL_FUNC(PCIERC1PERST), 523 /* USB3A functions */ 524 ASPEED_PINCTRL_FUNC(USB3AXH), 525 ASPEED_PINCTRL_FUNC(USB3AXH2B), 526 ASPEED_PINCTRL_FUNC(USB3AXHD), 527 ASPEED_PINCTRL_FUNC(USB3AXHP), 528 ASPEED_PINCTRL_FUNC(USB3AXHP2B), 529 ASPEED_PINCTRL_FUNC(USB3AXHPD), 530 /* USB3B functions */ 531 ASPEED_PINCTRL_FUNC(USB3BXH), 532 ASPEED_PINCTRL_FUNC(USB3BXH2A), 533 ASPEED_PINCTRL_FUNC(USB3BXHD), 534 ASPEED_PINCTRL_FUNC(USB3BXHP), 535 ASPEED_PINCTRL_FUNC(USB3BXHP2A), 536 ASPEED_PINCTRL_FUNC(USB3BXHPD), 537 /* USB2A functions */ 538 ASPEED_PINCTRL_FUNC(USB2AD0), 539 ASPEED_PINCTRL_FUNC(USB2AD1), 540 ASPEED_PINCTRL_FUNC(USB2AH), 541 ASPEED_PINCTRL_FUNC(USB2AHP), 542 ASPEED_PINCTRL_FUNC(USB2AHPD0), 543 ASPEED_PINCTRL_FUNC(USB2AXH), 544 ASPEED_PINCTRL_FUNC(USB2AXH2B), 545 ASPEED_PINCTRL_FUNC(USB2AXHD1), 546 ASPEED_PINCTRL_FUNC(USB2AXHP), 547 ASPEED_PINCTRL_FUNC(USB2AXHP2B), 548 ASPEED_PINCTRL_FUNC(USB2AXHPD1), 549 /* USB2B functions */ 550 ASPEED_PINCTRL_FUNC(USB2BD0), 551 ASPEED_PINCTRL_FUNC(USB2BD1), 552 ASPEED_PINCTRL_FUNC(USB2BH), 553 ASPEED_PINCTRL_FUNC(USB2BHP), 554 ASPEED_PINCTRL_FUNC(USB2BHPD0), 555 ASPEED_PINCTRL_FUNC(USB2BXH), 556 ASPEED_PINCTRL_FUNC(USB2BXH2A), 557 ASPEED_PINCTRL_FUNC(USB2BXHD1), 558 ASPEED_PINCTRL_FUNC(USB2BXHP), 559 ASPEED_PINCTRL_FUNC(USB2BXHP2A), 560 ASPEED_PINCTRL_FUNC(USB2BXHPD1), 561 }; 562 563 static const struct pinmux_ops aspeed_g7_soc0_pinmux_ops = { 564 .get_functions_count = aspeed_pinmux_get_fn_count, 565 .get_function_name = aspeed_pinmux_get_fn_name, 566 .get_function_groups = aspeed_pinmux_get_fn_groups, 567 .set_mux = aspeed_pinmux_set_mux, 568 .gpio_request_enable = aspeed_gpio_request_enable, 569 .strict = true, 570 }; 571 572 static const struct pinctrl_ops aspeed_g7_soc0_pinctrl_ops = { 573 .get_groups_count = aspeed_pinctrl_get_groups_count, 574 .get_group_name = aspeed_pinctrl_get_group_name, 575 .get_group_pins = aspeed_pinctrl_get_group_pins, 576 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, 577 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 578 .dt_free_map = pinctrl_utils_free_map, 579 }; 580 581 static const struct pinconf_ops aspeed_g7_soc0_pinconf_ops = { 582 .is_generic = true, 583 .pin_config_get = aspeed_pin_config_get, 584 .pin_config_set = aspeed_pin_config_set, 585 .pin_config_group_get = aspeed_pin_config_group_get, 586 .pin_config_group_set = aspeed_pin_config_group_set, 587 }; 588 589 /* pinctrl_desc */ 590 static const struct pinctrl_desc aspeed_g7_soc0_pinctrl_desc = { 591 .name = "aspeed-g7-soc0-pinctrl", 592 .pins = aspeed_g7_soc0_pins, 593 .npins = ARRAY_SIZE(aspeed_g7_soc0_pins), 594 .pctlops = &aspeed_g7_soc0_pinctrl_ops, 595 .pmxops = &aspeed_g7_soc0_pinmux_ops, 596 .confops = &aspeed_g7_soc0_pinconf_ops, 597 }; 598 599 static const struct aspeed_pin_config aspeed_g7_soc0_configs[] = { 600 /* GPIO18A */ 601 { PIN_CONFIG_DRIVE_STRENGTH, { AC14, AC14 }, SCU480, GENMASK(3, 0) }, 602 { PIN_CONFIG_BIAS_PULL_DOWN, { AC14, AC14 }, SCU480, GENMASK(5, 4) }, 603 { PIN_CONFIG_BIAS_PULL_UP, { AC14, AC14 }, SCU480, GENMASK(5, 4) }, 604 { PIN_CONFIG_BIAS_DISABLE, { AC14, AC14 }, SCU480, BIT(5) }, 605 { PIN_CONFIG_DRIVE_STRENGTH, { AE15, AE15 }, SCU484, GENMASK(3, 0) }, 606 { PIN_CONFIG_BIAS_PULL_DOWN, { AE15, AE15 }, SCU484, GENMASK(5, 4) }, 607 { PIN_CONFIG_BIAS_PULL_UP, { AE15, AE15 }, SCU484, GENMASK(5, 4) }, 608 { PIN_CONFIG_BIAS_DISABLE, { AE15, AE15 }, SCU484, BIT(5) }, 609 { PIN_CONFIG_DRIVE_STRENGTH, { AD14, AD14 }, SCU488, GENMASK(3, 0) }, 610 { PIN_CONFIG_BIAS_PULL_DOWN, { AD14, AD14 }, SCU488, GENMASK(5, 4) }, 611 { PIN_CONFIG_BIAS_PULL_UP, { AD14, AD14 }, SCU488, GENMASK(5, 4) }, 612 { PIN_CONFIG_BIAS_DISABLE, { AD14, AD14 }, SCU488, BIT(5) }, 613 { PIN_CONFIG_DRIVE_STRENGTH, { AE14, AE14 }, SCU48C, GENMASK(3, 0) }, 614 { PIN_CONFIG_BIAS_PULL_DOWN, { AE14, AE14 }, SCU48C, GENMASK(5, 4) }, 615 { PIN_CONFIG_BIAS_PULL_UP, { AE14, AE14 }, SCU48C, GENMASK(5, 4) }, 616 { PIN_CONFIG_BIAS_DISABLE, { AE14, AE14 }, SCU48C, BIT(5) }, 617 { PIN_CONFIG_DRIVE_STRENGTH, { AF14, AF14 }, SCU490, GENMASK(3, 0) }, 618 { PIN_CONFIG_BIAS_PULL_DOWN, { AF14, AF14 }, SCU490, GENMASK(5, 4) }, 619 { PIN_CONFIG_BIAS_PULL_UP, { AF14, AF14 }, SCU490, GENMASK(5, 4) }, 620 { PIN_CONFIG_BIAS_DISABLE, { AF14, AF14 }, SCU490, BIT(5) }, 621 { PIN_CONFIG_DRIVE_STRENGTH, { AB13, AB13 }, SCU494, GENMASK(3, 0) }, 622 { PIN_CONFIG_BIAS_PULL_DOWN, { AB13, AB13 }, SCU494, GENMASK(5, 4) }, 623 { PIN_CONFIG_BIAS_PULL_UP, { AB13, AB13 }, SCU494, GENMASK(5, 4) }, 624 { PIN_CONFIG_BIAS_DISABLE, { AB13, AB13 }, SCU494, BIT(5) }, 625 { PIN_CONFIG_DRIVE_STRENGTH, { AB14, AB14 }, SCU498, GENMASK(3, 0) }, 626 { PIN_CONFIG_BIAS_PULL_DOWN, { AB14, AB14 }, SCU498, GENMASK(5, 4) }, 627 { PIN_CONFIG_BIAS_PULL_UP, { AB14, AB14 }, SCU498, GENMASK(5, 4) }, 628 { PIN_CONFIG_BIAS_DISABLE, { AB14, AB14 }, SCU498, BIT(5) }, 629 { PIN_CONFIG_DRIVE_STRENGTH, { AF15, AF15 }, SCU49C, GENMASK(3, 0) }, 630 { PIN_CONFIG_BIAS_PULL_DOWN, { AF15, AF15 }, SCU49C, GENMASK(5, 4) }, 631 { PIN_CONFIG_BIAS_PULL_UP, { AF15, AF15 }, SCU49C, GENMASK(5, 4) }, 632 { PIN_CONFIG_BIAS_DISABLE, { AF15, AF15 }, SCU49C, BIT(5) }, 633 /* GPIO18B */ 634 { PIN_CONFIG_DRIVE_STRENGTH, { AF13, AF13 }, SCU4A0, GENMASK(3, 0) }, 635 { PIN_CONFIG_BIAS_PULL_DOWN, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) }, 636 { PIN_CONFIG_BIAS_PULL_UP, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) }, 637 { PIN_CONFIG_BIAS_DISABLE, { AF13, AF13 }, SCU4A0, BIT(5) }, 638 { PIN_CONFIG_DRIVE_STRENGTH, { AC13, AC13 }, SCU4A4, GENMASK(3, 0) }, 639 { PIN_CONFIG_BIAS_PULL_DOWN, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) }, 640 { PIN_CONFIG_BIAS_PULL_UP, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) }, 641 { PIN_CONFIG_BIAS_DISABLE, { AC13, AC13 }, SCU4A4, BIT(5) }, 642 { PIN_CONFIG_DRIVE_STRENGTH, { AD13, AD13 }, SCU4A8, GENMASK(3, 0) }, 643 { PIN_CONFIG_BIAS_PULL_DOWN, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) }, 644 { PIN_CONFIG_BIAS_PULL_UP, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) }, 645 { PIN_CONFIG_BIAS_DISABLE, { AD13, AD13 }, SCU4A8, BIT(5) }, 646 { PIN_CONFIG_DRIVE_STRENGTH, { AE13, AE13 }, SCU4AC, GENMASK(3, 0) }, 647 { PIN_CONFIG_BIAS_PULL_DOWN, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) }, 648 { PIN_CONFIG_BIAS_PULL_UP, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) }, 649 { PIN_CONFIG_BIAS_DISABLE, { AE13, AE13 }, SCU4AC, BIT(5) }, 650 }; 651 652 static const struct aspeed_pin_config_map aspeed_g7_soc0_pin_config_map[] = { 653 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 2, GENMASK(1, 0) }, 654 { PIN_CONFIG_BIAS_PULL_UP, -1, 3, GENMASK(1, 0) }, 655 { PIN_CONFIG_BIAS_DISABLE, -1, 0, BIT_MASK(0) }, 656 { PIN_CONFIG_DRIVE_STRENGTH, 3, 0, GENMASK(3, 0) }, 657 { PIN_CONFIG_DRIVE_STRENGTH, 6, 1, GENMASK(3, 0) }, 658 { PIN_CONFIG_DRIVE_STRENGTH, 8, 2, GENMASK(3, 0) }, 659 { PIN_CONFIG_DRIVE_STRENGTH, 11, 3, GENMASK(3, 0) }, 660 { PIN_CONFIG_DRIVE_STRENGTH, 16, 4, GENMASK(3, 0) }, 661 { PIN_CONFIG_DRIVE_STRENGTH, 18, 5, GENMASK(3, 0) }, 662 { PIN_CONFIG_DRIVE_STRENGTH, 20, 6, GENMASK(3, 0) }, 663 { PIN_CONFIG_DRIVE_STRENGTH, 23, 7, GENMASK(3, 0) }, 664 { PIN_CONFIG_DRIVE_STRENGTH, 30, 8, GENMASK(3, 0) }, 665 { PIN_CONFIG_DRIVE_STRENGTH, 32, 9, GENMASK(3, 0) }, 666 { PIN_CONFIG_DRIVE_STRENGTH, 33, 10, GENMASK(3, 0) }, 667 { PIN_CONFIG_DRIVE_STRENGTH, 35, 11, GENMASK(3, 0) }, 668 { PIN_CONFIG_DRIVE_STRENGTH, 37, 12, GENMASK(3, 0) }, 669 { PIN_CONFIG_DRIVE_STRENGTH, 38, 13, GENMASK(3, 0) }, 670 { PIN_CONFIG_DRIVE_STRENGTH, 39, 14, GENMASK(3, 0) }, 671 { PIN_CONFIG_DRIVE_STRENGTH, 41, 15, GENMASK(3, 0) }, 672 673 }; 674 675 static int aspeed_g7_soc0_sig_expr_set(struct aspeed_pinmux_data *ctx, 676 const struct aspeed_sig_expr *expr, bool enable) 677 { 678 int ret; 679 int i; 680 681 for (i = 0; i < expr->ndescs; i++) { 682 const struct aspeed_sig_desc *desc = &expr->descs[i]; 683 u32 pattern = enable ? desc->enable : desc->disable; 684 u32 val = (pattern << __ffs(desc->mask)); 685 686 if (!ctx->maps[desc->ip]) 687 return -ENODEV; 688 689 WARN_ON_ONCE(desc->ip != ASPEED_IP_SCU); 690 691 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, 692 desc->mask, val); 693 if (ret) 694 return ret; 695 } 696 697 ret = aspeed_sig_expr_eval(ctx, expr, enable); 698 if (ret < 0) 699 return ret; 700 701 return ret ? 0 : -EPERM; 702 } 703 704 static const struct aspeed_pinmux_ops aspeed_g7_soc0_ops = { 705 .set = aspeed_g7_soc0_sig_expr_set, 706 }; 707 708 static struct aspeed_pinctrl_data aspeed_g7_soc0_pinctrl_data = { 709 .pins = aspeed_g7_soc0_pins, 710 .npins = ARRAY_SIZE(aspeed_g7_soc0_pins), 711 .pinmux = { 712 .ops = &aspeed_g7_soc0_ops, 713 .groups = aspeed_g7_soc0_groups, 714 .ngroups = ARRAY_SIZE(aspeed_g7_soc0_groups), 715 .functions = aspeed_g7_soc0_functions, 716 .nfunctions = ARRAY_SIZE(aspeed_g7_soc0_functions), 717 }, 718 .configs = aspeed_g7_soc0_configs, 719 .nconfigs = ARRAY_SIZE(aspeed_g7_soc0_configs), 720 .confmaps = aspeed_g7_soc0_pin_config_map, 721 .nconfmaps = ARRAY_SIZE(aspeed_g7_soc0_pin_config_map), 722 }; 723 724 static int aspeed_g7_soc0_pinctrl_probe(struct platform_device *pdev) 725 { 726 return aspeed_pinctrl_probe(pdev, &aspeed_g7_soc0_pinctrl_desc, 727 &aspeed_g7_soc0_pinctrl_data); 728 } 729 730 static const struct of_device_id aspeed_g7_soc0_pinctrl_match[] = { 731 { .compatible = "aspeed,ast2700-soc0-pinctrl" }, 732 {} 733 }; 734 MODULE_DEVICE_TABLE(of, aspeed_g7_soc0_pinctrl_match); 735 736 static struct platform_driver aspeed_g7_soc0_pinctrl_driver = { 737 .probe = aspeed_g7_soc0_pinctrl_probe, 738 .driver = { 739 .name = "aspeed-g7-soc0-pinctrl", 740 .of_match_table = aspeed_g7_soc0_pinctrl_match, 741 .suppress_bind_attrs = true, 742 }, 743 }; 744 745 static int __init aspeed_g7_soc0_pinctrl_init(void) 746 { 747 return platform_driver_register(&aspeed_g7_soc0_pinctrl_driver); 748 } 749 arch_initcall(aspeed_g7_soc0_pinctrl_init); 750