xref: /linux/drivers/phy/ti/phy-ds125df111.c (revision 3d5e48944e824bddc20d7b874e784f7b279636fe)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2026 NXP */
3 
4 #include <linux/bitfield.h>
5 #include <linux/bits.h>
6 #include <linux/i2c.h>
7 #include <linux/iopoll.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/phy.h>
11 #include <linux/phy/phy.h>
12 #include <linux/slab.h>
13 
14 #define DS125DF111_NUM_CH			2
15 #define DS125DF111_NUM_VCO_GROUP_REG		5
16 
17 #define DS125DF111_CH_SELECT			0xff
18 #define DS125DF111_CH_SELECT_TARGET_MASK	GENMASK(3, 0)
19 #define DS125DF111_CH_SELECT_EN			BIT(2)
20 
21 #define DS125DF111_CH_CTRL			0x00
22 #define DS125DF111_CH_CTRL_RESET		BIT(2) /* self clearing */
23 
24 #define DS125DF111_CH_RST_SLEEP_US		10
25 #define DS125DF111_CH_RST_TIMEOUT_US		10000
26 
27 #define DS125DF111_VCO_GROUP_BASE		0x60
28 
29 #define DS125DF111_RATIOS			0x2f
30 #define DS125DF111_RATIOS_RATE_MASK		GENMASK(7, 6)
31 #define DS125DF111_RATIOS_SUBRATE_MASK		GENMASK(5, 4)
32 #define DS125DF111_RATIOS_MASK			GENMASK(7, 4)
33 
34 struct ds125df111_ch {
35 	struct phy *phy;
36 	struct ds125df111_priv *priv;
37 	int idx;
38 };
39 
40 struct ds125df111_priv {
41 	struct ds125df111_ch ch[DS125DF111_NUM_CH];
42 	struct i2c_client *client;
43 	struct mutex mutex; /* protects access to shared registers */
44 };
45 
46 enum ds125df111_mode {
47 	FREQ_1G,
48 	FREQ_10G,
49 };
50 
51 static const struct ds125df111_config {
52 	u8 vco_group[DS125DF111_NUM_VCO_GROUP_REG];
53 	u8 rate;
54 	u8 subrate;
55 } ds125df111_cfg[] = {
56 	[FREQ_1G] = {
57 		/* VCO group #0 = 10GHz, VCO group #1 = 10GHz */
58 		.vco_group = {0x00, 0xB2, 0x00, 0xB2, 0xCC},
59 		/* By using the following combination of rate and subrate we
60 		 * select divide ratios of 1, 2, 4, 8 on both groups
61 		 */
62 		.rate = 0x1,
63 		.subrate = 0x2,
64 	},
65 
66 	[FREQ_10G] = {
67 		/* VCO group #0 = 10.3125GHz, VCO group #1 = 10.3125GHz */
68 		.vco_group = {0x90, 0xB3, 0x90, 0xB3, 0xCD},
69 		/* By using the following combination of rate and subrate we
70 		 * select divide ratios of 1 on both groups
71 		 */
72 		.rate = 0x1,
73 		.subrate = 0x3,
74 	},
75 };
76 
77 static int ds125df111_rmw(struct ds125df111_priv *priv, u8 reg, u8 clr, u8 set)
78 {
79 	struct i2c_client *i2c = priv->client;
80 	int err;
81 	u8 val;
82 
83 	err = i2c_smbus_read_byte_data(i2c, reg);
84 	if (err < 0)
85 		return err;
86 
87 	val = (u8)err;
88 	val &= ~clr;
89 	val |= set;
90 
91 	err = i2c_smbus_write_byte_data(i2c, reg, val);
92 	if (err < 0)
93 		return err;
94 
95 	return 0;
96 }
97 
98 static int ds125df111_configure(struct phy *phy,
99 				const struct ds125df111_config *cfg)
100 {
101 	struct ds125df111_ch *ch = phy_get_drvdata(phy);
102 	struct ds125df111_priv *priv = ch->priv;
103 	struct i2c_client *i2c = priv->client;
104 	struct device *dev = &phy->dev;
105 	u8 ratios_val;
106 	int err, i;
107 	int val;
108 
109 	mutex_lock(&priv->mutex);
110 
111 	/* Make sure that any subsequent read/write operation will be directed
112 	 * only to the registers of the selected channel
113 	 */
114 	err = ds125df111_rmw(priv, DS125DF111_CH_SELECT,
115 			     DS125DF111_CH_SELECT_TARGET_MASK,
116 			     DS125DF111_CH_SELECT_EN | ch->idx);
117 	if (err < 0) {
118 		dev_err(dev, "Unable to select channel: %pe\n", ERR_PTR(err));
119 		goto out;
120 	}
121 
122 	/* Reset channel registers and wait until the bit was cleared */
123 	err = ds125df111_rmw(priv, DS125DF111_CH_CTRL, 0,
124 			     DS125DF111_CH_CTRL_RESET);
125 	if (err < 0) {
126 		dev_err(dev, "Error resetting channel configuration: %pe\n",
127 			ERR_PTR(err));
128 		goto out;
129 	}
130 
131 	err = read_poll_timeout(i2c_smbus_read_byte_data, val,
132 				val < 0 || !(val & DS125DF111_CH_CTRL_RESET),
133 				DS125DF111_CH_RST_SLEEP_US,
134 				DS125DF111_CH_RST_TIMEOUT_US, false, i2c,
135 				DS125DF111_CH_CTRL);
136 	if (err) {
137 		dev_err(dev, "Timed out waiting for channel reset: %pe\n",
138 			ERR_PTR(err));
139 		goto out;
140 	}
141 
142 	if (val < 0) {
143 		dev_err(dev, "Error reading reset status: %pe\n", ERR_PTR(val));
144 		err = val;
145 		goto out;
146 	}
147 
148 	/* Program the VCO group frequencies */
149 	for (i = 0; i < DS125DF111_NUM_VCO_GROUP_REG; i++) {
150 		err = i2c_smbus_write_byte_data(i2c,
151 						DS125DF111_VCO_GROUP_BASE + i,
152 						cfg->vco_group[i]);
153 		if (err < 0) {
154 			dev_err(dev, "Error programming VCO group: %pe\n",
155 				ERR_PTR(err));
156 			goto out;
157 		}
158 	}
159 
160 	/* Set the divide ratios for the VCO groups */
161 	ratios_val = FIELD_PREP(DS125DF111_RATIOS_RATE_MASK, cfg->rate) |
162 		FIELD_PREP(DS125DF111_RATIOS_SUBRATE_MASK, cfg->subrate);
163 	err = ds125df111_rmw(priv, DS125DF111_RATIOS, DS125DF111_RATIOS_MASK,
164 			     ratios_val);
165 	if (err < 0) {
166 		dev_err(dev, "Error programming the divide ratios: %pe\n",
167 			ERR_PTR(err));
168 		goto out;
169 	}
170 
171 out:
172 	mutex_unlock(&priv->mutex);
173 
174 	return err;
175 }
176 
177 static int ds125df111_set_mode(struct phy *phy, enum phy_mode mode, int submode)
178 {
179 	const struct ds125df111_config *cfg;
180 
181 	if (mode != PHY_MODE_ETHERNET)
182 		return -EINVAL;
183 
184 	switch (submode) {
185 	case PHY_INTERFACE_MODE_10GBASER:
186 		cfg = &ds125df111_cfg[FREQ_10G];
187 		break;
188 	case PHY_INTERFACE_MODE_1000BASEX:
189 	case PHY_INTERFACE_MODE_SGMII:
190 		cfg = &ds125df111_cfg[FREQ_1G];
191 		break;
192 	default:
193 		return -EINVAL;
194 	}
195 
196 	return ds125df111_configure(phy, cfg);
197 }
198 
199 static int ds125df111_validate(struct phy *phy, enum phy_mode mode, int submode,
200 			       union phy_configure_opts *opts __always_unused)
201 {
202 	if (mode != PHY_MODE_ETHERNET)
203 		return -EINVAL;
204 
205 	switch (submode) {
206 	case PHY_INTERFACE_MODE_10GBASER:
207 	case PHY_INTERFACE_MODE_1000BASEX:
208 	case PHY_INTERFACE_MODE_SGMII:
209 		return 0;
210 	default:
211 		return -EINVAL;
212 	}
213 }
214 
215 static const struct phy_ops ds125df111_ops = {
216 	.validate	= ds125df111_validate,
217 	.set_mode	= ds125df111_set_mode,
218 	.owner		= THIS_MODULE,
219 };
220 
221 static struct phy *ds125df111_xlate(struct device *dev,
222 				    const struct of_phandle_args *args)
223 {
224 	struct ds125df111_priv *priv = dev_get_drvdata(dev);
225 	u32 idx;
226 
227 	if (args->args_count != 1)
228 		return ERR_PTR(-EINVAL);
229 
230 	idx = args->args[0];
231 	if (idx >= DS125DF111_NUM_CH) {
232 		dev_err(dev, "Maximum number of channels is %d\n",
233 			DS125DF111_NUM_CH);
234 		return ERR_PTR(-EINVAL);
235 	}
236 
237 	return priv->ch[idx].phy;
238 }
239 
240 static int ds125df111_probe(struct i2c_client *client)
241 {
242 	struct device *dev = &client->dev;
243 	struct phy_provider *provider;
244 	struct ds125df111_priv *priv;
245 	int i, err;
246 
247 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
248 	if (!priv)
249 		return -ENOMEM;
250 	priv->client = client;
251 	err = devm_mutex_init(dev, &priv->mutex);
252 	if (err)
253 		return err;
254 
255 	i2c_set_clientdata(client, priv);
256 
257 	for (i = 0; i < DS125DF111_NUM_CH; i++) {
258 		struct ds125df111_ch *ch = &priv->ch[i];
259 		struct phy *phy;
260 
261 		phy = devm_phy_create(dev, NULL, &ds125df111_ops);
262 		if (IS_ERR(phy))
263 			return PTR_ERR(phy);
264 
265 		ch->idx = i;
266 		ch->priv = priv;
267 		ch->phy = phy;
268 
269 		phy_set_drvdata(phy, ch);
270 	}
271 
272 	provider = devm_of_phy_provider_register(dev, ds125df111_xlate);
273 
274 	return PTR_ERR_OR_ZERO(provider);
275 }
276 
277 static const struct of_device_id ds125df111_dt_ids[] = {
278 	{ .compatible = "ti,ds125df111", },
279 	{}
280 };
281 MODULE_DEVICE_TABLE(of, ds125df111_dt_ids);
282 
283 static struct i2c_driver ds125df111_driver = {
284 	.driver = {
285 		.name = "ds125df111",
286 		.of_match_table = ds125df111_dt_ids,
287 	},
288 	.probe = ds125df111_probe,
289 };
290 module_i2c_driver(ds125df111_driver);
291 
292 MODULE_AUTHOR("Ioana Ciornei <ioana.ciornei@nxp.com>");
293 MODULE_DESCRIPTION("TI DS125DF111 Retimer driver");
294 MODULE_LICENSE("GPL");
295