1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Phy drivers for STMicro platforms 4# 5config PHY_MIPHY28LP 6 tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" 7 depends on ARCH_STI 8 select GENERIC_PHY 9 help 10 Enable this to support the miphy transceiver (for SATA/PCIE/USB3) 11 that is part of STMicroelectronics STiH407 SoC. 12 13config PHY_ST_SPEAR1310_MIPHY 14 tristate "ST SPEAR1310-MIPHY driver" 15 select GENERIC_PHY 16 depends on MACH_SPEAR1310 || COMPILE_TEST 17 help 18 Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA. 19 20config PHY_ST_SPEAR1340_MIPHY 21 tristate "ST SPEAR1340-MIPHY driver" 22 select GENERIC_PHY 23 depends on MACH_SPEAR1340 || COMPILE_TEST 24 help 25 Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA. 26 27config PHY_STIH407_USB 28 tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family" 29 depends on RESET_CONTROLLER 30 depends on ARCH_STI || COMPILE_TEST 31 select GENERIC_PHY 32 help 33 Enable this support to enable the picoPHY device used by USB2 34 and USB3 controllers on STMicroelectronics STiH407 SoC families. 35 36config PHY_STM32_COMBOPHY 37 tristate "STMicroelectronics COMBOPHY driver for STM32MP25" 38 depends on ARCH_STM32 || COMPILE_TEST 39 select GENERIC_PHY 40 help 41 Enable this to support the COMBOPHY device used by USB3 or PCIe 42 controllers on STMicroelectronics STM32MP25 SoC. 43 This driver controls the COMBOPHY block to generate the PCIe 100Mhz 44 reference clock from either the external clock generator or HSE 45 internal SoC clock source. 46 47config PHY_STM32_USBPHYC 48 tristate "STMicroelectronics STM32 USB HS PHY Controller driver" 49 depends on ARCH_STM32 || COMPILE_TEST 50 depends on COMMON_CLK 51 select GENERIC_PHY 52 help 53 Enable this to support the High-Speed USB transceivers that are part 54 of some STMicroelectronics STM32 SoCs. 55 56 This driver controls the entire USB PHY block: the USB PHY controller 57 (USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is 58 used by an HS USB Host controller, and the second one is shared 59 between an HS USB OTG controller and an HS USB Host controller, 60 selected by a USB switch. 61