10696cc73SMatthew Leung /* SPDX-License-Identifier: GPL-2.0 */ 20696cc73SMatthew Leung /* 30696cc73SMatthew Leung * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 40696cc73SMatthew Leung */ 50696cc73SMatthew Leung 60696cc73SMatthew Leung #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_ 70696cc73SMatthew Leung #define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_ 80696cc73SMatthew Leung 9*eca0e717SRonak Raheja /* Only for QMP V10 PHY - QSERDES TX/RX registers */ 100696cc73SMatthew Leung 11*eca0e717SRonak Raheja /* TX registers */ 12*eca0e717SRonak Raheja #define QSERDES_V10_TX_CLKBUF_ENABLE 0x08 13*eca0e717SRonak Raheja #define QSERDES_V10_TX_TX_EMP_POST1_LVL 0x0c 14*eca0e717SRonak Raheja #define QSERDES_V10_TX_TX_DRV_LVL 0x14 15*eca0e717SRonak Raheja #define QSERDES_V10_TX_RESET_TSYNC_EN 0x1c 16*eca0e717SRonak Raheja #define QSERDES_V10_TX_PRE_STALL_LDO_BOOST_EN 0x20 17*eca0e717SRonak Raheja #define QSERDES_V10_TX_TX_BAND 0x24 18*eca0e717SRonak Raheja #define QSERDES_V10_TX_INTERFACE_SELECT 0x2c 19*eca0e717SRonak Raheja #define QSERDES_V10_TX_RES_CODE_LANE_TX 0x34 20*eca0e717SRonak Raheja #define QSERDES_V10_TX_RES_CODE_LANE_RX 0x38 21*eca0e717SRonak Raheja #define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x3c 22*eca0e717SRonak Raheja #define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x40 23*eca0e717SRonak Raheja #define QSERDES_V10_TX_TRANSCEIVER_BIAS_EN 0x54 24*eca0e717SRonak Raheja #define QSERDES_V10_TX_HIGHZ_DRVR_EN 0x58 25*eca0e717SRonak Raheja #define QSERDES_V10_TX_TX_POL_INV 0x5c 26*eca0e717SRonak Raheja #define QSERDES_V10_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 27*eca0e717SRonak Raheja #define QSERDES_V10_TX_BIST_PATTERN7 0x7c 28*eca0e717SRonak Raheja #define QSERDES_V10_TX_LANE_MODE_1 0x84 29*eca0e717SRonak Raheja #define QSERDES_V10_TX_LANE_MODE_2 0x88 30*eca0e717SRonak Raheja #define QSERDES_V10_TX_LANE_MODE_3 0x8c 31*eca0e717SRonak Raheja #define QSERDES_V10_TX_LANE_MODE_4 0x90 32*eca0e717SRonak Raheja #define QSERDES_V10_TX_LANE_MODE_5 0x94 33*eca0e717SRonak Raheja #define QSERDES_V10_TX_RCV_DETECT_LVL_2 0xa4 34*eca0e717SRonak Raheja #define QSERDES_V10_TX_TRAN_DRVR_EMP_EN 0xc0 35*eca0e717SRonak Raheja #define QSERDES_V10_TX_TX_INTERFACE_MODE 0xc4 36*eca0e717SRonak Raheja #define QSERDES_V10_TX_VMODE_CTRL1 0xc8 37*eca0e717SRonak Raheja #define QSERDES_V10_TX_PI_QEC_CTRL 0xe4 38*eca0e717SRonak Raheja 39*eca0e717SRonak Raheja /* RX registers */ 40*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_FO_GAIN 0x08 41*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_SO_GAIN 0x14 42*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_FASTLOCK_FO_GAIN 0x30 43*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 44*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c 45*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 46*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_PI_CONTROLS 0x44 47*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x4c 48*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x50 49*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_SB2_GAIN1 0x54 50*eca0e717SRonak Raheja #define QSERDES_V10_RX_UCDR_SB2_GAIN2 0x58 51*eca0e717SRonak Raheja #define QSERDES_V10_RX_AUX_DATA_TCOARSE_TFINE 0x60 52*eca0e717SRonak Raheja #define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1 0xc4 53*eca0e717SRonak Raheja #define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2 0xc8 54*eca0e717SRonak Raheja #define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0xcc 55*eca0e717SRonak Raheja #define QSERDES_V10_RX_VGA_CAL_CNTRL1 0xd4 56*eca0e717SRonak Raheja #define QSERDES_V10_RX_VGA_CAL_CNTRL2 0xd8 57*eca0e717SRonak Raheja #define QSERDES_V10_RX_GM_CAL 0xdc 58*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL2 0xec 59*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 60*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 61*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0xf8 62*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_IDAC_TSETTLE_HIGH 0xfc 63*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_IDAC_ENABLES 0x100 64*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x104 65*eca0e717SRonak Raheja #define QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 660696cc73SMatthew Leung #define QSERDES_V10_RX_SIGDET_ENABLES 0x118 670696cc73SMatthew Leung #define QSERDES_V10_RX_SIGDET_CNTRL 0x11c 68*eca0e717SRonak Raheja #define QSERDES_V10_RX_SIGDET_DEGLITCH_CNTRL 0x124 690696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c 700696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160 710696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164 720696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168 730696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c 740696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_01_LOW 0x170 750696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174 760696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178 770696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c 780696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180 790696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_10_LOW 0x184 800696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188 810696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c 820696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190 830696cc73SMatthew Leung #define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194 84*eca0e717SRonak Raheja #define QSERDES_V10_RX_DFE_EN_TIMER 0x1a0 850696cc73SMatthew Leung #define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 86*eca0e717SRonak Raheja #define QSERDES_V10_RX_DCC_CTRL1 0x1a8 87*eca0e717SRonak Raheja #define QSERDES_V10_RX_VTH_CODE 0x1b0 88*eca0e717SRonak Raheja #define QSERDES_V10_RX_SIGDET_CAL_CTRL1 0x1e4 890696cc73SMatthew Leung #define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8 900696cc73SMatthew Leung 910696cc73SMatthew Leung #endif 92