1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_ 7 #define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_ 8 9 /* Only for QMP V10 PHY - QSERDES TX/RX registers */ 10 11 /* TX registers */ 12 #define QSERDES_V10_TX_CLKBUF_ENABLE 0x08 13 #define QSERDES_V10_TX_TX_EMP_POST1_LVL 0x0c 14 #define QSERDES_V10_TX_TX_DRV_LVL 0x14 15 #define QSERDES_V10_TX_RESET_TSYNC_EN 0x1c 16 #define QSERDES_V10_TX_PRE_STALL_LDO_BOOST_EN 0x20 17 #define QSERDES_V10_TX_TX_BAND 0x24 18 #define QSERDES_V10_TX_INTERFACE_SELECT 0x2c 19 #define QSERDES_V10_TX_RES_CODE_LANE_TX 0x34 20 #define QSERDES_V10_TX_RES_CODE_LANE_RX 0x38 21 #define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x3c 22 #define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x40 23 #define QSERDES_V10_TX_TRANSCEIVER_BIAS_EN 0x54 24 #define QSERDES_V10_TX_HIGHZ_DRVR_EN 0x58 25 #define QSERDES_V10_TX_TX_POL_INV 0x5c 26 #define QSERDES_V10_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 27 #define QSERDES_V10_TX_BIST_PATTERN7 0x7c 28 #define QSERDES_V10_TX_LANE_MODE_1 0x84 29 #define QSERDES_V10_TX_LANE_MODE_2 0x88 30 #define QSERDES_V10_TX_LANE_MODE_3 0x8c 31 #define QSERDES_V10_TX_LANE_MODE_4 0x90 32 #define QSERDES_V10_TX_LANE_MODE_5 0x94 33 #define QSERDES_V10_TX_RCV_DETECT_LVL_2 0xa4 34 #define QSERDES_V10_TX_TRAN_DRVR_EMP_EN 0xc0 35 #define QSERDES_V10_TX_TX_INTERFACE_MODE 0xc4 36 #define QSERDES_V10_TX_VMODE_CTRL1 0xc8 37 #define QSERDES_V10_TX_PI_QEC_CTRL 0xe4 38 39 /* RX registers */ 40 #define QSERDES_V10_RX_UCDR_FO_GAIN 0x08 41 #define QSERDES_V10_RX_UCDR_SO_GAIN 0x14 42 #define QSERDES_V10_RX_UCDR_FASTLOCK_FO_GAIN 0x30 43 #define QSERDES_V10_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 44 #define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c 45 #define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 46 #define QSERDES_V10_RX_UCDR_PI_CONTROLS 0x44 47 #define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x4c 48 #define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x50 49 #define QSERDES_V10_RX_UCDR_SB2_GAIN1 0x54 50 #define QSERDES_V10_RX_UCDR_SB2_GAIN2 0x58 51 #define QSERDES_V10_RX_AUX_DATA_TCOARSE_TFINE 0x60 52 #define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1 0xc4 53 #define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2 0xc8 54 #define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0xcc 55 #define QSERDES_V10_RX_VGA_CAL_CNTRL1 0xd4 56 #define QSERDES_V10_RX_VGA_CAL_CNTRL2 0xd8 57 #define QSERDES_V10_RX_GM_CAL 0xdc 58 #define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL2 0xec 59 #define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 60 #define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 61 #define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0xf8 62 #define QSERDES_V10_RX_RX_IDAC_TSETTLE_HIGH 0xfc 63 #define QSERDES_V10_RX_RX_IDAC_ENABLES 0x100 64 #define QSERDES_V10_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x104 65 #define QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 66 #define QSERDES_V10_RX_SIGDET_ENABLES 0x118 67 #define QSERDES_V10_RX_SIGDET_CNTRL 0x11c 68 #define QSERDES_V10_RX_SIGDET_DEGLITCH_CNTRL 0x124 69 #define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c 70 #define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160 71 #define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164 72 #define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168 73 #define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c 74 #define QSERDES_V10_RX_RX_MODE_01_LOW 0x170 75 #define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174 76 #define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178 77 #define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c 78 #define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180 79 #define QSERDES_V10_RX_RX_MODE_10_LOW 0x184 80 #define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188 81 #define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c 82 #define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190 83 #define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194 84 #define QSERDES_V10_RX_DFE_EN_TIMER 0x1a0 85 #define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 86 #define QSERDES_V10_RX_DCC_CTRL1 0x1a8 87 #define QSERDES_V10_RX_VTH_CODE 0x1b0 88 #define QSERDES_V10_RX_SIGDET_CAL_CTRL1 0x1e4 89 #define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8 90 91 #endif 92