1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_COM_V10_60_H_ 7 #define QCOM_PHY_QMP_QSERDES_COM_V10_60_H_ 8 9 /* Only for QMP V10_60 PHY - QSERDES COM registers */ 10 #define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1 0x00 11 #define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1 0x04 12 #define QSERDES_V10_60_COM_CP_CTRL_MODE1 0x10 13 #define QSERDES_V10_60_COM_PLL_RCTRL_MODE1 0x14 14 #define QSERDES_V10_60_COM_PLL_CCTRL_MODE1 0x18 15 #define QSERDES_V10_60_COM_CORECLK_DIV_MODE1 0x1c 16 #define QSERDES_V10_60_COM_LOCK_CMP1_MODE1 0x20 17 #define QSERDES_V10_60_COM_LOCK_CMP2_MODE1 0x24 18 #define QSERDES_V10_60_COM_DEC_START_MODE1 0x28 19 #define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1 0x30 20 #define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1 0x34 21 #define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1 0x38 22 #define QSERDES_V10_60_COM_HSCLK_SEL_1 0x3c 23 #define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0 0x60 24 #define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0 0x64 25 #define QSERDES_V10_60_COM_CP_CTRL_MODE0 0x70 26 #define QSERDES_V10_60_COM_PLL_RCTRL_MODE0 0x74 27 #define QSERDES_V10_60_COM_PLL_CCTRL_MODE0 0x78 28 #define QSERDES_V10_60_COM_CORECLK_DIV_MODE0 0x7c 29 #define QSERDES_V10_60_COM_LOCK_CMP1_MODE0 0x80 30 #define QSERDES_V10_60_COM_LOCK_CMP2_MODE0 0x84 31 #define QSERDES_V10_60_COM_DEC_START_MODE0 0x88 32 #define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0 0x90 33 #define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0 0x94 34 #define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0 0x98 35 #define QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1 0x9c 36 #define QSERDES_V10_60_COM_BG_TIMER 0xbc 37 #define QSERDES_V10_60_COM_SSC_PER1 0xcc 38 #define QSERDES_V10_60_COM_SSC_PER2 0xd0 39 #define QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN 0xdc 40 #define QSERDES_V10_60_COM_CLK_ENABLE1 0xe0 41 #define QSERDES_V10_60_COM_SYS_CLK_CTRL 0xe4 42 #define QSERDES_V10_60_COM_PLL_IVCO 0xf4 43 #define QSERDES_V10_60_COM_SYSCLK_EN_SEL 0x110 44 #define QSERDES_V10_60_COM_LOCK_CMP_EN 0x120 45 #define QSERDES_V10_60_COM_LOCK_CMP_CFG 0x124 46 #define QSERDES_V10_60_COM_VCO_TUNE_MAP 0x140 47 #define QSERDES_V10_60_COM_CLK_SELECT 0x164 48 #define QSERDES_V10_60_COM_CORE_CLK_EN 0x170 49 #define QSERDES_V10_60_COM_CMN_CONFIG_1 0x174 50 #define QSERDES_V10_60_COM_CMN_MISC1 0x184 51 #define QSERDES_V10_60_COM_CMN_MODE 0x188 52 #define QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL 0x198 53 #define QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO 0x2b4 54 55 #endif 56