1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef QCOM_PHY_QMP_PCS_V10_H_ 7 #define QCOM_PHY_QMP_PCS_V10_H_ 8 9 /* Only for QMP V10 PHY - PCS registers */ 10 11 #define QPHY_V10_PCS_SW_RESET 0x000 12 #define QPHY_V10_PCS_PCS_STATUS1 0x014 13 #define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040 14 #define QPHY_V10_PCS_START_CONTROL 0x044 15 #define QPHY_V10_PCS_POWER_STATE_CONFIG1 0x090 16 #define QPHY_V10_PCS_LOCK_DETECT_CONFIG1 0x0c4 17 #define QPHY_V10_PCS_LOCK_DETECT_CONFIG2 0x0c8 18 #define QPHY_V10_PCS_LOCK_DETECT_CONFIG3 0x0cc 19 #define QPHY_V10_PCS_LOCK_DETECT_CONFIG6 0x0d8 20 #define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc 21 #define QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB 0x168 22 #define QPHY_V10_PCS_G3S2_PRE_GAIN 0x170 23 #define QPHY_V10_PCS_RX_SIGDET_LVL 0x188 24 #define QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 25 #define QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 26 #define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198 27 #define QPHY_V10_PCS_RX_CONFIG 0x1b0 28 #define QPHY_V10_PCS_ALIGN_DETECT_CONFIG1 0x1c0 29 #define QPHY_V10_PCS_ALIGN_DETECT_CONFIG2 0x1c4 30 #define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0 31 #define QPHY_V10_PCS_PCS_TX_RX_CONFIG2 0x1d4 32 #define QPHY_V10_PCS_EQ_CONFIG1 0x1e0 33 #define QPHY_V10_PCS_EQ_CONFIG2 0x1e4 34 #define QPHY_V10_PCS_EQ_CONFIG5 0x1f0 35 36 #endif 37