1*2f7b4bc4SPalash Kambar /* SPDX-License-Identifier: GPL-2.0 */ 2*2f7b4bc4SPalash Kambar /* 3*2f7b4bc4SPalash Kambar * Copyright (c) 2026, The Linux Foundation. All rights reserved. 4*2f7b4bc4SPalash Kambar */ 5*2f7b4bc4SPalash Kambar 6*2f7b4bc4SPalash Kambar #ifndef QCOM_PHY_QMP_PCS_UFS_V7_H_ 7*2f7b4bc4SPalash Kambar #define QCOM_PHY_QMP_PCS_UFS_V7_H_ 8*2f7b4bc4SPalash Kambar 9*2f7b4bc4SPalash Kambar /* Only for QMP V7 PHY - UFS PCS registers */ 10*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_PHY_START 0x000 11*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL 0x004 12*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_SW_RESET 0x008 13*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_PCS_CTRL1 0x01c 14*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_PLL_CNTL 0x028 15*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c 16*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY 0x060 17*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY 0x094 18*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_LINECFG_DISABLE 0x140 19*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2 0x150 20*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_READY_STATUS 0x16c 21*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1 0x1b8 22*2f7b4bc4SPalash Kambar #define QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1 0x1c0 23*2f7b4bc4SPalash Kambar 24*2f7b4bc4SPalash Kambar #endif 25