xref: /linux/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h (revision 16e6a1a3cb3fa5fa11cd76a9d71235d927923329)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2026, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef QCOM_PHY_QMP_PCS_UFS_V7_H_
7 #define QCOM_PHY_QMP_PCS_UFS_V7_H_
8 
9 /* Only for QMP V7 PHY - UFS PCS registers */
10 #define QPHY_V7_PCS_UFS_PHY_START			0x000
11 #define QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL		0x004
12 #define QPHY_V7_PCS_UFS_SW_RESET			0x008
13 #define QPHY_V7_PCS_UFS_PCS_CTRL1			0x01c
14 #define QPHY_V7_PCS_UFS_PLL_CNTL			0x028
15 #define QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x02c
16 #define QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY		0x060
17 #define QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY		0x094
18 #define QPHY_V7_PCS_UFS_LINECFG_DISABLE			0x140
19 #define QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2			0x150
20 #define QPHY_V7_PCS_UFS_READY_STATUS			0x16c
21 #define QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1		0x1b8
22 #define QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1		0x1c0
23 
24 #endif
25