1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: jitao.shi <jitao.shi@mediatek.com>
5 *
6 * Copyright (c) 2026 Collabora Ltd.
7 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
8 */
9
10 #include "phy-mtk-io.h"
11 #include "phy-mtk-mipi-dsi.h"
12
13 #define MIPITX_LANE_CON 0x0004
14 #define RG_DSI_CPHY_T1DRV_EN BIT(0)
15 #define RG_DSI_ANA_CK_SEL BIT(1)
16 #define RG_DSI_PHY_CK_SEL BIT(2)
17 #define RG_DSI_CPHY_EN BIT(3)
18 #define RG_DSI_PHYCK_INV_EN BIT(4)
19 #define RG_DSI_PWR04_EN BIT(5)
20 #define RG_DSI_BG_LPF_EN BIT(6)
21 #define RG_DSI_BG_CORE_EN BIT(7)
22 #define RG_DSI_PAD_TIEL_SEL BIT(8)
23
24 #define MIPITX_VOLTAGE_SEL 0x0008
25 #define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6)
26 #define RG_DSI_PRD_REF_SEL GENMASK(5, 0)
27 #define RG_DSI_PRD_REF_MINI 0
28 #define RG_DSI_PRD_REF_DEF 4
29 #define RG_DSI_PRD_REF_MAX 7
30
31 #define MIPITX_PRESERVED 0x000c
32 #define MIPITX_PRESERVED_DEF 0xffff0040
33 #define MIPITX_PRESERVED_MINI 0xffff00f0
34
35 #define MIPITX_PLL_PWR 0x0028
36 #define AD_DSI_PLL_SDM_PWR_ON BIT(0)
37 #define AD_DSI_PLL_SDM_ISO_EN BIT(1)
38 #define MIPITX_PLL_CON0 0x002c
39 #define MIPITX_PLL_CON1 0x0030
40 #define RG_DSI_PLL_EN BIT(0)
41 #define RG_DSI_PLL_POSDIV GENMASK(10, 8)
42 #define MIPITX_PLL_CON2 0x0034
43 #define MIPITX_PLL_CON3 0x0038
44 #define MIPITX_PLL_CON4 0x003c
45 #define RG_DSI_PLL_IBIAS GENMASK(11, 10)
46
47 #define MIPITX_D2_SW_CTL_EN 0x015c
48 #define MIPITX_D0_SW_CTL_EN 0x025c
49 #define MIPITX_CK_CKMODE_EN 0x0320
50 #define DSI_CK_CKMODE_EN BIT(0)
51 #define MIPITX_CK_SW_CTL_EN 0x035c
52 #define MIPITX_D1_SW_CTL_EN 0x045c
53 #define MIPITX_D3_SW_CTL_EN 0x055c
54 #define DSI_SW_CTL_EN BIT(0)
55
56 #define DSI_PHY_XTAL_CLK_HZ 26000000
57 #define DSI_PHY_PLL_MIN_RATE_HZ 125000000
58 #define DSI_PHY_PLL_MAX_RATE_HZ 2000000000
59
mtk_mipi_tx_pll_enable(struct clk_hw * hw)60 static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
61 {
62 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
63 void __iomem *base = mipi_tx->regs;
64 u32 voltage = RG_DSI_PRD_REF_MINI;
65 u32 pres = MIPITX_PRESERVED_MINI;
66 unsigned long long pcw_calc;
67 unsigned int txdiv, txdiv0;
68 u32 pcw;
69
70 dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
71
72 if (mipi_tx->data_rate >= DSI_PHY_PLL_MAX_RATE_HZ) {
73 /* Select higher signaling voltage for fast data rates */
74 voltage = RG_DSI_PRD_REF_DEF;
75 pres = MIPITX_PRESERVED_DEF;
76 txdiv = 1;
77 txdiv0 = 0;
78 } else if (mipi_tx->data_rate >= 1000000000) {
79 txdiv = 2;
80 txdiv0 = 1;
81 } else if (mipi_tx->data_rate >= 500000000) {
82 txdiv = 4;
83 txdiv0 = 2;
84 } else if (mipi_tx->data_rate > 250000000) {
85 txdiv = 8;
86 txdiv0 = 3;
87 } else if (mipi_tx->data_rate >= 125000000) {
88 txdiv = 16;
89 txdiv0 = 4;
90 } else {
91 return -EINVAL;
92 }
93
94 pcw_calc = ((u64)(mipi_tx->data_rate / 2) * txdiv) << 24;
95 pcw_calc = div_u64(pcw_calc, DSI_PHY_XTAL_CLK_HZ);
96
97 if (pcw_calc > U32_MAX) {
98 dev_err(mipi_tx->dev, "Calculated PCW=%llu overflow!\n", pcw_calc);
99 return -EINVAL;
100 }
101 pcw = (u32)pcw_calc;
102
103 mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_PRD_REF_SEL, voltage);
104 writel(pres, base + MIPITX_PRESERVED);
105
106 /* Enable the SDM and wait for power to stabilize */
107 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
108 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
109 udelay(30);
110
111 /* Disable isolation and program PLL's PCW and dividers */
112 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
113 writel(pcw, base + MIPITX_PLL_CON0);
114 mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);
115
116 /* Enable the PLL and wait for the clock output to stabilize */
117 mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
118 udelay(30);
119
120 return 0;
121 }
122
mtk_mipi_tx_pll_disable(struct clk_hw * hw)123 static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
124 {
125 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
126 void __iomem *base = mipi_tx->regs;
127
128 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
129
130 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
131 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
132 }
133
mtk_mipi_tx_pll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)134 static int mtk_mipi_tx_pll_determine_rate(struct clk_hw *hw,
135 struct clk_rate_request *req)
136 {
137 req->rate = clamp_val(req->rate,
138 DSI_PHY_PLL_MIN_RATE_HZ, DSI_PHY_PLL_MAX_RATE_HZ);
139
140 return 0;
141 }
142
143 static const struct clk_ops mtk_mipi_tx_pll_ops = {
144 .enable = mtk_mipi_tx_pll_enable,
145 .disable = mtk_mipi_tx_pll_disable,
146 .determine_rate = mtk_mipi_tx_pll_determine_rate,
147 .set_rate = mtk_mipi_tx_pll_set_rate,
148 .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
149 };
150
mtk_mipi_tx_power_on_signal(struct phy * phy)151 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
152 {
153 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
154 void __iomem *base = mipi_tx->regs;
155
156 /* BG_LPF_EN / BG_CORE_EN */
157 writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
158 /* Wait for MIPI core to enable */
159 usleep_range(30, 100);
160 writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
161
162 /* Switch OFF each Lane */
163 mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
164 mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
165 mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
166 mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
167 mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
168
169 /*
170 * The MIPI TX drive strength is in the range of 3000 ~ 6000 microamps:
171 * RG_DSI_HSTX_LDO_REF_SEL expresses an offset from the minimum drive
172 * strength (3000uA) and can add a maximum offset of 3000uA, reaching a
173 * maximum drive strength of 3000+3000=6000uA.
174 */
175 mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,
176 (mipi_tx->mipitx_drive - 3000) / 200);
177
178 mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
179 }
180
mtk_mipi_tx_power_off_signal(struct phy * phy)181 static void mtk_mipi_tx_power_off_signal(struct phy *phy)
182 {
183 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
184 void __iomem *base = mipi_tx->regs;
185
186 /* Switch ON each lane one by one */
187 mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
188 mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
189 mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
190 mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
191 mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
192
193 writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
194 writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON);
195 }
196
197 const struct mtk_mipitx_data mt8196_mipitx_data = {
198 .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
199 .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
200 .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
201 };
202